A duty cycle adjustment circuit that maintains a fixed delay on the rising edge

By combining two independent delay lines and logic operations, the accuracy problem of duty cycle correction under high-frequency clock is solved, achieving high-precision duty cycle correction and fixed rising edge timing, thereby improving the sampling accuracy and stability of the integrated circuit.

CN122600941APending Publication Date: 2026-08-18SHANGHAI UNIVISTA IND SOFTWARE GRP CO LTD +1
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Patent Information

Application Number
CN202610785349.3
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-06-02
Publication Date
2026-08-18

AI Technical Summary

Technical Problem

Existing technologies struggle to achieve high-precision duty cycle correction under high-frequency clocks, and conventional circuits cannot maintain a fixed delay for the rising edge of the clock, affecting the sampling accuracy and system stability of dual-edge sampling circuits.

Method used

Two independent delay lines are used to delay the input clock for different durations, and the signals are fused through logic operations to generate a corrected clock. Combined with the sign bit signal and a multiplexer, the duty cycle is continuously adjustable in both directions to ensure a fixed rising edge timing.

Benefits of technology

It achieves precise duty cycle correction for high-frequency clocks, with a correction accuracy of within ±1%, ensuring consistent rising edge timing, improving circuit reliability and adaptability, and is suitable for high-frequency, highly integrated integrated circuits.

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Abstract

The application relates to the technical field of integrated circuits, in particular to a duty cycle adjustment circuit capable of keeping the rising edge fixed delay. The duty cycle adjustment circuit comprises a first delay line module, a second delay line module, a logic operation unit, a first or logic operation unit and a multiplexer. The first input end and the second input end of the first delay line module are connected with a first delay control signal and an external input clock signal respectively, and the output of the first delay line module is a first delay clock signal. The first input end and the second input end of the second delay line module are connected with a second delay control signal and the external input clock signal respectively, and the output of the second delay line module is a second delay clock signal. The first input end and the second input end of the logic operation unit are connected with the first delay clock signal and the second delay clock signal respectively, and the output end of the logic operation unit is a clock and signal. The first input end and the second input end of the first or logic operation unit are connected with the first delay clock signal and the second delay clock signal respectively, and the output end of the first or logic operation unit is a clock or signal. The first input end and the second input end of the multiplexer are connected with the clock and signal and the clock or signal respectively, and the multiplexer is used for controlling the output of the clock and signal or the clock or signal according to a symbol bit signal. The application can accurately correct the duty cycle.
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