Semiconductor package structure and method of manufacturing the same

Abstract

This application relates to a semiconductor packaging structure and its fabrication method. The fabrication method includes: providing a first temporary substrate, forming conductive pillars and micropads on one side of the first temporary substrate; providing a first chip, flip-bonding the first chip to one side of the first temporary substrate; forming a molding compound layer on one side of the first temporary substrate; forming a bump structure on the side of the molding compound layer away from the first temporary substrate; forming a second temporary substrate on the side of the bump structure away from the molding compound; removing the first temporary substrate to expose the first chip pads and the end faces of the conductive pillars on the front side of the first chip away from the bump structure; forming a redistribution layer on the side of the molding compound layer away from the bump structure; and mounting a second chip on the side of the redistribution layer away from the molding compound. In this application, forming the bump structure first and then the redistribution layer reduces one bonding process, simplifies the fabrication process, shortens the fabrication time, and reduces material consumption.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a semiconductor packaging structure and its fabrication method. Background Technology

[0002] Co-Packaged Optics (CPO) technology is a technique that integrates electronic integrated circuits (EICs) and photonic integrated circuits (PICs) into a single package. In the current field of communication technology, CPO technology has become a focal point and a key area of ​​research in recent years.

[0003] However, existing optoelectronic co-packaging processes have problems such as requiring multiple temporary bonding and debonding operations, excessively long processes, and high material consumption. Summary of the Invention

[0004] Based on this, this application provides a semiconductor packaging structure and its fabrication method, which can reduce bonding processes, shorten the process, and save material consumption.

[0005] In a first aspect, this application provides a method for fabricating a semiconductor packaging structure, comprising:

[0006] A first temporary substrate is provided, and a conductive pillar is formed on one side of the first temporary substrate;

[0007] A first chip is provided, and the first chip is flip-chip bonded to one side of the first temporary substrate on which the conductive pillars are formed;

[0008] A molding layer is formed on one side of the first temporary substrate, the molding layer molding the first chip and the conductive pillar, and exposing the end face of the conductive pillar away from the first temporary substrate;

[0009] A bump structure is formed on the side of the molding layer away from the first temporary substrate, and the bump structure is electrically connected to the conductive pillar;

[0010] A second temporary substrate is formed on the side of the bump structure away from the molding layer;

[0011] Remove the first temporary substrate to expose the first chip pad on the front side of the first chip and the end face of the conductive pillar away from the bump structure;

[0012] A redistribution layer is formed on the side of the molding layer away from the bump structure, and the redistribution layer is electrically connected to the first chip pad and the conductive pillar;

[0013] A second chip is mounted on the side of the redistribution layer away from the molding compound, and the second chip pad of the second chip is electrically connected to the redistribution layer.

[0014] In some embodiments of this application, while forming conductive pillars on one side of the first temporary substrate, micro pads are also formed on one side of the first temporary substrate, and the micro pads and conductive pillars are located on the same side of the first temporary substrate.

[0015] In some embodiments of this application, flip-chip bonding the first chip to the side of the first temporary substrate where the conductive pillars are formed includes: bonding the first chip pad of the first chip to the side of the micro pad away from the first temporary substrate via a first solder joint.

[0016] A separation film is formed on one side surface of the first temporary substrate, and the micro pads and the conductive pillars are formed on the surface of the separation film away from the first temporary substrate;

[0017] Removing the first temporary substrate to expose the first chip pads and the end faces of the conductive pillars away from the bump structure on the front side of the first chip includes: removing the separation film and the first temporary substrate; thinning the molding compound and the conductive pillars; and removing the micro pads and the first solder joints to expose the first chip pads.

[0018] In some embodiments of this application, before forming the bump structure on the side of the encapsulation layer away from the first temporary substrate, the method further includes:

[0019] A covering dielectric layer is formed on the side of the molding layer away from the first temporary substrate;

[0020] A first interconnect plug is formed within the covering medium layer, and the first interconnect plug is electrically connected to the conductive post; the bump structure is formed on the surface of the covering medium layer away from the molding layer, and is electrically connected to the first interconnect plug.

[0021] In some embodiments of this application, a second temporary substrate is formed on the side of the bump structure away from the molding layer, including:

[0022] A bonding layer is formed, which covers the bump structure;

[0023] The second temporary substrate is bonded to the surface of the bonding layer away from the bump structure.

[0024] In some embodiments of this application, after mounting the second chip on the side of the redistribution layer away from the molding compound, the method further includes:

[0025] A bottom fill layer is formed, which fills the gap between the second chip and the redistribution layer;

[0026] Remove the second temporary substrate to expose the bump structure.

[0027] In some embodiments of this application, removing the second temporary substrate to expose the bump structure includes:

[0028] The structure obtained after forming the bottom filler layer is attached to the surface of the scribe film;

[0029] Remove the second temporary substrate to expose the bump structure;

[0030] The structure obtained after removing the second temporary substrate is peeled off from the dicing film.

[0031] In some embodiments of this application, both the first temporary substrate and the second temporary substrate comprise a glass substrate.

[0032] In some embodiments of this application, the first chip includes an electronic chip, and the second chip includes a photonic chip; after forming a redistribution layer on the side of the encapsulation layer away from the bump structure, and before mounting the second chip on the side of the redistribution layer away from the encapsulation layer, the method further includes: removing at least a portion of the redistribution layer and a portion of the encapsulation layer to form a groove; the orthographic projection of the optical port region of the photonic chip on the surface of the second temporary substrate is located within the orthographic projection of the groove on the surface of the second temporary substrate.

[0033] Secondly, embodiments of this application also provide a semiconductor packaging structure, which is prepared by the semiconductor packaging structure preparation method described in the first aspect.

[0034] The embodiments of this application may have, or at least have, the following advantages:

[0035] The semiconductor packaging structure and its fabrication method in this application first form a bump structure and then form a redistribution layer, which can reduce one bonding process, simplify the fabrication process, shorten the fabrication process, and reduce material consumption.

[0036] Details of one or more embodiments of this application are set forth in the following drawings and description. Other features, objects, and advantages of this application will become apparent from the specification, drawings, and claims. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 A flowchart illustrating a method for fabricating a semiconductor packaging structure according to an embodiment of this application;

[0039] Figure 2 This is a schematic cross-sectional view of the structure obtained after forming a separation film in a method for preparing a semiconductor packaging structure according to an embodiment of this application.

[0040] Figure 3 A schematic cross-sectional view of the structure obtained after forming conductive pillars and micro pads in a method for fabricating a semiconductor packaging structure according to an embodiment of this application;

[0041] Figure 4 This is a schematic cross-sectional view of the structure obtained in step S20 of the method for preparing a semiconductor packaging structure according to an embodiment of this application.

[0042] Figure 5 and Figure 6 This is a schematic diagram of the structure obtained in step S30 of the method for preparing a semiconductor packaging structure according to an embodiment of this application;

[0043] Figure 7 This is a schematic cross-sectional view of the structure obtained in step S40 of the method for fabricating a semiconductor packaging structure according to an embodiment of this application.

[0044] Figure 8 This is a schematic cross-sectional view of the structure obtained in step S50 of the method for fabricating a semiconductor packaging structure according to an embodiment of this application.

[0045] Figure 9 and Figure 10 This is a schematic cross-sectional view of the structure obtained in step S60 of the method for fabricating a semiconductor packaging structure according to an embodiment of this application.

[0046] Figure 11 This is a schematic cross-sectional view of the structure obtained in step S70 of the method for fabricating a semiconductor packaging structure according to an embodiment of this application.

[0047] Figure 12 This is a schematic cross-sectional view of the structure obtained after forming a groove in a method for fabricating a semiconductor packaging structure according to an embodiment of this application.

[0048] Figure 13This is a schematic cross-sectional view of the structure obtained in step S80 of the method for fabricating a semiconductor packaging structure according to an embodiment of this application.

[0049] Figure 14 This is a schematic cross-sectional view of the structure obtained after forming the bottom filling layer in a method for fabricating a semiconductor packaging structure according to an embodiment of this application.

[0050] Figure 15 A schematic diagram of the cross-sectional structure of the structure obtained after the bottom filling layer is formed is attached to the surface of the scriber membrane;

[0051] Figure 16 This is a schematic diagram of the cross-sectional structure of the structure obtained after removing the second temporary substrate.

[0052] Explanation of reference numerals in the attached figures:

[0053] 10. First temporary substrate; 11. Separation membrane; 12. Conductive pillar; 13. Micropad; 14. First chip; 141. First chip pad; 15. First solder joint; 16. Molding layer; 17. Cover dielectric layer; 171. First interconnect plug; 18. Bump structure; 19. Bonding layer; 20. Second temporary substrate; 21. Redistribution layer; 211. Dielectric layer; 212. Metal wiring layer; 213. Second interconnect plug; 22. Groove; 23. Second chip; 231. Second chip pad; 24. Second solder joint; 25. Bottom filler layer; 26. Dicing film; A1: Effective area; B1: Ineffective area. Detailed Implementation

[0054] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0056] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0057] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0058] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0059] The structure of embodiments of the present invention should not be limited to the specific shape shown in the accompanying drawings, but includes shape deviations due to, for example, manufacturing techniques.

[0060] It is understood that in the accompanying drawings of this application, some adjacent membrane layers with the same processed membrane material are drawn as connected to make them resemble the actual structure.

[0061] Please see Figure 1 This application provides a method for preparing a semiconductor packaging structure, which may include the following steps: S10~S80.

[0062] S10: Provide a first temporary substrate and form a conductive pillar on one side of the first temporary substrate.

[0063] S20: Provide a first chip and flip-bond the first chip to one side of a first temporary substrate on which conductive pillars are formed.

[0064] S30: A molding layer is formed on one side of the first temporary substrate. The molding layer molds the first chip and the conductive pillar, and exposes the end face of the conductive pillar away from the first temporary substrate.

[0065] S40: A bump structure is formed on the side of the molding layer away from the first temporary substrate, and the bump structure is electrically connected to the conductive pillar.

[0066] S50: A second temporary substrate is formed on the side of the bump structure away from the molding layer.

[0067] S60: Remove the first temporary substrate to expose the first chip pads and conductive pillars on the front side of the first chip away from the bump structure.

[0068] S70: A redistribution layer is formed on the side of the molding layer away from the bump structure, and the redistribution layer is electrically connected to the first chip pad and conductive pillar.

[0069] S80: A second chip is mounted on the side of the redistribution layer away from the molding compound, and the second chip pad of the second chip is electrically connected to the redistribution layer.

[0070] In the semiconductor packaging structure fabrication method of this application embodiment, a bump structure is formed first, and then a redistribution layer is formed, which can reduce one bonding process, simplify the fabrication process, shorten the fabrication process, and reduce material consumption.

[0071] In some embodiments, in step S10, while forming a conductive pillar on one side of the first temporary substrate, a micropad (upad) is also formed on one side of the first temporary substrate, and the micropad and the conductive pillar are located on the same side of the first temporary substrate.

[0072] In some embodiments, step S20, flip-chip bonding the first chip to the side of the first temporary substrate where the conductive pillar is formed, includes: bonding the first chip pad of the first chip to the side of the micro pad away from the first temporary substrate via the first solder point.

[0073] In some embodiments, a separation membrane is formed on one side surface of the first temporary substrate, and micropads and conductive pillars are formed on the surface of the separation membrane away from the first temporary substrate.

[0074] In some embodiments, before forming the bump structure on the side of the encapsulation layer away from the first temporary substrate, between steps S30 and S40, the following is further included: forming a cover dielectric layer on the side of the encapsulation layer away from the first temporary substrate; forming a first interconnect plug in the cover dielectric layer, the first interconnect plug being electrically connected to a conductive pillar; and forming the bump structure on the surface of the cover dielectric layer away from the encapsulation layer and being electrically connected to the first interconnect plug.

[0075] In some embodiments, step S50, forming a second temporary substrate on the side of the bump structure away from the molding layer, may include the following steps: S501~S502.

[0076] S501: Form a bonding layer that covers the bump structure.

[0077] S502: Bond the second temporary substrate to the surface of the bonding layer away from the bump structure.

[0078] In some embodiments, step S60, removing the first temporary substrate to expose the first chip pads and conductive pillars on the front side of the first chip away from the bump structure, includes: removing the separation film and the first temporary substrate; thinning the molding compound and conductive pillars; and removing the micropads and first solder joints to expose the first chip pads.

[0079] In some embodiments, the first chip may include an electronic chip, and the second chip may include a photonic chip.

[0080] In some examples, after forming the redistribution layer on the side of the molding compound away from the bump structure and before mounting the second chip on the side of the redistribution layer away from the molding compound, i.e., between steps S70 and S80, the following may also be included: at least a portion of the redistribution layer and a portion of the molding compound layer are removed to form a groove; the orthographic projection of the optical port area of ​​the photonic chip on the surface of the second temporary substrate lies within the orthographic projection of the groove on the surface of the second temporary substrate. Specifically, the groove can be formed by, but is not limited to, multiple cuts; of course, an etching process can also be used to form the groove.

[0081] In some embodiments, after step S80, that is, after mounting the second chip on the side of the redistribution layer away from the molding compound, the following steps are further included: S901~S902.

[0082] S901: Form a bottom fill layer to fill the gap between the second chip and the redistribution layer;

[0083] S902: Remove the second temporary substrate to expose the bump structure.

[0084] In some embodiments, step S902, removing the second temporary substrate to expose the bump structure, may include the following: attaching the structure obtained after forming the bottom fill layer to the surface of the scribe film; removing the second temporary substrate to expose the bump structure; and peeling the structure obtained after removing the second temporary substrate from the scribe film.

[0085] In some embodiments, the first temporary substrate and the second temporary substrate mentioned in the above scheme may both include, but are not limited to, glass substrates. For example, in other embodiments, the first temporary substrate and the second temporary substrate may also include silicon substrates, gallium nitride substrates, silicon carbide substrates, sapphire substrates, or ceramic substrates, etc. Of course, in other embodiments, the first temporary substrate may also be a substrate of a different material from the second temporary substrate.

[0086] It should be understood that although the steps in the flowchart of Figure 1 are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in Figure 1 may include multiple steps or multiple stages, which are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps.

[0087] To more clearly illustrate the chip packaging methods in the above embodiments, please refer to the following embodiments. Figures 1 to 16 I understand.

[0088] In one embodiment, see Figure 1 The method for preparing the semiconductor packaging structure provided in this application may include steps S10 to S80.

[0089] In some embodiments, please refer to Figure 2 In step S10, the first temporary substrate 10 provided can be a glass substrate. The size and thickness of the first temporary substrate 10 can be set according to actual needs, and are not specifically limited here.

[0090] In some embodiments, the release film 11 formed on one side surface of the first temporary substrate 10 can be an adhesive film layer to facilitate the fixation and adhesion of the first temporary substrate 10, micropads, conductive pillars, and molding compound. In one example, the adhesion force between the release film 11 and the first temporary substrate 10 can be greater than the adhesion force between the release film 11 and the molding compound, micropads, and conductive pillars, so that the first temporary substrate 10 can be removed by peeling or other means. In another example, the adhesion force between the release film 11 and the first temporary substrate 10 can be less than the adhesion force between the release film 11 and the molding compound, micropads, and conductive pillars. In this case, the release film 11 can remain on the surface of the molding compound after the first temporary substrate 10 is removed, and then the release film 11 can be removed by a separate removal process. This avoids the micropads or conductive pillars from shifting due to large external forces when removing the first temporary substrate 10.

[0091] In some embodiments, please refer to Figure 3 The conductive pillar 12 and the micro pad 13 can both be made of metal materials. For example, the conductive pillar 12 can be a copper pillar, and the micro pad 13 can be a copper pad, etc.

[0092] In some embodiments, the number of conductive posts 12 can be multiple, and the multiple conductive posts 12 can be arranged at intervals.

[0093] In some embodiments, please refer to Figure 4 The first chip 14 provided in step S20 may include an electronic chip, and a first chip pad 141 is formed on the front side of the first chip 14. There may be multiple first chip pads 141 on the front side of the first chip 14, and the multiple first chip pads 141 may be arranged at intervals on the front side of the first chip 14. The first chip pads 141 are used to electrically bring out the structures inside the first chip 14 that need to be electrically led out.

[0094] In some embodiments, the first chip pad 141 of the first chip 14 can be bonded to the micro pad 13 by the first solder point 15. The number of the first solder points 15, the number of the first chip pads 141, and the number of the micro pads 13 can all be multiple, and the number of the three can be the same. The first solder points 15, the first chip pads 141, and the micro pads 13 can be set in a one-to-one correspondence.

[0095] The first chip 14 is bonded to the side of the first temporary substrate 10 with conductive pillars 12 based on the first solder joint 15 using a flip-chip process. It has self-calibration capability during reflow and has low precision requirements.

[0096] In some embodiments, the material of the first chip pad 141 may be the same as the material of the micro pad 13; the material of the first solder joint 15 may include, but is not limited to, tin.

[0097] In some embodiments, the conductive post 12 may be located outside the first chip 14 and have a gap from the first chip 14; specifically, the conductive post 12 may be located on both sides of the first chip 14, on one side of the first chip 14, or around the first chip 14.

[0098] In some embodiments, please refer to Figure 5 and Figure 6 In step S30, the molding layer 16 can be formed using, but is not limited to, compression molding or transfer molding. The material of the molding layer 16 may include epoxy resin, polyimide resin, benzocyclobutene resin, or polybenzoxazole resin, with or without fillers; or it may include polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyimide, ethylene-vinyl acetate copolymer, or polyvinyl alcohol, with or without fillers. In some examples, the filler may include inorganic or organic fillers.

[0099] In some embodiments, the top surface of the formed molding layer 16 (the surface of the molding layer 16 away from the first temporary substrate 10) may be higher than the back surface of the first chip 14 and the top surface of the conductive pillar 12 (the surface of the conductive pillar 12 away from the first temporary substrate 10), such as... Figure 5 As shown.

[0100] In some embodiments, after forming the molding compound 16, a thinning process may be performed on the molding compound 16 so that the surface of the molding compound 16 away from the first temporary substrate 10, the back side of the first chip 14, and the surface of the conductive pillar 12 away from the first temporary substrate 10 are all flush. Figure 6As shown. It should be noted that, after flip-chip bonding, the back surface of the first chip 14 can be flush with the surface of the conductive post 12 away from the first temporary substrate 10, or there can be a height difference between the back surface of the first chip 14 and the surface of the conductive post 12 away from the first temporary substrate 10. If there is a height difference between the back surface of the first chip 14 and the surface of the conductive post 12 away from the first temporary substrate 10, in this step, when thinning the molding compound 16, the higher of the two, the first chip 14 and the conductive post 12, is also thinned, so that after the thinning process, the surface of the molding compound 16 away from the first temporary substrate 10, the back surface of the first chip 14, and the surface of the conductive post 12 away from the first temporary substrate 10 are all flush. In this step, provided that the surface of the molding layer 16 away from the first temporary substrate 10, the back side of the first chip 14, and the surface of the conductive pillar 12 away from the first temporary substrate 10 are all flush, the back side of the first chip 14 can be thinned. Since the back side of the first chip 14 can be thinned here, the first chip 14 does not need to be processed and ground to an extremely thin thickness before packaging, which can reduce the risk of the first chip 14 cracking during processing.

[0101] In some embodiments, after step S30, the process may further include: forming a cover dielectric layer 17 on the side of the molding layer 16 away from the first temporary substrate 10 using, but not limited to, an adhesive coating process; forming a first interconnect plug 171 within the cover dielectric layer 17, the first interconnect plug 171 being electrically connected to the conductive post 12, such as... Figure 7 As shown. Specifically, the covering dielectric layer 17 may include, but is not limited to, a polyimide layer, etc. Specifically, forming a first interconnect plug 171 within the covering dielectric layer 17 may include the following: forming a first interconnect hole within the covering dielectric layer 17 using photolithography and etching processes, the first interconnect hole exposing the conductive pillar 12; forming the first interconnect plug 171 within the first interconnect hole using, but not limited to, electroplating processes. The material of the first interconnect plug 171 may be the same as the material of the conductive pillar 12.

[0102] As an example, such as Figure 7 The resulting structure may include an effective region A1 and an ineffective region B1; the micro pad 13, the first chip 14 and the first chip pad 141 are all located within the effective region A1, the separation membrane 11, the molding layer 16 and the covering dielectric layer 17 are all located within the effective region A1 and within the ineffective region B1; the conductive pillar 12, the first interconnect plug 171 and the bump structure 18 are partly located within the effective region A1 and partly located within the ineffective region B1.

[0103] In some embodiments, the bump structure (C4, Controlled Collapse ChipConnection) 18 formed in step S40 may include metal bumps, or the bump structure 18 may include metal bumps and solder caps located on the top surface of the metal bumps, such as... Figure 7 As shown. In some examples, the material of the metal bump may include tin or a tin alloy, including one or more of tin silver, tin zinc, tin lead, tin indium, tin gold, tin copper, tin silver copper, tin silver zinc, tin bismuth indium, tin zinc indium, or tin silver antimony; the material of the metal bump may include metals, specifically one or more of aluminum, copper, nickel, tin, titanium, tungsten, platinum, chromium, tantalum, gold, and silver; the material of the solder cap may include tin or a tin alloy, including one or more of tin silver, tin zinc, tin lead, tin indium, tin gold, tin copper, tin silver copper, tin silver zinc, tin bismuth indium, tin zinc indium, or tin silver antimony.

[0104] In some embodiments, in step S501, the bonding layer 19 may be formed using, but is not limited to, physical vapor deposition, chemical vapor deposition, or atomic layer deposition processes. The bonding layer 19 may include, but is not limited to, a bonding adhesive layer formed using processes such as coating. The thickness of the bonding layer 19 is greater than the height of the bump structure 18 to ensure that the bump structure 18 does not protrude from the side of the bonding layer 19 away from the first temporary substrate 10, facilitating the bonding of the second temporary substrate 20.

[0105] In some embodiments, in step S502, the second temporary substrate 20 may be bonded to the surface of the bonding layer 19 away from the first temporary substrate 10 using bonding processes such as thermoforming bonding, but not limited to thermoforming bonding. Figure 8 As shown. Specifically, both the bonding layer 19 and the second temporary substrate 20 extend from the effective region A1 into the ineffective region B1.

[0106] In some embodiments, in step S60, the separation film 11 can be destroyed or removed using processes such as laser or high temperature to simultaneously remove the first temporary substrate 10; of course, in other examples, the first temporary substrate 10 can be removed first, such as... Figure 9 As shown, the separation film 11 is then removed. Specifically, the first temporary substrate 10 can be removed by, but is not limited to, grinding or etching processes.

[0107] In some embodiments, after removing the separation film 11 and the first temporary substrate 10 in step S60, the process may further include thinning the molding compound 16 and the conductive pillars 12, and removing the micropads 13 and the first solder joints 15, resulting in the structure shown below. Figure 10As shown. Specifically, the molding compound 16 and the conductive pillar 12 can be thinned using a grinding process (e.g., chemical mechanical polishing). During the thinning process of the molding compound 16 and the conductive pillar 12, the micro pads 13 and the first solder joint 15 are removed.

[0108] In some embodiments, please refer to Figure 11 The redistribution layer 21 formed in step S70 can be a structure comprising multiple dielectric layers 211 and multiple metal wiring layers 212. The dielectric layer 211 can be made of polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO), or other suitable polymer-based dielectric materials. The metal wiring layer 212 can be made of one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, W, and WN. It should be noted that adjacent metal wiring layers 212 in the redistribution layer 21 are electrically connected via a second interconnect plug 213. A pad structure similar to a micropad is formed on the surface of the redistribution layer 21 away from the first temporary substrate 10 to achieve electrical connection between the redistribution layer and other structures. Specifically, the redistribution layer 21 extends from the effective region A1 to the ineffective region B1.

[0109] In some embodiments, please refer to Figure 12 The preset blade can be used to make multiple cuts in the invalid region B1, including the redistribution layer 21, encapsulation layer 16, cover dielectric layer 17, and bonding layer 19, to form a groove 22. The groove 22 penetrates the redistribution layer 21, encapsulation layer 16, and cover dielectric layer 17 along the thickness direction and extends into the bonding layer 19. It should be noted that when cutting adjacent sides, the blade width of the preset blade can partially overlap.

[0110] In some embodiments, please refer to Figure 13 In step S80, a second chip pad 231 is formed on the front side of the mounted second chip 23. The second chip pad 231 of the second chip 23 can be electrically connected to the redistribution layer 21 via the second solder joint 24. The material of the second chip pad 231 can be the same as the material of the first chip pad 141, and the material of the second solder joint 24 can be the same as the material of the first solder joint 15.

[0111] The optical port area of ​​the photonic chip (i.e., the second chip 23) is projected onto the surface of the second temporary substrate 20, and the groove 22 is projected onto the surface of the second temporary substrate 20. The groove 22 serves as a clearance space for the optical port area of ​​the subsequently formed second chip, ensuring that the normal operation of the optical port area of ​​the second chip is not affected. Specifically, the optical port area may include, but is not limited to, the area where the optical device is located in the second chip 23, the area for optical fiber connection and fixation, the processing area reserved for subsequent optical packaging processes, etc.

[0112] In some embodiments, please refer to Figure 14 The underfill (UF) layer 25 can be formed using processes such as dispensing, but not limited to these. The material of the underfill layer 25 may include, but is not limited to, resin.

[0113] In some embodiments, step S902, removing the second temporary substrate 20 to expose the bump structure 18, may include: attaching the structure obtained after forming the bottom fill layer 25 to the surface of the scribe film 26, such as... Figure 15 As shown; the second temporary substrate 20 is removed, exposing the bump structure 18, as... Figure 16 As shown; the structure obtained after removing the second temporary substrate 20 is peeled off from the dicing film 26.

[0114] In another embodiment, please refer to Figures 1 to 15 Continue reading Figure 16 This application also provides a packaging structure, which can adopt the following semiconductor packaging structure: Figures 1 to 16 The semiconductor packaging structure described herein is prepared by the method for preparing the semiconductor packaging structure.

[0115] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0116] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0117] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor packaging structure, characterized in that, include: A first temporary substrate is provided, and a conductive pillar is formed on one side of the first temporary substrate; A first chip is provided, and the first chip is flip-chip bonded to one side of the first temporary substrate on which the conductive pillars are formed; A molding layer is formed on one side of the first temporary substrate, the molding layer molding the first chip and the conductive pillar, and exposing the end face of the conductive pillar away from the first temporary substrate; A bump structure is formed on the side of the molding layer away from the first temporary substrate, and the bump structure is electrically connected to the conductive pillar; A second temporary substrate is formed on the side of the bump structure away from the molding layer; Remove the first temporary substrate to expose the first chip pad on the front side of the first chip and the end face of the conductive pillar away from the bump structure; A redistribution layer is formed on the side of the molding layer away from the bump structure, and the redistribution layer is electrically connected to the first chip pad and the conductive pillar; A second chip is mounted on the side of the redistribution layer away from the molding compound, and the second chip pad of the second chip is electrically connected to the redistribution layer.

2. The method for fabricating a semiconductor packaging structure according to claim 1, characterized in that, While forming a conductive pillar on one side of the first temporary substrate, a micro pad is also formed on one side of the first temporary substrate, and the micro pad and the conductive pillar are located on the same side of the first temporary substrate.

3. The method for preparing a semiconductor packaging structure according to claim 2, characterized in that, Flip-bonding the first chip to the side of the first temporary substrate where the conductive pillars are formed includes: bonding the first chip pad of the first chip to the side of the micro pad away from the first temporary substrate via a first solder joint. A separation film is formed on one side surface of the first temporary substrate, and the micro pads and the conductive pillars are formed on the surface of the separation film away from the first temporary substrate; Removing the first temporary substrate to expose the first chip pads and the end faces of the conductive pillars away from the bump structure on the front side of the first chip includes: removing the separation film and the first temporary substrate; thinning the molding compound and the conductive pillars; and removing the micro pads and the first solder joints to expose the first chip pads.

4. The method for preparing a semiconductor packaging structure according to claim 1, characterized in that, Before forming the bump structure on the side of the molding layer away from the first temporary substrate, the method further includes: A covering dielectric layer is formed on the side of the molding layer away from the first temporary substrate; A first interconnect plug is formed within the covering medium layer, and the first interconnect plug is electrically connected to the conductive post; the bump structure is formed on the surface of the covering medium layer away from the molding layer, and is electrically connected to the first interconnect plug.

5. The method for fabricating a semiconductor packaging structure according to claim 1, characterized in that, A second temporary substrate is formed on the side of the bump structure away from the molding layer, comprising: A bonding layer is formed, which covers the bump structure; The second temporary substrate is bonded to the surface of the bonding layer away from the bump structure.

6. The method for fabricating a semiconductor packaging structure according to claim 1, characterized in that, After mounting the second chip on the side of the redistribution layer away from the molding compound, the method further includes: A bottom fill layer is formed, which fills the gap between the second chip and the redistribution layer; Remove the second temporary substrate to expose the bump structure.

7. The method for fabricating a semiconductor packaging structure according to claim 6, characterized in that, Removing the second temporary substrate to expose the bump structure includes: The structure obtained after forming the bottom filler layer is attached to the surface of the scribe film; Remove the second temporary substrate to expose the bump structure; The structure obtained after removing the second temporary substrate is peeled off from the dicing film.

8. The method for preparing a semiconductor packaging structure according to claim 1, characterized in that, Both the first temporary substrate and the second temporary substrate comprise a glass substrate.

9. The method for preparing a semiconductor packaging structure according to any one of claims 1 to 8, characterized in that, The first chip includes an electronic chip, and the second chip includes a photonic chip; after forming a redistribution layer on the side of the encapsulation layer away from the bump structure, and before mounting the second chip on the side of the redistribution layer away from the encapsulation layer, the method further includes: removing at least a portion of the redistribution layer and a portion of the encapsulation layer to form a groove; the orthographic projection of the optical port area of ​​the photonic chip on the surface of the second temporary substrate is located within the orthographic projection of the groove on the surface of the second temporary substrate.

10. A semiconductor packaging structure, characterized in that, The semiconductor packaging structure is prepared by the semiconductor packaging structure preparation method as described in any one of claims 1 to 9.

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