A digital power control method
Patent Information
- Application Number
- CN201218007972.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2012-12-26
- Publication Date
- 2015-01-21
- Estimated Expiration
- 2032-12-26
AI Technical Summary
但该方法一是无法独立控制模拟器各个通道内的信号功率,二是控制精度不高,往往只有1dB的控制精度,无法达到0.1dB的精度甚至更高的精度
[0022] (1) The method is simple and no longer requires an external analog power control chip and an external analog attenuator, thus reducing the production cost of the simulator.
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Figure CN122664136B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a simple, high-precision digital power control method, which is applied to the precise control of signal power generated by a high-dynamic satellite constellation simulator. Background Technology
[0002] Currently, there are no publicly available international documents on methods for precise control of signal power in satellite constellation simulators. Domestically, the common approach is to use analog chips soldered onto circuit boards or external analog attenuators for power control. However, this method has two limitations: firstly, it cannot independently control the signal power within each channel of the simulator; secondly, the control precision is low, often only 1dB, failing to achieve 0.1dB or higher precision. When the simulator simulates the carrier's flight and attitude changes, it cannot simulate the actual satellite signal power, thus hindering effective testing and verification of receiver performance. Summary of the Invention
[0003] The technical problem solved by this invention is to overcome the shortcomings of the prior art and provide a brand-new method for generating digital signal power, which enables the simulator to independently control the signal power in each channel, thereby realistically simulating the power situation of the signal in space and improving the power control accuracy by one or even several orders of magnitude.
[0004] The technical solution of the present invention is: a digital power control method, comprising the following steps:
[0005] (1) Determine the power control coefficient bit width as PA by adjusting the quantization level bit width OUT of the digital signal as needed;
[0006] (2) Calculate the power control coefficient A p The power control coefficient A p The calculation formula is as follows:
[0007] x dB For the power value that needs to be adjusted, A p The range is (0~(2 PA-1 -1));
[0008] (3) A p The signal is quantized into a binary number, with the number of bits being PA. The quantized binary number is then used as the final power control coefficient and multiplied by the digital signal whose power needs to be adjusted to achieve power control.
[0009] In step (2), the power control coefficient A p The calculation formula is implemented as follows:
[0010] Step a: Establish the formula
[0011]
[0012] Among them, A s The amplitude of the digital signal whose power needs to be adjusted, where A s The full value of the quantization level OUT (2) OUT-1 -1),
[0013] Step b: Expand formula (1) to obtain
[0014] 20((PA-1)log2-log A p )=x dB (2)
[0015] Rearranging formula (2), we get log A p value
[0016]
[0017] Step c: Rearrange formula (3) to obtain
[0018]
[0019] The relationship between the power control coefficient bit width PA and the quantization level bit width OUT of the digital signal whose power needs to be adjusted is: PA-OUT≥2.
[0020] When the number of bits in the binary number resulting from multiplying the power control coefficient in step (3) with the digital signal whose power needs to be adjusted is higher than the number of bits in the digital signal that the system can output, truncation processing is required. That is, according to the marking from the highest bit to the lowest bit, the corresponding number of bits are truncated and output starting from the second highest bit.
[0021] The advantages of this invention compared to the prior art are:
[0022] (1) The method is simple and no longer requires an external analog power control chip and an external analog attenuator, thus reducing the production cost of the simulator.
[0023] (2) It adopts digital control technology, which can independently control the signal power of each channel in the simulator.
[0024] (3) The power accuracy is controllable and can theoretically reach any accuracy, which is far superior to the traditional 1dB control accuracy. Attached Figure Description
[0025] Figure 1 This is a flowchart of the power control method of the present invention;
[0026] Figure 2 This is a schematic diagram illustrating the implementation of the power control method of the present invention. Detailed Implementation
[0027] like Figure 1 As shown, this invention relates to a digital power control method, comprising the following steps:
[0028] (1) The power control coefficient is determined by adjusting the quantization level OUT of the digital signal to the required power, with the highest bit of OUT being the sign bit and the highest bit of PA being the sign bit. In practice, PA-OUT ≥ 2 is generally required, mainly considering the sign bit.
[0029] (2) Calculate the power control coefficient A p The power control coefficient A p The calculation formula is as follows: x dB The power value that needs to be adjusted is, in other words, the decibel level that needs to be reduced. A p The range is (0~(2 PA-1 -1));
[0030] The derivation of this formula is as follows:
[0031] Step a: Establish the formula
[0032]
[0033] Among them, A s The amplitude of the digital signal whose power needs to be adjusted, where A s The full value of the quantization level OUT (2) OUT-1 -1),
[0034] Step b: Expand formula (1) to obtain
[0035] 20((PA-1)log2-logA p )=x dB (2)
[0036] Rearranging formula (2), we get logA p value
[0037]
[0038] Step c: Rearrange formula (3) to obtain
[0039]
[0040] (3) A pThe data is quantized into a binary number, with the number of bits (PA) as the final power control coefficient. This quantized binary number is then multiplied by the digital signal whose power needs adjustment to achieve power control. In practical calculations, the number of bits in the resulting binary number may exceed the number of bits the system can output. In this case, truncation is required. This involves extracting the appropriate number of bits from the second-highest bit position, based on the markings from the most significant bit to the least significant bit, for output. Figure 2 As shown.
[0041] The present invention will be further described below with reference to embodiments:
[0042] (1) The digital signal is 16 bits, i.e., OUT = 16, and the power x that needs to be adjusted is... dB The value is 30dB. The digital signal output after power adjustment is 16 bits, so the number of bits PA of the power control coefficient needs to be greater than the number of bits OUT of the digital signal. Here it is set to 18 bits, that is, PA = 18 (in actual selection, PA ≥ 18 is sufficient).
[0043] (2) According to the formula Calculate A p ,get
[0044] A was obtained by sorting. p =4144.8605747358981580375897465552
[0045] (3) A p The quantization is done to an 18-bit binary number, that is, 4145 is quantized into the binary number 000001000000110001. The resulting binary number is 34 bits. Since the system can only output a 16-bit digital signal, 16 bits are then extracted from the second most significant bit to the least significant bit as the final output signal A. s If A' is marked as [33:0] from the most significant bit to the least significant bit, then the 16-bit number [32:17] is extracted as the final output. s With A p If the resulting binary number can meet the requirements for the number of bits in the digital signal output by the system, then no truncation is required.
[0046] For example: when the amplitude A of a digital signal with adjustable power needs to be adjusted. s =32767, when A p When it is 4145 (decimal), after A s With A p After multiplication and truncation, A s =1036 (according to the formula) Get x dB=30, which meets the power control requirements.
[0047] This embodiment utilizes a multiplication logic circuit built on an FPGA to perform the multiplication operation between the digital signal requiring power adjustment and the power control coefficient. The power control coefficient is then calculated and input on a DSP according to a formula, ultimately achieving precise control of the digital signal power.
[0048] The contents not described in detail in this specification are common knowledge to those skilled in the art.
Claims
1. A digital power control method, characterized in that... Includes the following steps: (1) Determine the power control coefficient bit width as PA by adjusting the quantization level bit width OUT of the digital signal as needed; (2) Calculate the power control coefficient A p The power control coefficient A p The calculation formula is as follows: x dB For the power value that needs to be adjusted, A p The range is (0~(2 Pa-1 -1)); (3) A p The signal is quantized into a binary number, with the number of bits being PA. The quantized binary number is then used as the final power control coefficient and multiplied by the digital signal whose power needs to be adjusted to achieve power control.
2. The digital power control method according to claim 1, characterized in that, In step (2), the power control coefficient A p The calculation formula is implemented as follows: Step a: Establish the formula Among them, A s The amplitude of the digital signal whose power needs to be adjusted is represented by the full value of the quantization level bits OUT, i.e., A. s =2 OUT-1 -1, Step b: Expand formula (1) to obtain 20((PA-1)log2-logA p )=x dB (2) Rearranging formula (2), we get logA p value Step c: Rearrange formula (3) to obtain 3. The digital power control method according to claim 1, characterized in that, The relationship between the power control coefficient bit width PA and the quantization level bit width OUT of the digital signal whose power needs to be adjusted is: PA-OUT≥2.
4. The digital power control method according to claim 1, characterized in that, When the number of bits in the binary number resulting from multiplying the power control coefficient in step (3) with the digital signal whose power needs to be adjusted is higher than the number of bits in the digital signal that the system can output, truncation processing is required. That is, according to the marking from the highest bit to the lowest bit, the corresponding number of bits are truncated and output starting from the second highest bit.