Circuit, chip and electronic equipment for ESD (Electro-Static Discharge) device
By connecting the current limiting resistor between the parasitic transistor emitter of the ESD device and the external power supply, the chip area and cost increase caused by the increase in the parasitic transistor spacing of the ESD device is solved, and the effect of reducing the risk of parasitic transistor opening and chip cost is achieved.
Patent Information
- Application Number
- CN202421247723.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-31
- Publication Date
- 2025-03-07
- Estimated Expiration
- 2034-05-31
AI Technical Summary
In the prior art, the increase in the spacing of parasitic transistors of ESD devices leads to an increase in chip area, cost, and the risk of parasitic transistor opening increases.
By connecting the current limiting resistor between the emitter of the parasitic transistor of the ESD device and the external power supply, the current of the collector is reduced, thereby reducing the spacing of the parasitic transistor, reducing the risk of opening, and reducing the chip area.
It realizes the reduction of the spacing and opening risks of parasitic transistors of ESD devices, reduces chip costs, and saves chip area.
Smart Images
Figure CN222582063U_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of electronic technology, and in particular, relates to a circuit, a chip and an electronic device for an ESD device. Background Art
[0002] In the related art, the method for solving the risk of electrostatic discharge (ESD) devices parasitic transistors such as NPN transistors is generally to increase the distance between the two N-type semiconductors in the parasitic NPN, where the parasitic transistor is related to voltage. The greater the voltage connected to the N-type semiconductor at one end of the parasitic NPN transistor, the greater the distance between the two N-type semiconductors. If a chip has many pins (PINs) with high voltage voltage, and there will be many parasitic NPN transistors in the circuit at the same time, then the distance between these parasitic NPN transistors will increase the chip area on the layout and increase the cost of the chip. Utility Model Content
[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a circuit, a chip and an electronic device for an ESD device, which reduces the current of the collector by connecting a current limiting resistor between the emitter of the parasitic transistor of the ESD device and an external power supply, thereby reducing the spacing between the parasitic transistors of the ESD device and reducing the risk of the parasitic transistors being turned on. At the same time, the chip area can be reduced to achieve the purpose of reducing chip costs.
[0004] In a first aspect, the present application provides a circuit for an ESD device, the circuit comprising:
[0005] ESD devices, parasitic transistors, current limiting resistors and external power supplies;
[0006] The collector of the parasitic transistor is connected to the base of the ESD device and the emitter of the ESD device, the base of the parasitic transistor is connected to the collector of the ESD device, the emitter of the parasitic transistor is connected to the external power supply, and the current limiting resistor is arranged between the emitter of the parasitic transistor and the external power supply.
[0007] According to the circuit for ESD devices of the present application, a current limiting resistor is connected between the emitter of the parasitic transistor of the ESD device and an external power supply to reduce the current of the collector, thereby reducing the spacing between the parasitic transistors of the ESD device and reducing the risk of turning on the parasitic transistors. At the same time, the chip area can be reduced, thereby achieving the purpose of reducing chip costs.
[0008] According to an embodiment of the present application, the parasitic transistor is an NPN transistor.
[0009] According to the circuit for ESD devices of the present application, by connecting a current limiting resistor between one of the N-type semiconductors in the ESD parasitic NPN and an external power supply, the current of the N-type semiconductor at one end is reduced, and the distance between the two N-type semiconductors in the parasitic NPN is reduced, the risk of the parasitic NPN of the ESD device being turned on can be reduced, the chip area can be reduced, and the chip cost can be reduced.
[0010] According to an embodiment of the present application, the ESD device is a PNP transistor.
[0011] According to an embodiment of the present application, the base of the ESD device and the emitter of the ESD device are connected and serve as an external I / O interface, and the collector of the ESD device is grounded.
[0012] According to an embodiment of the present application, the input voltage of the external I / O interface is any one of 6V to 24V, 29V, 36V and 45V.
[0013] According to an embodiment of the present application, the resistance value of the current limiting resistor is determined according to the input voltage of the external I / O interface.
[0014] According to an embodiment of the present application, when the input voltage of the external I / O interface is 36V, the resistance of the current limiting resistor is 300 ohms.
[0015] According to one embodiment of the present application, the parasitic transistor is formed by an electron collecting guard ring and the ESD device; the electron collecting guard ring is used to absorb carriers injected into the substrate through the external I / O interface.
[0016] In a second aspect, the present application provides a chip, comprising: a circuit for an ESD device as described in the first aspect above.
[0017] In a third aspect, the present application provides an electronic device comprising the chip as described in the second aspect.
[0018] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:
[0020] Figure 1 It is one of the structural schematic diagrams of the circuit for ESD device provided in the embodiment of the present application;
[0021] Figure 2It is one of the structural schematic diagrams of the ESD device provided in the embodiment of the present application;
[0022] Figure 3 is a cross-sectional view of an ESD device provided in an embodiment of the present application;
[0023] Figure 4 This is one of the structural schematic diagrams of the amplified parasitic NPN transistor provided in the embodiment of the present application;
[0024] Figure 5 This is the second structural schematic diagram of the ESD device provided in the embodiment of the present application;
[0025] Figure 6 This is the second structural schematic diagram of the amplified parasitic NPN transistor provided in the embodiment of the present application;
[0026] Figure 7 It is one of the simulation result schematic diagrams provided in the embodiment of the present application;
[0027] Figure 8 This is the second schematic diagram of the simulation results provided in the embodiment of the present application;
[0028] Fig. 9 It is a schematic diagram of the area calculation of the chip provided in the embodiment of the present application;
[0029] Fig.10 is a schematic diagram of the structure of the chip provided in the embodiment of the present application;
[0030] Fig.11 It is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application.
[0031] Reference numerals: 10, circuit for ESD device; 110, ESD device; 120, parasitic transistor; 130, external power supply; 20, chip; 30, electronic device; R: current limiting resistor. DETAILED DESCRIPTION
[0032] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.
[0033] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.
[0034] The circuit, chip and electronic device for ESD device provided in the embodiment of the present application are described in detail below with reference to the accompanying drawings through specific embodiments and their application scenarios.
[0035] like Figure 1 As shown, the circuit 10 for an ESD device includes: an ESD device 110 , a parasitic transistor 120 , a current limiting resistor R and an external power source 130 .
[0036] The collector of the parasitic transistor 120 is connected to the base of the ESD device 110 and the emitter of the ESD device 110, the base of the parasitic transistor 120 is connected to the collector of the ESD device 110, the emitter of the parasitic transistor 120 is connected to the external power supply 130, and the current limiting resistor R is arranged between the emitter of the parasitic transistor 120 and the external power supply 130.
[0037] It is understandable that the ESD device 110 uses a high-voltage ESD circuit in a BCD process.
[0038] BCD process, namely Bipolar-CMOS-DMOS process, is a technology that integrates three different types of semiconductor devices, namely bipolar transistors (Bipolar), complementary metal oxide semiconductors (CMOS) and double-diffused metal oxide semiconductors (DMOS), into the same chip. The main advantage of BCD process is that it integrates the advantages of these three devices, and has the characteristics of high efficiency (low energy consumption), high strength (no secondary breakdown), high withstand voltage and high-speed switching. It can not only reduce power consumption and improve system performance, but also increase reliability and reduce costs.
[0039] The collector of the parasitic transistor 120 (NPN transistor) is connected to the base of the ESD device 110, and the base of the ESD device 110 is connected to the emitter of the ESD device 110, so the collector of the parasitic transistor 120 (NPN transistor) is also connected to the emitter of the ESD device 110; the base of the parasitic transistor 120 (NPN transistor) is connected to the collector of the ESD device 110; the emitter of the parasitic transistor 120 (NPN transistor) is connected to the external power supply 130 (pad VCC PAD); the current limiting resistor R is set between the emitter of the parasitic transistor 120 (NPN transistor) and the external power supply 130.
[0040] In a chip designed using the BCD process, using the circuit for an ESD device provided in the embodiment of the present application not only reduces the parasitic NPN risk of the ESD device and improves chip reliability, but also saves chip area and reduces chip cost.
[0041] According to the circuit for ESD devices provided in the embodiments of the present application, a current limiting resistor is connected between the emitter of the parasitic transistor of the ESD device and an external power supply to reduce the current of the collector, thereby reducing the spacing between the parasitic transistors of the ESD device and reducing the risk of turning on the parasitic transistors. At the same time, the chip area can be reduced, thereby achieving the purpose of reducing chip costs.
[0042] In some embodiments, the ESD device 110 is a PNP transistor.
[0043] It is understandable that the ESD device 110 of the present application adopts a high-voltage ESD circuit in the BCD process, and the high-voltage ESD circuit in the BCD process is generally composed of a PNP transistor connected to a pad and a ground (substrate), such as Figure 2 shown.
[0044] See also Figure 3 ,for Figure 2 The corresponding cross-sectional view of the ESD device 110. The emitter P (E) and the base N (B) are connected to the pad (I / O PIN PAD), the I / O PIN PAD is the negative terminal (cathode), the pad is the position connected to the chip pin, and a pin contains at least one or more pads, and the collector P (C) is connected to the ground (GND), and GND is the positive terminal (anode).
[0045] In some embodiments, the parasitic transistor 120 is an NPN transistor.
[0046] It can be understood that the parasitic transistor 120 in the embodiment of the present application is an NPN transistor.
[0047] Among them, the connection of the parasitic NPN transistor is as follows Figure 4shown.
[0048] In some embodiments, the parasitic transistor 120 is formed by an electron collecting guard ring and the ESD device 110; the electron collecting guard ring is used to absorb carriers injected into the substrate through the external I / O interface.
[0049] In the embodiment of the present application, the Human-Body Model (HBM) model is used as an example, and the working principle of the ESD device PNP is as follows: when the pad (I / O PIN PAD) is positively charged to the ground (GND) by 2KV, the PN junction composed of the base (B) and the collector (C) breaks down first, and the breakdown current reduces the potential of the DNW near the E pole. When the potential of E (P) is higher than the potential of DNW, the EB junction is turned on and snapback occurs, discharging the positive electricity to the ground (GND). When the pad (I / O PIN PAD) is -2KV to the ground, the base B and the collector C form a forward-conducting diode PN junction (diode), discharging the negative electricity to the ground (GND).
[0050] Since the pad (I / O PIN PAD) may have transients, when the I / O PIN PAD is pulled to a negative potential, the pad (I / O PIN PAD) will inject electrons into the substrate, some of which are collected by the electric field of the active circuit, causing noise or latch problems in the chip's internal circuit. In order to prevent ESD devices from causing noise or latch problems in the chip's internal circuit, it is necessary to add an additional electron collection protection ring to all ESD devices, as shown in the following example. Figure 5 As shown, the electron collection protection ring is generally connected to the highest stable voltage potential of the chip (i.e., the external power supply 130, the pad VCC PAD), and the pad (i.e., I / OPIN PAD) can be sucked away by the electron collection protection ring. Figure 5 The carriers injected into the substrate by the IO PAD in the circuit can reduce the interference and latch-up problems of the internal circuit. However, the addition of the electron collection guard ring will cause the ESD device to parasitic NPN, such as Figure 5 The parasitic NPN transistor in the dotted box, here DNW (Deep N-WELL, deep N well) and NBL (N-type Buried Layer, N-type buried layer) are both N-type wells, the process manufacturing is just different in depth and concentration, N+ is N injection and DNW, NBL are both N-type, here it is said that N+ to DNW to NBL are connected, representing the N of the parasitic ESD, P+, P-EPI and P+Substrate are all P-type, representing the P in the parasitic NPN of the ESD device, so the N in the parasitic PNP of the ESD device, the substrate P and the N of the electron collection guard ring form a parasitic NPN as shown Figure 6When I / O PAD is negatively charged, P is grounded to 0V, and I / O PAD (N) and P are used as the emitter junction of NPN. At this time, the emitter junction will be forward biased. The external power supply VCCPAD (N) is generally connected to a stable high-voltage power supply and P is used as the collector junction of NPN. At this time, the collector is reverse biased, which meets the conditions for NPN amplification. Then there is a path between I / O PAD and the external power supply (pad VCC PAD). If the distance between the N-type semiconductor and the N-type semiconductor in the parasitic NPN transistor (such as Figure 5 The spacing S) is not enough, the NPN semiconductor is enlarged, the electron collection protection ring is not enough to withstand the large current, local heat will occur, and breakdown will occur over time, and the chip will burn out.
[0051] See also Figure 5 , the distance S between the two N-type semiconductors in the parasitic NPN transistor is related to the voltage of Vce (the voltage difference between the pad VCC PAD and the pad I / OPAD). The reason is that the opening conditions of the NPN transistor are the same. When the Vbe voltage (the voltage difference between the collector and the emitter) is greater than or equal to 0.7v, and Vbc is reverse biased, the NPN transistor will start the amplification function, and there is a current path between the collector and the emitter. At this time, the higher the Vce, the greater the leakage. At the same time, the power consumption generated by the leakage is equal to the leakage current multiplied by Vce. Therefore, the larger the Vce, the greater the leakage power consumption, which will eventually lead to excessive power consumption, severe local heating, and damage. Therefore, if the Vce voltage is large, then S should be increased accordingly. Since the amplification factor β value of the NPN transistor is related to S, the larger the S, the smaller the amplification factor β value of the NPN transistor. Therefore, the amplification factor β of the NPN transistor can be reduced by increasing the distance S and the width of the base region P(B). When the NPN is turned on, Ic=β*Ib, thereby reducing the leakage current. Ic is the collector current of the parasitic NPN transistor, and Ib is the base current of the parasitic NPN transistor.
[0052] In some embodiments, the base of the ESD device 110 and the emitter of the ESD device 110 are connected and serve as an external I / O interface, and the collector of the ESD device 110 is grounded.
[0053] It is understandable that, in the embodiment of the present application, the base of the ESD device 110 and the emitter of the ESD device 110 are short-circuited together and connected to the pad IO PAD. The collector of the ESD device 110 is grounded.
[0054] In some embodiments, the input voltage of the external I / O interface is any one of 6V to 24V, 29V, 36V and 45V.
[0055] In some embodiments, the resistance of the current limiting resistor is determined according to an input voltage of the external I / O interface.
[0056] In actual implementation, the resistance value of the current limiting resistor is related to the input voltage of the external I / O interface. Therefore, the resistance value of the current limiting resistor can be determined according to the input voltage of the external I / O interface to reduce the collector current, thereby reducing the spacing between the parasitic transistors of the ESD device and reducing the risk of the parasitic transistors turning on. In general, the resistance value of the current limiting resistor is positively correlated with the input voltage of the external I / O interface. The greater the input voltage of the external I / O interface, the greater the resistance value of the current limiting resistor.
[0057] In some embodiments, the resistance of the current limiting resistor is 300 ohms.
[0058] It can be understood that in the general process rule, the spacing S between the two N-type semiconductors of the parasitic NPN transistor is different for different Vce voltage ranges. In the BCD process, Vce is generally defined as low voltage when it is less than or equal to 5V, and high voltage when it is greater than or equal to 6V. Figure 1 The distance S between the two N-type semiconductors of the parasitic NPN transistor in the dotted box is related to the Vce voltage (because the input voltage of the external power supply VCC PAD is fixed), so it can be discussed in the following cases:
[0059] When the voltage of the pad I / O PAD is 6V-24V, the distance S between the N-type semiconductors of the NPN transistor is 30um;
[0060] When the voltage of the pad I / O PAD is 29V, the distance S between the N-type semiconductors of the NPN transistor is 50um;
[0061] When the voltage of the pad I / O PAD is 36V, the distance S between the N-type semiconductors of the NPN transistor is 56um;
[0062] When the voltage of the pad I / O PAD is 45V, the distance S between the N-type semiconductors of the NPN transistor is 60um.
[0063] If the circuit for ESD device proposed in the embodiment of the present application is adopted, a current limiting resistor R is connected between one of the N-type semiconductors (electron collection protection ring) in the parasitic NPN transistor of the ESD device and the external power supply. Figure 1As shown, the resistance of the current limiting resistor R is about 300 ohms, so the current Ic=β*Ib of the electron collection protection ring will be reduced, because the current limiting resistor can play a role in current limiting, so Ib will be reduced, the current will be reduced, and the power consumption will naturally be reduced, so as to reduce the distance between the N-type semiconductor and the N-type semiconductor in the parasitic NPN transistor of the ESD device, and the distance can be reduced to about 50%. When the pad I / OPAD is positively charged to VCC PAD by 2KV, the VCC pad PAD is floating at this time, and the VCC voltage is 0V.
[0064] The connection of the parasitic NPN transistor is as follows Figure 4 As shown, P is the substrate end (the voltage of the substrate is also 0V when one side is grounded), and N (connected to pad I / O PAD) is positively charged to VCC (+2KV). At this time, there are many holes near the pad I / O PAD, so the substrate close to the pad I / O PAD will absorb holes, causing the voltage of the substrate to be easily raised to 0.7V, and the emitter formed by P (substrate) and N (electron collection guard ring) is forward biased, and P (substrate) and N (pad I / O PAD) are reverse biased, which meets the conditions of NPN amplification. Therefore, there is a leakage path directly between pad IO PAD and VCC PAD, and the current size is: Ic=β*Ib. When the current limiting resistor R with a size of 300 ohms is first connected to N (electron collection guard ring), the other end of the current limiting resistor R is connected to pad VCC PAD, due to the current limiting effect of the current limiting resistor, Ib will decrease, and Ic=β*Ib will decrease accordingly. When the voltage difference Vce remains unchanged, because the power consumption P generated by leakage is equal to the leakage current multiplied by Vce (that is, P=Ic*Vce), the power consumption P will also decrease. At this time, the power consumption P will not damage the chip. Under the same power consumption and the same voltage difference Vce, since the power consumption P=Ic*Vce=β*Ib*Vce, the other end of the current limiting resistor is connected to the pad VCC PAD. Due to the current limiting effect of the current limiting resistor, Ib decreases, then β can increase. Generally, the β value is inversely proportional to the width of the base region (that is, the spacing between the N-type semiconductor and the N-type semiconductor).
[0065] like Figure 7, the electron collection protection ring is not connected to the current limiting resistor R, and is directly connected to the VCC PAD current simulation data. When the voltage connected to the pad I / O PAD is 36V, the spacing between the base region (the N-type semiconductor and the N-type semiconductor in the NPN transistor) is 56um. At this time, the simulation shows that Ic=60MA, Ib=35MA, Ie=Ic+Ib=95MA, I(NBL_ISO)=330MA, I(SUB)=235MA, Ie is the parasitic NPN transistor emitter current, I(NBL_ISO) is the current of the electron collection protection ring, and I(SUB) is the ground current, which meets Ie=I(NBL_ISO)-I(SUB)=95MA. At this time, the parasitic NPN transistor is amplified, and there is a path between N(c) and N(e). The amplification factor β=Ic / Ib=1.86, which is very small and will not burn the chip because the chip static discharge time is very short.
[0066] After many simulation experiments, the following conclusions and data were obtained: Figure 8 As shown, when the electron collection protection ring is connected to a 300 ohm resistor and the voltage connected to the pad I / O PAD is 36V, the spacing S between the base region (the N-type semiconductor and the N-type semiconductor of the parasitic NPN transistor) is 28um. At this time, the simulation shows that Ic=2MA, Ib=2MA, I(NBL_ISO)=896uA, I(SUB)=850uA, which meets Ie=I(NBL_ISO)-I(SUB)=46uA. Ie is not equal to the sum of Ib and Ic. At this time, the NPN is cut off and there is no leakage path between N(c) and N(e).
[0067] The two simulation data show that when the voltage of the pad I / O PAD is 36V, the electron collection protection ring is directly connected to VCCPAD and the electron collection protection ring is connected to a 300 ohm resistor, the spacing between the base region (the N-type semiconductor and the N-type semiconductor of the parasitic NPN transistor) changes from 56um to 28um, so the electron collection protection ring is connected to a 300 ohm resistor, which can reduce the spacing of the parasitic NPN transistor to 50%. Figure 1 The distance S between the N-type semiconductor and the N-type semiconductor in the parasitic NPN Figure 1 The distance S1 between the electron collection guard ring NBL and the I / O PAD NBL is shown in Table 1:
[0068] Table 1
[0069]
[0070] in Figure 4 yes Figure 1The enlarged view of the parasitic NPN transistor in the dotted box, for example, a chip with high-voltage pins supports a maximum operating voltage input and output of 24V. If this chip design may require about 40 high-voltage 24VPINs, then these 40 24V ESD discharge tubes (usually 24V PNP) all meet the 24V requirement. Fig. 9 A (NBL) is the NBL area of the 24V PNP discharge tube, B is the electron collection protection ring (N) of the PNP discharge tube, and the parasitic B (N2) P (GND) A (NBL) has a spacing S = 30um. The circuit for ESD devices proposed in the embodiment of the present application is adopted: by connecting a current limiting resistor to one of the N (electron collection protection ring) of the parasitic NPN transistor of the ESD device, the current limiting resistor is about 300 ohms, reducing the current of the electron collection protection ring, thereby reducing the spacing between the two N-type semiconductors of the parasitic NPN of the ESD device, then the spacing S = 15um. Fig. 9 As shown, the area of A(NBL) is: X*Y. If X=100um, Y=200um, then Fig. 9 The area in the dotted box in the middle right half of the figure is saved by: 160*260-130*230=11700um compared to the area in the dotted box in the left half of the figure 2 This is the area that can be reduced by a 24V PNP bleeder. This chip has 40 similar 24V PNP bleeders, so the overall area reduction of the chip is: 40*11700=468000um 2 .
[0071] Similar I / O devices or high-voltage devices serving as switching power can also use the circuit for ESD devices proposed in the embodiments of the present application to save chip area accordingly.
[0072] According to the circuit for ESD devices provided in the embodiments of the present application, by connecting a current limiting resistor between one of the N-type semiconductors in the ESD parasitic NPN and an external power supply, the current of the N-type semiconductor at one end is reduced, and the distance between the two N-type semiconductors in the parasitic NPN is reduced, the risk of the parasitic NPN of the ESD device being turned on can be reduced, the chip area can be reduced, and the chip cost can be reduced.
[0073] The embodiment of the present application also provides a chip 20.
[0074] like Fig.10 As shown, the chip 20 includes the circuit 10 for ESD devices of the above embodiment, and can achieve the same effect. To avoid repetition, it will not be described again.
[0075] An embodiment of the present application also provides an electronic device.
[0076] like Fig.11 As shown, the electronic device 30 includes the chip 20 mentioned above.
[0077] The electronic device 30 may be a terminal or other device other than a terminal. Exemplarily, the electronic device may be a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted electronic device, a mobile Internet device (MID), an augmented reality (AR) / virtual reality (VR) device, a robot, a wearable device, an ultra-mobile personal computer (UMPC), a netbook or a personal digital assistant (PDA), etc. It may also be a server, a network attached storage (NAS), a personal computer (PC), a television (TV), a teller machine or a self-service machine, etc., which is not specifically limited in the embodiments of the present application.
[0078] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.
[0079] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.
[0080] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.
Claims
1. A circuit for an ESD device, characterized in that, include: ESD devices, parasitic transistors, current limiting resistors and external power supplies; The collector of the parasitic transistor is connected to the base of the ESD device and the emitter of the ESD device, the base of the parasitic transistor is connected to the collector of the ESD device, the emitter of the parasitic transistor is connected to the external power supply, and the current limiting resistor is arranged between the emitter of the parasitic transistor and the external power supply.
2. The circuit for an ESD device according to claim 1, characterized in that: The parasitic transistor is an NPN transistor.
3. The circuit for an ESD device according to claim 1, characterized in that: The ESD device is a PNP transistor.
4. The circuit for an ESD device according to claim 3, characterized in that: The base of the ESD device and the emitter of the ESD device are connected and serve as an external I / O interface, and the collector of the ESD device is grounded.
5. The circuit for an ESD device according to claim 4, characterized in that: The input voltage of the external I / O interface is any one of 6V to 24V, 29V, 36V and 45V.
6. The circuit for an ESD device according to claim 5, characterized in that: The resistance value of the current limiting resistor is determined according to the input voltage of the external I / O interface.
7. The circuit for an ESD device according to claim 6, characterized in that: When the input voltage of the external I / O interface is 36V, the resistance of the current limiting resistor is 300 ohms.
8. The circuit for an ESD device according to any one of claims 4 to 7, characterized in that: The parasitic triode is formed by an electron collecting guard ring and the ESD device; the electron collecting guard ring is used to absorb carriers injected into the substrate through the external I / O interface.
9. A chip, characterized in that: A circuit for an ESD device comprising the circuit as claimed in any one of claims 1 to 8.
10. An electronic device, characterized in that: Comprising the chip as claimed in claim 9.