Metal oxide semiconductor field effect transistor cell structure, transistor and circuit structure

Abstract

The utility model relates to a metal oxide semiconductor field effect transistor cell structure, a transistor and a circuit structure. The metal oxide semiconductor field effect transistor cell structure comprises a first metal layer, a substrate layer, an epitaxial layer, a gate structure, a Schottky barrier layer and a second metal layer, the epitaxial layer comprises a first conductive type drift region, a second conductive type well region, an enhancement region and a JFET region, and the second conductive type well region, the enhancement region and the JFET region are all located on the side, away from the substrate layer, of the first conductive type drift region; the JFET region further comprises a plurality of second conductive type enhancement regions, and the second conductive type enhancement regions and the second conductive type well regions are arranged at intervals in the first direction so as to form a depletion region when a reverse electric field is applied. According to the technical scheme of the invention, the leakage current of the Schottky barrier diode is reduced, and the switching speed and switching loss of the metal oxide semiconductor field effect transistor are improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a metal oxide semiconductor field effect transistor cell structure, a transistor and a circuit structure. Background Art

[0002] Compared with similar Si devices, silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) have the characteristics of high turn-off voltage, low on-resistance, high switching frequency, high efficiency and good high-temperature performance. Currently, its research and productization process is in a rapid development period. SiC MOSFETs are being fully promoted in industries such as automotive electronics, train traction, photovoltaics, and motors.

[0003] In order not to increase the extra design cost, the body diode of the metal oxide semiconductor field effect transistor is generally used as the freewheeling diode. However, its own body diode has serious bipolar degradation phenomenon, high turn-on voltage and large reverse recovery current. On the one hand, this will cause system oscillation and cause system instability. On the other hand, it will inevitably increase the loss of the system.

[0004] In the related art, in order to solve the above problems, a Schottky barrier diode is usually integrated into a metal oxide semiconductor field effect transistor, and the role of a freewheeling diode is realized by taking advantage of the low turn-on voltage, short reverse recovery time, and no reverse recovery current of the Schottky barrier diode (SBD). However, the Schottky barrier of the Schottky barrier diode will drop under high reverse bias, which will lead to a large reverse leakage current, which will also bring serious turn-off loss. At the same time, the integration of the Schottky barrier diode often requires additional chip area, resulting in a larger chip area. Utility Model Content

[0005] In order to solve the above technical problems or at least partially solve the above technical problems, the present disclosure provides a metal oxide semiconductor field effect transistor cell structure and a transistor, which reduce the leakage current of the Schottky barrier diode and improve the switching speed and switching loss of the metal oxide semiconductor field effect transistor.

[0006] In a first aspect, the present disclosure provides a metal oxide semiconductor field effect transistor cell structure, comprising: a first metal layer, a substrate layer, an epitaxial layer, a gate structure, a Schottky barrier layer, and a second metal layer;

[0007] The epitaxial layer is located on one side of the substrate layer, the second metal layer is located on a side of the substrate layer away from the epitaxial layer, the first metal layer is located on a side of the epitaxial layer away from the substrate layer, the gate structure and the Schottky barrier layer are located between the epitaxial layer and the first metal layer, and the gate structure and the Schottky barrier layer are arranged along a first direction;

[0008] The epitaxial layer comprises a first conductive type drift region, a second conductive type well region, an enhancement region and a JFET region, wherein the second conductive type well region, the enhancement region and the JFET region are all located on a side of the first conductive type drift region away from the substrate layer, and the Schottky barrier layer is located on a side of the JFET region away from the substrate layer;

[0009] The JFET region further includes a plurality of second conductivity type enhancement regions, and the second conductivity type enhancement regions and the second conductivity type well regions are arranged at intervals along the first direction to form a depletion region when a reverse electric field is applied.

[0010] Optionally, along a second direction, the second conductivity type enhancement regions are arranged at intervals; wherein the second direction is perpendicular to the first direction.

[0011] Optionally, along the second direction, intervals between adjacent second conductivity type enhancement regions are equal.

[0012] Optionally, a surface of the second conductive type enhancement region facing away from the substrate layer is spaced apart from a surface of the Schottky barrier layer close to the substrate layer.

[0013] Optionally, along the third direction, the depth of the second conductive type enhancement region is less than or equal to the depth of the second conductive type well region;

[0014] The third direction is a direction perpendicular to the plane where the first direction is located.

[0015] Optionally, the enhancement region includes a second conductivity type enhancement source region type base region and a first conductivity type enhancement source region;

[0016] Along the first direction, the second conductivity type enhanced source region type base region is located on a side of the first conductivity type enhanced source region away from the JFET region.

[0017] Optionally, the gate structure includes a gate oxide layer and a gate electrode. Along the direction of the epitaxial layer away from the substrate layer, the gate oxide layer covers the second conductivity type well region, at least part of the enhancement region and at least part of the JFET region, and the gate electrode is provided on a layer of the gate oxide layer away from the substrate layer.

[0018] In a second aspect, the present disclosure further provides a metal oxide semiconductor field effect transistor, comprising the metal oxide semiconductor field effect transistor cell structure as described in the first aspect.

[0019] Optionally, the metal oxide semiconductor field effect transistor is in a strip shape, a quadrilateral shape or a hexagon shape.

[0020] In a third aspect, the present disclosure further provides a circuit structure, comprising the metal oxide semiconductor field effect transistor as described in the second aspect.

[0021] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages:

[0022] The metal oxide semiconductor field effect transistor cell structure provided by the present invention includes: a first metal layer, a substrate layer, an epitaxial layer, a gate structure, a Schottky barrier layer and a second metal layer; the epitaxial layer is located on one side of the substrate layer, the second metal layer is located on the side of the substrate layer away from the epitaxial layer, the first metal layer is located on the side of the epitaxial layer away from the substrate layer, the gate structure and the Schottky barrier layer are located between the epitaxial layer and the first metal layer, and the gate structure and the Schottky barrier layer are arranged along a first direction; the epitaxial layer includes a first conductive type drift region, a second conductive type well region, an enhancement region and a JFET region, and the second conductive type well region, the enhancement region and the JFET region are all located on the side of the first conductive type drift region away from the substrate layer; the JFET region also includes a second conductive type enhancement region, and the second conductive type enhancement region and the second conductive type well region are arranged at intervals along the first direction to form a depletion region when a reverse electric field is applied. Therefore, the present disclosure uses the Schottky diode structure introduced by setting the Schottky barrier layer to effectively improve the problems of excessive forward turn-on voltage drop and long reverse recovery time of the parasitic body diode of the metal oxide semiconductor field effect transistor, thereby meeting the circuit design requirements in actual use, reducing the circuit design cost, and avoiding the problems of reduced system reliability and increased capacitance and switching loss caused by a single integrated device. And by setting the second conductive type enhancement region and the second conductive type well region at intervals, when applying a reverse electric field, the second conductive type enhancement region, the second conductive type well region and the drift region covered by the JFET region will form a depletion region, and the reverse electric field is shielded by the depletion region to avoid the reverse electric field from being applied to the Schottky barrier layer, thereby reducing the leakage current of the Schottky barrier diode, improving the switching speed of the metal oxide semiconductor field effect transistor, and reducing the switching loss of the metal oxide semiconductor field effect transistor. In this way, the problems of excessive forward turn-on voltage and long reverse recovery time can be effectively improved without increasing the cell size of the metal oxide semiconductor field effect transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0025] Figure 1 A schematic diagram of a three-dimensional structure of a metal oxide semiconductor field effect transistor cell structure provided by an embodiment of the present disclosure;

[0026] Figure 2 A schematic diagram of a process for preparing a metal oxide semiconductor field effect transistor cell structure provided in an embodiment of the present disclosure;

[0027] Figure 3-Figure 8 for Figure 2 The cross-sectional three-dimensional structure schematic diagram of each step in a method for preparing a metal oxide semiconductor field effect transistor cell structure is shown.

[0028] Among them, the correspondence between the figure marks and the structure names is: 1. First metal layer; 2. Substrate layer; 3. Epitaxial layer; 4. Gate structure; 5. Schottky barrier layer; 6. Second metal layer; 31. First conductivity type drift region; 32. Second conductivity type well region; 33. Enhancement region; 34. JFET region; 35. Second conductivity type enhancement region; 331. Second conductivity type enhancement source region type base region; 332. First conductivity type enhancement source region; 41. Gate oxide layer; 42. Gate electrode; 43. Isolation medium. DETAILED DESCRIPTION

[0029] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0030] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0031] When SiC-type MOSFETs are used in inductive load circuits, a freewheeling diode is usually required in parallel in the circuit. In most current applications, in order not to increase additional design costs, the body diode of the MOSFET itself is generally used as a freewheeling diode. However, the body diode of the SiC-type MOSFET itself has serious bipolar degradation, a high turn-on voltage, and a large reverse recovery current. On the one hand, this will cause system oscillation and instability, and on the other hand, it will inevitably increase system losses. Therefore, solving the problem of dynamic switching losses, especially the dynamic power consumption of the device due to reverse recovery charge during reverse recovery, has become one of the key points in the design of SiC-type MOSFET devices.

[0032] Because of the above problems, attempts are made to integrate a diode inside the silicon carbide metal oxide semiconductor field effect transistor to achieve this function, which not only avoids the problem of the parasitic body diode, but also does not require a freewheeling diode to be separately connected in parallel outside the device. Since the Schottky barrier diode has a low turn-on voltage, a very short reverse recovery time, and no reverse recovery current, an integrated Schottky barrier diode is usually chosen to achieve the role of a freewheeling diode. However, the Schottky barrier diode has a more serious problem, that is, the drop of the Schottky barrier under high reverse bias will cause a large reverse leakage current, which will also cause serious turn-off losses. At the same time, the integration of the Schottky barrier diode often requires additional chip area, resulting in a larger chip area.

[0033] Figure 1 A schematic diagram of a three-dimensional structure of a metal oxide semiconductor field effect transistor cell structure provided by an embodiment of the present disclosure. Figure 1 As shown, the metal oxide semiconductor field effect transistor cell structure includes: a first metal layer 1, a substrate layer 2, an epitaxial layer 3, a gate structure 4, a Schottky barrier layer 5 and a second metal layer 6; the epitaxial layer 3 is located on one side of the substrate layer 2, the second metal layer 6 is located on the side of the substrate layer 2 away from the epitaxial layer 3, the first metal layer 1 is located on the side of the epitaxial layer 3 away from the substrate layer 2, the gate structure 4 and the Schottky barrier layer 5 are located between the epitaxial layer 3 and the first metal layer 1, and the gate structure 4 and the Schottky barrier layer 5 are arranged along a first direction X; the epitaxial layer 3 includes a first A conductive type drift region 31, a second conductive type well region 32, an enhancement region 33 and a JFET region 34, wherein the second conductive type well region 32, the enhancement region 33 and the JFET region 34 are all located on the side of the first conductive type drift region 31 away from the substrate layer 2, and the Schottky barrier layer 5 is located on the side of the JFET region 34 away from the substrate layer 2; the JFET region 34 also includes a second conductive type enhancement region 35, and the second conductive type enhancement region 35 and the second conductive type well region 32 are arranged at intervals along the first direction X to form a depletion region when a reverse electric field is applied.

[0034] It should be noted that, one of the first metal layer 1 and the second metal layer 6 is a source metal layer, and the other is a drain metal layer. Specifically, in the metal oxide semiconductor field effect transistor cell structure described in the embodiment of the present disclosure, the first metal layer 1 is the source metal layer, and the second metal layer 6 is the drain metal layer. Similarly, the first conductivity type and the second conductivity type described below, one is P-type and the other is N-type, the two can be interchangeable, and cannot be understood as a limitation on the doping type of a certain structure. For the sake of ease of description, in this application, unless otherwise specified, the first conductivity type is N-type and the second conductivity type is P-type as an example, and a detailed description is given in combination with the embodiment of the present disclosure.

[0035] For clarity, Figure 1 The figure shows a half cell structure in the metal oxide semiconductor field effect transistor cell structure, that is, a cell structure includes Figure 1 The two half-cell structures are mirror-symmetrical.

[0036] Specifically, Figure 1 As shown, for example, a heavily doped single-crystal silicon carbide wafer of the first conductivity type with a certain thickness can be selected as the N-type substrate layer 2 of the chip, and an epitaxial layer 3 is formed on the substrate layer 2. When the metal oxide semiconductor field effect transistor is turned on, the current flows through the epitaxial layer 3. The epitaxial layer 3 can be doped with the first conductivity type particles. According to the chip withstand voltage requirements, the thickness of the epitaxial layer 3 provided in the embodiment of the present disclosure is, for example, 5 to 100 μm, and the doping concentration is, for example, 5E14 to 2E16 cm -3 It should be noted that the epitaxial layer 3 of other thicknesses and doping concentrations may also be selected as long as they meet the use requirements, and the embodiments of the present disclosure are not limited thereto.

[0037] The metal oxide semiconductor field effect transistor cell structure also includes a first metal layer 1 and a second metal layer 6. The specific materials of the first metal layer 1 and the second metal layer 6 can be selected from the source and drain metals commonly used in the art, for example, Ni, Al / Ti, Pt, Al, Ag and other metals or composite metals can be selected. The gate structure 4 is located between the epitaxial layer 3 and the first metal layer 1. The gate structure 4 can include, for example, a gate oxide layer 41 and a gate electrode 42 stacked and arranged in sequence along the epitaxial layer 3 away from the substrate layer 2. An isolation medium 43 is also provided between the gate electrode 42 and the first metal layer 1. The isolation medium 43 is used to isolate the gate electrode 42 and the first metal layer 1 to avoid short circuit. It should be noted that other methods can also be used to isolate the gate electrode 42 and the first metal layer 1 to avoid short circuit, and the embodiments of the present disclosure are not limited to this.

[0038] Silicon carbide doping types are divided into P-type and N-type, + is heavily doped (high doping concentration), - is lightly doped (low doping concentration), P-type is doped with IIIA group elements, such as boron, aluminum, gallium, indium, and thallium. N-type is doped with VA group elements, such as nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), and magnesium (Mc). In the subsequent embodiments of this disclosure, + represents high doping concentration and - represents low doping concentration.

[0039] A first conductive type drift region 31, a second conductive type well region 32, an enhancement region 33 and a JFET (Junction Field-Effect Transistor) region are formed in the epitaxial layer 3 by multiple ion implantations. The first conductive type drift region 31 may be, for example, an N-drift region. When the metal oxide semiconductor field effect transistor is turned on, the current between the first metal layer 1 and the second metal layer 6 mainly passes through the first conductive type drift region 31. The structure and characteristics of the first conductive type drift region 31 may directly affect the current control capability of the metal oxide semiconductor field effect transistor.

[0040] Multiple ion implantations are performed in the epitaxial layer 3 to form a second conductive type well region 32, an enhancement region 33, and a JFET region 34. The order of formation is not limited in the embodiment of the present disclosure, and the process requirements can be met. In the metal oxide semiconductor field effect transistor cell structure, the JFET region 34 is located between adjacent second conductive type well regions 32. For the convenience of illustration, Figure 1 The JFET region 34 is not specifically shown. The JFET region 34 is two highly doped P regions made on the same N-type semiconductor. The specific working principle is well known to those skilled in the art and will not be described in detail in the embodiment of the present disclosure.

[0041] Figure 1 exemplarily shows that the surface of the enhancement region 33 facing away from the substrate layer 2, the surface of the second conductive type well region 32 facing away from the substrate layer 2 not covered by the enhancement region 33, and the surface of the JFET region 34 facing away from the substrate layer 2 are all in contact with the gate structure 4. Along the first direction X, the enhancement region 33 is located on the side of the second conductive type well region 32 facing away from the JFET region 34, and is located on the inner surface of the side of the second conductive type well region 32 facing away from the first conductive type drift region 31, and the surfaces of the enhancement region 33, the second conductive type well region 32, and the JFET region 34 facing away from the first conductive type drift region 31 are flush.

[0042] The Schottky barrier layer 5 is located on the side of the epitaxial layer 3 away from the substrate layer 2 and is arranged along the first direction X with the gate structure 4, and is located on the side of the JFET region 34 away from the substrate layer 2. The Schottky barrier layer 5 serves as the anode of the Schottky barrier diode. The Schottky barrier layer 5 includes, for example, a Schottky metal, which is set to a metal or alloy with low contact resistivity, preferably titanium, aluminum, nickel, or an alloy synthesized by any components of titanium, aluminum, and nickel. The surface of the enhancement region 33 away from the substrate layer 2, the surface of the gate structure 4 away from the substrate layer 2, and the surface of the Schottky barrier layer 5 away from the substrate layer 2 are all arranged in contact with the first metal layer 1.

[0043] The Schottky diode is a metal-semiconductor device made by using the Schottky barrier layer 5 including Schottky metal as the anode and the N-type semiconductor as the cathode, and utilizing the barrier formed on the contact surface of the two to have the rectifying property. Because there are a large number of electrons in the N-type semiconductor and only a very small number of free electrons in the precious metal, the electrons diffuse from the semiconductor with high concentration to the metal with low concentration. Therefore, without affecting the performance of the metal oxide semiconductor field effect transistor, the introduction of the Schottky diode effectively improves the problems of excessive forward turn-on voltage drop and long reverse recovery time of the parasitic body diode of the metal oxide semiconductor field effect transistor, thereby meeting the circuit design requirements in actual use, reducing the circuit design cost, and avoiding the problems of reduced system reliability, increased capacitance and switching loss caused by separate integrated devices.

[0044] When a reverse electric field is applied to the metal oxide semiconductor field effect transistor, due to the characteristics of the Schottky barrier diode, when a high reverse bias is applied, the Schottky barrier drops, resulting in a large reverse leakage current, which also causes serious turn-off losses. In order to solve this problem, the embodiment of the present disclosure sets a second conductive type enhancement region 35, i.e., a P+ region, in the JFET region 34, and the second conductive type enhancement region 35 is spaced apart from the second conductive type well region 32. When a reverse electric field is applied to the metal oxide semiconductor field effect transistor, a depletion region is formed between the second conductive type enhancement region 35, the second conductive type well region 32, and the drift region covered by the JFET region 34. The depletion region is used to shield the reverse electric field, and the reverse electric field is prevented from being applied to the Schottky barrier layer 5, thereby reducing the leakage current of the Schottky barrier diode, improving the switching speed of the metal oxide semiconductor field effect transistor, and reducing the switching loss of the metal oxide semiconductor field effect transistor.

[0045] The embodiment of the present disclosure introduces a Schottky diode structure by setting a Schottky barrier layer 5, effectively improving the problems of excessive forward turn-on voltage drop and long reverse recovery time of the parasitic body diode of the metal oxide semiconductor field effect transistor, thereby meeting the circuit design requirements in actual use, reducing the circuit design cost, avoiding the problems of reduced system reliability and increased capacitance and switching loss caused by a single integrated device, and by setting the second conductive type enhancement region 35 and the second conductive type well region 32 at intervals, when a reverse electric field is applied, a depletion region is formed between the second conductive type enhancement region 35, the second conductive type well region 32 and the drift region covered by the JFET region 34, and the reverse electric field is shielded by the depletion region to prevent the reverse electric field from being applied to the Schottky barrier layer 5, thereby reducing the leakage current of the Schottky barrier diode, improving the switching speed of the metal oxide semiconductor field effect transistor, and reducing the switching loss of the metal oxide semiconductor field effect transistor. In this way, the problems of excessive forward turn-on voltage and long reverse recovery time can be effectively improved without increasing the cell size of the metal oxide semiconductor field effect transistor.

[0046] Alternatively, if Figure 1 As shown, the JFET region 34 includes second conductive type enhancement regions 35 arranged at intervals along a second direction Y; wherein the second direction Y is perpendicular to the first direction X.

[0047] Specifically, Figure 1 As shown, the JFET region 34 also includes second conductive type enhancement regions 35 arranged at intervals along the second direction Y. When the metal oxide semiconductor field effect transistor is turned on by applying an electric field, the current needs to flow through the first conductive type drift region 31 and the first conductive type drift region 31 covered by the JFET region 34. However, the second conductive type enhancement region 35 cannot conduct electricity, so the second conductive type enhancement region 35 can be arranged in the JFET region 34, and can be arranged at intervals along the first direction X and along the second direction Y, so as to avoid the problem that the second conductive type enhancement region 35 occupies too much area of ​​the JFET region 34, thereby affecting the conductive performance of the metal oxide semiconductor field effect transistor, and improving the conductivity of the metal oxide semiconductor field effect transistor.

[0048] Alternatively, if Figure 1 As shown, along the second direction Y, the intervals between adjacent second conductive type enhancement regions 35 are equal.

[0049] Specifically, Figure 1In the second direction, for example, the first second conductivity type enhancement region 35, the second second conductivity type enhancement region 35 and the third second conductivity type enhancement region 35 may be included, and the distance between the first second conductivity type enhancement region 35 and the second second conductivity type enhancement region 35 is equal to the distance between the second second conductivity type enhancement region 35 and the third second conductivity type enhancement region 35. Such an arrangement can simplify the process preparation of the second conductivity type enhancement region 35, and the second conductivity type enhancement region 35 is arranged uniformly, so as to improve the uniformity of the depletion region formed by the second conductivity type enhancement region 35 and the second conductivity type well region 32 when a reverse electric field is applied, and better shield the reverse electric field.

[0050] Alternatively, if Figure 1 As shown, the surface of the second conductive type enhancement region 35 facing away from the substrate layer 2 is spaced apart from the surface of the Schottky barrier layer 5 close to the substrate layer 2 .

[0051] Specifically, Figure 1 As shown, from the working principle of the Schottky barrier diode, it can be known that the Schottky barrier layer 5 needs to be in contact with N-type ions to form a Schottky barrier diode for use, and the second conductive type enhancement region 35 is doped with P-type ions, so it is necessary to arrange the surface of the second conductive type enhancement region 35 away from the substrate layer 2 and the surface of the Schottky barrier layer 5 close to the substrate layer 2 to be spaced apart. In addition, the surface of the second conductive type enhancement region 35 away from the substrate layer 2 and the surface of the Schottky barrier layer 5 close to the substrate layer 2 are spaced apart, which can also leave a current path for the metal oxide semiconductor field effect transistor, avoid affecting the conduction of the metal oxide semiconductor field effect transistor, and improve the reliability of the metal oxide semiconductor field effect transistor.

[0052] Alternatively, if Figure 1 As shown, along the third direction Z, the depth of the second conductive type enhancement region 35 is less than or equal to the depth of the second conductive type well region 32; wherein the third direction Z is a direction perpendicular to the plane where the first direction X is located.

[0053] Specifically, Figure 1 As shown, since the second conductive type enhancement region 35 needs to form a depletion region together with the second conductive type well region 32, the second conductive type enhancement region 35 alone or the second conductive type well region 32 alone cannot play a shielding role. Therefore, in order to reduce the manufacturing cost, it can be arranged in the third direction Z that the depth of the second conductive type enhancement region 35 is less than or equal to the depth of the second conductive type well region 32. Thus, while the second conductive type enhancement region 35 and the depth of the second conductive type well region 32 form a depletion region, the manufacturing cost is also reduced and material waste is avoided.

[0054] Alternatively, if Figure 1As shown, the enhancement region 33 includes a second conductivity type enhancement source region type base region 331 and a first conductivity type enhancement source region 332 ; along the first direction X, the second conductivity type enhancement source region type base region 331 is located on a side of the first conductivity type enhancement source region 332 away from the JFET region 34 .

[0055] Specifically, Figure 1 As shown, the enhancement region 33 may include, for example, a second conductivity type enhancement source region type base region 331, i.e., a P+ type source region type base region and a first conductivity type enhancement source region 332, i.e., an N+ type source region. In the first direction X, the first conductivity type enhancement source region 332 and the second conductivity type enhancement source region type base region 331 are adjacent to and in contact with each other, and the first conductivity type enhancement source region 332 is closer to the JFET region 34 than the second conductivity type enhancement source region type base region 331. The enhancement region 33 may be used to control the metal oxide semiconductor field effect transistor, and the specific working principle is well known to those skilled in the art and will not be elaborated herein.

[0056] Alternatively, if Figure 1 As shown, the gate structure 4 includes a gate oxide layer 41 and a gate electrode 42. Along the direction of the epitaxial layer 3 away from the substrate layer 1, the gate oxide layer 41 covers the second conductive type well region 32, at least part of the enhancement region 33 and at least part of the JFET region 34. The gate electrode 42 is provided on a layer of the gate oxide layer 41 away from the substrate layer 2.

[0057] Exemplarily, the gate oxide layer 41 starts from the enhancement region 33 and ends at the JFET region 34 . The gate electrode 42 may include conductive polysilicon or other materials as the gate electrode, which is not limited in the embodiments of the present disclosure.

[0058] A metal oxide semiconductor field effect transistor cell structure provided by the embodiment of the present disclosure introduces a Schottky diode structure by setting a Schottky barrier layer 5, effectively improving the problems of excessive forward turn-on voltage drop and long reverse recovery time of the parasitic body diode of the metal oxide semiconductor field effect transistor, thereby meeting the circuit design requirements in actual use, reducing the circuit design cost, and avoiding the problems of reduced system reliability and increased capacitance and switching loss caused by a single integrated device. And by setting the second conductive type enhancement region 35 and the second conductive type well region 32 at intervals, when a reverse electric field is applied, a depletion region will be formed between the second conductive type enhancement region 35, the second conductive type well region 32 and the drift region covered by the JFET region 34, and the reverse electric field is shielded by the depletion region to prevent the reverse electric field from being applied to the Schottky barrier layer 5, thereby reducing the leakage current of the Schottky barrier diode, improving the switching speed of the metal oxide semiconductor field effect transistor, and reducing the switching loss of the metal oxide semiconductor field effect transistor. In this way, the problems of excessive forward turn-on voltage and long reverse recovery time can be effectively improved without increasing the size of the metal oxide semiconductor field effect transistor cell.

[0059] The present disclosure also provides a metal oxide semiconductor field effect transistor, including the metal oxide semiconductor field effect transistor cell structure as described in the above embodiment. The metal oxide semiconductor field effect transistor includes at least one metal oxide semiconductor field effect transistor cell structure, so the metal oxide semiconductor field effect transistor has the beneficial effects of the metal oxide semiconductor field effect transistor cell structure, which will not be described in detail here.

[0060] Optionally, the metal oxide semiconductor field effect transistor may be, for example, in a strip shape, a quadrilateral shape, or a hexagon shape, which is not limited in the embodiments of the present disclosure.

[0061] The disclosed embodiment also provides a circuit structure, including the metal oxide semiconductor field effect transistor provided in the above embodiment. Therefore, the circuit structure has the beneficial effects of the metal oxide semiconductor field effect transistor, which will not be elaborated here.

[0062] The disclosed embodiment also provides a method for manufacturing a metal oxide semiconductor field effect transistor cell structure. Figure 2 A schematic diagram of a process for manufacturing a metal oxide semiconductor field effect transistor cell structure provided by an embodiment of the present disclosure is shown in FIG. Figure 2 As shown, including:

[0063] S101, forming an epitaxial layer on a substrate layer.

[0064] Specifically, Figure 3As shown, an epitaxial layer 3 is grown on a substrate layer 2. The substrate layer 2 is, for example, an N-type heavily doped single-crystal silicon carbide wafer. The doping concentration and thickness of the epitaxial layer 3 are adjusted and designed according to the device withstand voltage and on-resistance requirements. For example, the thickness of the epitaxial layer 3 is, for example, 5 to 100 μm.

[0065] S102 , forming a first conductivity type drift region, a second conductivity type well region, an enhancement region and a JFET region in the epitaxial layer.

[0066] Specifically, Figure 4 As shown, the epitaxial layer 3 can be doped with first conductive type ions, that is, N-type ions, to form a first conductive type drift region 31. According to the withstand voltage of the chip, the first conductive type ion doping concentration is, for example, 5E14-2E16cm -3 .

[0067] For example, a photolithography process and multiple ion implantation of second conductivity type impurity ions may be used to form the second conductivity type well region 32, and first conductivity type impurity ions and second conductivity type impurity ions may be implanted to form the enhancement region 33, and the concentration of the second conductivity type impurity ions in the enhancement region 33 is greater than the concentration of the second conductivity type impurity ions in the second conductivity type well region 32. The first conductivity type impurity ions are implanted into the epitaxial layer 3 to form the JFET region 34.

[0068] In some embodiments, ion implantation may be performed on the surface of the epitaxial layer 3 facing away from the substrate layer 2. For example, second conductivity type impurity ions may be first implanted on the surface of the epitaxial layer 3 facing away from the substrate layer 2 to form a second conductivity type well region 32, and then first conductivity type impurity ions and / or second conductivity type impurity ions may be implanted on the surface of the epitaxial layer 3 facing away from the substrate layer 2 to form an enhancement region 33. The enhancement region 33 is located on the side of the second conductivity type well region 32 facing away from the substrate layer 2.

[0069] S103 , forming a second conductivity type enhancement region in the JFET region, the enhancement region being spaced apart from the second conductivity type well region along the first direction.

[0070] Specifically, Figure 5 As shown, a photolithography process and multiple ion implantation of second conductivity type impurities, ie, P-type impurities, are performed on the side of the JFET region 34 away from the substrate layer 2 to form a second conductivity type enhancement region 35 spaced apart from the second conductivity type well region 32 along the first direction.

[0071] Optionally, forming a second conductive type enhancement region in the JFET region and arranged in a first direction with a second conductive type well region spaced apart from each other includes:

[0072] The JFET region is implanted with morphological ions in a grid shape to form a second conductivity type enhancement region.

[0073] Specifically, the second conductivity type enhancement region can be formed in the JFET region by injecting ions in a three-dimensional grid pattern. For example, aluminum ions can be injected, thereby enabling the second conductivity type enhancement regions to be arranged in intervals in the first direction and the second direction.

[0074] For example, the ion concentration of the second conductive type enhancement regions arranged at intervals is, for example, 1E17 cm -3 and 1E20cm -3 The distance between the surface of the second conductive type enhancement region on the side away from the substrate layer and the surface of the Schottky barrier layer on the side away from the substrate layer is, for example, 0.1-0.3 μm, and the depth of the implanted second conductive type enhancement region along the third direction is greater than or equal to 0.2 μm and less than or equal to the depth of the second conductive type well region.

[0075] S104 , forming a gate structure on a side of the epitaxial layer away from the substrate layer.

[0076] Specifically, for example, a whole layer of gate oxide layer 41 can be formed by oxidation process on the side of epitaxial layer 3 away from substrate layer 2, for example, 50nm SiO2 can be thermally oxidized at 1350°C as gate oxide layer 41. Polycrystalline silicon with a thickness of 500nm is deposited on the side of gate oxide layer 41 away from epitaxial layer 3 as gate electrode 42, and part of gate electrode 42 and gate oxide layer 41 are etched away by etching process to form a gate oxide layer 41 as shown in FIG. Figure 6 The gate structure 4 is shown. After the gate structure 4 is formed, a dielectric layer is deposited as a gate electrode 42 and an isolation dielectric 43 spaced from the first metal layer 1. The thickness of the isolation dielectric 43 is, for example, 1 μm, which may include 0.5 μm SiO2 and 0.5 μm BPSG (Boro-phospho-silicate Glass).

[0077] It should be noted that other types of materials may be used as the isolation medium as long as they can meet the use requirements of the isolation medium, and the embodiments of the present disclosure are not limited to this.

[0078] S105 , forming a Schottky barrier layer on a side of the epitaxial layer away from the substrate layer, wherein the Schottky barrier layer and the gate structure are arranged along a first direction.

[0079] Specifically, Figure 7As shown, for example, a Schottky metal can be formed on the side of the epitaxial layer 3 away from the substrate layer 2 as the Schottky barrier layer 5, and the Schottky metal is set to a metal or alloy with low contact resistivity, preferably titanium, aluminum, nickel, or an alloy synthesized by any components such as titanium, aluminum, and nickel. The Schottky barrier layer 5 and the gate structure 4 are arranged along the first direction, and the Schottky barrier layer 5 and the gate structure 4 are separated by an isolation dielectric 43.

[0080] S106, forming a first metal layer on a side of the epitaxial layer away from the substrate layer, and forming a second metal layer on a side of the substrate layer away from the epitaxial layer.

[0081] Specifically, Figure 8 As shown, a first metal layer 1, such as a source metal, is formed on the side of the epitaxial layer 3 away from the substrate layer 2 by a photolithography process. The substrate layer 2 is thinned to reach a target thickness of, for example, 100 to 200 μm, and a layer of metal is deposited on the side of the substrate layer 2 away from the epitaxial layer 3 as a second metal layer 6, such as a drain metal, to form a structure as shown in FIG. Figure 1 The metal oxide semiconductor field effect transistor cell structure is shown.

[0082] Optionally, forming an enhancement region on a side of the first conductive type drift region facing away from the substrate includes:

[0083] Ions are implanted into first conductivity type impurities to form a first conductivity type enhanced source region, and ions are implanted into second conductivity type impurities to form a second conductivity type enhanced source region type base region. The first conductivity type enhanced source region and the second conductivity type enhanced source region type base region constitute an enhanced region.

[0084] For example, reference may be made to Figure 4 For example, after ion implantation is performed along the surface of the epitaxial layer 3 away from the substrate layer 2 to form the second conductivity type well region 32, ion implantation is continued along the surface of the epitaxial layer 3 away from the substrate layer 2, for example, first conductivity type impurities are implanted to form a first conductivity type enhanced source region 332, that is, an N+ type source region. Ion implantation is continued along the surface of the epitaxial layer 3 away from the substrate layer 2, for example, second conductivity type impurities are implanted to form a second conductivity type enhanced source region type base region 331, that is, a P+ source region type base region. The first conductivity type enhanced source region 332 and the second conductivity type enhanced source region type base region 331 constitute an enhanced region.

[0085] It should be noted that the order of forming the first conductivity type enhanced source region 332 and the second conductivity type enhanced source region type base region 331 can be set according to the actual requirements of the process, and the embodiments of the present disclosure are not limited to this.

[0086] Optionally, before forming the Schottky barrier layer on the side of the epitaxial layer facing away from the substrate layer, the method includes:

[0087] An ohmic contact is formed on a surface of the epitaxial layer located in the enhancement region facing away from the substrate layer.

[0088] Specifically, please refer to Figure 6 and Figure 7 Before forming the Schottky barrier layer 5, a source metal hole is opened on the surface of the epitaxial layer 3 located in the enhancement region 33 away from the substrate layer 2 by a photolithography process, and nickel metal is deposited and annealed at 950°C to form an ohmic contact. When the semiconductor doping concentration is very high, when the semiconductor with a high doping concentration contacts the metal, a low barrier layer is formed, and electrons can pass through the barrier by the tunnel effect, thereby forming an ohmic contact with low resistance. For example, the N+ region and the source electrode form an ohmic contact. The characteristics of the ohmic contact are that the current-voltage characteristic of the contact surface is linear, and the contact resistance is negligible relative to the bulk resistance of the semiconductor. When a current passes through, the voltage drop generated is smaller than the voltage drop on the device.

[0089] Before forming the Schottky barrier layer 5 , a Schottky contact is opened on the surface of the epitaxial layer 3 in the JFET region 34 away from the substrate layer 2 by photolithography, and the Schottky contact metal is annealed at 400° C. to form the Schottky barrier layer 5 .

[0090] The present disclosure discloses a metal oxide semiconductor field effect transistor cell structure, which introduces a Schottky diode structure by setting a Schottky barrier layer, effectively improving the problems of excessive forward turn-on voltage drop and long reverse recovery time of the parasitic body diode of the metal oxide semiconductor field effect transistor, thereby meeting the circuit design requirements in actual use, reducing the circuit design cost, and avoiding the problems of reduced system reliability and increased capacitance and switching loss caused by a single integrated device. And by setting the second conductive type enhancement region and the second conductive type well region at intervals, when a reverse electric field is applied, a depletion region is formed in the drift region covered by the second conductive type enhancement region, the second conductive type well region and the JFET region, and the reverse electric field is shielded by the depletion region to avoid the reverse electric field being applied to the Schottky barrier layer, thereby reducing the leakage current of the Schottky barrier diode, improving the switching speed of the metal oxide semiconductor field effect transistor, and reducing the switching loss of the metal oxide semiconductor field effect transistor. In this way, the problems of excessive forward turn-on voltage and long reverse recovery time can be effectively improved without increasing the size of the metal oxide semiconductor field effect transistor cell. Furthermore, the manufacturing method does not require any additional process steps and can be realized by simply changing the mask shape of the corresponding layer, which is simple and feasible.

[0091] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0092] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A metal oxide semiconductor field effect transistor cell structure, characterized in that: include: A first metal layer, a substrate layer, an epitaxial layer, a gate structure, a Schottky barrier layer, and a second metal layer; The epitaxial layer is located on one side of the substrate layer, the second metal layer is located on a side of the substrate layer away from the epitaxial layer, the first metal layer is located on a side of the epitaxial layer away from the substrate layer, the gate structure and the Schottky barrier layer are located between the epitaxial layer and the first metal layer, and the gate structure and the Schottky barrier layer are arranged along a first direction; The epitaxial layer comprises a first conductive type drift region, a second conductive type well region, an enhancement region and a JFET region, wherein the second conductive type well region, the enhancement region and the JFET region are all located on a side of the first conductive type drift region away from the substrate layer, and the Schottky barrier layer is located on a side of the JFET region away from the substrate layer; The JFET region further includes a plurality of second conductivity type enhancement regions, and the second conductivity type enhancement regions and the second conductivity type well regions are arranged at intervals along the first direction to form a depletion region when a reverse electric field is applied.

2. The metal oxide semiconductor field effect transistor cell structure according to claim 1, characterized in that: Along a second direction, the second conductive type enhancement regions are arranged at intervals; wherein the second direction is perpendicular to the first direction.

3. The metal oxide semiconductor field effect transistor cell structure according to claim 2, characterized in that: Along the second direction, intervals between adjacent second conductivity type enhancement regions are equal.

4. The metal oxide semiconductor field effect transistor cell structure according to claim 1, characterized in that: A surface of the second conductive type enhancement region facing away from the substrate layer is spaced apart from a surface of the Schottky barrier layer close to the substrate layer.

5. The metal oxide semiconductor field effect transistor cell structure according to claim 1, characterized in that: Along the third direction, the depth of the second conductive type enhancement region is less than or equal to the depth of the second conductive type well region; The third direction is a direction perpendicular to the plane where the first direction is located.

6. The metal oxide semiconductor field effect transistor cell structure according to claim 1, characterized in that: The enhancement region includes a second conductivity type enhancement source region type base region and a first conductivity type enhancement source region; Along the first direction, the second conductivity type enhanced source region type base region is located on a side of the first conductivity type enhanced source region away from the JFET region.

7. The metal oxide semiconductor field effect transistor cell structure according to claim 1, characterized in that: The gate structure includes a gate oxide layer and a gate electrode. Along the direction of the epitaxial layer away from the substrate layer, the gate oxide layer covers the second conductivity type well region, at least part of the enhancement region and at least part of the JFET region. The gate electrode is provided on a layer of the gate oxide layer away from the substrate layer.

8. A metal oxide semiconductor field effect transistor, characterized in that: It comprises the metal oxide semiconductor field effect transistor cell structure as described in any one of claims 1 to 7.

9. The metal oxide semiconductor field effect transistor according to claim 8, characterized in that: The metal oxide semiconductor field effect transistor is in a stripe shape, a quadrilateral shape or a hexagon shape.

10. A circuit structure, characterized in that: Comprising the metal oxide semiconductor field effect transistor as described in any one of claims 8-9.

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