Semiconductor device

Abstract

Semiconductor device (100, 100C - 100I), comprising: - a MOS transistor (M1, Q1, Q2) which features: - a first semiconductor layer (1) of a first conductivity type, - a second semiconductor layer (2) of a first conductivity type, which is provided on a first main surface of the first semiconductor layer (1) and has a lower impurity concentration of a first conductivity type than that of the first semiconductor layer (1), - a first defect region (3a) of a second conductivity type, which is provided in an upper layer part of the second semiconductor layer (2), - a second defect area (4) of a first conductivity type, which is provided in an upper layer part of the first defect area (3a), - a gate electrode (5) which is provided such that it is opposite at least the first defect region (3a) and the second semiconductor layer (2) with an intermediate gate insulating film (OX), - a first main electrode (6, 61) which is at least partially connected to the second defect area (4) and is designed so that it is not in direct contact with the first defect area (3a), and - a second main electrode (7) connected to a second main surface of the first semiconductor layer (1) on a side opposite a side provided with the first main electrode (6, 61); - a parasitic transistor (PT) configured with the second impurity region (4) as emitter, the first semiconductor layer (1) and the second semiconductor layer (2) as collector and the first impurity region (3a) as base; - a parasitic diode (PD) configured with the first defect region (3a) as the anode and the first semiconductor layer (1) and the second semiconductor layer (2) as the cathode; and - a pn junction diode (PND) configured with the first defect region (3a) as the anode and the second defect region (4) as the cathode, wherein: - a ratio (Ic / le) of a collector current (Ic) to an emitter current (le) of the parasitic transistor (PT) is 1 / 1000 or less, and - a transition breakdown voltage of the pn junction diode (PND) is equal to or greater than a threshold (Vth) of a gate voltage for switching ON the MOS transistor (M1, Q1, Q2).

Description

BACKGROUND OF THE INVENTIONField of the invention

[0001] The present invention relates to a semiconductor device. Description of the background technology

[0002] For example, as a form of a power metal-oxide-semiconductor field-effect transistor (MOSFET), there is a vertical double-diffused MOSFET (VDMOS), which is used in Fig. 1 of D. Fuoss, “Vertical DMOS Power Field Effect Transistors Optimized For High-Speed ​​Operation,” IEDM Tech. Digest, p. 250, 1982. In a VDMOS, a p-type impurity region and an n-type impurity region are formed by means of double diffusion on an upper layer portion of an n-type epitaxial layer formed on a substrate having a relatively high concentration (n +) of n-type impurities. In addition, a gate electrode is provided so as to span the p-type impurity region and the n-type epitaxial layer with a gate oxide film interposed therebetween, a source electrode is connected to the n-type impurity region, and a drain electrode is provided on a main surface of the substrate opposite to a side provided with the source electrode.

[0003] In an inverter configured by connecting two power MOSFETs in series between PN lines, there is a case where a parasitic diode of the MOSFET is used as a freewheeling diode to cause operation under a forward bias voltage. An operation (synchronous rectification operation) to keep a gate in the ON state for a certain period is generally performed to suppress a forward bias voltage (Vf) generated in the diode and reduce power loss. To prevent a short circuit (power supply short circuit) between the PN lines, it is necessary to return the gate to the OFF state before and after this operation. Therefore, the operation under a forward bias of the parasitic diode takes place at a time before and after this operation.

[0004] When the parasitic diode is forward biased, hole injection occurs into the n-type epitaxial layer, and the injected holes may temporarily flow in reverse, causing energy loss when the parasitic diode returns to reverse bias.

[0005] Furthermore, in SiC semiconductor devices made of silicon carbide (SiC), there is a problem of bipolar deterioration in which crystal defects expand at a time of recombination of holes injected into the n-type epitaxial layer, so that both the forward bias voltage (Vf) of the parasitic diode and an ON resistance (Ron) of the MOSFET increase.

[0006] DE 102 17 610 A1 relates to a metal-semiconductor contact with a semiconductor layer and with a metallization applied to the semiconductor layer, wherein such a high dopant concentration is introduced into the semiconductor layer that an ohmic metal-semiconductor contact is formed between the metallization and the semiconductor layer. The metallization and / or the semiconductor layer are formed such that only a fraction of the introduced doping concentration is electrically effective, and that a contact with only this fraction of the doping concentration is possible.

[0007] US 2013 / 0 026 568 A1 discloses a semiconductor power device supported on a semiconductor substrate having a bottom layer acting as a bottom electrode and an epitaxial layer overlying the bottom layer as a bottom layer. The semiconductor power device comprises a plurality of FET cells. Each cell further comprises a body region extending from a top surface into the epitaxial layer. The body region includes a region of heavy body dopant. An insulated gate is disposed on the top surface of the epitaxial layer, overlapping a first portion of the body region. A barrier control layer is disposed on the top surface of the epitaxial layer adjacent to the body region, remote from the insulated gate.A conductive layer overlies the top surface of the epitaxial layer and covers a second part of the body region, and the heavy body dopant region extends over the barrier control layer, forming a Schottky junction diode.

[0008] JP 2016-167 537 A describes a vertical MOSFET configured to prevent the operation of a parasitic diode because, during the operation of a parasitic diode with a pn junction, a forward current flows between a well of the first conductivity type and a drift layer of the second conductivity type and light is generated according to the band gap energy.This known vertical MOSFET comprises a semiconductor substrate of the second conductivity type with wells of the first conductivity type on one surface side; source electrodes arranged closer to the surface side than the wells of the first conductivity type, and additional diodes, each of which is electrically connected between the well of the first conductivity type and the source electrode and which are connected in reverse direction to a first parasitic diode formed by the semiconductor substrate of the second conductivity type and the well of the first conductivity type.

[0009] JP 2011-014740 A discloses a semiconductor device that can simultaneously improve the recovery characteristics of a flyback diode and the avalanche resistance of a MOSFET in a semiconductor device with the MOSFET and the Schottky barrier diode (SBD) connected in reverse parallel to the MOSFET on the same semiconductor substrate. The device comprises a source electrode in contact with a source region of the MOSFET, a control electrode in a base region, and an SBD electrode in contact with the SBD. When the MOSFET is on, the potentials of the control electrode and the SBD electrode are controlled to suppress the occurrence of an avalanche breakdown. During flyback, the potentials of the control electrode and the SBD electrode are controlled to prevent current flow into a parasitic diode of the MOSFET and allow current to flow into the SBD to improve the recovery characteristics. SUMMARY

[0010] Semiconductor devices capable of reducing energy loss and suppressing bipolar deterioration are provided.

[0011] The object underlying the invention is achieved in a semiconductor device according to the invention with the features of claim 1, alternatively in a semiconductor device according to the invention with the features of claim 6, further alternatively in a semiconductor device according to the invention with the features of claim 7, and finally further alternatively in a semiconductor device according to the invention with the features of claim 8. Advantageous further developments are the subject of the respective dependent claims.

[0012] An embodiment of the semiconductor device according to the present invention includes, among others: a MOS transistor provided with a first semiconductor layer of a first conductivity type, a second semiconductor layer of a first conductivity type provided on a first main surface of the first semiconductor layer and having a lower impurity concentration of a first conductivity type than that of the first semiconductor layer, a first impurity region of a second conductivity type provided in an upper layer part of the second semiconductor layer, a second impurity region of a first conductivity type provided in an upper layer part of the first impurity region, a gate electrode provided so as to oppose at least the first impurity region and the second semiconductor layer with a gate insulating film interposed therebetween, a first main electrode,which is at least partially connected to the second impurity region and provided so as not to be in direct contact with the first impurity region, and is provided with a second main electrode connected to a second main surface of the first semiconductor layer on a side opposite to a side provided with the first main electrode; a parasitic transistor configured with the second impurity region as the collector, the first semiconductor layer and the second semiconductor layer as the emitter, and the first impurity region as the base; a parasitic diode configured with the first impurity region as the anode and the first semiconductor layer and the second semiconductor layer as the cathode; and a pn junction diode configured with the first impurity region as the anode and the second impurity region as the cathode.

[0013] According to the above semiconductor device, when a voltage of the second main electrode is lower than a threshold gate voltage for turning the transistor ON, the transistor is automatically turned ON, and a current flows through the transistor channel. Therefore, hole injection from the first impurity region into the second semiconductor layer is suppressed. This suppresses the occurrence of energy loss due to transient reverse flow of holes when the parasitic diode returns to reverse bias, and enables the suppression of bipolar degradation in the case of application to SiC semiconductor devices.

[0014] These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is an equivalent circuit of a general VDMOS; Fig. 2 to 4 are diagrams for explaining an operation under a forward bias of a parasitic diode which takes place at a time before and after a synchronous rectification operation; Fig. 5 to 7 are diagrams to explain a general operation when a semiconductor device is used as an inverter; Fig. 8 is a cross-sectional view showing a configuration of a semiconductor device of a first preferred embodiment according to the present invention; Fig. 9 is a plan view showing a configuration of the semiconductor device of the first preferred embodiment according to the present invention; Fig. 10 is an equivalent circuit diagram of the semiconductor device of the first preferred embodiment according to the present invention; Fig. 11 to 13 are diagrams for explaining an operation of the semiconductor device of the first preferred embodiment according to the present invention; Fig. 14 is a cross-sectional view showing a configuration of a semiconductor device of a second preferred embodiment according to the present invention; Fig. 15 is a plan view showing a configuration of the semiconductor device of the second preferred embodiment according to the present invention; Fig. 16 is an equivalent circuit diagram of the semiconductor device of the second preferred embodiment according to the present invention; Fig. 17 and Fig. 18 are plan views showing a configuration of the semiconductor device of the second preferred embodiment according to the present invention; Fig. 19 is a view showing a configuration in which an external resistor is added in the semiconductor device of the second preferred embodiment according to the present invention; Fig. 20 is a cross-sectional view showing a configuration of a semiconductor device of a third preferred embodiment according to the present invention; Fig. 21 is an equivalent circuit diagram of the semiconductor device of the third preferred embodiment according to the present invention; Fig. 22 to 24 are plan views showing a configuration of the semiconductor device of the third preferred embodiment according to the present invention; Fig. 25 is a cross-sectional view showing a configuration of a semiconductor device of a fourth preferred embodiment according to the present invention; Fig. 26 is an equivalent circuit diagram of the semiconductor device of the fourth preferred embodiment according to the present invention; Fig. 27 is a cross-sectional view showing another configuration of the semiconductor device of the fourth preferred embodiment according to the present invention; Fig. 28 is a cross-sectional view showing a configuration of a semiconductor device of a fifth preferred embodiment according to the present invention; Fig. 29 is an equivalent circuit diagram of the semiconductor device of the fifth preferred embodiment according to the present invention; Fig. 30 is a view showing a configuration in which an external voltage clamping diode is added in the semiconductor device of the fifth preferred embodiment according to the present invention; Fig. 31 is a cross-sectional view showing a configuration of a semiconductor device of a sixth preferred embodiment according to the present invention; Fig. 32 is an equivalent circuit diagram of the semiconductor device of the sixth preferred embodiment according to the present invention; Fig. 33 is a view showing a configuration in which an external diode is added in the semiconductor device of the sixth preferred embodiment according to the present invention; Fig. 34 is a cross-sectional view showing a configuration of a semiconductor device of a seventh preferred embodiment according to the present invention; Fig. 35 is an equivalent circuit diagram of the semiconductor device of the seventh preferred embodiment according to the present invention; Fig. 36 is a cross-sectional view showing a configuration of a semiconductor device of an eighth preferred embodiment according to the present invention; Fig. 37 is an equivalent circuit diagram of the semiconductor device of the eighth preferred embodiment according to the present invention; Fig. 38 is a cross-sectional view showing a configuration of a semiconductor device of a ninth preferred embodiment according to the present invention; and Fig. 39 is a cross-sectional view showing a configuration of a semiconductor device of a tenth preferred embodiment according to the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS<Einführung>

[0015] Before describing preferred embodiments, reference is made to Fig. 1 to 4 describe the operation of a VDMOS. Fig. 1 is an equivalent circuit of a general VDMOS. As in Fig. As shown in Figure 1, there is a parasitic NPN transistor PT (parasitic transistor) between a drain terminal DT and a source terminal ST of a MOS transistor M1. A base electrode of the parasitic PNP transistor PT is connected to a back gate of the MOS transistor M1. Furthermore, there is a parasitic diode PD between the back gate of the MOS transistor M1 and the drain terminal DT.

[0016] Here, voltages of the drain terminal DT, the source terminal ST, and a gate terminal GT are a drain voltage Vd, a source voltage Vs, and a gate voltage Vg, respectively, and a back-gate voltage is a back-gate voltage Vbg. Note that the following description is given using the source terminal ST as a reference potential.

[0017] Next, with reference to Fig. 2 to 4 describe an operation under a forward bias of a parasitic diode which takes place before and after a synchronous rectification operation for preventing a power supply short circuit due to the synchronous rectification operation.

[0018] In Fig. 2, the gate voltage Vg and the source voltage Vs are 0 V, the drain voltage Vd is +V, and the MOS transistor M1 is in the OFF state. When the drain voltage Vd changes to a negative side and enters the state of Fig. 3, the drain voltage is clamped to -Vf by the forward bias voltage Vf of the parasitic diode PD, and a current flows through the parasitic diode PD. During this period, the parasitic diode PD acts as a freewheeling diode.

[0019] As in Fig. Next, as shown in Figure 4, when a positive bias voltage is applied to the gate terminal GT, the MOS transistor M1 is turned ON, the drain voltage Vd returns from -Vf to approximately 0 V when the ON resistance of the MOS transistor M1 is sufficiently low, and a current flows through the MOS transistor M1 in a lower resistance state. This state is a state in which a synchronous rectification operation is performed.

[0020] To get from here to the state of Fig. 2, the gate is switched OFF once to return to the state of Fig. 3 and then return to the state of Fig. 2. Since the parasitic diode PD is in the state of Fig. 3 is forward biased, holes are injected into an n-type (first conductivity type) epitaxial layer. The injected holes then temporarily flow in reverse when the state changes to the state of Fig. 2, and the parasitic diode PD returns to reverse bias, causing energy loss. Furthermore, in a case where there is a parasitic resistance between the source and the backgate, a reverse bias occurs between an emitter and a base of the parasitic NPN transistor PT due to a current due to the reverse flow of holes, and the parasitic NPN transistor PT is turned ON.

[0021] In the state of Fig. 2, MOS transistor M1 is initially in the OFF state. However, when a plurality of MOS transistors M1 are connected in series to form an inverter, a power supply short circuit occurs when the parasitic NPN transistor PT is turned ON, and a voltage higher than the breakdown voltage may be applied to MOS transistor M1, which may cause dielectric breakdown.

[0022] In the following, with reference to Fig. 5 to 7, a general operation when a MOS transistor is used as an inverter is described, and a cause of the dielectric breakdown described above is described.

[0023] An equivalent circuit of a conventional MOS transistor has the Fig. 1 and has a parasitic diode. For example, as a drive circuit for a motor, as shown in Fig. 5, MOS transistors Q1 and Q2 are connected in series between a power terminal VT and a ground GND to control input / output of a current to an output terminal OT. Note that Fig. 5 to 7 show parasitic diodes D1 and D2, which are to be used as freewheeling diodes, while the parasitic npn transistor is omitted for convenience.

[0024] Fig. 5 shows a state in which the MOS transistor Q2 on the high potential side is ON and a current I is output from the output terminal OT through the MOS transistor Q2.

[0025] Since the motor is driven, a coil (not shown) should be connected to the output terminal OT. For example, at the moment the MOS transistor Q2 on the high-potential side is turned OFF from the ON state, the current I is maintained by an inductance component (L component) of the coil, and, as shown in Fig. As shown in Figure 6, the parasitic diode D1 of the MOS transistor Q1 is forward biased on the low potential side to flow the current I. In this case, the output terminal OT becomes a negative bias (-Vf) by the forward bias voltage Vf of the diode, and a drain voltage of the MOS transistor Q1 becomes lower than the source voltage.

[0026] When the MOS transistor Q1 is turned ON, the current I flows through the MOS transistor Q1 in a direction opposite to a normal direction, as shown in Fig. 7. If the ON resistance of the MOS transistor Q1 is small, the voltage at the output terminal OT changes from -Vf to approximately 0 V, and the loss is further reduced. This operation is the synchronous rectification operation. When the upper and lower MOS transistors Q1 and Q2 are turned ON simultaneously, a current flows from the power terminal VT to the ground GND, causing a power supply short circuit, resulting in dielectric breakdown. Therefore, each time switching is performed, a state in which both the upper and lower MOS transistors are OFF is required.

[0027] In this way, the operation of the inverter that controls the motor contains the state of Fig. 6, in which the drain has a lower potential than the source of the MOS transistor, always occurs, and a current must flow at this time. Operation under a forward bias of the parasitic diode is typically used. However, when a parasitic diode is used as a freewheeling diode, energy loss occurs when the parasitic diode returns to a reverse bias after the parasitic diode is forward biased. SiC semiconductor devices also have a problem of bipolar deterioration, in which crystal defects expand at the time of hole recombination, so both the forward bias of the parasitic diode and the on-resistance of the MOSFET increase.

[0028] The inventor recognized the problem of using a parasitic diode as a freewheeling diode and came up with the technical idea of ​​allowing a freewheeling current to flow without using a parasitic diode. <Erste bevorzugte Ausführungsform> <vorrichtungskonfiguration>

[0029] Fig. 8 is a cross-sectional view showing a configuration of a semiconductor device 100 of a first preferred embodiment of the present invention. As shown in Fig. 8, in the semiconductor device 100, on a main surface (first main surface) of a substrate 1 (first semiconductor layer) of an n-type (first conductivity type) having a relatively high concentration (n + ) of n-type impurities, an epitaxial layer 2 (second semiconductor layer) of an n-type is formed, which has a lower concentration (n - ) of n-type impurities than that of the substrate 1, and an impurity region 3a (first impurity region) of a p-type (second conductivity type) is formed in an upper layer part of the epitaxial layer 2. Further, an impurity region 4 (second impurity region) of an n-type is formed in an upper layer part of the impurity region 3a. In addition, a gate electrode 5 is provided so as to span the impurity region 3a and the epitaxial layer 2 with a gate insulating film OX interposed therebetween, and a source electrode 6 (first main electrode) is connected on the impurity region 4. On another main surface (second main surface) of the substrate 1, which is opposite to a side provided with the source electrode 6, a drain electrode 7 (second main electrode) is provided.

[0030] Fig. Fig. 9 is an example of a plan view when the semiconductor device 100 is viewed from the source electrode 6 side, and the gate electrode 5 is omitted for convenience. Note that Fig. 9 is a plan view in a case where the source electrode 6 and the impurity region 4 are formed in a stripe shape; but the plan view shape of the source electrode 6 and the impurity region 4 is not limited to these.

[0031] Fig. 10 is an equivalent circuit diagram of the semiconductor device 100. As in Fig. As shown in Figure 10, a parasitic NPN transistor PT is connected in parallel with a MOS transistor between a drain terminal DT and a source terminal ST of the semiconductor device 100. A base of the parasitic NPN transistor PT is connected to a back gate of the MOS transistor. Furthermore, a parasitic diode PD is connected between the back gate of the MOS transistor and the drain terminal DT, and a pn junction diode PND is connected between the back gate and the source terminal ST.

[0032] Here, voltages of the drain terminal DT, the source terminal ST, and a gate terminal GT are a drain voltage Vd, a source voltage Vs, and a gate voltage Vg, respectively, and a voltage of the back gate is a back gate voltage Vbg.

[0033] In the semiconductor device 100 of the first preferred embodiment, the source electrode 6 is provided exclusively in contact with the impurity region 4, that is, a source region, and the pn junction diode PND by means of a pn junction between the impurity region 4 and the impurity region 3a can be obtained.

[0034] On the other hand, although the parasitic npn transistor PT can operate because the base and an emitter of the parasitic npn transistor PT, that is, the impurity region 3a and the impurity region 4, are not short-circuited, the operation of the parasitic npn transistor can be suppressed because a lifetime of the impurity region 3a is shortened so that Ic / Ie is 1 / 1000 or less (Ic / Ie ≤ 1 / 1000) in an emitter current Ie and a collector current Ic of the parasitic npn transistor.

[0035] In the case of a Si semiconductor device made of silicon (Si), an example of lifetime control includes forming defects in a crystal by means of platinum diffusion, gold diffusion, electron beam irradiation, proton irradiation, helium irradiation, and the like on the impurity region 3a.

[0036] Platinum and gold themselves remain in Si, creating an energy level that allows for efficient recombination of electrons and holes. Platinum or gold is therefore generally sputtered thinly onto the Si surface and allowed to diffuse into Si at 800 to 900°C.

[0037] Electrons, protons, and helium themselves do not remain in Si, but are implanted into Si at high energy to form a defect in the Si crystal at a specific rate when they stop in Si. The energy level of this defect serves to induce recombination of electrons and holes.

[0038] Furthermore, in the case of a SiC semiconductor device, a lifetime satisfying Ic / le ≤ 1 / 1000 can be obtained by forming the impurity region 3a by depositing aluminum (Al) at a dose of 1 × 10 13 up to 1 × 10 14 cm -2 implanted and annealed for activation at 1600 to 1800°C.

[0039] Activation annealing is a processing to electrically activate a dopant introduced by ion implantation, and high-frequency induction heating, infrared lamp heating, electron impact heating, or the like is used for heating.

[0040] Note that a short lifetime region may be partially formed in the impurity region 3a or may be formed in the entire impurity region 3a. <operation>

[0041] Next, with reference to Fig. 11 to 13, an operation of the semiconductor device 100 is described. Note that in Fig. 11 to 13 the parasitic npn transistor is omitted for the sake of convenience.

[0042] In Fig. 11, the gate voltage Vg and the source voltage Vs are 0 V, the drain voltage Vd is +V, and the MOS transistor in the semiconductor device 100 is in the OFF state. Here, there is a junction capacitance a between the back gate and the drain terminal DT, there is a junction capacitance b between the back gate and the source terminal ST, and the junction capacitance a and the junction capacitance b are connected in series between the drain terminal DT and the source terminal ST. Fig. 11 additionally shows a series connection of the junction capacitance a and the junction capacitance b.

[0043] If the drain voltage Vd changes to the negative side and the drain voltage Vd changes in the direction of applying a forward bias to the parasitic diode PD, a voltage of each part here changes from in Fig. 11 as shown to Fig. 12, and the drain voltage Vd decreases from Fig. 11 to Fig. 12. However, junction capacitance a and junction capacitance b are connected in series, and charges accumulated in junction capacitance a move to junction capacitance b, while a potential difference of junction capacitance a decreases. Therefore, the back-gate voltage Vbg also decreases.

[0044] Fig. Figure 12 shows a state where the gate voltage Vg and the source voltage Vs are 0 V, the drain voltage Vd is -V, and the back-gate voltage Vbg is -α. Until the junction capacitance a changes to a forward bias voltage, a relationship of the following equation (1) is established. α≥V

[0045] In Fig. 12 is a relative potential of the drain terminal DT α - V, is a relative potential of the back gate 0 V and is a relative potential of the gate terminal GT and the source terminal ST α.

[0046] Of the relative potential of each part, when a coefficient of a back-gate bias effect is β (0 < β ≤ 1) and a threshold value of the gate voltage for turning ON the MOS transistor is Vth, the MOS transistor is turned ON when the following equation (2) is satisfied, and a current flows from the source terminal ST in a direction opposite to a normal direction to the drain terminal DT. α≥Vth+β(α−V)

[0047] Then, a condition of a voltage V for turning ON the MOS transistor can be expressed by the following equation (3). V≥{Vth−α(1−β)} / β

[0048] Here, the smaller the second term on the right side of equation (3), the more severe the condition is. Therefore, if α is replaced by V using equation (1), it can be expressed by the following equation (4). V≥Vth

[0049] Consequently, from equation (1), α can be expressed by equation (5) below. α≥Vth

[0050] As described above, when the drain voltage Vd becomes lower than -Vth, the MOS transistor is automatically turned ON, and a current flows through a channel of the semiconductor device 100. Therefore, hole injection from the impurity region 3a to the epitaxial layer 2 is suppressed compared with a case where the parasitic diode PD is forward biased to allow a current to flow.

[0051] In order to improve a junction breakdown voltage of the pn junction diode PND, it is conceivable to lower the concentration of the impurity region 3a and form the impurity region 3a deeper so that a depletion layer expanding toward the inside of the impurity region 3a in a breakdown voltage holding state does not reach the impurity region 4 from the pn junction between the impurity region 3a and the epitaxial layer 2, or to configure the semiconductor device 100 with a wide band gap semiconductor such as SiC.

[0052] Note that if the state of Fig. 12 from a voltage is applied such that the drain voltage Vd becomes a positive bias, an operation is initiated in which the junction capacitance a is charged with the junction capacitance b of the pn junction diode PND. As in Fig. 13, the back-gate voltage Vbg then increases up to the forward bias voltage Vf of the parasitic diode PD, and the threshold value Vth decreases as a reverse back-gate bias effect.

[0053] As described above, in the semiconductor device 100 of the first preferred embodiment, by setting the junction breakdown voltage of the pn junction diode PND to Vth or higher, the MOS transistor is automatically turned ON when the drain voltage Vd becomes lower than -Vth, and a current flows through the channel of the semiconductor device 100. Therefore, hole injection from the impurity region 3a into the epitaxial layer 2 is suppressed. This suppresses the occurrence of energy loss due to a transient reverse flow of holes when the MOS transistor enters the state of Fig. 11, and the parasitic diode PD returns to a reverse bias. Furthermore, even in a case where there is a parasitic resistance between the source and the back gate, no forward bias is generated between the emitter and the base of the parasitic NPN transistor PT, and the parasitic NPN transistor PT is prevented from turning ON. This suppresses the parasitic PNP transistor PT from turning ON, and the occurrence of a power supply short circuit can be avoided if the semiconductor device 100 forms an inverter. <Zweite bevorzugte Ausführungsform>

[0054] Fig. 14 is a cross-sectional view showing a configuration of a semiconductor device 100A of a second preferred embodiment according to the present invention. As shown in Fig. As shown in Figure 14, in the semiconductor device 100A, there is a region where an impurity region 4 is partially not provided in a lower part of a source electrode 6. In this region, there is an impurity region 3a, and the source electrode 6 is in direct contact with the impurity region 3a. Note that in Fig. 14 the same components as those of the with reference to Fig. 8 are designated by the same reference numerals and redundant description is omitted.

[0055] Fig. 15 is an example of a plan view when the semiconductor device 100A is viewed from the side of the source electrode 6, in which a gate electrode 5 and the source electrode 6 are omitted for convenience, and an outline of the source electrode 6 is indicated by a dashed line. The arrow cross-sectional view taken along a line AA in Fig. 15 is taken, corresponds Fig. 8, and the arrow cross-sectional view taken along BB corresponds Fig. 14.

[0056] In the semiconductor device 100 of the first preferred embodiment, as shown in Fig. 11, it is described that since the junction capacitance a and the junction capacitance b are connected in series, the back-gate voltage Vbg decreases, and charges accumulated in the junction capacitance a move to the junction capacitance b while the potential difference of the junction capacitance a decreases.

[0057] However, if the potential of the impurity region 3a, that is, the back-gate voltage Vbg, becomes too low with respect to the impurity region 4, the effective threshold value Vth increases due to the back-gate bias effect, and there is a possibility of deterioration of the gate insulating film OX and dielectric breakdown when a gate voltage Vg equal to or higher than a standard upper limit is applied to turn ON the MOS transistor in this state.

[0058] In contrast, an increase in the potential of the impurity region 3a causes a forward bias for the pn junction diode PND, which increases the current of the MOS transistor. This forward bias is limited by being clamped by the forward bias voltage Vf of the pn junction diode PND; but the effective threshold Vth is lowered by the reverse back-gate bias effect. Consequently, if the back-gate voltage Vbg becomes too high, the ON-state current increases more than necessary, a permissible time decreases at a time of a power supply short circuit, and there is a possibility of causing unstable operation of the MOS transistor due to a current change caused by fluctuations in the back-gate voltage Vbg.

[0059] Accordingly, in the semiconductor device 100A of the second preferred embodiment, a configuration is adopted in which a resistor is added instead of the pn junction diode PND in order to suppress the above-described fluctuation of the back-gate voltage Vbg.

[0060] Fig. 16 is an equivalent circuit diagram of the semiconductor device 100A. As in Fig. As shown in Figure 16, a contact resistance CR is added between a back gate of a MOS transistor and a source terminal ST instead of the pn junction diode PND. That is, as shown in Fig. As shown in Figure 14, a region is formed where the impurity region 4 is partially absent from the lower part of the source electrode 6. In this region, a connecting portion is provided in which the source electrode 6 is in direct contact with the impurity region 3a. Consequently, instead of the pn junction diode PND, a contact resistance is added between the source electrode 6 and the impurity region 3a in the connecting portion.

[0061] By adopting such a configuration, it is possible to suppress excessive decrease and excessive increase of a back-gate voltage Vbg, avoid deterioration of a gate insulating film OX and dielectric breakdown, suppress unstable operation of the MOS transistor, and reduce an allowable time at a time of a power supply short circuit due to a current change caused by fluctuation of the back-gate voltage Vbg.

[0062] Note that in Fig. 15, the region is partially provided where the impurity region 4 is not provided in a case where the source electrode 6 and the impurity region 4 are formed in a stripe shape. However, the shape in plan view of the source electrode 6 and the impurity region 4 is not limited to this. For example, as shown in Fig. 17, a square pattern cell structure may be adopted in which the source electrode 6 and the impurity region 4 have a quadrangular shape in plan view, or a configuration in which cells partially not provided with the impurity region 4 and other cells are arranged in a configuration in which a plurality of square pattern cells as shown in Fig. 18 shown can be adopted.

[0063] As in Fig. Further, as shown in Fig. 19, a configuration may be adopted in which a pad CP is provided in direct contact with the impurity region 3a as a back gate on a part of a substrate 1, and an external resistor ER is arranged between the source electrode 6 provided on the impurity region 4 and the pad CP. As the external resistor ER, for example, polysilicon can be used, the impurity concentration of which is adjusted to obtain a predetermined resistance value.

[0064] Note that in Fig. 15, Fig. 17 and Fig. 18, it has been described that the impurity region 3a is present in the region where the impurity region 4 is not provided. However, a p-type impurity region having a higher impurity concentration may be provided on a surface of the impurity region 3a in order to improve an ohmic contact resistance between the source electrode 6 and the pad CP. <Dritte bevorzugte Ausführungsform>

[0065] Fig. 20 is a cross-sectional view showing a configuration of a semiconductor device 100B of a third preferred embodiment according to the present invention. As shown in Fig. 20, the semiconductor device 100B has a configuration in which a source electrode 61 is configured by a Schottky electrode forming a Schottky junction with an impurity region 3a, and the source electrode 61 is in direct contact with the impurity region 3a.

[0066] Fig. 21 is an equivalent circuit diagram of the semiconductor device 100B. As in Fig. As shown in Figure 21, a Schottky diode SD is formed between a back gate of a MOS transistor and a source terminal ST. In this case, the impurity region 3a is a p-type semiconductor region and thus serves as the anode, and the source electrode 61 serves as the cathode.

[0067] Since the forward bias voltage Vf of the Schottky diode is lower than the forward bias voltage Vf of a pn diode, an increase in the back-gate voltage Vbg can be clamped by the forward bias voltage Vf of the Schottky diode SD. Note that the forward bias voltage Vf of the Schottky diode is approximately one-half to two-thirds of the forward bias voltage Vf of the pn junction diode.

[0068] This can suppress an increase in the back-gate voltage Vbg and suppress unstable operation of the MOS transistor and a decrease in an allowable time at a time of a power supply short circuit due to a current change caused by fluctuation of the back-gate voltage Vbg.

[0069] Note that when a drain voltage Vd becomes lower than -Vth, the MOS transistor is automatically turned ON, and a current flows through a channel of the semiconductor device 100B. Therefore, hole injection from the impurity region 3a into an epitaxial layer 2 is suppressed compared to a case where a parasitic diode PD is forward-biased to allow a current to flow.

[0070] Furthermore, a lifetime of the impurity region 3a is shortened so that Ic / le is 1 / 1000 or less (Ic / le ≤ 1 / 1000) in an emitter current le and a collector current Ic of a parasitic NPN transistor to suppress operation of the parasitic NPN transistor. Note that, as the source electrode 61, it is possible to use any electrode material used in the manufacture of semiconductor devices, such as Al-Si, Al-Si-Cu (copper), Al-Cu, and W (tungsten), as long as a silicide of titanium (Ti) is formed on a surface of the impurity region 3a. Note that the source electrode 6 of the first and second preferred embodiments can also be formed of Al-Si, Al-Si-Cu, Al-Cu, and W.

[0071] Fig. 22 is an example of a plan view when the semiconductor device 100B is viewed from the side of the source electrode 61, in which a gate electrode 5 and the source electrode 61 are omitted for convenience, and an outline of the source electrode 61 is indicated by a dashed line. As in Fig. 22, the source electrode 61 and an impurity region 4 are formed in a stripe shape, and the source electrode 61 is in direct contact with the stripe-shaped impurity region 3a in a portion where the impurity region 4 is not provided.

[0072] Note that the plan view shape of the source electrode 61, the impurity region 4, and the impurity region 3a is not limited to these. For example, as shown in Fig. 23, a square pattern cell structure may be adopted in which the source electrode 61, the impurity region 4 and the impurity region 3a have a quadrangular shape in plan view, or a configuration in which cells partially not provided with the impurity region 4 and other cells are arranged in a configuration in which a plurality of square pattern cells as shown in Fig. 24 shown combined can be adopted.

[0073] Furthermore, there is also a procedure to replace the Fig. 19. In this case, a pad in direct contact with the impurity region 3a may be provided as a back gate on a portion of a substrate 1, and a Schottky diode may be arranged between the pad and the source electrode. <Vierte bevorzugte Ausführungsform>

[0074] Fig. 25 is a cross-sectional view showing a configuration of a semiconductor device 100C of a fourth preferred embodiment according to the present invention. As shown in Fig. 25, in the semiconductor device 100C, there is a region where an impurity region 4 is partially not provided in a lower part of a source electrode 6. In this region, there is an impurity region 3a, and on the impurity region 3a, a narrow band gap layer 9 formed of a material having a narrower band gap than that of the impurity region 3a and containing an n-type impurity is provided. However, an impurity concentration of the n-type impurity in the narrow band gap layer 9 is desirably higher than that in the impurity region 4. The source electrode 6 is then provided in contact with the narrow band gap layer 9 and in contact with the impurity region 4. Note that the source electrode 6 does not necessarily have to be in contact with the impurity region 4 as long as the narrow band gap layer 9 is provided in contact with the impurity region 4.

[0075] Fig. 26 is an equivalent circuit diagram of the semiconductor device 100C. As in Fig. As shown in Figure 26, a low forward bias diode LD is formed between a back gate of a MOS transistor and a source terminal ST. The low forward bias diode LD is a pn junction diode in which the impurity region 3a serves as the anode and the narrow band gap layer 9 serves as the cathode.

[0076] Here, if the semiconductor device 100C is a SiC semiconductor device using the substrate 1 as a SiC substrate, the narrow band gap layer 9 can be formed by a Si layer. In this case, the forward bias voltage Vf of the low forward bias diode LD is about 0.6 V, which is a forward bias voltage of the pn junction in the Si semiconductor device. Furthermore, since the forward bias voltage of the pn junction in the SiC semiconductor device is about 2.7 V, it is possible to suppress an increase in a back-gate voltage Vbg and suppress unstable operation of the MOS transistor and a decrease in an allowable time at a time of a power supply short circuit due to a current change caused by fluctuations in the back-gate voltage Vbg.

[0077] Note that when the drain voltage Vd becomes lower than -Vth, the MOS transistor is automatically turned ON, and current flows through a channel of the semiconductor device 100C. Therefore, hole injection from the impurity region 3a into an epitaxial layer 2 is suppressed compared to a case where a parasitic diode PD is forward-biased to allow a current to flow.

[0078] Further, a lifetime of the impurity region 3a is shortened so that Ic / le is 1 / 1000 or less (Ic / Ie ≤ 1 / 1000) in an emitter current le and a collector current Ic of a parasitic npn transistor to suppress an operation of the parasitic npn transistor.

[0079] Meanwhile, as a plan view shape when the semiconductor device 100C is viewed from the source electrode 6 side, for example, a configuration similar to the plan view shape of the semiconductor device 100C shown in Fig. 15. Further, if the source electrode 6 and the impurity region 4 are formed in a stripe shape, a configuration may be adopted in which a region is partially provided in which the impurity region 4 is not provided and the narrow band gap layer 9 is provided on the impurity region 3a of this region.

[0080] The plan view shape of the source electrode 6 and the impurity region 4 is not limited to these. For example, similar to the plan view shape of the semiconductor device 100A as shown in Fig. 17, a square pattern cell structure may be adopted in which the source electrode 6 and the impurity region 4 have a quadrangular shape in plan view, or a configuration in which cells partially not provided with the impurity region 4 and other cells are arranged in a configuration in which a plurality of square pattern cells as shown in Fig. 18 shown combined can be adopted.

[0081] Furthermore, there is also a procedure to replace the Fig. 19 to provide an external low forward bias diode. In this case, a configuration may be adopted in which a pad in direct contact with the impurity region 3a is provided as a back gate on a part of the substrate 1, and a pn junction diode made of Si is arranged as a low forward bias diode between the pad and the source electrode.

[0082] Here, if the semiconductor device 100C is a Si semiconductor device with the substrate 1 as a Si substrate, it is as in Fig. 27, it is possible to provide a narrow band gap region 91 implanted with a Group IV element instead of providing the narrow band gap layer 9. By implanting the Group IV element into the Si semiconductor layer, a lattice spacing in the implanted region in the Si semiconductor layer is widened, and a semiconductor having a narrower band gap than the Si semiconductor layer is formed. Meanwhile, as the Group IV element, germanium (Ge), for example, can be used. The narrow band gap region 91 is formed to a depth passing through the impurity region 4 in a thickness direction so as to reach the inside of the impurity region 3a.

[0083] In this case, the pn junction diode having the impurity region 3a as the anode and the impurity region 4 as the cathode becomes a low forward bias diode due to the presence of the narrow band gap region 91 and becomes the same in terms of the equivalent circuit as in Fig. 26. <Fünfte bevorzugte Ausführungsform>

[0084] Fig. 28 is a cross-sectional view showing a configuration of a semiconductor device 100D of a fifth preferred embodiment according to the present invention. As shown in Fig. As shown in FIG. 28, in the semiconductor device 100D, in an impurity region 3a, an impurity region 3b (third impurity region) containing p-type impurities is provided so as to be sandwiched between impurity regions 4, and a voltage clamp diode having a low breakdown voltage is formed by utilizing a pn junction between the impurity region 3b and the impurity region 4. Note that an impurity concentration of the impurity region 3b is higher than that of the impurity region 3a. In addition, an impurity concentration of the p-type impurities in the impurity region 3b is desirably higher than that of the impurity region 3a.

[0085] Furthermore, in the example of Fig. 28, a plan view shape of the impurity region 3b and the impurity region 4 is a stripe shape, and a source electrode 6 is provided so as to be individually connected to the impurity regions 4 on both sides of the impurity region 3b.

[0086] Fig. 29 is an equivalent circuit diagram of the semiconductor device 100D. As in Fig. As shown in Figure 29, a voltage clamp diode CD is formed between a back gate of a MOS transistor and a source terminal ST. The voltage clamp diode CD is a pn junction diode in which the impurity region 3b serves as the anode and the impurity region 4 serves as the cathode.

[0087] The voltage clamp diode CD has a function similar to that of the pn junction diode PND of the semiconductor device 100 of the first preferred embodiment. In the semiconductor device 100, when the drain voltage Vd changes toward applying a forward voltage to the parasitic diode PD, the back-gate voltage Vbg decreases, and the decrease stops at the pn junction breakdown voltage of the pn junction diode PND. However, if this pn junction breakdown voltage is too high, an effective threshold Vth increases, and a gate voltage Vg equal to or higher than a standard upper limit is required to turn the MOS transistor ON in this state.

[0088] If the effective threshold value Vth becomes too high, a gate voltage Vg equal to or higher than the standard upper limit must be applied to turn ON the MOS transistor in this state, which may cause deterioration of the gate insulating film and dielectric breakdown due to an excessive decrease in the back-gate voltage Vbg.

[0089] On the other hand, in the semiconductor device 100D, by providing a voltage clamp diode CD having a low breakdown voltage instead of the pn junction diode PND, a decrease in a back gate voltage Vbg stops at a pn junction breakdown voltage of a voltage clamp diode CD, and an effective threshold value Vth can be prevented from becoming unnecessarily high.

[0090] Note that when the drain voltage Vd becomes lower than -Vth, a MOS transistor is automatically turned ON, and a current flows through a channel of the semiconductor device 100D. Therefore, hole injection from the impurity region 3a into an epitaxial layer 2 is suppressed compared to a case where a parasitic diode PD is forward-biased to allow a current to flow.

[0091] Furthermore, a lifetime of the impurity region 3a is shortened so that Ic / le is 1 / 1000 or less (Ic / Ie ≤ 1 / 1000) in an emitter current le and a collector current Ic of a parasitic npn transistor to suppress operation of the parasitic npn transistor.

[0092] Note that the clamping voltage of the voltage clamping diode CD, that is, the pn junction breakdown voltage, is at least equal to or higher than the threshold value Vth of the MOS transistor and equal to or lower than the maximum gate voltage. For example, when the gate drive voltage of the MOS transistor is 15V, the maximum gate voltage, which is the maximum voltage that can be applied to the gate electrode 5, is often 24V. In this case, 24V or less is selected, and a specific value is selected considering the balance between the stability of the back gate voltage Vbg and the ON operation of the MOS transistor.

[0093] The pn junction breakdown voltage of the voltage clamp diode CD decreases as the impurity concentration of the impurity region 3b and the impurity region 4 decreases. For example, in a case where the semiconductor device 100D is a Si semiconductor device, the pn junction breakdown voltage is calculated to be about 11 V when the impurity concentration of the impurity region 3b is 1 × 10 17 cm -3 and the pn junction breakdown voltage is calculated to be about 3 V when the impurity concentration of the impurity region 3b is 1 × 10 18 cm -3 amounts.

[0094] Note that in the semiconductor device 100D, a pn junction diode is also formed between the impurity region 3a and the impurity region 4. However, since the back-gate voltage Vbg is determined by the lower pn junction breakdown voltage, the presence of the pn junction diode between the impurity region 3a and the impurity region 4 is ignored and is in Fig. 29 not shown.

[0095] In Fig. 28, the voltage clamp diode CD is provided by utilizing the pn junction between the impurity region 3b and the impurity region 4. However, a configuration can be adopted in which, as in Fig. 30, an electrode 11 is provided in contact with the impurity region 3a, and an external voltage clamp diode ED is arranged between the source electrode 6 and the electrode 11.

[0096] Furthermore, there is also a procedure to replace the Fig. 19. In this case, a pad in direct contact with the impurity region 3a may be provided as a back gate on a portion of the substrate 1, and a voltage clamp diode may be arranged between the pad and the source electrode. <Sechste bevorzugte Ausführungsform>

[0097] Fig. 31 is a cross-sectional view showing a configuration of a semiconductor device 100E of a sixth preferred embodiment according to the present invention. As shown in Fig. As shown in FIG. 31, in the semiconductor device 100E, in an impurity region 3a, an impurity region 8 (third impurity region) containing p-type impurities is provided so as to be surrounded by an impurity region 4, and a junction capacitance of a pn junction diode formed by a pn junction between the impurity region 3a and the impurity region 4 is increased. Although illustration is omitted, the impurity region 4 below the impurity region 8 is partially removed to provide a portion where the impurity region 8 is in contact with the impurity region 3a.

[0098] In the semiconductor device 100D of the fifth preferred embodiment, the P + Impurity region 3b is provided to be sandwiched between impurity regions 4 to form the voltage clamp diode with a low breakdown voltage. However, in semiconductor device 100E, impurity region 8 is formed to be surrounded by impurity region 4. This enlarges a pn junction area of ​​a pn junction diode (first pn junction diode) between impurity region 4 and impurity region 8 and a pn junction area of ​​a pn junction diode (second pn junction diode) between impurity region 4 and impurity region 3a, and a pn junction diode with a large junction capacitance can be obtained.

[0099] Fig. 32 is an equivalent circuit diagram of the semiconductor device 100E. As in Fig. As shown in Figure 32, a pn junction diode HD with a large junction capacitance is formed between a back gate of the semiconductor device 100E and a source terminal ST. The pn junction diode HD includes the first pn junction diode and the second pn junction diode described above. In the pn junction diode HD, the impurity region 8 serves as the anode, and the impurity region 4 serves as the cathode.

[0100] The semiconductor device 100E is similar to the semiconductor device 100 of the first preferred embodiment in that a diode is formed at this position. However, in the semiconductor device 100, the back-gate voltage Vbg decreases as the drain voltage Vd changes toward applying a forward voltage to the parasitic diode PD; but the decrease stops at a pn junction breakdown voltage of the pn junction diode PND. However, if this pn junction breakdown voltage is too high, an effective threshold Vth increases, and a gate voltage Vg equal to or higher than a standard upper limit is required to turn the MOS transistor ON in this state.

[0101] In contrast, when the drain voltage Vd changes toward applying a forward bias to the pn junction diode PND, a current of the MOS transistor increases. This forward bias is limited by being clamped by the forward bias voltage Vf of the pn junction diode PND; however, the effective threshold Vth is lowered by a reverse back-gate bias effect. Consequently, if the back-gate voltage Vbg becomes too high, the ON-state current increases more than necessary, and a permissible time at a time of a power supply short circuit decreases. Furthermore, there is a possibility of inducing unstable operation of the MOS transistor due to a current change caused by fluctuations in the back-gate voltage Vbg.

[0102] Furthermore, if the effective threshold value Vth becomes too high, a gate voltage Vg equal to or higher than the standard upper limit value must be applied to turn ON the MOS transistor in this state, which may cause deterioration of the gate insulating film OX and dielectric breakdown due to an excessive decrease in the back-gate voltage Vbg.

[0103] In the semiconductor device 100E, on the other hand, by increasing a junction capacitance of the pn junction diode HD, it is possible to suppress an excessive decrease and an excessive increase of a back-gate voltage Vbg, prevent deterioration of a gate insulating film OX and dielectric breakdown, and suppress unstable operation of a MOS transistor and a decrease of an allowable time at a time of a power supply short circuit due to a current change caused by fluctuation of the back-gate voltage Vbg.

[0104] Note that when a drain voltage Vd becomes lower than -Vth, the MOS transistor is automatically turned ON, and a current flows through a channel of the semiconductor device 100E. Therefore, hole injection from the impurity region 3a into an epitaxial layer 2 is suppressed compared to a case where a parasitic diode PD is forward-biased to allow a current to flow.

[0105] A lifetime of the impurity region 3a is further shortened so that Ic / le is 1 / 1000 or less (Ic / le ≤ 1 / 1000) in an emitter current le and a collector current Ic of a parasitic npn transistor to suppress an operation of the parasitic npn transistor.

[0106] An increase in the junction capacitance of the pn junction diode increases the charge Q accumulated in the junction capacitance. When the junction capacitance is C and the voltage of the junction capacitance between electrodes is V, it is expressed by Q = CV, and the current is dQ / dt. Therefore, when the junction capacitance increases, a change in the voltage V must be suppressed.

[0107] Note that in the semiconductor device 100D of the fifth preferred embodiment, a P + Impurity region 3b is provided so as to be sandwiched between impurity regions 4 to form the voltage clamp diode with a low breakdown voltage. However, semiconductor device 100D is similar to semiconductor device 100E in that a junction capacitance of the pn junction diode is increased because a plurality of pn junction diodes are to be connected in parallel between impurity region 3a and impurity region 4 even in the case of providing a voltage clamp diode.

[0108] In Fig. 31, in order to increase the junction capacitance of the pn junction diode, the impurity region 8 is provided and the pn junction between the impurity region 8 and the impurity region 4 is used. However, a configuration can be adopted in which, as in Fig. 33, an electrode 11 is provided in contact with the impurity region 3a, and an external capacitor EC is arranged between the source electrode 6 and the electrode 11. <Siebte bevorzugte Ausführungsform>

[0109] Fig. 34 is a cross-sectional view showing a configuration of a semiconductor device 100F of a seventh preferred embodiment according to the present invention. As shown in Fig. 34, the semiconductor device 100F has a configuration in which a MOS capacitor in the semiconductor device 100 of the first preferred embodiment shown in Fig. 8 is added.

[0110] That is, an impurity region 3a is provided in an upper layer portion of an epitaxial layer 2, separated from an impurity region 3a, and an impurity region 4 is provided in the upper layer portion thereof. In this impurity region 4, a gate electrode 5 is provided with a gate insulating film OX interposed therebetween to form a MOS transistor structure. This gate electrode 5 is connected to an electrode 11 provided to contact the impurity region 3a, which is a back gate of the MOS transistor. A source electrode 6 is further formed on the impurity region 4 forming the MOS transistor structure; this source electrode 6 is short-circuited to a source electrode 6 of the MOS transistor, and a MOS capacitor is added to the MOS transistor of the semiconductor device 100 shown in the first preferred embodiment.

[0111] Fig. 35 is an equivalent circuit diagram of the semiconductor device 100F. As in Fig. 35, a pn junction diode PND is formed between a back gate of the semiconductor device 100F and a source terminal ST, and a MOS capacitor MC is connected to the pn junction diode PND in parallel.

[0112] In the semiconductor device 100 of the first preferred embodiment, the back-gate voltage Vbg decreases as the drain voltage Vd changes toward applying a breakdown voltage to the parasitic diode PD; however, the decrease stops at a pn junction breakdown voltage of the pn junction diode PND. However, if this pn junction breakdown voltage is too high, an effective threshold Vth increases, and a gate voltage Vg equal to or higher than a standard upper limit is required to turn the MOS transistor ON in this state.

[0113] Conversely, when the drain voltage Vd changes toward the application of the forward bias to the pn junction diode PND, a current of the MOS transistor increases. This forward bias is limited by being clamped by the forward bias Vf of the pn junction diode PND; however, the effective threshold Vth is lowered by a reverse back-gate bias effect. Consequently, if the back-gate voltage Vbg becomes too high, the ON-state current increases more than necessary, and a permissible time at a time of a power supply short circuit decreases. Furthermore, there is a possibility of unstable operation of the MOS transistor due to a current change caused by fluctuations in the back-gate voltage Vbg.

[0114] Furthermore, if the effective threshold value Vth becomes too high, a gate voltage Vg equal to or higher than the standard upper limit value must be applied to turn ON the MOS transistor in this state, which may cause deterioration of the gate insulating film OX and dielectric breakdown due to an excessive decrease in the back-gate voltage Vbg.

[0115] On the other hand, in the semiconductor device 100E, by adding the MOS capacitor MC, it is possible to suppress excessive decrease and excessive increase of the back-gate voltage Vbg, prevent deterioration of the gate insulating film OX and dielectric breakdown, and suppress unstable operation of the MOS transistor and a decrease in the allowable time at a time of a power supply short circuit due to a current change caused by the fluctuation of the back-gate voltage Vbg. The reason is the same as the reason that the fluctuation of the back-gate voltage Vbg can be suppressed by increasing the junction capacitance of the pn junction diode in the sixth preferred embodiment.

[0116] Furthermore, Fig. 34, the MOS capacitor is added by forming the MOS transistor structure. As shown in Fig. However, as shown in Figure 33, an external capacitor EC may be arranged therebetween. <Achte bevorzugte Ausführungsform>

[0117] Fig. 36 is a cross-sectional view showing a configuration of a semiconductor device 100G of an eighth preferred embodiment according to the present invention. As shown in Fig. 36 is shown, in the semiconductor device 100G, in the semiconductor device 100 of the first preferred embodiment shown in Fig. As shown in Fig. 8, an upper layer part of the impurity region 3a is provided with an impurity region 4 (second region) separated from the impurity region 4 (first region) connected to the source electrode 6, and a short-circuit electrode 13 is provided so as to span from the impurity region 4 to the impurity region 3a. Note that the short-circuit electrode 13 is provided to short-circuit the impurity region 4 and the impurity region 3a.

[0118] Fig. 37 is an equivalent circuit diagram of the semiconductor device 100G. As shown in Fig. 37, a pn junction diode PND is formed between a back gate of a MOS transistor and a source terminal ST, and an npn transistor T1 in which an emitter and a base are short-circuited is added in parallel to the pn junction diode PND.

[0119] By adopting such a configuration, when a negative bias voltage is applied to the back gate, the negative bias voltage is clamped by a punch-through voltage between the impurity regions 4, and a decrease in a back gate voltage Vbg is suppressed.

[0120] In the semiconductor device 100 of the first preferred embodiment, the back-gate voltage Vbg decreases as the drain voltage Vd changes toward applying a forward bias to the parasitic diode PD; however, the decrease stops at a pn junction breakdown voltage of the pn junction diode PND. However, if this pn junction breakdown voltage is too high, an effective threshold Vth increases, and a gate voltage Vg equal to or higher than a standard upper limit is required to turn the MOS transistor ON in this state.

[0121] In the semiconductor device 100G, on the other hand, a decrease in the back-gate voltage Vbg is suppressed by a punch-through between the impurity regions 4. Therefore, an excessive increase in the effective threshold value Vth is suppressed, and it is possible to prevent deterioration of the gate insulating film OX and dielectric breakdown due to application of a gate voltage Vg equal to or higher than a standard upper limit.

[0122] Furthermore, Fig. 36 shows a configuration in which second impurity regions 4 are provided in the upper layer part of a common impurity region 3a. However, a configuration may be adopted in which an impurity region 4 connected to the short-circuit electrode 13 and an impurity region 4 connected to the source electrode 6 are provided in separate impurity regions 3a, and the impurity regions 3a are short-circuited. <Neunte bevorzugte Ausführungsform>

[0123] Fig. 38 is a cross-sectional view showing a configuration of a semiconductor device 100H of a ninth preferred embodiment according to the present invention. As shown in Fig. 38 is shown, in the semiconductor device 100H, in the semiconductor device 100 of the first preferred embodiment shown in Fig. As shown in Fig. 8, the upper layer part of the impurity region 3a is provided with an impurity region 4 (second region) separated from the impurity region 4 (first region) connected to the source electrode 6, and a short-circuit electrode 13 is provided so as to span from the impurity region 4 to the impurity region 3a. A MOS transistor is then added by forming a gate electrode 5 so as to span between peripheral portions of the two impurity regions 4 with a gate insulating film OX interposed therebetween. Note that the gate electrode 5 of the added MOS transistor is short-circuited to the gate electrode 5 of the semiconductor device 100H.

[0124] By adopting such a configuration, in a situation where the back-gate voltage Vbg decreases, since a positive bias of the same value as the decreased back-gate voltage Vbg is relatively applied to a gate of the added MOS transistor, the added MOS transistor is turned ON when the gate voltage of the added MOS transistor reaches a threshold value. Since a large current flows when the gate voltage is expected to exceed the threshold value, fluctuation in the back-gate voltage Vbg near the threshold value is suppressed in this state. Therefore, it is possible to prevent deterioration of the gate insulating film OX and dielectric breakdown, and to suppress unstable operation of the MOS transistor and a decrease in an allowable time at a time of a power supply short circuit due to a current change caused by fluctuation of the back-gate voltage Vbg.

[0125] As mentioned with reference to Fig. Furthermore, as described in Figure 12, when the drain voltage Vd decreases and becomes a negative bias, the back-gate voltage Vbg also decreases and becomes a negative bias to some extent. This is because the impurity region 3a is floating, and the negative back-gate bias remains even when a gate terminal GT is returned to 0 V. When the negative back-gate bias remains, a significant threshold is increased by a back-gate bias effect.

[0126] In the semiconductor device 100H, however, when the gate terminal GT is fixed to a positive bias by a synchronous rectification operation, the added MOS transistor is also turned ON, and the impurity region 3a and the impurity region 4 are short-circuited via the short-circuit electrode 13. Therefore, after the synchronous rectification is completed, the back-gate bias effect is lost. Therefore, even if the added MOS transistor is turned OFF after the synchronous rectification, deterioration of the hole injection suppression effect can be avoided because the back-gate bias effect has been eliminated. <Zehnte bevorzugte Ausführungsform>

[0127] Fig. 39 is a cross-sectional view showing a configuration of a semiconductor device 100I of a tenth preferred embodiment according to the present invention. Fig. 39 is obtained by converting the semiconductor device 100 of the first preferred embodiment shown in Fig. 8 is used for a trench type semiconductor device.

[0128] As in Fig. As shown in Fig. 39, the semiconductor device 100I is the same as the semiconductor device 100 in that a p-type impurity region 3a is formed in an upper layer part of an epitaxial layer 2, and an n-type impurity region 4 is formed in an upper layer part of the impurity region 3a. However, a trench TR is provided extending from an outermost surface of the epitaxial layer 2 to a depth exceeding a bottom surface of the impurity region 3a so as to be in contact with side surfaces of the impurity region 3a and the impurity region 4. A gate insulating film OX is then provided to cover an inner surface of the trench TR, and a gate electrode 5 is filled in the trench TR covered with the gate insulating film OX. In addition, the same components as those of the semiconductor device 100 are denoted by the same reference numerals, and redundant description will be omitted.

[0129] Thus, even in the trench-type semiconductor device, a source electrode 6 is configured to be in contact with the impurity region 4 alone. Since a lifetime of the impurity region 3a is shortened so that Ic / Ie is 1 / 1000 or less in an emitter current Ie and a collector current Ic of a parasitic NPN transistor, operation of the parasitic NPN transistor can be suppressed. Furthermore, by setting a junction breakdown voltage of a pn junction diode to Vth or higher, the semiconductor device 100I is automatically turned ON when a drain voltage Vd becomes lower than -Vth and a current flows through a channel of the semiconductor device 100I. Therefore, hole injection from the impurity region 3a into the epitaxial layer 2 is suppressed.This suppresses the occurrence of energy loss due to a transient reverse flow of holes when a parasitic diode PD of the semiconductor device 100I returns from a forward bias voltage to a reverse bias voltage. Furthermore, even in a case where there is a parasitic resistance between a source and a back gate, no forward bias voltage is generated between an emitter and a base of the parasitic NPN transistor, and the parasitic NPN transistor is prevented from turning ON. This prevents the parasitic NPN transistor from turning ON, and the occurrence of a power supply short circuit can be avoided if the semiconductor device 100I forms an inverter.

[0130] Meanwhile, a p-type impurity region is provided at a bottom part of the trench TR to prevent dielectric breakdown of the gate insulating film OX at the bottom part of the trench, and a p-type impurity region may be provided along a side surface of the trench TR to cause the impurity region to short-circuit with the impurity region 3a.

[0131] In the first to tenth preferred embodiments described above, the substrate 1 is a Si substrate or a SiC substrate, but may be a semiconductor substrate such as a GaN substrate, or may have a configuration in which a multilayer epitaxial growth layer is formed on a semiconductor substrate such as a Si substrate, a SiC substrate, or a GaN substrate, and then the semiconductor substrate is removed by a mechanical, chemical, or other method to provide the epitaxial growth layer alone. In this case, the substrate 1 can be referred to as a semiconductor layer containing n-type impurities at a relatively high concentration.< / operation> < / vorrichtungskonfiguration>

Claims

[1] A semiconductor device (100, 100C - 100I), comprising: - a MOS transistor (M1, Q1, Q2) which has: - a first semiconductor layer (1) of a first conductivity type, - a second semiconductor layer (2) of a first conductivity type provided on a first main surface of the first semiconductor layer (1) and having a lower impurity concentration of a first conductivity type than that of the first semiconductor layer (1), - a first impurity region (3a) of a second conductivity type provided in an upper layer part of the second semiconductor layer (2), - a second impurity region (4) of a first conductivity type provided in an upper layer part of the first impurity region (3a), - a gate electrode (5) provided so as to be opposite at least the first impurity region (3a) and the second semiconductor layer (2) with a gate insulating film (OX) arranged therebetween, - a first main electrode (6, 61) which is at least partially connected to the second impurity region (4) and is provided such that it is not in direct contact with the first impurity region (3a), and - a second main electrode (7) connected to a second main surface of the first semiconductor layer (1) on a side opposite to a side provided with the first main electrode (6, 61); - a parasitic transistor (PT) configured with the second impurity region (4) as an emitter, the first semiconductor layer (1) and the second semiconductor layer (2) as a collector, and the first impurity region (3a) as a base; - a parasitic diode (PD) configured with the first impurity region (3a) as the anode and the first semiconductor layer (1) and the second semiconductor layer (2) as the cathode; and - a pn junction diode (PND) configured with the first impurity region (3a) as the anode and the second impurity region (4) as the cathode, wherein: - a ratio (Ic / le) of a collector current (Ic) to an emitter current (le) of the parasitic transistor (PT) is 1 / 1000 or less, and - a junction breakdown voltage of the pn junction diode (PND) is equal to or greater than a threshold value (Vth) of a gate voltage for turning ON the MOS transistor (M1, Q1, Q2). [2] The semiconductor device (100, 100C 100I) according to claim 1, further comprising a MOS capacitor (MC) provided between the first main electrode (6, 61) and the first impurity region (3a). [3] A semiconductor device (100, 100C 100I) according to claim 1, wherein: - the second impurity region (4) has: - a first region to be connected to the first main electrode (6, 61); and - a second area provided separately from the first area, and - the semiconductor device (100, 100C 100I) further comprises a short-circuit electrode (13) provided on the second region and on the first impurity region (3a) and short-circuiting the second region and the first impurity region (3a). [4] A semiconductor device (100, 100C 100I) according to claim 3, wherein the gate electrode (5) is also provided between peripheral portions of the first and second regions with the gate insulating film (OX) interposed therebetween. [5] The semiconductor device (100, 100C 100I) according to claim 1, wherein the gate electrode (5) is provided in a trench (TR) provided in the second semiconductor layer (2) so as to be in contact with side surfaces of the first and second impurity regions (3a, 4) and reach a depth exceeding a bottom surface of the first impurity region (3a) with the gate insulating film (OX) interposed therebetween. [6] A semiconductor device (100, 100B), comprising: - a MOS transistor (M1, Q1, Q2) which has: - a first semiconductor layer (1) of a first conductivity type, - a second semiconductor layer (2) of a first conductivity type provided on a first main surface of the first semiconductor layer (1) and having a lower impurity concentration of a first conductivity type than that of the first semiconductor layer (1), - a first impurity region (3a) of a second conductivity type provided in an upper layer part of the second semiconductor layer (2), - a second impurity region (4) of a first conductivity type provided in an upper layer part of the first impurity region (3a), - a gate electrode (5) provided so as to be opposite at least the first impurity region (3a) and the second semiconductor layer (2) with a gate insulating film (OX) arranged therebetween, - a first main electrode (6, 61) which is at least partially connected to the second impurity region (4) and at least partially in Schottky connection with the first impurity region (3a), and - a second main electrode (7) connected to a second main surface of the first semiconductor layer (1) on a side opposite to a side provided with the first main electrode (6, 61); - a parasitic transistor (PT) configured with the second impurity region (4) as an emitter, the first semiconductor layer (1) and the second semiconductor layer (2) as a collector, and the first impurity region (3a) as a base; - a parasitic diode (PD) configured with the first impurity region (3a) as the anode and the first semiconductor layer (1) and the second semiconductor layer (2) as the cathode; and - a Schottky diode (SD) configured with the first impurity region (3a) as the anode and the first main electrode (6, 61) as the cathode, wherein: - a ratio (Ic / le) of a collector current (Ic) to an emitter current (le) of the parasitic transistor (PT) is 1 / 1000 or less, and - a diode breakdown voltage of the Schottky diode (SD) is equal to or greater than a threshold value (Vth) of a gate voltage for turning ON the MOS transistor (M1, Q1, Q2). [7] A semiconductor device (100, 100C), comprising: - a MOS transistor (M1, Q1, Q2) which has: - a first semiconductor layer (1) of a first conductivity type, - a second semiconductor layer (2) of a first conductivity type provided on a first main surface of the first semiconductor layer (1) and having a lower impurity concentration of a first conductivity type than that of the first semiconductor layer (1), - a first impurity region (3a) of a second conductivity type provided in an upper layer part of the second semiconductor layer (2), - a second impurity region (4) of a first conductivity type provided in an upper layer part of the first impurity region (3a), - a gate electrode (5) provided so as to be opposite at least the first impurity region (3a) and the second semiconductor layer (2) with a gate insulating film (OX) arranged therebetween, - a narrow band gap layer (9) of a first conductivity type, which is at least partially connected to the first impurity region (3a) and has a narrower band gap than that of the first impurity region (3a), - a first main electrode (6, 61) which is at least partially connected to the narrow band gap layer (9) and is provided so that it is not in direct contact with the first impurity region (3a), and - a second main electrode (7) connected to a second main surface of the first semiconductor layer (1) on a side opposite to a side provided with the first main electrode (6, 61); - a parasitic transistor (PT) configured with the second impurity region (4) as an emitter, the first semiconductor layer (1) and the second semiconductor layer (2) as a collector, and the first impurity region (3a) as a base; - a parasitic diode (PD) configured with the first impurity region (3a) as the anode and the first semiconductor layer (1) and the second semiconductor layer (2) as the cathode; and - a pn junction diode (LD, PND) configured with the first impurity region (3a) as the anode and the narrow band gap layer (9) as the cathode, wherein: - a ratio (Ic / le) of a collector current (Ic) to an emitter current (le) of the parasitic transistor (PT) is 1 / 1000 or less, and - a junction breakdown voltage of the pn junction diode (LD, PND) is equal to or greater than a threshold value (Vth) of a gate voltage for turning ON the MOS transistor (M1, Q1, Q2). [8] A semiconductor device (100, 100D), comprising: - a MOS transistor (M1, Q1, Q2) which has: - a first semiconductor layer (1) of a first conductivity type, - a second semiconductor layer (2) of a first conductivity type provided on a first main surface of the first semiconductor layer (1) and having a lower impurity concentration of a first conductivity type than that of the first semiconductor layer (1), - a first impurity region (3a) of a second conductivity type provided in an upper layer part of the second semiconductor layer (2), - a second impurity region (4) of a first conductivity type provided in an upper layer part of the first impurity region (3a), - a third impurity region (3b, 8) of a second conductivity type, which is provided in an upper layer part of the first impurity region (3a) or the second impurity region (4) and is at least partially in contact with the second impurity region (4), - a gate electrode (5) provided so as to be opposite to the first impurity region (3a) and the second semiconductor layer (4) with a gate insulating film (OX) arranged therebetween, - a first main electrode (6, 61) which is at least partially connected to the second impurity region (4) and is provided such that it is not in direct contact with the first impurity region (3a), and - a second main electrode (7) connected to a second main surface of the first semiconductor layer (1) on a side opposite to a side provided with the first main electrode (6, 61); - a parasitic transistor (PT) configured with the second impurity region (4) as an emitter, the first semiconductor layer (1) and the second semiconductor layer (2) as a collector, and the first impurity region (3a) as a base; - a parasitic diode (PD) configured with the first impurity region (3a) as an anode and the first semiconductor layer (1) and the second semiconductor layer (2) as a cathode; - a first pn junction diode (CD, HD) configured with the third impurity region (3b, 8) as the anode and the second impurity region (4) as the cathode; and - a second pn junction diode (PND) configured with the first impurity region (3a) as an anode and the second impurity region (4) as a cathode, wherein: - a ratio (Ic / le) of a collector current (Ic) to an emitter current (le) of the parasitic transistor (PT) is 1 / 1000 or less, and - a junction breakdown voltage of the first pn junction diode (CD, HD) is equal to or greater than a threshold value (Vth) of a gate voltage for turning ON the MOS transistor (M1, Q1, Q2) and equal to or less than a maximum voltage that can be applied to the gate electrode (5) of the MOS transistor (M1, Q1, Q2).

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