Driver control circuit for power semiconductor element

Abstract

Driver control circuit (51-54, 61-63) for a power semiconductor element (100) having a control terminal (101), the driver control circuit comprising: a driver (3) for causing a voltage shift at the control terminal in response to a turn-on command or a turn-off command; a detector (4, 15, 16) configured to detect an electrical quantity (Vg, Ig) of the control terminal; a delay signal generator (5) configured to generate a delay signal (dVG, dVig) by adding a delay time to a detection signal (VG, Vig) of the electrical quantity detected by the detector; a subtractor (6) configured to generate a difference signal (VD, VDig) between the detection signal and the delay signal; and a short-circuit condition detector (7) configured to detect a short-circuit condition in the power semiconductor element based on a comparison result between the difference signal and a reference value (VR1, VR2) when the driver is operated in response to the turn-on command.

Description

Technical area

[0001] The present invention relates to a driver control circuit for a power semiconductor device. More particularly, it relates to a driver control circuit having a hard switching fault detection function (short-circuit condition in a power semiconductor device) such as an insulated-gate bipolar transistor (IGBT) and a metal-oxide-semiconductor field-effect transistor (MOSFET). State of the art

[0002] If a hard switching fault occurs, a high short-circuit current flows through a power semiconductor device such as an IGBT and a MOSFET, which can lead to thermal damage of the power semiconductor device. Therefore, there is a need for functions to detect a short-circuit condition in the power semiconductor device and protect it.

[0003] PTD 1 (Japanese Patent Laid-Open No. 2001-197724) discloses a driver circuit for a power semiconductor element. The driver circuit is configured to detect a voltage across the main terminals of the power semiconductor element (a collector-emitter voltage in an IGBT) to determine that an overcurrent condition or a short-circuit condition is occurring when the voltage across the main terminals is higher than a prescribed determination value. PTD 2 (Japanese Patent Laid-Open No. 2007-259533) discloses a protection circuit configured to detect a collector current and a gate-emitter voltage in a power semiconductor element (IGBT).

[0004] Under the hard switching failure operating condition, the gate-emitter voltage instantly rises to a gate drive power supply voltage, and a large collector current flows through it. If the gate-emitter voltage is higher than a predetermined voltage and the collector current value is higher than a predetermined current value, it is determined that a hard switching failure has occurred. PTD 3 (Patent No. 3883925) discloses a driver circuit configuration for detecting a hard switching failure based only on the gate-emitter voltage of a power semiconductor device (IGBT).

[0005] More specifically, during a hard switching fault, the so-called mirror period, which occurs under normal operating conditions, does not occur. Consequently, the hard switching fault is detected when the gate-emitter voltage exceeds a reference value within the detection period, which corresponds to a mirror period. BibliographyPatent document Patent Document 1: Japanese Patent Laid-Open No. 2001-197724 (paragraphs

[0022] to

[0028] and Fig. 1 to 3) Patent Document 2: Japanese Patent Laid-Open No. 2007-259533 (paragraphs

[0013] to

[0017] and Fig. 1) Patent Document 3: Patent No. 3883925 (paragraphs

[0023] to

[0026] and

[0034] ). Summary of the inventionTechnical problem

[0006] The driver circuit disclosed in PTD 1 is configured to detect the collector-emitter voltage at the power semiconductor element, thereby detecting that a hard switching fault has occurred. In order to distinguish between normal operation and a hard switching fault, the determination process cannot be performed for a certain period of time after the power-on operation. This poses a problem in that a long time is required to detect a hard switching fault. Furthermore, it is necessary to use a high-voltage diode as the collector-emitter voltage detecting element, which also poses a problem of rising costs.

[0007] The protection circuit in PTD 2 is configured to use a collector current and a gate-emitter voltage to detect a hard switching fault. As a result, two control values ​​must be detected, resulting in increased device size and increased costs. For the driver circuit in PTD 3, the detection period must be set to match the physical parameters of the power semiconductor device and the driver circuit to prevent erroneous detection of a hard switching fault.

[0008] Consequently, if the detection period is set inappropriately, the driver circuit may fail to detect the hard switching fault or may make an erroneous detection.

[0009] The present invention was conceived to solve the problems described above. It is an object of the present invention to provide a driver control circuit capable of detecting a short-circuit condition in a power semiconductor element inexpensively, directly, and accurately.

[0010] Solution to the Problem A drive control circuit for a power semiconductor element according to the present invention is provided as a drive control circuit for a power semiconductor element having a control terminal.

[0011] The driver control circuit includes a driver, a detector, a delay signal generator, a subtractor, and a short-circuit condition detector. The driver applies a voltage to the control terminal in response to an on command or an off command. The detector is configured to detect an electrical quantity of the control terminal. The delay signal generator is configured to generate a delay signal by adding a delay time to a detection signal of the electrical quantity detected by the detector. The subtractor is configured to generate a difference signal between the detection signal and the delay signal.The short-circuit condition detector is configured to detect a hard switching fault based on a comparison result between the difference signal and a reference value when the driver is operating in response to the power-on command. By providing such a configuration, based on whether the peak value of the difference signal between the delay signal and the detection signal of a single electrical quantity in the control terminal exceeds a reference voltage, a hard switching fault can be detected without having to combine timing conditions.

[0012] Therefore, the hard switching fault can be detected accurately and at low cost. Furthermore, the peak value of the differential signal occurs at the time when the behavior of the electrical quantity varies significantly between normal operation and the hard switching fault, i.e., at the beginning of the mirror period. Consequently, a hard switching fault can be detected immediately before the power-on process.

[0013] Advantageous Effects of the Invention According to the present invention, a hard shifting failure can be detected inexpensively, immediately, and accurately. Short description of the drawings Fig. 1 is a block diagram showing the configuration of a drive control circuit for a power semiconductor element according to the first embodiment of the present invention. Fig. 2 is a circuit diagram showing a configuration example of a Fig. 1 shows the delay signal generator. Fig. 3 is a circuit diagram showing a configuration example of a Fig. 1 shown subtractor. Fig. Figure 4 is a conceptual waveform diagram showing the behavior of a voltage and a current at the time when the power semiconductor element is turned on in a normal operation. Fig. Figure 5 is a conceptual waveform diagram showing the behavior of a voltage and a current at the time when the power semiconductor element is turned on in a hard switching fault. Fig. 6 is a waveform diagram illustrating the behavior of a gate-emitter voltage and its delay voltage in the drive control circuit according to the first embodiment. Fig. 7 is a waveform diagram illustrating the behavior of a voltage difference signal in the drive control circuit according to the first embodiment. Fig. 8 is a waveform diagram of a signal showing the determination result in the drive control circuit according to the first embodiment. Fig. 9 is a circuit diagram showing another configuration example of the Fig. 1 shown subtractor. Fig. 10 is a block diagram showing the configuration of a drive control circuit for a power semiconductor element according to the second embodiment of the present invention. Fig. 11 is a waveform diagram illustrating the behavior of a gate current and its delay current in the drive control circuit according to the second embodiment. Fig. 12 is a waveform diagram illustrating the behavior of a current difference signal in the drive control circuit according to the second embodiment. Fig. 13 is a block diagram showing the configuration of a drive control circuit for a power semiconductor element according to the first modification of the second embodiment of the present invention. Fig. 14 is a waveform diagram for illustrating the operation of a determination period setting unit used in Fig. 13 is shown. Fig. 15 is a block diagram showing the configuration of a drive control circuit for a power semiconductor element according to the second modification of the second embodiment of the present invention. Fig. 16 is a block diagram showing the configuration of a drive control circuit for a power semiconductor element according to the third embodiment of the present invention. Fig. 17 is a block diagram showing the configuration of a drive control circuit for a power semiconductor element according to the first modification of the third embodiment of the present invention. Fig. 18 is a table showing the correspondence relationship between a selection signal and output data from an output terminal in the Fig. 17 shows the driver control circuit. Fig. 19 is a diagram showing an example of the output data (analog) from the output terminal in the Fig. 17 shows the driver control circuit. Fig. 20 is a diagram showing an example of the output data (digital) from the output terminal at the time when the selection signal in the Fig. 17 has a value of “10”. Fig. 21 is a diagram showing an example of the output data (digital) from the output terminal at the time when the selection signal in the Fig. 17 has a value of “11”. Fig. 22 is a block diagram showing the configuration of a drive control circuit for a power semiconductor element according to the second modification of the third embodiment of the present invention. Description of embodiments

[0014] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. First embodiment

[0015] Fig. 1 is a block diagram showing the configuration of a drive control circuit for a power semiconductor element according to the first embodiment of the present invention.

[0016] With reference to Fig. 1, a driver control circuit 51 according to the first embodiment controls a power semiconductor element 100 to turn it on and off. In the following description, an IGBT is exemplified as the power semiconductor element 100. Accordingly, according to the voltage at the gate 101, which serves as a "control terminal," the power semiconductor element 100 is controlled to be in a "closed state (turned on)" or an "open state (turned off)." In the "closed state (turned on)," a current path is formed between a collector 102 and an emitter 103, each of which is a "main terminal." In the "open state (turned off)," the current path is interrupted. The power semiconductor element 100 is not limited to an IGBT, but may be a fully controllable power semiconductor element such as a MOSFET.

[0017] First, an explanation will be given below regarding the configuration of a circuit portion included in the configuration of the driver control circuit 51, which is configured to control the power semiconductor element 100 to turn on and off. The driver control circuit 51 includes a control command unit 10, a voltage driver 3, gate resistors 2a and 2b, and a soft turn-off unit 9.

[0018] The control command unit 10 generates a control signal Sg in response to an on / off command from outside the driver control circuit 51. The control signal Sg is set to a logic high level (hereinafter simply referred to as "H level") or a logic low level (hereinafter simply referred to as "L level").

[0019] The control command unit 10 shifts the control signal Sg from the H level to the L level when the power semiconductor element 100 is instructed to be turned off. The control signal Sg is in turn shifted from the L level to the H level when the power semiconductor element 100 is instructed to be turned on.

[0020] The voltage driver 3 includes semiconductor switches 21 and 22. The semiconductor switch 21 is connected between the gate resistor 2a and a voltage node 19, which serves to supply a positive bias voltage Vp to the gate 101 with respect to the emitter 103. The semiconductor switch 22 is connected between the gate resistor 2b and a voltage node 20, which serves to supply a negative bias voltage Vn to the gate 101 with respect to the emitter 103. For example, the emitter 103 is set to 9 (V), the voltage node 19 is set to 24 (V), and the voltage node 20 is set to 0 (V), with the result that the positive bias voltage Vp is set to 15 (V) and the negative bias voltage Vn is set to -9 (V). In the following description, each semiconductor switch to be used is a semiconductor switching element such as a transistor. E.g. a bipolar transistor or a MOSFET.

[0021] Semiconductor switch 21 is turned on and off in response to the control signal Sg. Semiconductor switch 22, in turn, is turned on and off in response to the output from inverter 23, to which the control signal Sg is input. In other words, semiconductor switches 21 and 22 are turned on and off complementarily in response to the control signal Sg.

[0022] When the control signal Sg is set to an H level, the semiconductor switch 21 is turned on, connecting the gate 101 to the voltage node 19 through the gate resistor 2a. This causes the gate 101 to shift toward the positive bias voltage Vp, so that the power semiconductor element 100 is turned on. The transition speed of the gate-emitter voltage in the turn-on transient, i.e., the switching speed, varies according to the gate resistance value (the resistance value of the gate resistor 2a).

[0023] In turn, when the control signal Sg is set to an L level, the semiconductor switch 22 is turned on, thereby connecting the gate 101 to the voltage node 20 through the gate resistor 2b. This causes the gate 101 to be shifted toward the negative bias voltage Vn, so that the power semiconductor element 100 is turned off. The transition speed of the gate-emitter voltage in the turn-off transient, i.e., the switching speed, varies according to the gate resistance value. In the following description, the voltage at the gate 101 relative to the emitter 103 (the gate-emitter voltage Vge) in the power semiconductor element 100 is also simply referred to as "gate voltage Vg."

[0024] The soft-off unit 9 includes a semiconductor switch 24 and a gate resistor 2c connected in parallel with the gate resistor 2b. The semiconductor switch 24 is turned on and off in response to a protection signal S2 from a short-circuit protection circuit 8, which will be described later. When the semiconductor switch 24 is turned on or off, the gate resistance value can be changed during the turn-off process. More specifically, when the semiconductor switch 24 is turned on, the gate resistors 2b and 2c, which are connected in parallel with each other, are included in the discharge path of the gate 101.

[0025] When the semiconductor switch 24 is turned off, only the gate resistor 2b is included in the discharge path of the gate 101. Accordingly, when the semiconductor switch 24 is turned off, the gate resistance value increases compared to when the semiconductor switch 24 is turned on.

[0026] This reduces the transient speed at which the gate 101 changes toward the negative bias voltage Vn (switching speed), so that the power semiconductor element 100 is slowly turned off. The semiconductor switch 24 is turned on when the power semiconductor element 100 is in the normal state. In contrast, the semiconductor switch 24 is turned off in response to a protection signal S2 when the hard switching fault is detected. By shifting the voltage at the gate 101 in response to the control signal Sg according to a turn-on / turn-off command, the power semiconductor element 100 is controlled to turn on and off.

[0027] One embodiment of the "driver" can be configured by the control command unit 10 and the voltage driver 3. The following is an explanation of the configuration of a circuit portion included in the driver control circuit 51 and related to the detection of the hard switching error.

[0028] The driver control circuit 51 further includes a gate voltage detector 4, a delay signal generator 5, a subtractor 6, a short-circuit condition detector 7, a sample-and-hold unit 18, and a short-circuit protection circuit 8. The gate voltage detector 4 generates a detection signal VG according to the gate voltage Vg.

[0029] The detection signal VG is an analog voltage signal corresponding to the gate voltage Vg. The delay signal generator 5 generates a delay signal dVG obtained by delaying the detection signal VG by a prescribed delay time. Fig. 2 is a circuit diagram showing a configuration example of a delay signal generator 5.

[0030] With reference to Fig. 2, the delay signal generator 5 may be formed from an RC filter formed from a resistor 11 and a capacitor 12. If the RC filter is configured to receive an input as the detection signal VG and provide an output as the delay signal dVG, then the delay time corresponding to the RC time constant obtained according to the product of the resistance value of the resistor 11 and the capacitance value of the capacitor 12 may be applied between the detection signal VG and the delay signal dVG. Referring again to Fig. 1, a subtractor 6 outputs a voltage difference signal VD obtained by amplifying the voltage difference between the detection signal VG from the gate voltage detector 4 and the delay signal dVG from the delay signal generator 5.

[0031] Fig. 3 is a circuit diagram showing a configuration example of the subtractor 6. Referring to Fig. 3, the subtractor 6 may be formed of a subtractor circuit obtained by differential amplification and formed of the resistors R1 to R4 and an operational amplifier 13.

[0032] It is known that, assuming that the resistors R1 to R4 have resistance values ​​R1 to R4, the following equation (1) is obtained with an input voltage Va going to an inverting input terminal, an input voltage Vb going to a non-inverting input terminal, and an output voltage Vc from the subtractor circuit. Vc=(R1+R2R3+R4)R4R1Vb−R2R1Va

[0033] Assuming that the conditions R3 = R1 and R4 = R2 are satisfied, then the following equation (2) is obtained from equation (1). Vc=R2R1(Vb−Va)

[0034] When the detection signal VG is input to the non-inverting input terminal (Vb = VG) and the delay signal dVG is input to the inverting input terminal (Va = dVG), the voltage difference signal VD from the subtractor 6 is represented by the following equation (3).

[0035] In equation (3) kg = (R2 / R1), which corresponds to an increase in gain in the subtraction circuit. VD=kg⋅(VG−dVG)

[0036] With further reference to Fig. 1, the short-circuit condition detector 7 is formed by a voltage comparator (comparator). The short-circuit condition detector 7 outputs a determination signal S0 based on the comparison between the voltage difference signal VD from the subtractor 6 and a reference voltage VR1 from a reference voltage generator 17a. The reference voltage generator 17a is formed by a voltage divider connected between the voltage node 19 and the ground of the driver control circuit 51, or by a three-terminal regulator, and is configured to output a constant DC voltage corresponding to the reference voltage VR1.

[0037] For example, the determination signal S0 is set to an H level under the condition that VD > VR1. Then, the determination signal S0 is set to an L level under the condition that VD ≤ VR1. The sample-and-hold unit 18 outputs a signal S1 that maintains the determination signal S0 at an H level. When the signal S1 changes to an H level, the short-circuit protection circuit 8 sets the protection signal S2 from the power semiconductor element 100 to an H level. In this way, in the drive control circuit 51 according to the first embodiment, it is determined whether the power semiconductor element 100 is in a short-circuit state based on the behavior of the difference signal between the gate-emitter voltage detection signal and the delay signal of the detection signal.

[0038] The determination procedure is described below.

[0039] Fig. Figure 4 is a conceptual waveform diagram showing the behavior of a voltage and a current at the time when the power semiconductor element is turned on during normal operation. Referring to Fig. 4, in response to a turn-on command, the gate 101 is shifted to a positive bias voltage Vp at time t0.

[0040] In response, the gate voltage Vg rises, and the power semiconductor element 100 is also turned on. Consequently, the collector current Ic rises while the collector-emitter voltage Vce falls.

[0041] At this time, in the normal state (ie, the state in which a short circuit does not occur), there is a period during which the gate voltage Vg is maintained at a fixed value (ie, a mirror period). Fig. 5 shows a conceptual waveform diagram showing the behavior of a voltage and a current at the time when the power semiconductor element is turned on in a hard switching fault.

[0042] With reference to Fig. 5, under the hard switching fault condition, there is no mirror period, the gate voltage Vg rises very quickly to a positive bias voltage Vp, and an excessive collector current Ic flows.

[0043] In PTD2, two types of electrical quantities (a gate-emitter voltage and a collector current) are detected. If the gate voltage Vg is higher than a prescribed voltage value and the collector current Ic is higher than a prescribed current value, then it is determined that a hard switching fault has occurred. In PTD3, to detect a hard switching fault based only on the gate-emitter voltage, it is necessary to specify the determination period related to the mirror period in the normal state, that is, to specify a combination of timing conditions, which may lead to failed detection or erroneous detection of the hard switching fault.In general, in SiC MOS FETs, which are known as a power device useful for implementing a high-efficiency and downsized power converter, it is known that the gate-emitter voltage in the mirror period tends to increase slowly, compared with the characteristics in IGBT (. Fig. 5).

[0044] As a result, the difference in gate-emitter voltage between normal operation and the hard switching fault is small. This may raise concerns that it will be relatively difficult to detect the hard switching fault based solely on the gate-emitter voltage.

[0045] Fig. Figure 6 shows a waveform diagram illustrating the behavior of a gate-emitter voltage and its delay voltage in the driver control circuit according to the first embodiment. Fig. 6, the simulation results using a specific power semiconductor device (IGBT) 100 and specific circuit parameters of the driver control circuit 51 are compared between normal operation and the hard switching error. In Fig. 6 the horizontal axis shows the time axis, on which one scale division corresponds to 1 µs.

[0046] Fig. Figure 6 shows simulation waveforms of a gate voltage Vg during normal operation and a gate voltage Vg* under the hard switching fault. As can be seen from the comparison between Vg and Vg*, the mirror period begins at a time ta during normal operation, but the voltage rises very quickly without the mirror period occurring under the hard switching fault. Furthermore, Fig. 6 shows the simulation results regarding the delay voltage dVg and the delay voltage dVg*, which are obtained by setting a delay time in the delay signal generator 5 ( Fig. 2) are added to each of gate voltage Vg (normal state) and gate voltage Vg* (hard switching error).

[0047] In this case, the RC time constant in the delay signal generator 5 is defined as 2 µs.

[0048] Fig. Figure 7 shows a waveform diagram illustrating the behavior of a voltage difference signal in the driver control circuit according to the first embodiment. Fig. 7, the simulation result of the voltage difference signal output from the subtractor 6 is compared between normal operation and the hard switching error. The same time scale is used in Fig. 7 and Fig. 6 used.

[0049] With reference to Fig. 7, the voltage difference signal VD is calculated as the difference (Vg - dVg) between the delay voltage dVg and the gate voltage Vg in the normal state, as shown in Fig. 6. The voltage difference signal VD* is calculated as the difference (Vg* - dVg*) between Vg* and dVg* under the hard switching error, as shown in Fig. 6. In the Fig. In the circuit shown in Figure 1, the voltage difference signal VD is calculated from the detection signal VG, which corresponds to the gate voltages Vg, and from the delay signal dVG, which corresponds to the delay voltages dVg. At time ta and thereafter, a difference in behavior occurs between the voltage difference signals VD and VD*.

[0050] Specifically, the voltage difference signal VD in the normal state continuously decreases at time ta and thereafter. In contrast, the voltage difference signal VD* under the hard switching fault also increases at time ta and thereafter, and then begins to decrease at time tb and thereafter. Consequently, the voltage difference signal VD does not reach the range of the voltage difference signal VD* between time ta and time tb during the turn-on process. In this way, it is recognized that the gate-emitter voltage difference signal has a voltage range that can be reached under the hard switching fault, but that cannot be reached during normal operation.

[0051] As a result, it is possible to determine that the fault occurs during hard switching, based only on the maximum value (peak value) of the voltage difference signal from subtractor 6, but without providing a determination period, ie, without having to combine time conditions. As in Fig. For example, as shown in Figure 7, the reference voltage VR for detecting the hard switching fault can be set between the voltage value (VD* = VD) of the voltage difference signal at time ta and the peak value (VD*) of the voltage difference signal at time tb. The voltage difference signal also exceeds the reference voltage VR immediately at the beginning of the mirror period (immediately after time ta). It is necessary to set the delay time in the delay signal generator 5 such that there is a difference in the maximum value (peak value) of the voltage difference signal between normal operation and the hard switching fault.

[0052] With reference to Fig. 6, it is recognized that if the delay time of the gate-emitter voltage is too short, the voltage difference between the detection signal and the delay signal cannot be guaranteed. In turn, if the delay time is longer than the elapsed time during which the gate-emitter voltage rises from the negative bias voltage Vn to the positive bias voltage Vp in normal operation (Tp1 in Fig. 6; approximately 5 µs), then the level of the voltage difference signal in the hard switching fault cannot be guaranteed.

[0053] In the Fig. In the example shown in Figure 6, the delay signal generator 5 is formed by a first-order time delay system formed by an RC filter, and the delay time is set to correspond to a time constant of 2 µs, thereby setting the delay time to be shorter than the elapsed time Tp1 described above. This consequently causes a suitable difference in the peak value of the voltage difference signal between normal operation and the hard switching error, as shown in Fig. 6 and Fig. 7. Furthermore, taking into account the collector-emitter voltage Vce ( Fig. 4) as a voltage difference between the "main terminals", the delay time in the delay signal generator 5 is set to a similar length as the above, so that the delay time is set to be shorter than the elapsed time until the collector-emitter voltage Vce becomes lower than a prescribed voltage. Referring again to Fig. 1, in the driver control circuit 51 according to the first embodiment, the short-circuit condition detector 7, which is formed of a voltage comparator, sets the determination signal S0 at an H level or an L level according to the comparison between the voltage difference signal VD from the subtractor 6 and a reference voltage VR1.

[0054] Reference voltage VR1 is determined according to the reference voltage VR ( Fig. 7) taking into account the gain increase and the like in the subtractor 6.

[0055] Fig. 8 is a waveform diagram of a signal showing an example of the determination result in the drive control circuit 51 according to the first embodiment. Fig. Figure 8 shows the behavior of the signal at the time when the power semiconductor element 100 is in the short-circuit state. Referring to Fig. 8, the determination signal S0 is set to an H level by the short-circuit condition detector 7 during a period during which the voltage difference signal VD becomes higher than the reference voltage VR1.

[0056] Consequently, in short-circuit operation, the determination signal S0 changes from the L level to the H level at the time when the condition VD* > VR1 is fulfilled, immediately after the time ta in Fig. 7.

[0057] When the determination signal S0 changes to the H level, the signal S1 from the sample-and-hold unit 18 is subsequently held at the H level. This records the occurrence of a hard switching error. When the occurrence of a hard switching error is recorded, the short-circuit protection circuit 8 sets the protection signal S2 to the H level.

[0058] In addition to an external turn-on / turn-off command, when the protection signal S2 is set to the H level, the control command unit 10 shifts the control signal Sg to the L level. This issues a turn-off command, which is equivalent to causing the power semiconductor element 100 to turn off. This allows the power semiconductor element 100 to turn off. Furthermore, the control command unit 10 sets the control signal Sg to the L level during the period during which the protection signal S2 is set to the H level.

[0059] This equivalently prevents the generation of a turn-on command, which turns on the power semiconductor element 100 for which the hard switching fault was detected. Consequently, the generation of an overcurrent can be prevented.

[0060] By using a p-type MOSFET, the semiconductor switch 24 of the soft-off unit 9 is configured to turn on when the protection signal S2 is at an L level and turn off when the protection signal S2 is at an H level. When the power semiconductor element 100 for which the hard switching failure was detected is turned off, the gate-emitter voltage drops at a low rate. Consequently, it is possible to prevent the generation of a surge voltage across the collector and emitter when the power semiconductor element 100 is turned off.In this way, in the drive control circuit for the power semiconductor element in the present first embodiment, the gate-emitter voltage can be detected as an “electrical quantity at the control terminal,” and based on the peak value of the difference signal between the electrical quantity detection signal and the delay signal, the hard switching failure can be detected at the time immediately after the start of the mirror period in the normal state.

[0061] This allows the occurrence of the hard switching fault to be detected immediately and accurately by detecting only the gate-emitter voltage and without having to combine timing conditions.

[0062] Also, the power semiconductor element 100 can be protected from overcurrent by providing a configuration in which the determination signal S0 is held by the short-circuit condition detector 7 and the semiconductor switching element 100 is forcibly turned off when the hard switching fault is detected. Furthermore, the soft turn-off unit 9 is operated to suppress a surge voltage generated when the power semiconductor element 100 is turned off. Accordingly, the power semiconductor element 100 can be protected. [Modification of the first embodiment]

[0063] According to the modification of the first embodiment, another configuration example of the subtractor 6 will be described.

[0064] Fig. 9 is a circuit diagram showing another configuration example of the Fig. 1 shown subtractor 6.

[0065] With reference to Fig. 9, the subtractor 6 can be formed from the so-called measuring amplifier, which is formed from the resistors R0, R5 to R7 and the operational amplifiers 14a to 14c.

[0066] Compared with a subtraction circuit obtained by differential amplification as in Fig. As shown in Figure 3, the amplifier can achieve stabilized operation even in an environment with electromagnetic interference. Consequently, the amplifier is often used in commercial measurement circuits.

[0067] Assuming that the resistance values ​​of the resistors R0, R5, R6 and R7 are R0, R5, R6 and R7 respectively, the following equation (4) is obtained with the input voltage Va to the non-inverting input terminal of the operational amplifier 14a, the input voltage Vb to the non-inverting input terminal of the operational amplifier 14b and the output voltage Vc from the subtractor 6. Vc=R7R6(1+2R5R0)(Vb−Va)

[0068] When the outputs from the gate voltage detector 4 and the delay signal generator 5 are input to the subtractor 6 so that the conditions Vb = VG and Va = dVG are satisfied, the voltage difference signal VD proportional to the voltage difference between the detection signal VG and the delay signal dVG can be obtained, as shown in equation (3) described above. In the configuration example of Fig. 1, the following applies: Even if the Fig. 9 is used as the subtractor 6, as in the first embodiment, the occurrence of the hard switching error can be detected immediately and accurately based on the peak value of the voltage difference signal between the gate-emitter voltage and the delay signal of the gate-emitter voltage. [Second embodiment]

[0069] In the second embodiment, the configuration for detecting a hard switching failure based on the gate current differential signal (hereinafter also referred to as “current difference signal”) instead of the gate-emitter voltage differential signal will be described. Fig. 10 is a block diagram showing the configuration of a drive control circuit for a power semiconductor element according to the second embodiment of the present invention.

[0070] When comparing Fig. 10 with Fig. 1, the driver control circuit 52 according to the second embodiment differs from the driver control circuit 51 according to the first embodiment in that the driver control circuit 52 includes a gate current detector 15 and a reference voltage generator 17b instead of the gate voltage detector 4 and the reference voltage generator 17a, respectively. Since the configurations of other portions in the driver control circuit 52 are the same as those in the driver control circuit 51, their detailed descriptions will not be repeated here. In other words, in the driver control circuit 52 according to the second embodiment, the voltage driver 3 also shifts the voltage at the gate 101, thereby controlling the power semiconductor element 100 to turn on and off.

[0071] The gate current detector 15 can be formed, for example, from a current transformer (CT) and a Rogowski coil. The gate current detector 15 generates a detection signal Vig with a voltage value proportional to the gate current.

[0072] The delay signal generator 5 generates a delay signal dVig obtained by delaying a detection signal Vig from the gate current detector 15 by a prescribed delay time. The delay time obtained from the delay signal generator 5 is multiplied by the time constant of the RC filter in Fig. 2. Then, the subtractor 6 outputs a current difference signal VDig, which is obtained by amplifying the voltage difference between the detection signal Vig from the gate current detector 15 and the delay signal dVig from the delay signal generator 5. The subtractor 6 can also be formed by Fig. 3 or Fig. 9 is used. A short-circuit condition detector 7, formed by a voltage comparator, outputs a determination signal S0 based on the comparison between the current difference signal VDig from the subtractor 6 and a reference voltage VR2 from the reference voltage generator 17b.

[0073] The reference voltage generator 17b generates a reference voltage VR2 that is different from that generated by the reference voltage generator 17a. Similar to the reference voltage generator 17a, the reference voltage generator 17b can also be formed by a voltage divider, a three-terminal regulator, or the like. The behavior of the gate current in the power semiconductor element (IGBT) 100 will be described below with reference to Fig. 11 and Fig. 12 described.

[0074] In Fig. 11 and Fig. 12, the horizontal axis shows a common time axis, on which one scale division corresponds to 1 µs. In Fig. 11 and Fig. 12, each of the gate current Ig, its delay current dIg, and a current difference (Ig - dIg) therebetween is further represented on the basis of a current value.

[0075] In other words: In the Fig. The circuit shown in Figure 10 makes it possible to determine that the fault occurs during hard switching based on the above-described detection signal Vig, the delay signal dVig and the current difference signal VDig, which represent voltage values ​​corresponding to their respective current values.

[0076] Fig. 11 shows the simulation result of the gate current in the same turn-on process as that in Fig. 6. More specifically: Fig. Figure 11 further shows the simulation waveforms of the gate current Ig during normal operation, the gate current Ig* under the hard switching fault, and the delay currents dIg and dIg*. As can be seen from the comparison between the gate currents Ig and Ig*, a mirror period occurs from time tc during normal operation, but the gate current continuously decreases without a mirror period under the hard switching fault.

[0077] It should be noted that the time tc is considered to be the same time as the time ta in the gate-emitter voltage waveform ( Fig. 6 and Fig. 7) is defined.

[0078] The delay currents dIg and dIg* show the simulation result when the gate currents Ig and Ig* are input to the delay signal generator 5 ( Fig. 2). Also in the second embodiment, the delay time in the delay signal generator 5 must be appropriately set so that there is a difference in the peak value of the current difference signal between normal operation and the hard switching error.

[0079] More specifically, regarding the gate current, the level of the current difference signal under the hard switching fault cannot be guaranteed if the delay time is longer than the elapsed period from when the gate current Ig reaches the maximum value in normal operation to the end of the mirror period during which the gate current is kept approximately constant (Tp2 in Fig. 11; approximately 2.0 µs).

[0080] In the examples in Fig. 11 and Fig. 12 is the delay signal generator 5 ( Fig. 2) by a first-order time delay system formed by an RC filter, and the delay time is set to correspond to a time constant of 800 ns, thereby setting the delay time to be shorter than the elapsed time Tp2 described above. This consequently causes a suitable difference in the peak value of the voltage difference signal between normal operation and the hard switching fault, as shown in Fig. 6 and Fig. 7. With reference to Fig. 12, the current difference Id is calculated from the difference (Ig - dIg) between a delay current dIg and the gate current Ig in normal operation, as in Fig. 11 shown.

[0081] On the other hand, a current difference ID* is calculated from the difference (Ig - dIg*) between the delay current dIg* and the gate current Ig* under the hard switching error, as shown in Fig. 11 shown.

[0082] At time ta and thereafter, a difference in behavior occurs between the current differences ID and ID*. More precisely, the current difference ID in the normal state is kept approximately constant at time ta and after time tc. In contrast, the current difference ID* drops under the fault during hard switching at time tc and thereafter, and then it begins to rise. Consequently, the peak value (i.e., the minimum value) in the negative current range of the current difference ID* should exist in the current range that the current difference ID does not reach during the turn-on process. As shown in Fig. 12, a reference current IR for detecting a hard switching fault can therefore be specified between the current difference value (ID* = ID) at time tc and the peak value of ID*.

[0083] Even if a gate current is detected, the occurrence of a hard switching failure can be detected based only on the peak value of the current difference signal from the subtractor 6 without having to combine timing conditions as in the first embodiment.

[0084] With further reference to Fig. 10, the following applies: When the current difference signal VDig becomes lower than the reference voltage VR2, the short-circuit condition detector 7 sets the determination signal S0 at the H level. Taking into account the gain increase and the like in the subtractor 6, the reference voltage VR2 is adjusted according to the reference current IR ( Fig. 12).

[0085] In addition, the peak value of the current difference in Fig. 12 negative. In the configuration in Fig. 10, however, the destinations into which the delay signal dVig and the current difference signal VDig are input are swapped with each other in the subtractor 6 ( Fig. 3 or Fig. 9), with the result that the current difference signal VDig can also be generated according to the current difference, so that the peak value becomes positive. In this case, the targets in the short-circuit condition detector 7, to which the current difference signal VDig and the reference voltage VR2 are input, are swapped. The reference voltage VR2 is also set to a positive voltage.

[0086] If the polarity of the current difference signal VDig is the same as those in Fig. 12, and when the reference voltage VR2 is a negative voltage, the short-circuit condition detector 7 outputs the determination signal S0 at an H level during the period of VDig < VR2. Conversely, when the polarity of the current difference signal VDig is inverted and the reference voltage VR2 is a positive voltage, the short-circuit condition detector 7 outputs the determination signal S0 at an H level during the period of VDig > VR2. By appropriately inverting the polarity (+ / - terminal) of the input to the voltage comparator constituting the short-circuit condition detector 7, the determination signal S0 with the same polarity as in the first embodiment can be generated.

[0087] In this way, in the drive control circuit for the power semiconductor element in the present second embodiment, even if the gate current is detected as an "electrical quantity at the control terminal," the occurrence of a hard switching failure can be detected immediately and accurately, as in the first embodiment in which a gate-emitter voltage is detected. In other words, the hard switching failure can also be detected by detecting only a gate current without having to combine timing conditions.

[0088] Furthermore, in response to the determination signal S0, each of the sample-and-hold unit 18 and the short-circuit protection circuit 8 operates in the same manner as in the first embodiment, thereby turning off the power semiconductor element 100 according to the operation of the soft turn-off unit 9. This allows the power semiconductor element 100 to be protected. [First modification of the second embodiment]

[0089] Fig. 13 is a block diagram showing the configuration of a drive control circuit for a power semiconductor element according to the first modification of the second embodiment of the present invention.

[0090] When comparing Fig. 13 with Fig. 10, the drive control circuit 53 according to the first modification of the second embodiment differs from the drive control circuit 52 according to the second embodiment in that the drive control circuit 53 further includes a determination period setting unit 25.

[0091] Since the configurations of other sections in the driver control circuit 53 are the same as those in the driver control circuit 52, their detailed description will not be repeated here. The determination period setting unit 25 generates a signal Sw for specifying a period for a determination made by the short-circuit condition detector 7.

[0092] During the period in which the signal Sw is at an H level, the short-circuit condition detector 7 operates as shown in the second embodiment. When the current difference signal VDig exceeds the reference voltage VR2, the short-circuit condition detector 7 outputs the determination signal S0 at an H level. On the other hand, during the period in which the signal Sw is at an L level, the short-circuit condition detector 7 outputs the determination signal S0 at an L level.

[0093] Fig. 14 is a waveform diagram for illustrating the operation of the determination period setting unit 25. Fig. 14 shows the correspondence relationship between the current behaviors (a gate current, a delay current and a current difference) similar to Fig. 11 and Fig. 12 and a signal Sw from the determination period setting unit 25. With reference to Fig. 14, the signal Sw is set to an H level for specifying the determination period, namely in the period from time ts at which a switch-on command is issued to time tx.

[0094] Then, at time tx and thereafter, the signal Sw is set to an L level.

[0095] The time tx is set to correspond to the end timing of the mirror period, during which the gate current Ig is kept approximately constant in the normal state. The current difference ID becomes lower after time tx than before time tx, so that the difference between the reference current IR and the peak value of the current difference ID is small in the normal state. On the other hand, the negative peak value (minimum value) of the current difference ID* in the hard switching fault occurs before time tx. In addition, by considering the collector-emitter voltage Vce ( Fig. 4) as a voltage difference between the “main terminals”, the time tx can be set to a similar timing as the above, so that the period until time tx is set to be shorter than the elapsed period until when the collector-emitter voltage Vce becomes lower than a prescribed voltage.

[0096] By setting the signal Sw so that the period at and after time tx is excluded from the determination period, the possibility of erroneous detection of a hard switching failure can be reduced. Thus, according to the driver control circuit in the first modification of the present second embodiment, the determination period is limited, so that erroneous detection of the hard switching failure can be further prevented, in addition to the effect of the driver control circuit according to the second embodiment. [Second modification of the second embodiment]

[0097] Fig. 15 is a block diagram showing the configuration of a drive control circuit for a power semiconductor element according to the second modification of the second embodiment of the present invention.

[0098] When comparing Fig. 15 with Fig. 10, a drive control circuit 54 according to the second modification of the second embodiment differs from the drive control circuit 52 according to the second embodiment in that the drive control circuit 54 has a voltage across the gate resistance detector 16 instead of the gate current detector 15. Since the configurations of other portions in the drive control circuit 54 are the same as those in the drive control circuit 52, their detailed description will not be repeated here.

[0099] The voltage across the gate resistance detector 16 detects a voltage across the gate resistance 2a through which a current flows when the power semiconductor element is turned on, thereby equivalently detecting the gate current. Therefore, as with the subtractor 6 for calculating the voltage difference, the voltage across the gate resistance detector 16 can be obtained from a subtraction circuit obtained by differential amplification, as shown in Fig. 3, or formed from the measuring amplifier, as shown in Fig. 6. More precisely: When configuring in Fig. 3 or Fig. 6, the voltage at one end connected to the gate terminal side of the gate resistor 2a is input as an input voltage Va, and the voltage at the other end connected to the voltage driving side of the gate resistor 2a is input as an input voltage Vb, with the result that the detection signal Vig according to the gate current can be obtained as an output voltage Vc.

[0100] In the same manner as the driver control circuit 52 according to the second embodiment, the driver control circuit 54 can also detect the hard switching failure by using the detection signal Vig from the voltage across the gate resistance detector 16.

[0101] In addition, in combination with the first modification and the second modification of the second embodiment, the determination period setting unit 25 shown in Fig. 13, may be arranged in the driver control circuit 54, and the short-circuit condition detector 7 may also be operated only during a period during which the signal Sw is at an H level. [Third Embodiment]

[0102] In the third embodiment, the configuration for outputting the hard switching failure detection information outside the driver control circuit is explained, according to the first and second embodiments and their modifications. By outputting this information outside the driver control circuit, this information can be used, for example, to identify the cause of the failure in the power semiconductor element.

[0103] Fig. 16 is a block diagram showing the configurations of a power semiconductor element and its drive control circuit according to the third embodiment of the present invention. Referring to Fig. 16, the following applies: The driver control circuit 61 according to the third embodiment differs from the driver control circuit 51 ( Fig. 1) according to the first embodiment in that the driver control circuit 61 further comprises an output unit 91 and an output terminal PD.

[0104] The output unit 91 outputs a signal S1 from a sample-and-hold unit 18. As shown in Fig. As shown in Figure 8, signal S1 is set to an H level after the hard switching failure is detected. The output terminal PD is configured to be capable of electrical contact with the outside of the driver control circuit 61. Therefore, according to the driver control circuit in the third embodiment, by monitoring the voltage at the output terminal PD from the outside of the driver control circuit 61, it can be detected that the hard switching failure has occurred in the power semiconductor element 100.

[0105] The output unit 91 may output the output signal S1 showing the detection result of the hard switching failure as an analog signal, or it may output the digital signal according to the signal S1.

[0106] In other words, the output unit 91 may also be configured to output to the output terminal PD a “0” value indicating a normal state or a “1” value indicating a hard switching error.

[0107] [First modification of the third embodiment] Fig. 17 is a block diagram showing the configuration of a drive control circuit for a power semiconductor element according to the first modification of the third embodiment of the present invention.

[0108] With reference to Fig. 17, the driver control circuit 62 according to the first modification of the third embodiment differs from the driver control circuit 51 ( Fig. 1) according to the first embodiment in that the driver control circuit 62 further comprises a signal processor 92, an output unit 93, an output terminal PD, and a selection terminal PDS. In other words, the driver control circuit 62 differs from the driver control circuit 61 ( Fig. 16) in that the driver control circuit 62 further comprises a signal processor 92 and a selection terminal PDS.

[0109] The selection terminal PDS receives an input of a selection signal SL from outside the driver control circuit 62 (for example, from a controller not shown). The selection signal SL is used to select the data to be output from the output terminal PD and is configured, for example, by a 2-bit digital signal. In response to the voltage difference signal VD from the subtractor 6, the signal processor 92 outputs a signal Sx indicating its peak value.

[0110] For example, the signal Sx is an analog signal that has a voltage according to the peak value (the maximum value or the minimum value). As described with reference to Fig. As described in Figure 7, with respect to the voltage difference signal VD, its maximum value is extracted as a peak value so that the hard switching error can be detected. For example, the signal processor 92 may be formed from a peak hold circuit.

[0111] Fig. Fig. 18 is a table showing the correspondence relationship between the selection signal SL and output data from the output terminal PD. Referring to Fig. 18, the following applies: When the selection signal SL is “00”, the output unit 93 does not output any data to the output terminal PD.

[0112] When the selection signal SL is "01," the output unit 93 outputs the signal S1 from the sample-and-hold unit 18 to the output terminal PD. When the selection signal SL is "10," the output unit 93 outputs the signal Sx from the signal processor 92 to the output terminal PD. When the selection signal SL is "11," the output unit 93 outputs both the signal S1 and the signal Sx serially to the output terminal PD.

[0113] Fig. Fig. 19 is a diagram showing an example of the output of an analog signal from the output terminal PD in the driver control circuit 62 according to the first modification of the third embodiment. Referring to Fig. 19(a), when the selection signal is “01”, the output unit 93 outputs a pulse signal 151 having a duty ratio DT1 that varies according to the level of the signal S1.

[0114] In other words, the pulse signal 151 is generated such that an H-level period t is T × DT1 in one cycle T.

[0115] With reference to Fig. 19(b), when the selection signal is "10," the output unit 93 outputs a pulse signal 152 with a duty ratio DT2 that varies according to the signal Sx indicating the peak value of the voltage difference signal VD. In other words, the pulse signal 152 is generated such that the H-level period t is T × DT2 in the cycle T.

[0116] For example, the duty cycle DT2 is calculated by dividing a peak value (Sx) by a prescribed voltage Vx. For example, the prescribed voltage Vx may be specified to be higher than the reference voltage VR1.

[0117] With reference to Fig. 19(c), when the selection signal is "11", the output unit 93 outputs serial pulse signals including the pulse signal 151 as the first pulse and the pulse signal 152 as the second pulse. Fig. 20 shows an output signal (digital) from the output terminal PD at the time when the selection signal is “10”.

[0118] With reference to Fig. 20, when the selection signal SL is "10", the output unit 93 generates a serial signal including a start bit, a plurality of bits obtained by A / D converting a signal Sx (peak value) from the signal processor 92, and a stop bit.

[0119] The serial signal is output from the output terminal PD. In the example in Fig. 20, the signal Sx is converted into a 6-bit digital signal (zeroth bit b0 to fifth bit b5).

[0120] In addition, the A / D conversion of the peak value of the voltage difference signal VD may be performed in the signal processor 92. In this case, the signal processor 92 outputs the signal Sx as a multi-bit digital signal obtained by performing the A / D conversion of the peak value.

[0121] Fig. 21 shows an output signal (digital) from the output terminal PD at the time when the selection signal is "11". Referring to Fig. 21, when the selection signal SL is "11", the output unit 93 generates a serial signal including: a start bit; a 1-bit digital signal obtained by performing A / D conversion of the signal S1 from the sample and hold unit 18; a digital signal obtained by performing A / D conversion of the signal Sx (peak value) from the signal processor 92 into multiple bits; and a stop bit.

[0122] The serial signal is output from the output terminal PD. In the example in Fig. 21, the signal S1 is output using a sixth bit b6, and the signal Sx is output using 6 bits (zeroth bit b0 to fifth bit b5) as shown in Fig. 20.

[0123] Again, if the selection signal SL is "00," the output unit 93 does not output a signal to the output terminal PD. Furthermore, if the selection signal SL is "01," the output unit 91 generates a serial signal at the output terminal PD. This serial signal includes: a start bit; a 1-bit digital signal corresponding to the sixth bit b6 in Fig. 20; and a stop bit. In this way, according to the driver control circuit in the first modification of the third embodiment, the detection result of the hard switching failure (S1) and / or the peak value of the difference signal (Sx) can be selectively read out by means of the selection signal SL input to the selection terminal PDS.

[0124] In particular, not only the detection result (ie: hard switching failure or not), but also by reading the peak value of the voltage difference signal VD from outside, so that the peak value can be used, for example, to identify the nature of the failure in the power semiconductor element. [Second modification of the third embodiment]

[0125] Fig. 22 is a block diagram showing the configuration of a drive control circuit for a power semiconductor element according to the second modification of the third embodiment of the present invention.

[0126] With reference to Fig. 22, the driver control circuit 63 according to the second modification of the third embodiment differs from the driver control circuit 51 according to the first embodiment ( Fig. 1) in that the driver control circuit 63 further comprises a signal processor 92, an output unit 94, an output terminal PD, a selection terminal PDS, and a selection terminal PS. More specifically, the driver control circuit 63 differs from the driver control circuit 62 ( Fig. 17) in that it also has the selection connection PS.

[0127] The selection terminal PS receives an input of a 1-bit selection signal SE from outside the driver control circuit 62. The selection terminal PDS receives the input of a 2-bit selection signal SL as in the first modification of the third embodiment. The selection signal SE is used to designate an analog signal ( Fig. 19) or a digital signal ( Fig. 20 and Fig. 21) is used as an output signal from the output unit 94.

[0128] For example, if the selection signal SE is “1”, the output unit 94 outputs the detection result of the hard switching error (S1) and / or the peak value of the difference signal (Sx) in an analog signal format as shown in Fig. 19, according to the correspondence relationship shown in Fig. 19. When the selection signal SE is “0”, the output unit 94 outputs the detection result of the hard switching error (S1) and / or the peak value of the difference signal (Sx) in a digital signal format as shown in Fig. 22, Fig. 23 and the like, according to the correspondence relationship shown in Fig. 19 is shown.

[0129] In this way, according to the driver control circuit in the second modification of the third embodiment, the hard switching failure detection result (S1) and / or the peak value of the differential signal (Sx) can be output in an analog signal format or a digital signal format by the selection signal input to the selection terminal PS. Consequently, the flexibility of the driver control circuit for failure analysis of the power semiconductor element is improved.

[0130] In each of the third embodiment and its modification, the configuration of the driver control circuit 51 ( Fig. 1) according to the first embodiment for outputting the information (signal S1 and / or Sx) about the detection of the hard switching error to the outside. Such a configuration can be similarly applied to the driver control circuit described in each of the first and second embodiments and their modifications. Furthermore, each of the embodiments and their modifications can also be configured such that the operation of the soft-off unit 9 (turning off the semiconductor switch 24 ( Fig. 1)) and the switching off of the power semiconductor element 100 can be instructed from outside the driver control circuit.

[0131] In other words, the short-circuit protection circuit 8 within the driver control circuit may also be configured to instruct only the operation of the soft-turn-off unit 9 and the turning-off of the power semiconductor element 100.

[0132] Furthermore, in the present embodiment, a voltage control type element (IGBT) having a gate as a control terminal was described as the power semiconductor element. However, the drive control circuit according to each of the embodiments and their modifications can also be applied to a current control type element such as a bipolar transistor. The present invention can also be applied to any current control type element as long as a distinguishable difference in the peak value of the difference signal occurs between the normal state and the fault in hard switching, in which case the peak value of the difference signal is between the detection signal of the electrical quantity (e.g., a voltage or a current) in the control terminal (base) in the on-state and its delay signal.

[0133] It is to be understood that the embodiments disclosed herein are illustrative and non-restrictive in all respects. The scope of the present invention is defined by the language of the claims rather than by the above description, and is intended to include any modifications within the meaning and scope equivalent to the language of the claims. List of reference symbols 2a, 2b, 2c Gate resistance 3 voltage drivers 4 Gate voltage detector 5 Delay signal generator 6 subtractors 7 Short circuit condition detector 8 Short-circuit protection circuit 9 Soft shutdown unit 10 Control command unit 11 Resistor (signal delay circuit) 12 Capacitor (signal delay circuit) 13, 14a to 14c operational amplifiers 15 Gate current detector 16 Voltage across the gate resistance detector 17a, 17b reference voltage generator 18 Sample and hold unit 19, 20 voltage nodes 21, 22, 24 semiconductor switches 23 inverters 25 Determination period setting unit 51 to 54, 61 to 63 driver control circuit 91, 93, 94 Output unit 92 Signal processor 100 power semiconductor elements 101 Gate 102 collector 103 emitters 151, 152 pulse signal DT1, DT2 duty cycle (pulse signal) ID current difference IR reference current Ic collector current Ig gate current PD output connector PDS, PS selection connection R0 to R7 resistor (subtractor) S0 determination signal S1 signal (sample and hold unit) S2 protection signal SE, SL selection signal Sg control signal Sw Signal (determination period setting unit) Sx signal (peak value) T cycle VD voltage difference signal VDig current difference signal VG, Vig detection signal VR1, VR2 reference voltage (short circuit condition detector) Va, Vb input voltage (subtractor) Vc output voltage (subtractor) Vce collector-emitter voltage Vg gate voltage Vn negative bias Vp positive bias dIg delay current dVG, dVig delay signal dVg Delay voltage

Claims

[1] Driver control circuit (51-54, 61-63) for a power semiconductor element (100) having a control terminal (101), the driver control circuit comprising: a driver (3) for causing a voltage shift at the control terminal in response to a turn-on command or a turn-off command; a detector (4, 15, 16) configured to detect an electrical quantity (Vg, Ig) of the control terminal; a delay signal generator (5) configured to generate a delay signal (dVG, dVig) by adding a delay time to a detection signal (VG, Vig) of the electrical quantity detected by the detector; a subtractor (6) configured to generate a difference signal (VD, VDig) between the detection signal and the delay signal; and a short-circuit condition detector (7) configured to detect a short-circuit condition in the power semiconductor element based on a comparison result between the difference signal and a reference value (VR1, VR2) when the driver is operated in response to the turn-on command. [2] A driver control circuit (51-54, 61-63) for a power semiconductor element (100) according to claim 1, wherein when a maximum value of the difference signal (VD, VDig) exceeds the reference value (VR1, VR2) or when a minimum value of the difference signal becomes lower than the reference value, the short-circuit condition detector detects the short-circuit condition. [3] A drive control circuit (51-54, 61-63) for a power semiconductor element (100) according to claim 1, further comprising a sample-and-hold unit (18) configured to, when a first level as a ground state is shifted to a second level in response to detection of the short-circuit state by the short-circuit state detector (7), output a signal (SI) holding the second level. [4] A drive control circuit (51-54, 61-63) for a power semiconductor element (100) according to claim 1, further comprising a short-circuit protection circuit (8) configured to generate the turn-off command in response to the detection of the short-circuit condition by the short-circuit condition detector (7). [5] A driver control circuit (51-54, 61-63) for a power semiconductor element (100) according to claim 1, further comprising a soft turn-off unit (9) configured to reduce the speed for shifting the electrical quantity (Vg, Ig) by the driver (3) in response to the turn-off command, the soft turn-off unit operating in response to the detection of the short-circuit condition by the short-circuit condition detector (7). [6] Driver control circuit (51) for a power semiconductor element (100) according to one of claims 1 to 5, wherein the power semiconductor element is a voltage control type element having the control terminal and two main terminals (102, 103), wherein the control terminal serves as a gate (101), the driver (3) is configured to shift a voltage at the gate to a first voltage (Vp) in response to the turn-on command and to shift the voltage at the gate to a second voltage (Vn) in response to the turn-off command, and the electrical quantity is a gate-emitter voltage (Vg). [7] A driver control circuit (51) for a power semiconductor element (100) according to claim 6, wherein the delay time in the delay signal generator (5) is set to be shorter than an elapsed time (Tp1) during which the gate-emitter voltage (Vg) changes from the second voltage (Vn) to the first voltage (Vp) by the driver (3) in response to the turn-on command in a non-short-circuit state. [8] Driver control circuit (52-54) for a power semiconductor element (100) according to one of claims 1 to 5, wherein the power semiconductor element is a voltage control type element having the control terminal and two main terminals (102, 103), the control terminal serving as a gate (101), the driver (3) acting to shift a voltage at the gate to a first voltage (Vp) in response to the turn-on command and to shift the voltage at the gate to a second voltage (Vn) in response to the turn-off command, and the electrical quantity is a gate current (Ig). [9] A driver control circuit (52-54) for a power semiconductor element (100) according to claim 8, wherein the delay time in the delay signal generator is set to be shorter than an elapsed time (Tp2) from the time when the turn-on command is generated to the time when a voltage across the two main terminals (102, 103) of the power semiconductor element (100) drops to a prescribed voltage in a state in which the driver (3) operates in a non-short-circuit state in response to the turn-on command. [10] A drive control circuit (53) for a power semiconductor element (100) according to claim 8, further comprising a determination period setting unit (25) configured to set a determination period during which the short-circuit state detector (7) detects the short-circuit state, wherein the determination period setting unit is configured to set, as the determination period, a period from a time point at which the turn-on command is generated in a non-short-circuit state to a time point at which a voltage across the two main terminals (102, 103) of the power semiconductor element drops to a prescribed voltage. [11] A driver control circuit (61) for a power semiconductor element (100) according to any one of claims 1 to 5, further comprising: an output unit (91) configured to output a signal (SI) indicating a determination result obtained by the short-circuit condition detector (7); and an output port (PD) configured to output a signal from the output unit to the outside. [12] Driver control circuit (62) for a power semiconductor element (100) according to one of claims 1 to 5, further comprising: a signal processor (92) for generating a first signal (Sx) indicative of a peak value which is a maximum value or a minimum value of the difference signal (VD, VDig) in response to the difference signal from the subtractor; a selection terminal (PDS) for inputting - from outside the driver control circuit - a signal (SL) for designating at least one of the first signal and a second signal (SI) to be output, the second signal indicating the determination result obtained by the short-circuit condition detector (7); an output unit (93) configured to output at least one signal, designated as the signal to be output, among the first signal and the second signal in response to an input signal (SL) to the selection terminal; and an output terminal (PD) configured to output a signal from the output unit to the outside of the driver control circuit. [13] Driver control circuit (63) for a power semiconductor element (100) according to claim 12, wherein the first signal (Sx) is a digital signal having a plurality of bits and obtained by an analog-to-digital conversion of the peak value, the second signal (SI) is a digital signal indicating the determination result, and the output terminal (PD) is configured to output a serial signal comprising the first signal and the second signal to the outside of the driver control circuit when the input signal (SL) designating the first signal and the second signal as the signal to be output is input to the selection terminal (PDS).

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