Nitride semiconductor device, method for manufacturing nitride semiconductor device, and epitaxial substrate

Abstract

To provide a nitride semiconductor device, a method for manufacturing the nitride semiconductor device and an epitaxial substrate that can achieve both suppression of current collapse and high electron mobility.SOLUTION: A nitride semiconductor device comprises: a substrate; a buffer layer provided on the substrate; a channel layer provided on the buffer layer; a barrier layer provided on the channel layer; and a source electrode, a gate electrode and a drain electrode provided on the barrier layer. The channel layer includes: a first layer with a carbon concentration of 1×1017 cm-3 or higher; and a second layer provided on the first layer with a carbon concentration of 2×1016 cm-3 or lower. The thickness of the first layer is set to 20% or less of the thickness of the channel layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a nitride semiconductor device, a method for manufacturing a nitride semiconductor device, and an epitaxial substrate. [Background technology]

[0002] Nitride semiconductors have characteristics such as a high saturation electron velocity and a wide band gap. For this reason, various studies are being conducted on the application of nitride semiconductors to semiconductor devices with high voltage resistance and high output by utilizing these characteristics. For example, the band gap of GaN, a type of nitride semiconductor, is 3.4 eV, which is larger than the band gap of Si (1.1 eV) and the band gap of GaAs (1.4 eV). For this reason, GaN has a high breakdown electric field strength and is extremely promising as a material for semiconductor devices for power supplies that operate at high voltages and obtain high output.

[0003] As semiconductor devices using nitride semiconductors, there have been many reports on field effect transistors, especially high electron mobility transistors (HEMTs). For example, in the case of GaN-based HEMTs, AlGaN / GaN-HEMTs that use GaN as the channel layer and AlGaN as the barrier layer have attracted attention.

[0004] For GaN-based HEMTs, techniques aimed at reducing off-leakage current and techniques aimed at improving electrical breakdown characteristics have been proposed. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2016-213507 A [Patent Document 2] JP 2016-076681 A [Patent Document 3] U.S. Patent No. 9,608,075 [Patent Document 4] US Patent Application Publication No. 2021 / 0050422 Summary of the Invention [Problem to be solved by the invention]

[0006] However, in the conventional technology, when the channel layer is thinned to reduce the off-leak current, it is difficult to simultaneously suppress the current collapse and ensure high electron mobility.

[0007] An object of the present disclosure is to provide a nitride semiconductor device, a manufacturing method for a nitride semiconductor device, and an epitaxial substrate that can simultaneously suppress current collapse and ensure high electron mobility. [Means for solving the problem]

[0008] According to one embodiment of the present disclosure, a semiconductor device includes a substrate, a buffer layer provided on the substrate, a channel layer provided on the buffer layer, a barrier layer provided on the channel layer, and a source electrode, a gate electrode, and a drain electrode provided on the barrier layer, the channel layer having a carbon concentration of 1×10 17 cm -3 a first layer having a carbon concentration of 2×10 or more; 16 cm -3 and a second layer having a thickness of not more than 20% of a thickness of the channel layer, wherein the thickness of the first layer is not more than 20% of a thickness of the channel layer. Effect of the Invention

[0009] According to the present disclosure, it is possible to both suppress current collapse and ensure high electron mobility. [Brief description of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view showing a structure of a nitride semiconductor device according to a first embodiment. [Diagram 2]1A to 1C are cross-sectional views (part 1) illustrating a method for manufacturing a nitride semiconductor device according to a first embodiment. [Diagram 3] 5A to 5C are cross-sectional views (part 2) illustrating the method for manufacturing the nitride semiconductor device according to the first embodiment. [Figure 4] 5A to 5C are cross-sectional views (part 3) illustrating the method for manufacturing the nitride semiconductor device according to the first embodiment. [Diagram 5] FIG. 4 is a diagram showing the relationship between the thickness ratio of the first layer and the surface roughness Ra. [Figure 6] FIG. 13 is a graph showing the relationship between the thickness ratio of the first layer and the collapse rate. [Figure 7] FIG. 1 shows the results of a simulation. [Figure 8] FIG. 2 shows the results of the simulation. [Figure 9] FIG. 13 is a diagram showing a discrete package according to a second embodiment. [Figure 10] FIG. 11 is a wiring diagram showing a PFC circuit according to a third embodiment. [Figure 11] FIG. 13 is a wiring diagram showing a power supply device according to a fourth embodiment. [Figure 12] FIG. 13 is a wiring diagram showing an amplifier according to a fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The present inventors have conducted intensive research to determine the reason why it is difficult to simultaneously suppress current collapse and ensure high electron mobility when the channel layer is thinned in a conventional nitride semiconductor device. As a result, it has been found that when the channel layer is simply thinned, it is difficult to obtain good flatness on the surface of the channel layer, electrons are easily trapped, and current collapse occurs. It has also been found that, although it is possible to obtain good flatness even when the channel layer is thinned by increasing the amount of carbon (C) atoms contained in the channel layer, in this case, the carbon atoms are likely to cause electron scattering, and the electron mobility is reduced. Based on these findings, the present inventors have conducted intensive research to simultaneously suppress current collapse and ensure high electron mobility, and have come up with the following embodiment.

[0012] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In this specification and the drawings, components having substantially the same functional configurations are denoted by the same reference numerals, and redundant description may be omitted.

[0013] (First embodiment) First, a first embodiment will be described. The first embodiment relates to a nitride semiconductor device including a GaN-based HEMT, that is, a field effect transistor (FET). Fig. 1 is a cross-sectional view showing the structure of the nitride semiconductor device according to the first embodiment.

[0014] 1, the nitride semiconductor device 1 according to the first embodiment has a nitride epitaxial substrate 60. The nitride epitaxial substrate 60 has a substrate 10 and an epitaxial layer 50 of a nitride semiconductor provided on the substrate 10. The epitaxial layer 50 has, for example, an initial layer 21, a buffer layer 20, a channel layer 30, a barrier layer 40, and a cap layer 41.

[0015] The substrate 10 is, for example, a Si substrate whose upper surface is a (111) surface. The initial layer 21 is provided on the substrate 10. The initial layer 21 is, for example, an Al0.1 Ga 0.9 The buffer layer 20 is provided on the initial layer 21. The buffer layer 20 is, for example, an AlN layer having a thickness of 200 nm to 400 nm. x Ga 1-x The buffer layer 20 is an N layer. The Al composition x of the buffer layer 20 is, for example, 0.2 at the bottom surface of the buffer layer 20 and 0.8 at the top surface, and increases stepwise from the bottom surface to the top surface. For example, the buffer layer 20 is not doped with Fe. The buffer layer 20 may be doped with Fe.

[0016] The channel layer 30 is provided on the buffer layer 20. The channel layer 30 has a first layer 31 and a second layer 32. The channel layer 30 has a thickness of, for example, 50 nm to 200 nm. The first layer 31 is provided on the buffer layer 20. The first layer 31 is a GaN layer (i-GaN layer) that has a thickness of, for example, 20 nm to 40 nm and is not intentionally doped with impurities that impart a conductivity type. The first layer 31 contains carbon. The carbon concentration of the first layer 31 is 1×10 17 cm -3 The above is the case. The second layer 32 is provided on the first layer 31. The second layer 32 is, for example, a GaN layer (i-GaN layer) having a thickness of 130 nm to 180 nm and not intentionally doped with impurities that impart a conductivity type. The second layer 32 contains carbon. The carbon concentration of the second layer 32 is 2×10 16 cm -3 The thickness of the first layer 31 is 20% or less of the thickness of the channel layer 30. The band gap of the channel layer 30 is smaller than the band gap of the buffer layer 20. That is, the band gap of the buffer layer 20 is larger than the band gap of the channel layer 30.

[0017] The barrier layer 40 is provided on the channel layer 30. The barrier layer 40 is, for example, an n-type Al 0.31 Ga 0.69 The barrier layer 40 is an N layer (n-AlGaN layer). For example, Si is 5×10 18 cm -3The barrier layer 40 is doped with a concentration of about 1000 . The cap layer 41 is provided on the barrier layer 40. The cap layer 41 is, for example, a GaN layer having a thickness of 2 nm to 10 nm. The barrier layer 40 may be doped with an n-type impurity such as Si.

[0018] An isolation region that defines an element region is formed in the epitaxial layer 50, and a source electrode 70s and a drain electrode 70d are formed in the element region on the epitaxial layer 50. An insulating layer 80 that covers the source electrode 70s and the drain electrode 70d is formed on the epitaxial layer 50. A gate electrode 70g is formed on the insulating layer 80 between the source electrode 70s and the drain electrode 70d.

[0019] The source electrode 70s and the drain electrode 70d include, for example, a Ti film having a thickness of 50 nm to 150 nm and an Al film having a thickness of 100 nm to 500 nm thereon. The gate electrode 70g includes, for example, a Ni film having a thickness of 10 nm to 50 nm and an Au film having a thickness of 300 nm to 500 nm thereon. The insulating layer 80 is, for example, a film of an oxide, nitride or oxynitride of Si, Al, Hf, Zr, Ti, Ta or W, and is preferably a film of Si nitride (SiN). The thickness of the insulating layer 80 is, for example, 500 nm to 800 nm.

[0020] Next, a method for manufacturing the nitride semiconductor device 1 according to the first embodiment will be described. Figures 2 to 4 are cross-sectional views showing the method for manufacturing the nitride semiconductor device 1 according to the first embodiment.

[0021] 2, an epitaxial layer 50 including an initial layer 21, a buffer layer 20, a first layer 31, a second layer 32, a barrier layer 40, and a cap layer 41 is formed on a Si substrate 10. The epitaxial layer 50 can be formed by a crystal growth method such as a metal organic chemical vapor deposition (MOCVD) method or a molecular beam epitaxy (MBE) method.

[0022] When forming the epitaxial layer 50 by MOCVD, for example, a mixed gas of trimethylaluminum (TMA) gas as an Al source, trimethylgallium (TMG) gas as a Ga source, and ammonia (NH3) gas as an N source is used. In this case, the presence or absence of supply of TMA gas and TMG gas and the flow rate are appropriately set according to the composition of the nitride semiconductor layer to be grown. The flow rate of NH3 gas, which is a common raw material for each nitride semiconductor layer, is, for example, about 100 ccm to 10 LM.

[0023] For example, when forming a GaN layer as the first layer 31, the V / III ratio (the ratio of the flow rate of TMG gas to the flow rate of NH3 gas) in the source gas is set to 100 or less, the growth temperature is set to about 1000° C., and the pressure is set to about 10 kPa. When the first layer 31 is formed under such conditions, the carbon concentration of the first layer 31 is 1×10 17 cm -3 When the second layer 32 is formed under such conditions, the carbon concentration of the second layer 32 is 2×10 16 cm -3 The result is as follows.

[0024] Next, an element isolation region that defines an element region is formed in the epitaxial layer 50, and as shown in FIG. 3, a source electrode 70s and a drain electrode 70d are formed on the epitaxial layer 50 in the element region. The source electrode 70s and the drain electrode 70d can be formed by, for example, a lift-off method. That is, the region where the source electrode 70s is to be formed and the region where the drain electrode 70d is to be formed are exposed, and a photoresist pattern that covers the other regions is formed, and a metal film is formed by deposition using this pattern as a growth mask, and this pattern is removed together with the metal film thereon. In forming the metal film, for example, a Ti film with a thickness of 50 nm to 150 nm is formed, and an Al film with a thickness of 100 nm to 500 nm is formed thereon. Next, for example, a heat treatment (for example, rapid thermal annealing (RTA)) is performed at 400°C to 1000°C (for example, 600°C) in an N2 atmosphere to obtain an ohmic contact.

[0025] Thereafter, as shown in FIG. 4, an insulating layer 80 is formed on the epitaxial layer 50 to cover the source electrode 70s and the drain electrode 70d. The insulating layer 80 can be formed by, for example, a plasma CVD method. The insulating layer 80 may be formed by an atomic layer deposition (ALD) method or a sputtering method. Then, a gate electrode 70g is formed on the insulating layer 80 between the source electrode 70s and the drain electrode 70d. The gate electrode 70g can be formed by, for example, a lift-off method. That is, a photoresist pattern exposing a region where the gate electrode 70g is to be formed is formed, and a metal film is formed by a deposition method using this pattern as a growth mask, and this pattern is removed together with the metal film thereon. In forming the metal film, for example, a Ni film having a thickness of 10 nm to 50 nm is formed, and an Au film having a thickness of 300 nm to 500 nm is formed thereon.

[0026] In this manner, the nitride semiconductor device 1 according to the first embodiment can be manufactured.

[0027] In the nitride semiconductor device 1, a two-dimensional electron gas (2DEG) 35 is generated in the vicinity of the interface between the channel layer 30 and the barrier layer 40. In the on-state, electrons move from the source electrode 70s to the drain electrode 70d through the 2DEG 35. The electrons mainly move within the second layer 32. In the nitride semiconductor device 1, the carbon concentration in the second layer 32 is 2×10 16 cm -3 Since the valence rate is as low as or less than 100 nm, electron scattering is suppressed, and high electron mobility can be obtained.

[0028] The channel layer 30 includes a first layer 31 and a second layer 32, and the carbon concentration of the first layer 31 is 1×10 17 cm -3 Since the resistance is as high as above, good flatness can be obtained on the surface of the first layer 31. Accordingly, good flatness can also be obtained on the surface of the second layer 32. As a result, current collapse can be suppressed.

[0029] Furthermore, as will be described in detail later, the thickness of the first layer 31 is 20% or less of the thickness of the channel layer 30, so that current collapse can be easily suppressed.

[0030] In this way, according to the first embodiment, it is possible to both suppress current collapse and ensure high electron mobility.

[0031] Here, a first experiment and a second experiment conducted by the inventors of the present invention will be described.

[0032] In the first experiment, the relationship between the ratio of the thickness of the first layer 31 to the thickness of the channel layer 30 and the surface roughness Ra was investigated. In the first experiment, the thickness of the channel layer 30 was set to 200 nm, and five samples were produced in which the thicknesses of the first layer 31 and the second layer 32 were different, and the surface roughness Ra of the channel layer 30 was measured. The surface roughness Ra is the arithmetic average roughness. The results are shown in FIG. 5.

[0033] As shown in Fig. 5, when the thickness ratio of the first layer 31 is 0.5% or more, the surface roughness Ra is significantly lower than when the thickness ratio of the first layer 31 is 0%, i.e., when the first layer 31 does not exist. The lower the surface roughness Ra, the fewer electrons are trapped, and the easier it is to suppress current collapse. Therefore, in terms of surface roughness Ra, it is preferable that the thickness ratio of the first layer 31 is 0.5% or more. The thickness ratio of the first layer 31 is more preferably 5% or more.

[0034] In the second experiment, the relationship between the ratio of the thickness of the first layer 31 to the thickness of the channel layer 30 and the collapse rate was investigated. In the second experiment, the thickness of the channel layer 30 was set to 200 nm, and the collapse rate was calculated for nine conditions in which the thicknesses of the first layer 31 and the second layer 32 were different. Here, the relationship between the drain voltage and the drain current was obtained under the first condition simulating a pulse measurement and the second condition simulating a direct current (DC) measurement, and the ratio of the maximum value of the drain current under the first condition to the maximum value of the drain current under the second condition was taken as the collapse rate. Under the first condition, a pulsed stress voltage was applied to calculate the relationship between the drain voltage and the drain current. Specifically, under the first condition, a drain voltage of 50V and a gate voltage of -5V were applied to the transistor as voltages in a stress state, and the drain current was calculated when the drain voltage was changed from that stress state. Under the second condition, a DC voltage was applied, and the drain current was calculated when the drain voltage was changed without applying a stress voltage to the transistor. The results are shown in FIG. 6.

[0035] As shown in Fig. 6, when the thickness ratio of the first layer 31 is 0.5% or more, the collapse rate is higher than when the thickness ratio of the first layer 31 is 0%, i.e., when the first layer 31 does not exist. On the other hand, when the thickness ratio of the first layer 31 exceeds 20%, the collapse rate decreases as the thickness ratio of the first layer 31 increases. Therefore, in terms of the collapse rate, the thickness ratio of the first layer 31 is 20% or less, preferably 15% or less, and more preferably 10% or less. In terms of the collapse rate as well, it is preferable that the thickness ratio of the first layer 31 is 0.5% or more.

[0036] The thickness of the channel layer 30 is preferably 200 nm or less. When the thickness of the channel layer 30 is 200 nm or less, the off-leak current is easily suppressed. In the off state, the depletion layer spreads under the gate electrode 70g, and the movement of electrons through the 2DEG 35 is suppressed. However, some of the electrons may move through the portion between the end (lower end) of the depletion layer on the buffer layer 20 side and the buffer layer 20. However, when the thickness of the channel layer 30 is 200 nm or less, the depletion layer is likely to spread to the first layer 31, and carbon atoms are present at a high concentration in the portion where the electrons are intended to use as a path. In the portion where the electrons are intended to use as a path, the carbon atoms compensate for the residual electrons, so that the electrical resistance of this portion increases and the off-leak current is suppressed. Therefore, when the thickness of the channel layer 30 is 200 nm or less, the off-leak current is easily suppressed. On the other hand, when the thickness of the channel layer 30 is less than 50 nm, sufficient electron mobility may not be obtained. For this reason, the thickness of the channel layer 30 is preferably 50 nm or more. The thickness of the channel layer 30 is more preferably 100 nm or more.

[0037] Here, a simulation performed by the present inventors will be described. In this simulation, the distribution of electron density in the off state was calculated for the cases where the thickness of the channel layer 130 is 200 nm and 250 nm. FIG. 7 is a diagram showing the distribution of electron density in the off state when the thickness of the channel layer 130 is 200 nm. FIG. 8 is a diagram showing the distribution of electron density in the off state when the thickness of the channel layer 130 is 250 nm.

[0038] As shown in Fig. 7, when the thickness of the channel layer is 200 nm, substantially no electrons exist below the gate electrode 170g. This indicates that substantially no off-leak current flows between the source electrode and the drain electrode. On the other hand, as shown in Fig. 8, when the thickness of the channel layer is 250 nm, a small number of electrons exist below the gate electrode 170g. This indicates that an off-leak current may flow between the source electrode and the drain electrode.

[0039] The carbon concentration of the first layer 31 is 1×10 17 cm-3 If the carbon concentration is less than 1×10, a good surface roughness Ra may not be obtained on the surface of the channel layer 30. For this reason, the carbon concentration of the first layer 31 is set to 1×10 17 cm -3 More than 3×10 17 cm -3 More preferably, it is 5×10 17 cm -3 On the other hand, the carbon concentration of the first layer 31 is 1×10 19 cm -3 If the carbon concentration exceeds 1×10, the carbon atoms in the first layer 31 may trap electrons, resulting in increased current collapse. 19 cm -3 More preferably, it is 5×10 or less. 18 cm -3 More preferably, it is 1×10 18 cm -3 is less than.

[0040] The carbon concentration of the second layer 32 is 2×10 16 cm -3 If the carbon concentration exceeds 2×10, electron scattering may occur, and the electron mobility may decrease. 16 cm -3 or less, preferably 1×10 16 cm -3 More preferably, it is 5×10 15 cm -3 The following is the result.

[0041] The channel layer 30 may have a third layer between the first layer 31 and the second layer 32. The carbon concentration of the third layer is, for example, 2×10 16 cm -3 super 1×10 17 cm -3 The thickness of the third layer is preferably 10% or less, more preferably 5% or less, and further preferably 1% or less, of the thickness of the channel layer 30.

[0042] Second embodiment Next, a second embodiment will be described. The second embodiment relates to a discrete package of a HEMT. Fig. 9 is a diagram showing the discrete package according to the second embodiment.

[0043] In the second embodiment, as shown in Fig. 9, the back surface of a semiconductor device 1210 having a structure similar to that of the first embodiment is fixed to a land (die pad) 1233 using a die attaching agent 1234 such as solder. A wire 1235d such as an Al wire is connected to a drain pad 1226d to which a drain electrode 70d is connected, and the other end of the wire 1235d is connected to a drain lead 1232d integrated with the land 1233. A wire 1235s such as an Al wire is connected to a source pad 1226s connected to a source electrode 70s, and the other end of the wire 1235s is connected to a source lead 1232s independent from the land 1233. A wire 1235g such as an Al wire is connected to a gate pad 1226g connected to a gate electrode 70g, and the other end of the wire 1235g is connected to a gate lead 1232g independent from the land 1233. The land 1233, the semiconductor device 1210, and the like are packaged in a mold resin 1231 so that a part of the gate lead 1232g, a part of the drain lead 1232d, and a part of the source lead 1232s protrude.

[0044] Such a discrete package can be manufactured, for example, as follows. First, the semiconductor device 1210 is fixed to the land 1233 of the lead frame using a die attaching agent 1234 such as solder. Next, by bonding using wires 1235g, 1235d, and 1235s, the gate pad 1226g is connected to the gate lead 1232g of the lead frame, the drain pad 1226d is connected to the drain lead 1232d of the lead frame, and the source pad 1226s is connected to the source lead 1232s of the lead frame. After that, sealing is performed using the molding resin 1231 by the transfer molding method. Then, the lead frame is separated.

[0045] Third embodiment Next, a third embodiment will be described. The third embodiment relates to a PFC (Power Factor Correction) circuit equipped with a HEMT. Fig. 10 is a wiring diagram showing a PFC circuit according to the third embodiment.

[0046] The PFC circuit 1250 includes a switch element (transistor) 1251, a diode 1252, a choke coil 1253, capacitors 1254 and 1255, a diode bridge 1256, and an AC power supply (AC) 1257. The drain electrode of the switch element 1251 is connected to the anode terminal of the diode 1252 and one terminal of the choke coil 1253. The source electrode of the switch element 1251 is connected to one terminal of the capacitor 1254 and one terminal of the capacitor 1255. The other terminal of the capacitor 1254 is connected to the other terminal of the choke coil 1253. The other terminal of the capacitor 1255 is connected to the cathode terminal of the diode 1252. A gate driver is connected to the gate electrode of the switch element 1251. The AC 1257 is connected between both terminals of the capacitor 1254 via the diode bridge 1256. A direct current power supply (DC) is connected between both terminals of the capacitor 1255. In this embodiment, a semiconductor device having the same structure as in the first embodiment is used for the switch element 1251.

[0047] When manufacturing the PFC circuit 1250, the switch element 1251 is connected to the diode 1252 and the choke coil 1253, etc., using, for example, solder or the like.

[0048] (Fourth embodiment) Next, a fourth embodiment will be described. The fourth embodiment relates to a power supply device equipped with a HEMT, suitable for a server power supply. Fig. 11 is a wiring diagram showing the power supply device according to the fourth embodiment.

[0049] The power supply device is provided with a high-voltage primary circuit 1261 , a low-voltage secondary circuit 1262 , and a transformer 1263 disposed between the primary circuit 1261 and the secondary circuit 1262 .

[0050] The primary side circuit 1261 is provided with a PFC circuit 1250 according to the third embodiment, and an inverter circuit, for example, a full-bridge inverter circuit 1260, connected between both terminals of a capacitor 1255 of the PFC circuit 1250. The full-bridge inverter circuit 1260 is provided with a plurality of (four in this case) switch elements 1264a, 1264b, 1264c, and 1264d.

[0051] The secondary side circuit 1262 is provided with a plurality of (three in this case) switch elements 1265a, 1265b, and 1265c.

[0052] In this embodiment, semiconductor devices having the same structure as in the first embodiment are used for the switch element 1251 of the PFC circuit 1250 constituting the primary side circuit 1261, and the switch elements 1264a, 1264b, 1264c, and 1264d of the full bridge inverter circuit 1260. On the other hand, normal MIS type FETs (field effect transistors) using silicon are used for the switch elements 1265a, 1265b, and 1265c of the secondary side circuit 1262.

[0053] Fifth embodiment Next, a fifth embodiment will be described. The fifth embodiment relates to an amplifier including a HEMT. Fig. 12 is a wiring diagram showing the amplifier according to the fifth embodiment.

[0054] The amplifier includes a digital predistortion circuit 1271, mixers 1272a and 1272b, and a power amplifier 1273.

[0055] The digital predistortion circuit 1271 compensates for nonlinear distortion of the input signal. The mixer 1272a mixes the input signal, the nonlinear distortion of which has been compensated for, with an AC signal. The power amplifier 1273 includes a semiconductor device having a structure similar to that of the first embodiment, and amplifies the input signal mixed with the AC signal. In this embodiment, for example, by switching a switch, the output side signal can be mixed with the AC signal by the mixer 1272b and sent to the digital predistortion circuit 1271. This amplifier can be used as a high-frequency amplifier or a high-output amplifier. The high-frequency amplifier can be used, for example, in a transmitting / receiving device for a mobile phone base station, a radar device, and a microwave generating device.

[0056] In the present disclosure, the substrate may be a silicon carbide (SiC) substrate, a sapphire substrate, a silicon substrate, an AlN substrate, a GaN substrate, or a diamond substrate. The substrate may be conductive, semi-insulating, or insulating.

[0057] The structures of the gate electrode, source electrode, and drain electrode are not limited to those in the above-mentioned embodiment. For example, they may be composed of a single layer. Furthermore, the method of forming them is not limited to the lift-off method. Furthermore, if ohmic characteristics can be obtained, the heat treatment after the formation of the source electrode and drain electrode may be omitted. Heat treatment may be performed after the formation of the gate electrode.

[0058] As the structure of the gate electrode, a MIS (metal-insulator-semiconductor) type gate structure is used in the above embodiment, but a Schottky type gate structure may also be used.

[0059] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims.

[0060] Various aspects of the present disclosure are summarized below as appendices.

[0061] (Appendix 1) A substrate; a buffer layer provided on the substrate; a channel layer provided on the buffer layer; a barrier layer provided on the channel layer; a source electrode, a gate electrode and a drain electrode provided on the barrier layer; having The channel layer is Carbon concentration is 1×10 17 cm -3 The first layer is as above, A carbon layer having a carbon concentration of 2×10 16 cm -3 A second layer, having The nitride semiconductor device has a thickness of the first layer that is 20% or less of a thickness of the channel layer. (Appendix 2) 2. The nitride semiconductor device according to claim 1, wherein the channel layer has a thickness of 200 nm or less. (Appendix 3) 3. The nitride semiconductor device according to claim 1, wherein the buffer layer has a band gap larger than a band gap of the channel layer. (Appendix 4) 4. The nitride semiconductor device according to claim 1, wherein the first layer has a thickness of 0.5% or more of a thickness of the channel layer. (Appendix 5) A substrate; a buffer layer provided on the substrate; a channel layer provided on the buffer layer; a barrier layer provided on the channel layer; having The channel layer is Carbon concentration is 1×10 17 cm -3 The first layer is as above, A carbon layer having a carbon concentration of 2×10 16 cm -3 A second layer, having A nitride epitaxial substrate, wherein the first layer has a thickness that is 20% or less of the thickness of the channel layer. (Appendix 6) 6. The nitride epitaxial substrate according to claim 5, wherein the channel layer has a thickness of 200 nm or less. (Appendix 7) 7. The nitride epitaxial substrate according to claim 5, wherein the band gap of the buffer layer is larger than the band gap of the channel layer. (Appendix 8) 8. The nitride epitaxial substrate according to claim 5, wherein the first layer has a thickness of 0.5% or more of a thickness of the channel layer. (Appendix 9) forming a buffer layer over a substrate; forming a channel layer on the buffer layer; forming a barrier layer on the channel layer; forming a source electrode, a gate electrode and a drain electrode on the barrier layer; having The step of forming the channel layer includes: Carbon concentration is 1×10 17 cm -3 forming the first layer; On the first layer, a carbon concentration of 2×10 16 cm -3 forming a second layer, having A method for manufacturing a nitride semiconductor device, wherein the first layer has a thickness that is 20% or less of a thickness of the channel layer. (Appendix 10) 5. An amplifier comprising the nitride semiconductor device according to any one of claims 1 to 4. (Appendix 11) A power supply device comprising the nitride semiconductor device according to any one of claims 1 to 4. [Explanation of symbols]

[0062] 1: Nitride semiconductor device 10: Substrate 20: Buffer layer 30: Channel layer 31: 1st layer 32: 2nd layer 35:2DEG 40: Barrier layer 50: Epitaxial layer 60: Nitride epitaxial substrate 70d: Drain electrode 70g: Gate electrode 70s: source electrode

Claims

1. A substrate; a buffer layer provided on the substrate; a channel layer provided on the buffer layer; a barrier layer provided on the channel layer; a source electrode, a gate electrode and a drain electrode provided on the barrier layer; having The channel layer is Carbon concentration is 1 x 10 １７ cm －３ A first layer, A carbon layer having a carbon concentration of 2×10 １６ cm －３ a second layer, having A nitride semiconductor device, wherein the first layer has a thickness that is 20% or less of the thickness of the channel layer.

2. The nitride semiconductor device according to claim 1 , wherein the channel layer has a thickness of 200 nm or less.

3. The nitride semiconductor device according to claim 1 , wherein the band gap of the buffer layer is larger than the band gap of the channel layer.

4. A substrate; a buffer layer provided on the substrate; a channel layer provided on the buffer layer; a barrier layer provided on the channel layer; having The channel layer is Carbon concentration is 1 x 10 １７ cm －３ A first layer, A carbon layer having a carbon concentration of 2×10 １６ cm －３ a second layer, having A nitride epitaxial substrate, wherein the thickness of the first layer is 20% or less of the thickness of the channel layer.

5. The nitride epitaxial substrate according to claim 4 , wherein the channel layer has a thickness of 200 nm or less.

6. 6. The nitride epitaxial substrate according to claim 4, wherein the band gap of the buffer layer is larger than the band gap of the channel layer.

7. forming a buffer layer over a substrate; forming a channel layer on the buffer layer; forming a barrier layer on the channel layer; forming a source electrode, a gate electrode and a drain electrode on the barrier layer; having The step of forming the channel layer includes: Carbon concentration is 1 x 10 １７ cm －３ the step of forming the first layer; On the first layer, a carbon concentration of 2×10 １６ cm －３ forming a second layer, having A method for manufacturing a nitride semiconductor device, wherein the first layer has a thickness that is 20% or less of a thickness of the channel layer.

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