Hetero-junction bipolar transistor structure and forming method therefor

Abstract

A hetero-junction bipolar transistor structure and a forming method therefor, relating to the technical field of semiconductor manufacturing. The structure comprises: a substrate (200); located on the substrate (200), a collector layer (209), a base layer (208) and emission layers (205); emission electrodes (204), located on the emission layers (205); collectors (213), located on the collector layer (209); a base electrode (212), the base electrode (212) comprising a plurality of finger parts (212a), the plurality of finger parts (212a) being electrically connected to the base layer (208) separately; a passivation structure, the passivation structure exposing part of the top surfaces of the emission electrodes (204), part of the top surfaces of the collectors (213), and part of the top surfaces of the finger parts (212a) between adjacent emission layers (205); and an interconnection metal layer, the interconnection metal layer being electrically connected to the emission electrodes (204), the finger parts (212a) and the collectors (213), separately. By means of omitting the end part of the base electrode (212), the base layer (208) does not need to provide a placement position for the end part of the base electrode (212), thus effectively reducing the area of the base layer (208), and further reducing the area of a PN junction formed between the base layer (208) and the collector layer (209). The part providing placement for the end part of the base electrode (212) and not contributing to a current is removed from the base layer (208), thereby effectively improving the use efficiency of the device structure.

Description

Heterojunction bipolar transistor structure and forming method thereof

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on July 13, 2023, with application number 202310859897.2 and invention name “Heterojunction Bipolar Transistor Structure and Formation Method Thereof”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a heterojunction bipolar transistor structure and a forming method thereof. Background Art

[0003] With the development of society and the demand for high-performance and low-cost RF components in high-frequency bands in modern communications, traditional silicon devices are unable to meet these new performance requirements. Because heterojunction bipolar transistors (HBTs) offer significantly better high-frequency performance than silicon bipolar transistors, and their compatibility with silicon processes allows them to maintain the same low price as silicon, GaAs technology has made significant progress. GaAs HBT technology has become a mainstream technology in the RF integrated circuit market and has had a profound impact on the development of modern communications technology.

[0004] However, the existing heterojunction bipolar transistor structure still has many problems.

[0005] Summary of the Invention

[0006] The technical problem solved by the present invention is to provide a heterojunction bipolar transistor structure and a method for forming the same, thereby improving the utilization efficiency of the device, reducing parasitic capacitance, and improving device performance and process efficiency.

[0007] In order to solve the above problems, the present invention provides a heterojunction bipolar transistor structure, comprising: a substrate; a collector layer located on the substrate, a base layer located on the collector layer, and a plurality of emitter layers located on the base layer, wherein the plurality of emitter layers are arranged in parallel along a first direction, and the first direction is parallel to the surface of the substrate; an emitter electrode located on the emitter layer; a plurality of collector electrodes located on the exposed collector layer, wherein the collector electrodes are electrically connected to the collector layer; a base electrode, wherein the base electrode comprises a plurality of fingers, wherein the plurality of fingers are electrically connected to the exposed base layer, and wherein the fingers are located between adjacent emitter layers. a passivation structure located on the partial surface of the collector layer, the partial surface of the base electrode, the surface of the emitter layer, the partial surface of the emitter electrode and the partial surface of the collector, the passivation structure exposing the partial top surface of the emitter electrode, the partial top surface of the collector and the partial top surface of the finger between adjacent emitter layers, the passivation structure is used to electrically isolate the finger from the adjacent emitter layer; an interconnection metal layer, the interconnection metal layer is electrically connected to the exposed surface of the emitter electrode, the exposed surface of the finger and the exposed surface of the collector respectively.

[0008] Optionally, the passivation structure includes: a first passivation layer located on the surface of the emitter layer, the partial surface of the emitter electrode and the partial surface of the base layer, the first passivation layer exposing a portion of the top surface of the emitter electrode and a portion of the top surface of the base layer between adjacent emitter layers; a second passivation layer located on the partial surface of the collector layer, the partial surface of the collector, the partial surface of the base electrode and the surface of the first passivation layer, the second passivation layer exposing a portion of the top surface of the collector and a portion of the top surface of the finger.

[0009] Optionally, a plurality of the fingers are respectively electrically connected to the base layer exposed by the first passivation layer.

[0010] Optionally, the first passivation layer is used to electrically isolate the finger from the adjacent emission layer.

[0011] Optionally, the passivation structure has several first openings and several second openings, the first openings expose part of the top surface of the emitting electrode, the second openings expose part of the top surface of the finger between adjacent emitting layers, and the first openings and the second openings have no overlapping area along the first direction.

[0012] Optionally, the interconnect metal layer includes: a first interconnection portion, a second interconnection portion and a third interconnection portion that are separate from each other, wherein an isolation opening is provided between the first interconnection portion and the second interconnection portion, and the isolation opening extends along the first direction; the first interconnection portion is electrically connected to the exposed surface of the emitter electrode, the second interconnection portion is electrically connected to the exposed surface of the finger portion, and the third interconnection portion is electrically connected to the exposed surface of the collector electrode.

[0013] Optionally, along the second direction, a ratio of a length dimension of the top surface of the emitting electrode exposed by the passivation structure to a length dimension of the top surface of the emitting electrode not exposed is 5:1 to 10:1, and the first direction is perpendicular to the second direction.

[0014] Optionally, the method further includes: an isolation region located within the collector layer, wherein the isolation region has injected particles.

[0015] Optionally, the collector layer is doped with first ions; the base layer is doped with second ions, the electrical type of the first ions is different from the electrical type of the second ions, and the doping concentration of the second ions is greater than the doping concentration of the first ions.

[0016] Optionally, the emission layer is doped with a third ion, the electrical type of the third ion is different from the electrical type of the second ion, the electrical type of the third ion is the same as the electrical type of the first ion, the doping concentration of the third ion is greater than the doping concentration of the first ion, and the doping concentration of the third ion is less than the doping concentration of the second ion.

[0017] Correspondingly, the technical solution of the present invention also provides a method for forming a heterojunction bipolar transistor structure, comprising: providing a substrate, the substrate comprising a base, an initial collector layer located on the substrate, an initial base layer located on the initial collector layer, and an initial emitter layer located on the initial base layer; forming a plurality of emitter electrodes on the initial emitter layer, wherein the plurality of emitter electrodes cover part of the top surface of the initial emitter layer, and the plurality of emitter electrodes are arranged in parallel along a first direction, and the first direction is parallel to the surface of the substrate; etching the initial emitter layer using the plurality of emitter electrodes as masks until the top surface of the initial base layer is exposed, so that the initial emitter layer forms a plurality of emitter layers; forming a first passivation material layer on the surface of the initial base layer, the plurality of emitter layers and the plurality of emitter electrodes; selecting a reserved area on the initial base layer, wherein the plurality of emitter layers and the plurality of emitter electrodes are located on the reserved area, and forming a first mask layer on the first passivation material layer located in the reserved area, wherein the first mask layer covers the first passivation material layer located in the reserved area; using the first mask layer as a mask, etching the initial base layer, the initial The collector layer and the first passivation material layer are etched to form a base layer, a collector layer and a first passivation layer respectively; the first passivation layer is etched to expose a portion of the top surface of the base layer between the adjacent emitter layers on the reserved area; a base electrode is formed, the base electrode includes a plurality of fingers, the plurality of fingers are electrically connected to the exposed base layer, the fingers are located between adjacent emitter layers, and the first passivation layer is used to electrically isolate the fingers from the adjacent emitter layers; a plurality of collector electrodes are formed on the exposed collector layer, the collector electrodes are electrically connected to the collector layer; a second passivation layer is formed on the surface of the first passivation layer and the exposed surfaces of the collector layer, the base electrode and the collector electrode; the first passivation layer and the second passivation layer are etched to expose a portion of the top surface of a plurality of the emitter electrodes, the top surfaces of a plurality of the collector electrodes, and a portion of the top surface of the fingers between adjacent emitter layers; an interconnection metal layer is formed, the interconnection metal layer is electrically connected to the exposed surface of the emitter electrode, the exposed surface of the fingers, and the exposed surface of the collector electrode.

[0018] Optionally, the method for forming a plurality of emitting electrodes on the initial emitting layer includes: forming a first photoresist layer on the initial emitting layer, the first photoresist layer exposing a portion of the top surface of the initial emitting layer; forming an emitting electrode material layer on the exposed top surface of the initial emitting layer and the surface of the first photoresist layer using a vapor deposition process; and removing the emitting electrode material layer located on the first photoresist layer and the first photoresist layer using a stripping process to form a plurality of the emitting electrodes.

[0019] Optionally, after forming the base layer and the collector layer and before forming the base electrode, the method further includes: forming an isolation region in the collector layer.

[0020] Optionally, the method for forming the isolation region in the collector layer includes: selecting a functional region on the collector layer, wherein the base layer, the plurality of emitter layers and the plurality of emitter electrodes are located in the functional region; forming a second mask layer on the collector layer located in the functional region, wherein the second mask layer covers a portion of the collector layer, the plurality of emitter layers and the plurality of emitter electrodes; and using the second mask layer as a mask, performing particle injection treatment on the exposed collector layer to form the isolation region in the collector layer.

[0021] Optionally, etching the first passivation layer and the second passivation layer includes: etching the first passivation layer and the second passivation layer to form a plurality of first openings, wherein the first openings expose a portion of the top surface of the emitting electrode; etching the second passivation layer to form a plurality of second openings, wherein the second openings expose a portion of the top surface of the finger between adjacent emitting layers, and the first openings and the second openings have no overlapping area along the first direction.

[0022] Optionally, the method for forming the interconnect metal layer includes: forming an interconnect metal material layer, the interconnect metal material layer covering the second passivation layer, the exposed surface of the emitter electrode, the exposed surface of the finger, and the exposed surface of the collector; patterning the interconnect metal material layer to form the interconnect metal layer and the isolation opening, the interconnect metal layer including a first interconnection portion, a second interconnection portion and a third interconnection portion, the isolation opening being used to separate the first interconnection portion and the second interconnection portion, wherein the isolation opening located between the first interconnection portion and the second interconnection portion extends along the first direction; the first interconnection portion is electrically connected to the exposed surface of the emitter electrode, the second interconnection portion is electrically connected to the exposed surface of the finger, and the third interconnection portion is electrically connected to the exposed surface of the collector.

[0023] Optionally, after etching the first passivation layer and the second passivation layer, along the second direction, the ratio of the length dimension of the exposed top surface of the emitter electrode to the length dimension of the unexposed top surface is 5:1 to 10:1, and the first direction is perpendicular to the second direction.

[0024] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0025] In the heterojunction bipolar transistor structure of the technical solution of the present invention, the base electrode includes a plurality of fingers, and the plurality of fingers are electrically connected to the exposed base layer, and the fingers are located between adjacent emitter layers. By eliminating the end of the base electrode, the base layer does not need to provide a placement position for the end of the base electrode, which can effectively reduce the area of ​​the base layer, thereby reducing the area of ​​the PN junction formed between the base layer and the collector layer, so that when the device structure is working, the parasitic capacitance formed between the base layer and the collector layer is reduced, thereby improving the RF gain and cutoff frequency of the device structure and enhancing the performance of the device structure. Since the portion of the base layer that provides a placement for the end of the base electrode and cannot contribute current is removed from the base layer, the utilization efficiency of the device structure can be effectively improved.

[0026] In the method for forming a heterojunction bipolar transistor structure of the technical solution of the present invention, the base electrode includes a plurality of fingers, and the plurality of fingers are electrically connected to the exposed base layer, and the fingers are located between adjacent emission layers. By eliminating the end of the base electrode, the process difficulty can be effectively reduced. At the same time, the base layer does not need to provide a placement position for the end of the base electrode, which can effectively reduce the area of ​​the base layer, thereby reducing the area of ​​the PN junction formed between the base layer and the collector layer. When the device structure is working, the parasitic capacitance formed between the base layer and the collector layer is reduced, thereby improving the RF gain and cutoff frequency of the device structure and enhancing the performance of the device structure. Since the part of the base layer that provides a placement for the end of the base electrode and cannot contribute current is removed from the base layer, the utilization efficiency of the device structure can be effectively improved.

[0027] Furthermore, since the first opening and the second opening have no overlapping area along the first direction, the isolation opening only needs to extend along the first direction and be located between the first opening and the second opening to form the first and second interconnecting portions, which are separated from each other. The relatively regular morphology of the isolation opening effectively reduces the process difficulty in forming the first, second, and third interconnecting portions. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1 to 3 are schematic structural diagrams of a heterojunction bipolar transistor structure;

[0029] 4 to 26 are schematic structural diagrams of various steps of a method for forming a heterojunction bipolar transistor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] As described in the background art, the existing heterojunction bipolar transistor structure still has many problems, which will be described in detail below with reference to the accompanying drawings.

[0031] 1 to 3 are schematic diagrams of a heterojunction bipolar transistor structure.

[0032] Please refer to Figures 1 to 3, Figure 2 is a schematic cross-sectional view along line AA in Figure 1, and Figure 3 is a schematic cross-sectional view along line BB in Figure 1, a heterojunction bipolar transistor structure, comprising: a substrate 100; a collector layer 101 located on the substrate 100, a base layer 102 located on the collector layer 101, and a plurality of emitter layers 103 located on the base layer 102, wherein the plurality of emitter layers 103 are arranged in parallel along a first direction X; an emitter electrode 104 located on the emitter layer 103; a first passivation layer 105 located on a portion of the surface of the base layer 102, the surface of the emitter layer 103, and a portion of the surface of the emitter electrode 104, wherein the first passivation layer 105 exposes the emitter electrode 104. 04, and a portion of the top surface of the base layer 102 between and on one side of the adjacent emission layer 103; a base electrode 106, the base electrode including an end 106b, a plurality of fingers 106a and a plurality of connecting portions 106c, the plurality of fingers 106a are connected to the end 106b through the plurality of connecting portions 106c, and the plurality of fingers 106a are electrically connected to the exposed base layer 102, respectively, the end 106b and the connecting portion 103c are located on the base layer 102, and are electrically connected to the base layer 102; a plurality of collecting electrodes 107 are located on the collecting layer 101, and the collecting electrodes 107 are electrically connected to the collecting layer 101.

[0033] In this embodiment, since the end of the base electrode 106 is located on the base layer 102, the base layer 102 requires a larger area for the end of the base electrode 106 to be placed. However, when the area of ​​the base layer 102 is larger, the contact area between the base layer 102 and the collector layer 101 increases. Since the electrical types of the ions doped in the base layer 102 and the ions doped in the collector layer 101 are opposite, when the contact area between the base layer 102 and the collector layer 101 is larger, a larger PN junction is formed on the contact surface between the base layer 102 and the collector layer 101. When the device structure is working, a space charge region is formed in the middle of the PN junction, and the P pole and the N pole are equivalent to two electrodes. When the area of ​​the PN junction is larger, the corresponding parasitic capacitance is also larger, which in turn affects the performance of the device structure. In addition, the area provided by the base layer 102 for the end 106b of the base electrode 106 does not contribute to the current, resulting in low device utilization efficiency.

[0034] On this basis, the present invention provides a heterojunction bipolar transistor structure and a method for forming the same, wherein the base electrode includes a plurality of fingers, each of which is electrically connected to the exposed base layer, and the fingers are located between adjacent emitter layers. By eliminating the end of the base electrode, the base layer does not need to provide a placement location for the end of the base electrode, which can effectively reduce the area of ​​the base layer, thereby reducing the area of ​​the PN junction formed between the base layer and the collector layer, so that when the device structure is working, the parasitic capacitance formed between the base layer and the collector layer is reduced, thereby improving the RF gain and cutoff frequency of the device structure and enhancing the performance of the device structure. Since the portion of the base layer that provides a placement for the end of the base electrode and cannot contribute current is removed from the base layer, the utilization efficiency of the device structure can be effectively improved.

[0035] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0036] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to whether there is direct contact.

[0037] 4 to 26 are schematic structural diagrams of various steps of a method for forming a heterojunction bipolar transistor structure according to an embodiment of the present invention.

[0038] 4 , a substrate is provided, which includes a base 200 , an initial collector layer 201 on the base 200 , an initial base layer 202 on the initial collector layer 201 , and an initial emitter layer 203 on the initial base layer 202 .

[0039] In this embodiment, the substrate 200 is made of silicon.

[0040] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0041] Please refer to Figures 5 and 6. Figure 6 is a schematic cross-sectional view along line AA in Figure 5. A plurality of emitting electrodes 204 are formed on the initial emitting layer 203. The emitting electrodes 204 cover a portion of the top surface of the initial emitting layer 203. The emitting electrodes 204 are arranged in parallel along the first direction X.

[0042] In this embodiment, the first direction X is parallel to the surface of the substrate 200 .

[0043] In this embodiment, the method for forming a plurality of emitting electrodes 204 on the initial emitting layer 203 includes: forming a first photoresist layer (not shown) on the initial emitting layer 203, wherein the first photoresist layer exposes a portion of the top surface of the initial emitting layer 203; forming an emitting electrode material layer (not shown) on the exposed top surface of the initial emitting layer 203 and the surface of the first photoresist layer by an evaporation process; and removing the emitting electrode material layer on the first photoresist layer and the first photoresist layer by a stripping process to form a plurality of the emitting electrodes 204.

[0044] In this embodiment, the emitter electrode 204 is in ohmic contact with the initial emitter layer 203 .

[0045] In this embodiment, the emitter electrode 204 adopts a multi-layer metal structure, and the emitter electrode 204 is a multi-layer metal layer of titanium (Ti) film, platinum (Pt) film, titanium (Ti) film, platinum (Pt) film, and titanium (Ti) film stacked in sequence.

[0046] In other embodiments, the emitter electrode may also be a single-layer metal structure.

[0047] 7 , FIG7 and FIG6 are viewed in the same direction. The initial emission layer 203 is etched using the emission electrodes 204 as masks until the top surface of the initial base layer 202 is exposed, so that the initial emission layer 203 forms a plurality of emission layers 205 .

[0048] In this embodiment, the initial emission layer 203 is etched using a dry etching process.

[0049] In this embodiment, the process parameters of the dry etching process include: the etching gas includes: chlorine; the flow rate of the etching gas is 10sccm~500sccm: when the flow rate of the etching gas is greater than 500sccm, the etching rate is too fast, and it is easy to etch the initial base layer 202 under the initial emission layer 203, causing device failure; when the etching gas is less than 10sccm, the bottom material of the initial emission layer 203 is easy to not be completely etched, causing electron aggregation, heat, and device reliability failure.

[0050] By etching the initial emission layer 203 using the emission electrode 204 as a mask, the size of the emission layer 205 formed is the same as that of the emission electrode 204, which can effectively improve the electrical conductivity and thermal conductivity between the emission layer 205 and the emission electrode 204, thereby improving the performance of the device structure.

[0051] Referring to FIG. 8 , a first passivation material layer 206 is formed on the surfaces of the initial base layer 202 , the plurality of emission layers 205 , and the plurality of emission electrodes 204 .

[0052] In this embodiment, the first passivation material layer 206 is made of silicon nitride.

[0053] In this embodiment, the first passivation material layer 206 is formed by a plasma enhanced chemical vapor deposition process.

[0054] Please refer to Figures 9 and 10. Figure 10 is a schematic cross-sectional view along line BB in Figure 9. A reserved area is selected on the initial base layer 202. Several of the emission layers 205 and several of the emission electrodes 204 are located in the reserved area. A first mask layer 207 is formed on the first passivation material layer 206 located in the reserved area. The first mask layer 207 covers the first passivation material layer 206 located in the reserved area.

[0055] It should be noted that, in this embodiment, since the subsequently formed base layer does not need to provide a placement location for the end of the base electrode, the selection of the reserved area can be consistent with or slightly larger than the overall outline surrounded by the periphery of the several emission layers 205.

[0056] Please refer to Figure 11. The viewing directions of Figure 11 and Figure 10 are consistent. Using the first mask layer 207 as a mask, the initial base layer 202, the initial collector layer 201 and the first passivation material layer 206 are etched to form a base layer 208, a collector layer 209 and a first passivation layer 210 respectively.

[0057] In this embodiment, the collector layer 209 is doped with first ions; the base layer 208 is doped with second ions, the electrical type of the first ions is different from the electrical type of the second ions, and the doping concentration of the second ions is greater than the doping concentration of the first ions.

[0058] The emission layer 205 is doped with a third ion, the electrical type of the third ion is different from the electrical type of the second ion, the electrical type of the third ion is the same as the electrical type of the first ion, the doping concentration of the third ion is greater than the doping concentration of the first ion, and the doping concentration of the third ion is less than the doping concentration of the second ion.

[0059] In this embodiment, the collector layer 209 has a doping concentration of 1E16 atoms / cm 3 N-type gallium arsenide (GaAs); the base layer 208 has a doping concentration of 1E19atoms / cm 3The emitter layer 205 has a doping concentration of 1E17atoms / cm 3 N-type gallium arsenide.

[0060] Continuing to refer to FIG. 11 , in this embodiment, after the base layer 208 and the collector layer 209 are formed, the first mask layer 207 is removed.

[0061] Referring to FIG. 12 , an isolation region 211 is formed in the collector layer 209 .

[0062] In this embodiment, the method for forming the isolation region 211 in the collector layer 209 includes: selecting a functional region on the collector layer 209, wherein the base layer 208, the plurality of emitter layers 205 and the plurality of emitter electrodes 204 are located in the functional region; forming a second mask layer (not shown) on the functional region, wherein the second mask layer covers part of the collector layer 209, the plurality of emitter layers 205 and the plurality of emitter electrodes 204; and performing particle injection treatment on the exposed collector layer 209 using the second mask layer as a mask to form the isolation region 211 in the collector layer 209.

[0063] In this embodiment, the particles include hydrogen ions, helium ions, or argon ions.

[0064] In this embodiment, by forming the isolation region 211 , it is possible to effectively prevent the formed device structure from being electrically connected in series with device structures in other regions.

[0065] Please refer to Figures 13 to 15, Figure 14 is a schematic cross-sectional view along line CC in Figure 13, and Figure 15 is a schematic cross-sectional view along line DD in Figure 13. The first passivation layer 210 is etched to expose a portion of the top surface of the base layer 208 between the adjacent emission layers 205 on the reserved area; a base electrode 212 is formed, and the base layer electrode 212 includes a plurality of fingers 212a, and the plurality of fingers 212a are electrically connected to the exposed base layer 208, respectively. The fingers 212a are located between adjacent emission layers 205, and the first passivation layer 210 is used to electrically isolate the fingers 212a from the adjacent emission layers 205.

[0066] In this embodiment, by omitting the end of the base electrode 212, the process difficulty can be effectively reduced. At the same time, the base layer 208 does not need to provide a placement position for the end of the base electrode 212, which can effectively reduce the area of ​​the base layer 208, thereby reducing the area of ​​the PN junction formed between the base layer 208 and the collector layer 209. When the device structure is in operation, the parasitic capacitance formed between the base layer 208 and the collector layer 209 is reduced, thereby improving the RF gain and cutoff frequency of the device structure and enhancing the performance of the device structure. Since the portion of the base layer 208 that provides a placement for the end of the base electrode 212 and cannot contribute current is removed, the utilization efficiency of the device structure can be effectively improved.

[0067] In this embodiment, the finger portion 212 a is in ohmic contact with the base layer 208 .

[0068] In this embodiment, the finger portion 212 a adopts a multi-layer metal structure, and the finger portion 212 a is a multi-layer metal layer in which a platinum (Pt) film, a titanium (Ti) film, a Pt film, and a gold (Au) film are stacked in sequence.

[0069] In other embodiments, the finger portion may also be a single-layer metal structure.

[0070] Please refer to FIG. 16 and FIG. 17 . FIG. 17 is a schematic cross-sectional view along line EE in FIG. 16 . A plurality of collecting electrodes 213 are formed on the exposed collecting layer 209 . The collecting electrodes 213 are electrically connected to the collecting layer 209 .

[0071] In this embodiment, the collector electrode 213 and the collector layer 209 are in ohmic contact.

[0072] In this embodiment, the collector electrode 213 adopts a multi-layer metal structure, and the collector electrode 213 is a multi-layer metal layer in which titanium (Ti) film and gold (Au) film are stacked in sequence.

[0073] In other embodiments, the collector may also be a single-layer metal structure.

[0074] Please refer to FIG. 18 . The viewing directions of FIG. 18 and FIG. 17 are consistent. A second passivation layer 214 is formed on the surface of the first passivation layer 210 and the exposed surfaces of the collector layer 209 , the base electrode and the collector electrode 213 .

[0075] In this embodiment, the second passivation layer 214 is made of silicon nitride.

[0076] In this embodiment, the second passivation layer 214 is formed by a plasma enhanced chemical vapor deposition process.

[0077] Please refer to Figures 19 to 22, Figure 20 is a schematic cross-sectional view along line FF in Figure 19, Figure 21 is a schematic cross-sectional view along line GG in Figure 19, and Figure 22 is a schematic cross-sectional view along line HH in Figure 19. The first passivation layer 210 and the second passivation layer 214 are etched to expose portions of the top surfaces of several of the emitter electrodes 204, portions of the top surfaces of several of the collector electrodes 213, and portions of the top surfaces of the fingers between adjacent emitter layers 205.

[0078] In this embodiment, etching the first passivation layer 210 and the second passivation layer 214 includes: etching the first passivation layer 210 and the second passivation layer 214 to form a plurality of first openings (not marked), wherein the first openings expose a portion of the top surface of the emitting electrode 204; etching the second passivation layer 214 to form a plurality of second openings (not marked), wherein the second openings expose a portion of the top surface of the finger portion 212a between adjacent emitting layers 205, and the first openings and the second openings have no overlapping area along the first direction X.

[0079] In this embodiment, the method for etching the first passivation layer 210 and the second passivation layer 214 includes: forming a third mask layer (not shown) on the second passivation layer 214, the third mask layer exposing a portion of the top surface of the second passivation layer 214; etching the first passivation layer 210 and the second passivation layer 214 using the third mask layer as a mask until portions of the top surfaces of several of the emitter electrodes 204 are exposed; etching the second passivation layer 214 using the third mask layer as a mask until portions of the top surfaces of several of the collector electrodes 213 and portions of the top surfaces of the fingers between adjacent emitter layers 205 are exposed.

[0080] It should be noted that in this embodiment, since the fingers 212a and the emitting electrode 204 cannot be electrically connected, if the top surface of the emitting electrode 204 is completely exposed, the subsequently formed first interconnect will completely cover the emitting electrode 204. In this case, the subsequently formed second interconnect will not be able to lead out the fingers 212a. Therefore, it is necessary to leave a portion of the top surface of the emitting electrode 204 uncovered, and expose the portion of the fingers 212a corresponding to the unexposed emitting electrode 204 along the first direction X so that the second interconnect can lead out the fingers 212a. At the same time, electrical isolation between the first interconnect and the second interconnect is ensured to prevent short circuits between the emitting electrode 204 and the fingers 212a.

[0081] In this embodiment, after the first passivation layer 210 and the second passivation layer 214 are etched, along the second direction Y, the ratio of the length dimension of the exposed top surface of the emitter electrode 204 to the length dimension of the unexposed top surface is 5:1 to 10:1, and the first direction X is perpendicular to the second direction Y.

[0082] Please refer to Figures 23 to 26, Figure 24 is a schematic cross-sectional view along line II in Figure 23, Figure 25 is a schematic cross-sectional view along line JJ in Figure 23, and Figure 26 is a schematic cross-sectional view along line KK in Figure 23, to form an interconnection metal layer, which is electrically connected to the exposed surface of the emitter electrode 204, the exposed surface of the finger 212a, and the exposed surface of the collector 213, respectively.

[0083] In this embodiment, the method for forming the interconnect metal layer includes: forming an interconnect metal material layer (not shown), the interconnect metal material layer electrically covering the second passivation layer 214, the exposed surface of the emitter electrode 204, the exposed surface of the finger portion 212 a, and the exposed surface of the collector electrode 213; patterning the interconnect metal material layer to form the interconnect metal layer and an isolation opening (not shown), the interconnect metal layer including a first interconnect 215, a second interconnect 216, and a third interconnect 217, the isolation opening being used to separate the first interconnect 215 from the second interconnect 216, wherein the isolation opening located between the first interconnect 215 and the second interconnect 216 extends along the first direction X; the first interconnect 215 is electrically connected to the exposed surface of the emitter electrode 204, the second interconnect 216 is electrically connected to the exposed surface of the finger portion 212 a, and the third interconnect 217 is electrically connected to the exposed surface of the collector electrode 213.

[0084] In this embodiment, since the first opening and the second opening have no overlapping area along the first direction X, the isolation opening only needs to extend along the first direction X and be located between the first opening and the second opening to form the first interconnection 215 and the second interconnection 216, which are separated from each other. Since the isolation opening has a relatively regular morphology, the process difficulty in forming the first interconnection 215, the second interconnection 216, and the third interconnection 217 is effectively reduced.

[0085] In this embodiment, the base layer 208 and the interconnection metal layer are in ohmic contact.

[0086] In this embodiment, the interconnection metal layer adopts a multi-layer metal structure, and the interconnection metal layer is a multi-layer metal layer of platinum (Pt) film, titanium (Ti) film, platinum (Pt) film, and gold (Au) film stacked in sequence.

[0087] Correspondingly, the technical solution of the present invention also provides a heterojunction bipolar transistor structure, please continue to refer to Figures 23 to 26, including: a substrate 200; a collector layer 209 located on the substrate 200, a base layer 208 located on the collector layer 209, and a plurality of emitter layers 205 located on the base layer 208, wherein the plurality of emitter layers 205 are arranged in parallel along a first direction X, and the first direction X is parallel to the surface of the substrate 200; an emitter electrode 204 located on the emitter layer 205; a plurality of collector electrodes 213 located on the exposed collector layer 209, wherein the collector electrode 213 is electrically connected to the collector layer 209; a base electrode 212, wherein the base electrode 212 includes a plurality of finger portions 212a, wherein the plurality of finger portions 212a are electrically connected to the exposed base layer 208, respectively. The finger 212a is located between adjacent emission layers 205; a passivation structure is located on a portion of the surface of the collector layer 209, a portion of the surface of the base electrode 212, a portion of the surface of the emission layer 205, a portion of the surface of the emission electrode 204 and a portion of the surface of the collector 213, the passivation structure exposes a portion of the top surface of the emission electrode 204, a portion of the top surface of the collector 213, and a portion of the top surface of the finger 212a between adjacent emission layers 205, the passivation structure is used to electrically isolate the finger 212a from the adjacent emission layer 205; an interconnection metal layer, the interconnection metal layer is electrically connected to the exposed surface of the emitter electrode 204, the exposed surface of the finger 212a, and the exposed surface of the collector 213, respectively.

[0088] In this embodiment, by omitting the end of the base electrode 212, the base layer 208 does not need to provide a placement location for the end of the base electrode 212, which can effectively reduce the area of ​​the base layer 208, thereby reducing the area of ​​the PN junction formed between the base layer 208 and the collector layer 209. When the device structure is in operation, the parasitic capacitance formed between the base layer 208 and the collector layer 209 is reduced, thereby improving the RF gain and cutoff frequency of the device structure and enhancing the performance of the device structure. Since the portion of the base layer 208 that provides a placement for the end of the base electrode 212 and cannot contribute current is removed, the utilization efficiency of the device structure can be effectively improved.

[0089] In this embodiment, the passivation structure includes: a first passivation layer 210 located on the surface of the emitter layer 205, a portion of the surface of the emitter electrode 204 and a portion of the surface of the base layer 208, the first passivation layer 210 exposing a portion of the top surface of the emitter electrode 204 and a portion of the top surface of the base layer 208 between adjacent emitter layers 205; a second passivation layer 214 located on a portion of the surface of the collector layer 209, a portion of the surface of the collector 213, a portion of the surface of the base electrode 212 and the surface of the first passivation layer 210, the second passivation layer 214 exposing a portion of the top surface of the collector 213 and a portion of the top surface of the finger 212a.

[0090] In this embodiment, a plurality of the finger portions 212 a are electrically connected to the base layer 208 exposed by the first passivation layer 210 .

[0091] In this embodiment, the first passivation layer 210 is used to electrically isolate the finger portion 212 a from the adjacent emission layer 205 .

[0092] In this embodiment, the passivation structure has a plurality of first openings and a plurality of second openings, wherein the first openings expose a portion of the top surface of the emitting electrode 204, and the second openings expose a portion of the top surface of the finger 212a between adjacent emitting layers 205, and the first openings and the second openings have no overlapping area along the first direction X.

[0093] In this embodiment, the interconnect metal layer includes: a first interconnect 215, a second interconnect 216, and a third interconnect 217 that are separate from each other, wherein an isolation opening is provided between the first interconnect 215 and the second interconnect 216, and the isolation opening extends along the first direction X; the first interconnect 215 is electrically connected to the exposed surface of the emitter electrode 204, the second interconnect 216 is electrically connected to the exposed surface of the finger 212a, and the third interconnect 217 is electrically connected to the exposed surface of the collector electrode 213.

[0094] In this embodiment, the emitter electrode 204 adopts a single-layer metal structure or a multi-layer metal structure.

[0095] In this embodiment, the present invention further includes: an isolation region 211 located in the collector layer 209 , wherein the isolation region 211 has implanted particles.

[0096] In this embodiment, the collector layer 209 is doped with first ions; the base layer 208 is doped with second ions, the electrical type of the first ions is different from the electrical type of the second ions, and the doping concentration of the second ions is greater than the doping concentration of the first ions.

[0097] The emission layer 205 is doped with a third ion, the electrical type of the third ion is different from the electrical type of the second ion, the electrical type of the third ion is the same as the electrical type of the first ion, the doping concentration of the third ion is greater than the doping concentration of the first ion, and the doping concentration of the third ion is less than the doping concentration of the second ion.

[0098] In this embodiment, the collector layer 209 has a doping concentration of 1E16 atoms / cm 3 N-type gallium arsenide (GaAs); the base layer 208 has a doping concentration of 1E19atoms / cm 3 The emitter layer 205 has a doping concentration of 1E17atoms / cm 3 N-type gallium arsenide.

[0099] Please continue to refer to Figures 19 to 22. In this embodiment, along the second direction Y, the ratio of the length dimension of the top surface of the emitting electrode 204 exposed by the passivation structure to the length dimension of the top surface of the emitting electrode 204 not exposed is: 5:1 to 10:1, and the first direction X is perpendicular to the second direction Y.

[0100] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A heterojunction bipolar transistor structure, characterized in that: include: substrate; A collector layer located on the substrate, a base layer located on the collector layer, and a plurality of emitter layers located on the base layer, wherein the plurality of emitter layers are arranged in parallel along a first direction, and the first direction is parallel to the surface of the substrate; an emitting electrode located on the emitting layer; A plurality of collector electrodes located on the exposed collector layer, wherein the collector electrodes are electrically connected to the collector layer; A base electrode, the base electrode comprising a plurality of fingers, the plurality of fingers being electrically connected to the exposed base layers respectively, and the fingers being located between adjacent emission layers; a passivation structure located on a portion of the surface of the collector layer, a portion of the surface of the base electrode, a portion of the surface of the emitter layer, a portion of the surface of the emitter electrode and a portion of the surface of the collector, wherein the passivation structure exposes a portion of the top surface of the emitter electrode, a portion of the top surface of the collector and a portion of the top surface of the finger between adjacent emitter layers, and the passivation structure is used to electrically isolate the finger from the adjacent emitter layer; An interconnection metal layer is electrically connected to the exposed surface of the emitter electrode, the exposed surface of the finger portion, and the exposed surface of the collector electrode, respectively.

2. The heterojunction bipolar transistor structure according to claim 1, characterized in that: The passivation structure includes: a first passivation layer located on the surface of the emitter layer, the partial surface of the emitter electrode and the partial surface of the base layer, the first passivation layer exposes a portion of the top surface of the emitter electrode and a portion of the top surface of the base layer between adjacent emitter layers; a second passivation layer located on a portion of the surface of the collector layer, the partial surface of the collector, the partial surface of the base electrode and the surface of the first passivation layer, the second passivation layer exposes a portion of the top surface of the collector and a portion of the top surface of the finger.

3. The heterojunction bipolar transistor structure according to claim 2, characterized in that: A plurality of the fingers are respectively electrically connected to the base layer exposed by the first passivation layer.

4. The heterojunction bipolar transistor structure according to claim 2, characterized in that: The first passivation layer is used to electrically isolate the finger from the adjacent emission layer.

5. The heterojunction bipolar transistor structure according to claim 1, characterized in that: The passivation structure has a plurality of first openings and a plurality of second openings, wherein the first openings expose a portion of the top surface of the emitting electrode, and the second openings expose a portion of the top surface of the fingers between adjacent emitting layers, and the first openings and the second openings have no overlapping area along the first direction.

6. The heterojunction bipolar transistor structure according to claim 5, characterized in that: The interconnect metal layer includes: a first interconnect part, a second interconnect part and a third interconnect part which are separate from each other, wherein an isolation opening is provided between the first interconnect part and the second interconnect part, and the isolation opening extends along the first direction; the first interconnect part is electrically connected to the exposed surface of the emitter electrode, the second interconnect part is electrically connected to the exposed surface of the finger part, and the third interconnect part is electrically connected to the exposed surface of the collector electrode.

7. The heterojunction bipolar transistor structure according to claim 1, characterized in that: Along the second direction, the ratio of the length dimension of the top surface of the emitting electrode exposed by the passivation structure to the length dimension of the top surface of the emitting electrode not exposed is 5:1-10:1, and the first direction is perpendicular to the second direction.

8. The heterojunction bipolar transistor structure according to claim 1, characterized in that: Also includes: An isolation region is located in the collector layer, and has implanted particles in the isolation region.

9. The heterojunction bipolar transistor structure according to claim 1, characterized in that: The collector layer is doped with first ions; the base layer is doped with second ions, the electrical type of the first ions is different from the electrical type of the second ions, and the doping concentration of the second ions is greater than the doping concentration of the first ions.

10. The heterojunction bipolar transistor structure according to claim 9, characterized in that: The emission layer is doped with third ions, the electrical type of the third ions is different from the electrical type of the second ions, the electrical type of the third ions is the same as the electrical type of the first ions, the doping concentration of the third ions is greater than the doping concentration of the first ions, and the doping concentration of the third ions is less than the doping concentration of the second ions.

11. A method for forming a heterojunction bipolar transistor structure, characterized in that: include: Providing a substrate, the substrate comprising a base, an initial collector layer located on the base, an initial base layer located on the initial collector layer, and an initial emitter layer located on the initial base layer; forming a plurality of emitting electrodes on the initial emitting layer, wherein the plurality of emitting electrodes cover a portion of the top surface of the initial emitting layer, and the plurality of emitting electrodes are arranged in parallel along a first direction, wherein the first direction is parallel to the substrate surface; Using the plurality of emission electrodes as masks, etching the initial emission layer until the top surface of the initial base layer is exposed, so that the initial emission layer forms a plurality of emission layers; Forming a first passivation material layer on the surfaces of the initial base layer, the plurality of the emission layers and the plurality of the emission electrodes; A reserved area is selected on the initial base layer, a plurality of the emission layers and a plurality of the emission electrodes are located on the reserved area, and a first mask layer is formed on the first passivation material layer located in the reserved area, wherein the first mask layer covers the first passivation material layer located in the reserved area; Using the first mask layer as a mask, etching the initial base layer, the initial collector layer and the first passivation material layer to form a base layer, a collector layer and a first passivation layer respectively; Etching the first passivation layer to expose a portion of the top surface of the base layer between the adjacent emission layers on the reserved area; forming a base electrode, wherein the base electrode comprises a plurality of fingers, wherein the plurality of fingers are electrically connected to the exposed base layer respectively, and the fingers are located between adjacent emission layers, and the first passivation layer is used to electrically isolate the fingers from the adjacent emission layers; forming a plurality of collector electrodes on the exposed collector layer, wherein the collector electrodes are electrically connected to the collector layer; forming a second passivation layer on a surface of the first passivation layer and exposed surfaces of the collector layer, the base electrode and the collector electrode; Etching the first passivation layer and the second passivation layer to expose partial top surfaces of several of the emitter electrodes, top surfaces of several of the collector electrodes, and partial top surfaces of the fingers between adjacent emitter layers; An interconnection metal layer is formed, wherein the interconnection metal layer is electrically connected to the exposed surface of the emitter electrode, the exposed surface of the finger portion, and the exposed surface of the collector electrode, respectively.

12. The method for forming a heterojunction bipolar transistor structure according to claim 11, wherein: The method for forming a plurality of emitting electrodes on the initial emitting layer comprises: forming a first photoresist layer on the initial emitting layer, wherein the first photoresist layer exposes a portion of the top surface of the initial emitting layer; forming an emitting electrode material layer on the exposed top surface of the initial emitting layer and the surface of the first photoresist layer by an evaporation process; and removing the emitting electrode material layer on the first photoresist layer and the first photoresist layer by a stripping process to form a plurality of the emitting electrodes.

13. The method for forming a heterojunction bipolar transistor structure according to claim 11, wherein: After forming the base layer and the collector layer and before forming the base electrode, the method further includes: forming an isolation region in the collector layer.

14. The method for forming a heterojunction bipolar transistor structure according to claim 13, wherein: The method for forming the isolation region in the collector layer includes: selecting a functional region on the collector layer, wherein the base layer, the plurality of emitter layers and the plurality of emitter electrodes are located in the functional region; forming a second mask layer on the collector layer located in the functional region, wherein the second mask layer covers a portion of the collector layer, the plurality of emitter layers and the plurality of emitter electrodes; and using the second mask layer as a mask, performing a particle injection process on the exposed collector layer to form the isolation region in the collector layer.

15. The method for forming a heterojunction bipolar transistor structure according to claim 11, wherein: The etching process of the first passivation layer and the second passivation layer includes: etching the first passivation layer and the second passivation layer to form a plurality of first openings, wherein the first openings expose a portion of the top surface of the emitting electrode; etching the second passivation layer to form a plurality of second openings, wherein the second openings expose a portion of the top surface of the finger between adjacent emitting layers, and the first openings and the second openings have no overlapping area along the first direction.

16. The method for forming a heterojunction bipolar transistor structure according to claim 15, characterized in that: The method for forming the interconnection metal layer comprises: forming an interconnection metal material layer, the interconnection metal material layer covers the second passivation layer, the exposed surface of the emitter electrode, the exposed surface of the finger, and the exposed surface of the collector; patterning the interconnection metal material layer to form the interconnection metal layer and the isolation opening, the interconnection metal layer comprises a first interconnection part, a second interconnection part and a third interconnection part, the isolation opening is used to separate the first interconnection part and the second interconnection part, wherein the isolation opening located between the first interconnection part and the second interconnection part extends along the first direction; the first interconnection part is electrically connected to the exposed surface of the emitter electrode, the second interconnection part is electrically connected to the exposed surface of the finger, and the third interconnection part is electrically connected to the exposed surface of the collector.

17. The method for forming a heterojunction bipolar transistor structure according to claim 11, wherein: After etching the first passivation layer and the second passivation layer, along the second direction, the ratio of the length dimension of the exposed top surface of the emitter electrode to the length dimension of the unexposed top surface is 5:1-10:1, and the first direction is perpendicular to the second direction.

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