Pulse signal monitoring circuit, chip, and electronic device

Abstract

Embodiments of the present disclosure provide a pulse signal monitoring circuit, a chip, and an electronic device. The circuit comprises a pulse monitoring module. The pulse monitoring module comprises: a pulse period monitoring module used for monitoring, on the basis of a reference clock signal, the period of a pulse signal to be tested and the period change between two adjacent periods; and a pulse duty ratio monitoring module used for monitoring, on the basis of the reference clock signal, the duty ratio of said pulse signal and the duty ratio change between two adjacent periods.

Description

Pulse signal monitoring circuit, chip and electronic device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure is based on Chinese patent application CN202311263663.8, filed on September 27, 2023, entitled “Pulse signal monitoring circuit, chip and electronic device”, and claims the priority of the patent application. All the contents disclosed therein are incorporated into this disclosure by reference. Technical Field

[0003] The present disclosure relates to the field of electronic circuits, and in particular to a pulse signal monitoring circuit, a chip, and an electronic device. Background Art

[0004] With the growing trend toward electrification, intelligence, and the Internet of Things (IoT) in automobiles, automotive-grade chips are required to integrate an increasing number of functions to meet market demands. Integrated Circuit (IC) design, especially System-on-Chip (SOC) design, requires the integration of increasing amounts of intellectual property (IP) to meet these increasingly complex market demands. Furthermore, as a means of transportation, automotive products are closely linked to life safety, placing even higher demands on the safety and reliability of these chips.

[0005] To ensure the stability of pulse signals on digital automotive chips, the pulse sources in digital chips are mainly generated by on-chip oscillators, phase-locked loops, and external crystal oscillators. Long-term operation or noise interference from the external environment is very likely to cause the pulse signal to fail, resulting in relatively large safety accidents and threatening personal safety.

[0006] Currently, chip pulse signal monitoring primarily focuses on clock signals with a 50% duty cycle, with no monitoring for pulse signals with duty cycles other than 50%. Clock monitoring falls into two main categories: First, monitoring clock frequency deviation. Related technologies employ three links to monitor frequency deviation, making implementation cumbersome and unable to detect clock loss. Second, monitoring clock loss: When a clock signal is present, a periodic pulse signal is output. When the clock signal is lost, a high or low level signal is output. However, if the frequency of the clock signal under test changes, a high or low level signal is also output, making it impossible to determine if the clock has lost lock.

[0007] In summary, there is no good solution to the above problems.

[0008] Summary of the Invention

[0009] The embodiments of the present disclosure provide a pulse signal monitoring circuit, a chip, and an electronic device to at least solve the problem in the related art that a pulse signal with a duty cycle other than 50% cannot be monitored.

[0010] According to one embodiment of the present disclosure, a pulse signal monitoring circuit is provided, which includes: a pulse period monitoring module for monitoring the period of a pulse signal to be measured and the period change between two adjacent periods based on a reference clock signal; and a pulse duty cycle monitoring module for monitoring the duty cycle of the pulse signal to be measured and the duty cycle change between two adjacent periods based on a reference clock signal.

[0011] According to another embodiment of the present disclosure, a chip is provided, comprising the pulse signal monitoring circuit in any one of the above embodiments.

[0012] According to yet another embodiment of the present disclosure, an electronic device is provided, comprising the pulse signal monitoring circuit in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIG1 is a block diagram of a pulse signal monitoring circuit according to an embodiment of the present disclosure;

[0014] FIG2 is a structural block diagram of a pulse period monitoring module according to an embodiment of the present disclosure;

[0015] FIG3 is a structural block diagram of a pulse duty cycle monitoring module according to an embodiment of the present disclosure;

[0016] FIG4 is a structural block diagram of a pulse signal monitoring circuit according to an embodiment of the present disclosure;

[0017] FIG5 is a structural block diagram of a clock frequency deviation monitoring module according to an embodiment of the present disclosure;

[0018] FIG6 is a structural block diagram of a clock presence monitoring module according to an embodiment of the present disclosure;

[0019] 7 is a structural block diagram of a pulse signal monitoring circuit according to another embodiment of the present disclosure;

[0020] FIG8 is a schematic diagram of a processing flow of a pulse monitoring module according to an embodiment of the present disclosure;

[0021] FIG9 is a schematic diagram of a processing flow of a clock monitoring module according to an embodiment of the present disclosure;

[0022] FIG10 is a schematic diagram of a signal aggregation process of multiple clock monitoring modules according to an embodiment of the present disclosure;

[0023] FIG11 is a waveform diagram of a pulse period monitoring module according to an embodiment of the present disclosure;

[0024] FIG12 is a waveform diagram of a pulse duty cycle monitoring module according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings and in conjunction with embodiments.

[0026] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0027] The pulse signal monitoring circuit in the embodiment of the present disclosure is mainly used in chips to realize real-time monitoring of pulse signals in the chip. Chip products may include but are not limited to automotive electronic chips, consumer electronic chips, communication chips, etc.

[0028] The present disclosure provides a pulse signal monitoring circuit. FIG1 is a block diagram of the pulse signal monitoring circuit according to the present disclosure. As shown in FIG1 , the pulse signal monitoring circuit includes a pulse monitoring module 10 .

[0029] In this embodiment, the pulse monitoring module 10 may include the following structure:

[0030] A pulse period monitoring module 12 is configured to monitor the period of the pulse signal to be measured and the period variation between two adjacent periods based on a reference clock signal;

[0031] The pulse duty cycle monitoring module 14 is configured to monitor the duty cycle of the pulse signal to be measured and the change in the duty cycle between two adjacent cycles based on the reference clock signal.

[0032] In this embodiment, the pulse signal to be measured may be a pulse signal with any duty cycle.

[0033] Through the embodiments disclosed herein, pulse signals of any duty cycle can be monitored, and period anomaly monitoring and duty cycle anomaly monitoring of pulse signals can be realized, which solves the problem in related technologies that pulse signals with duty cycles other than 50% cannot be monitored. Signal anomalies in the chip can be discovered in a timely manner to ensure stable operation of the chip system.

[0034] In some embodiments, the pulse monitoring module 10 may include a first synchronizer 16 for synchronizing the input pulse signal to be measured to the clock domain of the reference clock signal to output a synchronized pulse signal.

[0035] In some embodiments, the pulse monitoring module 10 may further include a first edge monitoring module 18, whose input end is connected to the output end of the first synchronizer, for monitoring the rising edge of the synchronization pulse signal and outputting a first trigger signal when the rising edge of the synchronization pulse signal arrives.

[0036] In some embodiments, the first edge monitoring module 18 is further configured to monitor the falling edge of the synchronization pulse signal and output a third trigger signal when the falling edge of the synchronization pulse signal arrives.

[0037] In some embodiments, the pulse period monitoring module and the pulse duty cycle monitoring module may share a synchronizer and an edge detection module, or may each independently use a synchronizer and an edge detection module.

[0038] In this embodiment, the synchronizer is used to synchronize the asynchronous signal to the input clock domain through synchronization processing. The synchronizer can synchronize the reset signal to the desired clock domain for release and reduce the probability of metastable state that may occur when the reset signal is released due to crossing clock domains.

[0039] FIG2 is a block diagram of the structure of the pulse period monitoring module according to an embodiment of the present disclosure. As shown in FIG2 , the pulse period monitoring module 12 may include the following structures:

[0040] The period calculation module 122, whose input end is connected to the output end of the first edge monitoring module, is used to start counting the reference clock signal when the first trigger signal arrives, and end counting when the first trigger signal arrives next time, and output the pulse signal period.

[0041] The period change monitoring module 124 has an input end connected to the output end of the period calculation module and is used to compare whether the periods of two adjacent pulse signals are the same, and output a second trigger signal when the periods of the two adjacent pulse signals are different.

[0042] The change cycle counting module 126 has an input end connected to the output end of the period change monitoring module and is used to count the second trigger signal.

[0043] In some embodiments, the pulse period monitoring module is also used to compare the number of second trigger signals output by the change period counting module 126 with a preset period change threshold, and output a period change alarm signal when the number of the second trigger signals is greater than the preset period change threshold.

[0044] In an exemplary embodiment, the pulse period monitoring module uses a single edge detection module. In this case, the pulse period monitoring module also includes a rising edge monitoring module 128, whose input end is connected to the output end of the first synchronizer, for monitoring the rising edge of the synchronization pulse signal and outputting a first trigger signal when the rising edge of the synchronization pulse signal arrives.

[0045] In this embodiment, the input end of the period calculation module 122 is connected to the output end of the rising edge monitoring module.

[0046] In some embodiments, the pulse period monitoring module may include a combination of one or more of the above structures, depending on monitoring requirements. The pulse period monitoring module may only support real-time monitoring of the pulse period or pulse frequency, or it may generate an indication signal when the pulse changes to a certain value, and the central control determines whether to respond.

[0047] In some embodiments, the period calculation module 122 and the change period counting module 126 can be implemented as counters. The period calculation module can use the rising edge of the first trigger signal, i.e., the synchronization pulse signal, as a counting mark, starting at one counting mark and ending at the next counting mark, recording the current value and then clearing it to zero. The change period counting module can use the rising edge of the second trigger signal as a counting mark, and clear it to zero when an alarm signal is output or the pulse signal period returns to normal.

[0048] In some embodiments, the period variation threshold may be set according to the sensitivity of the alarm abnormality. The smaller the period variation threshold, the higher the sensitivity to the pulse signal period abnormality.

[0049] Through the embodiments of the present disclosure, real-time monitoring of the pulse period of a pulse signal with any duty cycle can be achieved, and abnormal period conditions of the pulse signal can be discovered in a timely manner, thereby ensuring the normal operation of the chip system.

[0050] In some other embodiments, the first edge monitoring module 18 is further configured to monitor the falling edge of the synchronization pulse signal and output a third trigger signal when the falling edge of the synchronization pulse signal arrives.

[0051] FIG3 is a block diagram of a pulse duty cycle monitoring module according to an embodiment of the present disclosure. As shown in FIG3 , the pulse duty cycle monitoring module 14 may include the following structures:

[0052] The duty cycle calculation module 142, whose input end is connected to the output end of the first edge monitoring module, is used to start counting the reference clock signal when the first trigger signal arrives, and end counting when the third trigger signal arrives to obtain the number of high-level pulses, determine the ratio of the number of high-level pulses to the pulse signal period as the pulse signal duty cycle, and output the pulse signal duty cycle.

[0053] The duty cycle change monitoring module 144 has an input end connected to the output end of the duty cycle calculation module and is used to compare whether the duty cycles of two adjacent pulse signals are the same. When the duty cycles of the two adjacent pulse signals are different, the fourth trigger signal is output.

[0054] The duty cycle change counting module 146 has an input end connected to the output end of the duty cycle change monitoring module and is used to count the fourth trigger signal.

[0055] In some embodiments, the pulse duty cycle monitoring module can also compare the number of fourth trigger signals output by the duty cycle change counting module 146 with a preset duty cycle change threshold, and output a duty cycle change alarm signal when the number of the fourth trigger signals is greater than the preset duty cycle change threshold.

[0056] In an exemplary embodiment, the pulse duty cycle monitoring module uses a separate edge detection module. In this case, the pulse period monitoring module also includes a falling edge monitoring module 148, whose input end is connected to the output end of the first synchronizer, for monitoring the falling edge of the synchronization pulse signal and outputting a third trigger signal when the falling edge of the synchronization pulse signal arrives.

[0057] In this embodiment, the duty cycle calculation module 142 has an input end connected to the output end of the rising edge monitoring module and the output end of the falling edge monitoring module.

[0058] In some embodiments, the pulse duty cycle monitoring module may include a combination of one or more of the above structures, depending on monitoring requirements. The pulse duty cycle monitoring module may only support real-time monitoring of the duty cycle, or it may generate an indication signal when the duty cycle changes to a certain value, and the central control determines whether to respond.

[0059] In some embodiments, the duty cycle calculation module 142 and the duty cycle change counting module 146 may be implemented using counters.

[0060] In this embodiment, the duty cycle calculation module can use the rising edge of the first trigger signal, i.e., the synchronization pulse signal, as the count start mark, and the falling edge of the third trigger signal, i.e., the synchronization pulse signal, as the count end mark, record the current value and then reset it to zero. The duty cycle is then calculated in combination with the pulse signal period obtained in the period calculation module 122.

[0061] In this embodiment, the duty cycle change counting module may use the rising edge of the fourth trigger signal as a counting mark, and clear it when outputting an alarm signal or when the duty cycle of the pulse signal returns to normal.

[0062] In some embodiments, the duty cycle change threshold can be set according to the sensitivity of the alarm abnormality. The smaller the duty cycle change threshold, the higher the sensitivity to the abnormal duty cycle of the pulse signal.

[0063] Through the embodiments of the present disclosure, pulse signals of any duty cycle can be monitored, abnormal duty cycle monitoring of pulse signals can be achieved, signal abnormalities in the chip can be discovered in a timely manner, and stable operation of the chip system can be guaranteed.

[0064] In another embodiment, when the pulse period monitoring module and the pulse duty cycle monitoring module share an edge monitoring module, the rising edge monitoring module and the falling edge monitoring module are the same edge monitoring module, namely, the first edge monitoring module 18 .

[0065] FIG4 is a structural block diagram of a pulse signal monitoring circuit according to an embodiment of the present disclosure. As shown in FIG4 , the pulse signal monitoring circuit may further include a clock monitoring module 20 .

[0066] In this embodiment, the clock monitoring module 20 includes the following structure:

[0067] A clock frequency deviation monitoring module 22, configured to monitor the frequency and frequency deviation of a clock signal to be measured based on the reference clock signal;

[0068] The clock presence monitoring module 24 is configured to monitor the presence status of the clock signal to be measured based on the reference clock signal.

[0069] In this embodiment, the clock signal to be measured may be a pulse signal with a duty cycle of 50%.

[0070] In this embodiment, the reference clock signal is the only reference of the clock monitoring module and may be derived from an external crystal oscillator or a stable clock generation unit. The stability of the reference clock must be ensured.

[0071] Through the embodiments of the present disclosure, flexible monitoring of pulse signals and clock signals with duty cycles other than 50% can be achieved, and different monitoring modules can be called or connected for processing according to monitoring requirements, thereby expanding the scope of application of the chip monitoring system.

[0072] In some embodiments, the clock monitoring module further includes:

[0073] A frequency divider, configured to divide the input clock signal to be measured based on a preset frequency division coefficient and output a frequency-divided signal;

[0074] A second synchronizer, whose input end is connected to the output end of the frequency divider, is used to synchronize the frequency-divided signal to the clock domain of the reference clock signal and output a synchronized clock signal;

[0075] a second edge monitoring module, whose input end is connected to the output end of the second synchronizer, for monitoring the rising edge of the synchronization clock signal and outputting a fifth trigger signal when the rising edge of the synchronization clock signal arrives;

[0076] A counting module, whose input end is connected to the output end of the second edge monitoring module, is used to start counting the reference clock signal when the fifth trigger signal arrives, and end counting when the fifth trigger signal arrives next time, and output the count value.

[0077] In some embodiments, if the frequency of the clock signal to be measured is correct, the count value is the frequency ratio of the reference clock signal and the synchronous clock signal (or the divided clock signal to be measured).

[0078] In some embodiments, the clock frequency deviation monitoring module and the clock presence monitoring module may share a frequency divider, a synchronizer, an edge detection module, and a counting module, or may be used independently.

[0079] FIG5 is a block diagram of a clock frequency deviation monitoring module according to an embodiment of the present disclosure. As shown in FIG5 , the clock frequency deviation monitoring module 22 may include the following structures:

[0080] The frequency deviation detection module 222 has an input end connected to the output end of the counting module and is configured to output a frequency deviation alarm signal when the count value is greater than a preset frequency deviation upper limit or less than a preset frequency deviation lower limit.

[0081] The frequency detection module 224 has an input end connected to the output end of the counting module, and is used to determine the frequency of the clock signal to be measured according to the counting value, the frequency division coefficient and the reference clock frequency.

[0082] In this embodiment, the frequency deviation upper limit value and the frequency deviation lower limit value can be flexibly configured according to the requirements of frequency deviation detection accuracy. The frequency deviation upper limit value is the sum of the standard count value when no frequency deviation occurs and the frequency deviation detection accuracy, and the frequency deviation lower limit value is the difference between the standard count value and the frequency deviation detection accuracy.

[0083] In some embodiments, the frequency detection module requires a stable clock source as a reference clock. The reference clock can come from an external crystal oscillator, an off-chip clock chip, or other stable clock sources. According to the Nyquist sampling theorem, to ensure accurate sampling, the reference clock frequency must be greater than twice the frequency of the clock to be measured.

[0084] FIG6 is a block diagram of a clock presence monitoring module according to an embodiment of the present disclosure. As shown in FIG6 , the clock presence monitoring module 24 may include the following structures:

[0085] The in-place detection module 242 has an input end connected to the output end of the counting module, receives the input count value and a preset in-place detection threshold, and is used to determine that the in-place state of the clock signal to be measured is a lost state when the count value is greater than the in-place detection threshold, and output an in-place alarm signal.

[0086] In some embodiments, the presence detection threshold may be set according to the frequency range of the clock signal to be detected.

[0087] In an exemplary embodiment, if the clock signal to be measured is not lost, the signal width after frequency division ranges from 0.5M to 2M, where M is the pulse width of the stable and non-lost low-speed clock source, and the in-position detection threshold can also be set to 0.5M to 2M.

[0088] In an exemplary embodiment, when the clock frequency deviation monitoring module and the clock presence monitoring module share the frequency divider, the second synchronizer, the second edge monitoring module, and the counting module, an input end of the clock frequency deviation monitoring module and an input end of the clock presence monitoring module are connected to an output end of the same counting module;

[0089] In another exemplary embodiment, when the clock frequency deviation monitoring module and the clock presence monitoring module do not share the frequency divider, the second synchronizer, the second edge monitoring module and the counting module, the clock frequency deviation monitoring module and the clock presence monitoring module respectively include a group of the frequency divider, the second synchronizer, the second edge monitoring module and the counting module.

[0090] In this embodiment, the input ends of the frequency deviation detection module, the frequency detection module, and the presence detection module may be connected to the counting modules in the corresponding groups.

[0091] FIG7 is a block diagram of a pulse signal monitoring circuit according to another embodiment of the present disclosure. As shown in FIG7 , the pulse signal monitoring circuit may further include the following structures:

[0092] There are multiple clock monitoring modules 20 , frequency deviation monitoring and aggregation modules 30 and in-position monitoring and aggregation modules 40 .

[0093] In this embodiment, the plurality of clock monitoring modules are configured to output multiple frequency deviation detection signals and multiple in-position detection signals, wherein each of the clock signals to be measured is input into one of the clock monitoring modules, and a frequency deviation detection signal is output from the clock frequency deviation monitoring module of each of the clock monitoring modules, and a in-position detection signal is output from the clock in-position monitoring module of each of the clock monitoring modules, wherein the frequency deviation detection signal includes a frequency deviation alarm signal and a normal frequency deviation signal, and the in-position detection signal includes an in-position alarm signal and a normal in-position signal;

[0094] In this embodiment, the frequency deviation monitoring and aggregation module has an input end connected to the output ends of the multiple clock monitoring modules, receives the input multiple frequency deviation detection signals and a preset frequency deviation detection mask, determines whether each frequency deviation detection signal is output according to the frequency deviation detection mask, performs an OR operation on the masked multiple frequency deviation detection signals, and outputs a summarized frequency deviation detection result.

[0095] In this embodiment, the input end of the on-site monitoring summary module is connected to the output ends of the multiple clock monitoring modules, receives the input multiple on-site detection signals and a preset on-site detection mask, determines whether each of the multiple on-site detection signals is output according to the on-site detection mask, and performs an OR operation on the multiple on-site detection signals after mask processing, and outputs a summarized on-site detection result.

[0096] Through the disclosed embodiments, multiple clock inputs can be monitored, and the monitoring results can be aggregated and reported through aggregation logic. Depending on the monitoring scenario's sensitivity to clock frequency deviation or presence status, the frequency deviation detection mask and presence detection mask can be configured to determine whether the monitoring results are output.

[0097] FIG8 is a schematic diagram of a processing flow of a pulse monitoring module according to an embodiment of the present disclosure. As shown in FIG8 , the pulse monitoring module includes the following structure:

[0098] The synchronizer, through synchronization processing, realizes the synchronous release of the asynchronous signal in the input clock domain. In this embodiment, it is used to synchronize the clock domain of the input pulse (in_pulse), i.e., the pulse signal to be measured, with the clock domain of the reference clock.

[0099] The rising edge sampler samples the rising edge of the input pulse under the control of the working clock gating signal (wclk_gate).

[0100] The period calculation module calculates the number of reference clocks between two adjacent rising edges of the pulse signal to be measured, that is, the period of the pulse signal.

[0101] The cycle change monitoring module compares whether the number of cycles has changed between the previous and next cycles.

[0102] The change cycle counting module records the number of changes in the cycle number.

[0103] The falling edge sampler samples the falling edge of the input pulse under the control of the working clock gating signal (wclk_gate).

[0104] The duty cycle calculation module calculates the number of reference clocks between the rising edge and the falling edge of the pulse signal to be measured, and calculates the duty cycle of the pulse to be measured in combination with the period output by the period calculation module.

[0105] The duty cycle change monitoring module compares the duty cycles calculated twice to see if they have changed.

[0106] The duty cycle change counting module records the number of duty cycle changes.

[0107] In this embodiment, the synchronizer is equivalent to the first synchronizer in the above embodiment, and the rising edge sampler and the falling edge sampler are equivalent to the first edge monitoring module in the above embodiment.

[0108] In some embodiments, the pulse monitoring module further includes registers for storing processing results of other modules.

[0109] In this embodiment, the workflow of the pulse monitoring module may include the following steps:

[0110] Step S101 , synchronizing input pulses in a reference clock domain.

[0111] Step S102: sampling the rising edge of the input pulse to identify the range of a single cycle.

[0112] Step S103, calculate the number of cycles, determine the number of reference clocks between two rising edges, and when a rising edge is encountered, clear the counter to zero, perform the next round of counting, and store the current count value in the register. The reference clock divided by the current value is the frequency value of the pulse.

[0113] Step S104, when the pulse high level is valid, start counting the number of cycles of the reference clock, and record the current value after counting to the maximum value. Since the number of pulses in the entire cycle has been obtained in step S103, the duty cycle can be obtained by dividing it.

[0114] In step S105, the count values ​​of step S103 and step S104 are monitored and compared with the count values ​​of the next cycle. If the difference is greater than a threshold, an interrupt is reported, indicating that the cycle and duty cycle have changed.

[0115] In some embodiments, the threshold value in step S105 can be set according to the sensitivity of monitoring. The minimum threshold value can be zero. As long as the number of cycles or duty cycles of two adjacent ones are different, an interrupt signal is reported.

[0116] In some embodiments, after step S105, the process further includes counting the number of period changes or duty cycle changes, and comparing the number of changes with a period change threshold or a duty cycle change threshold, and generating a corresponding alarm signal when the threshold is exceeded.

[0117] In an exemplary embodiment, the pulse monitoring module is used to perform period monitoring and duty cycle monitoring on pulse signals with any duty cycle, and the clock monitoring module is used to perform frequency deviation monitoring and in-position monitoring on pulse signals with a duty cycle of 50% (ie, clock signals).

[0118] FIG9 is a schematic diagram of a processing flow of a clock monitoring module according to an embodiment of the present disclosure. As shown in FIG9 , the clock monitoring module includes the following structure:

[0119] The frequency divider provides clocks of different frequencies and divides the original clock frequency to be measured to achieve the purpose of frequency reduction.

[0120] Synchronizers, through synchronization processing, enable the synchronous release of asynchronous signals in the input clock domain. This allows the clock signal under test to be synchronized to the desired clock domain for release, and reduces the probability of metastability that may occur when the clock signal under test is released due to crossing clock domains.

[0121] The rising edge sampler is used to monitor the rising edge of the clock signal to be measured.

[0122] The counter is used to realize the counting function, mainly to calculate the number of reference clocks between two adjacent rising edges of the clock to be measured.

[0123] The frequency deviation detection module is used to compare the count value with the frequency deviation lower limit and the frequency deviation upper limit to determine whether the clock is out of lock and output the frequency deviation status (ie, the frequency deviation detection signal).

[0124] The frequency detection module is used to calculate the frequency of the clock signal.

[0125] The presence detection module is used to compare the count value with the presence detection threshold to determine whether clock loss occurs and output a presence status (ie, a presence detection signal).

[0126] In this embodiment, the synchronizer is equivalent to the second synchronizer, the rising edge sampler is equivalent to the second edge monitoring module, and the counter is equivalent to the calculation module.

[0127] In some embodiments, the clock monitoring module further includes registers for storing processing results of other modules.

[0128] In some embodiments, the clock monitoring module supports three functions, namely, clock frequency deviation monitoring and reporting, clock presence monitoring and reporting, and clock frequency monitoring.

[0129] In an exemplary embodiment, the workflow of the clock monitoring module for monitoring and reporting clock frequency deviation may include the following steps:

[0130] In step S201, a configurable frequency division coefficient is generated. This coefficient can be derived from other clock domains and then needs to be synchronized to the clock domain to be tested. After the signal is stable, it is used in subsequent frequency division units.

[0131] In step S202, the clock to be tested is divided, where the division coefficient comes from step S201, and the clock to be tested is divided to at least half of the reference clock. The reference clock serves as the only benchmark for the clock monitoring module and can be derived from an external crystal oscillator or a stable clock generation unit. The stability of the reference clock must be guaranteed.

[0132] Step S203, synchronize the divided clock to be measured in the reference clock domain, synchronize it in the reference clock domain, and use it for the rising edge sampler. Each cycle after the division is used as a cycle of the counter. If the frequency of the clock to be measured is normal, then the count value will be the frequency ratio of the reference clock and the divided clock to be measured.

[0133] Step S204, generating a counting flag, counting until the frequency division flag is pulled high and then cleared to zero and counted again, this flag is the rising edge of the clock to be measured after frequency division in the reference clock domain, and the high level duration is one reference clock cycle.

[0134] Step S205 , counting starts from zero in the reference clock domain, and is cleared and restarted when the counting flag is pulled high.

[0135] Step S206, judging whether the counting period is within an acceptable range. According to the requirements for clock quality, the frequencies of the clock to be measured and the reference clock can provide upper and lower threshold values ​​for counting. If the counting value is lower than the lower limit or higher than the upper limit, a clock frequency abnormality will be reported.

[0136] In the disclosed embodiment, the frequency division coefficient and threshold of the clock to be measured can be flexibly configured. For different chips and scenarios, it is only necessary to modify the parameters according to the actual situation, which makes the system more flexible and maintainable.

[0137] In an exemplary embodiment, the workflow of the clock monitoring module for monitoring and reporting clock presence may include the following steps:

[0138] In step S301, a configurable frequency division coefficient is generated. This coefficient can be derived from other clock domains and then needs to be synchronized to the clock domain to be tested. After the signal is stable, it is used in subsequent frequency division units.

[0139] In step S302, the clock to be tested is divided, where the division coefficient comes from step S301, and the clock to be tested is divided to at least half of the reference clock. The reference clock is the only benchmark of this monitoring unit and can be derived from an external crystal oscillator or a stable clock generation unit. The stability of the reference clock must be guaranteed.

[0140] Step S303, synchronize the divided clock to be measured in the reference clock domain, synchronize it in the reference clock domain, and use it for the rising edge sampler. Each cycle after division is used as a cycle of the counter. If the frequency of the clock to be measured is normal, then the count value will be the frequency ratio of the reference clock and the divided clock to be measured.

[0141] Step S304, generating a counting flag, counting until the frequency division flag is pulled high and then cleared to zero and counted again. This flag is the rising edge of the clock to be measured after frequency division in the reference clock domain, and the high level duration is one reference clock cycle.

[0142] Step S305 , counting starts from zero in the reference clock domain, and is cleared and restarted when the counting flag is pulled high.

[0143] In step S306, the count value in step S305 is compared with the set threshold. When the count value is greater than the threshold, it means that the clock has not flipped as expected, and the loss alarm is raised.

[0144] In an exemplary embodiment, the workflow of the clock monitoring module for performing clock frequency monitoring may include the following steps:

[0145] In step S401, a configurable frequency division coefficient is generated. This coefficient can be derived from other clock domains and then needs to be synchronized to the clock domain to be tested. After the signal is stable, it is used in subsequent frequency division units.

[0146] In step S402, the clock to be tested is divided, where the division coefficient comes from step S401, and the clock to be tested is divided to at least half of the reference clock. The reference clock is the only benchmark of this monitoring unit and can be derived from an external crystal oscillator or a stable clock generation unit. The stability of the reference clock must be guaranteed.

[0147] Step S403, synchronize the divided clock to be measured in the reference clock domain, synchronize it in the reference clock domain, and use it for the rising edge sampler. Each cycle after the division is used as a cycle of the counter. If the frequency of the clock to be measured is normal, then the count value will be the frequency ratio of the reference clock and the divided clock to be measured.

[0148] Step S404: Generate a counting flag. Count until the frequency division flag is pulled high and then cleared and counted again. This flag is the rising edge of the clock to be measured after frequency division in the reference clock domain. The high level duration is one reference clock cycle.

[0149] Step S405, counting starts from zero in the reference clock domain, and when the count flag is pulled high, it is cleared and restarted, and the count value is output. According to the reference clock frequency and the frequency division coefficient, the count value can be used to calculate the frequency of the clock to be measured.

[0150] FIG10 is a schematic diagram of a signal aggregation process of multiple clock monitoring modules according to an embodiment of the present disclosure. As shown in FIG10 , multiple clock signals to be measured can be monitored by instantiating the clock monitoring module multiple times.

[0151] In this embodiment, the monitoring results of the clock monitoring module can be sent through register reading and writing. If the output status of multiple clock sources needs to be summarized, a one-bit status bit can be generated through the summary logic for reporting.

[0152] In some embodiments, if certain scenarios are not sensitive to clock frequency deviation or in-bit status, a mask bit can be added to determine whether the monitoring result is output by configuring the mask bit. However, the mask value does not affect the operation of the monitoring module. The clock monitoring module is only affected by the internal enable signal of the module.

[0153] In this embodiment, the mask includes a frequency deviation detection mask and a presence monitoring mask.

[0154] In some embodiments, the effective level and level of the mask can be set according to actual needs.

[0155] In one exemplary embodiment, a two-level mask with an active-high level is used as an example. A mask bit of 1 masks the detection signal, and a detection signal of 1 indicates an alarm signal output. Each mask bit is inverted and an AND operation is performed on the corresponding frequency deviation / presence detection signal. An alarm signal is output only when the mask bit is 0 and the detection signal is 1; otherwise, no alarm signal is output. When aggregating the signals, an OR operation is performed on multiple masked frequency deviation / presence detection signals. If any frequency deviation / presence alarm signal is output, the aggregated frequency deviation / presence detection result is output as 1, generating an alarm.

[0156] In some embodiments, the logic operation process of the mask high level is as follows:

[0157] Y0=clock_unlock0&&(~mask0)

[0158] ...

[0159] Y N=clock_unlock N &&(~mask N )

[0160] Y total =|{Y0,Y1,Y2,Y3...Y N}

[0161] Among them, Y0, Y N Indicates the frequency deviation / in-place detection signals after mask processing. Since the frequency deviation abnormality can also be called clock unlock, clock_unlock0 to clock_unlockN respectively represent the frequency deviation detection signals. The frequency deviation detection signal can be replaced by the in-place detection signal. mask0, mask N Indicates the mask bit corresponding to each detection signal, Y total Indicates the summarized frequency offset / presence detection results.

[0162] In one exemplary embodiment, a two-level mask with an active-low level is used as an example. A mask bit of 0 blocks the detection signal, while a detection signal of 1 signals an alarm output. An AND operation is performed on each mask bit and the corresponding frequency deviation / presence detection signal. An alarm signal is output only when both the mask bit and the detection signal are 1; otherwise, no alarm signal is output. When signals are aggregated, an OR operation can be performed on multiple masked frequency deviation / presence detection signals. If any frequency deviation / presence alarm signal is output, the aggregated frequency deviation / presence detection result is output as 1, generating an alarm.

[0163] In some embodiments, the logic operation process of the mask low level is as follows:

[0164] Y0=clock_unlock0&&(mask0)

[0165] ...

[0166] Y N =clock_unlock N &&(mask N )

[0167] Y total =|{Y0,Y1,Y2,Y3...Y N}

[0168] Among them, Y0, Y N Indicates the frequency deviation / in-place detection signals after mask processing. Since the frequency deviation abnormality can also be called clock unlock, clock_unlock0 to clock_unlockN respectively represent the frequency deviation detection signals, mask0, mask N Indicates the mask bit corresponding to each detection signal, Ytotal Indicates the summarized frequency offset / presence detection results.

[0169] In some embodiments, when summarizing the clock presence status, the frequency deviation detection signal clock_unlock may be replaced with the presence detection signal.

[0170] FIG11 is a waveform diagram of a pulse period monitoring module according to an embodiment of the present disclosure. As shown in FIG11 , the pulse period monitoring module involves the following signals:

[0171] Reference clock (ref_clk), input pulse (in_pulse), input pulse synchronization signal (in_pulse_sync), input frequency count flag (in_freq_cnt_flag), input frequency count (in_freq_cnt).

[0172] In this embodiment, the reference clock may come from a stable clock source such as an external crystal oscillator, an off-chip clock chip, etc. To ensure sampling accuracy, the reference clock frequency must be greater than twice the pulse frequency.

[0173] In this embodiment, the input pulse (in_pulse) is synchronized to the clock domain of the reference clock (ref_clk) to generate an input pulse synchronization signal (in_pulse_sync). The input frequency count flag (in_freq_cnt_flag) serves as a cycle completion marker, triggered by the rising edge of the input pulse synchronization signal (in_pulse_sync), and can last for one reference signal cycle.

[0174] In this embodiment, the input frequency count (in_freq_cnt) is used to count the number of reference clocks between two adjacent input frequency count flags. After the counter counts from one flag bit to the next flag bit, it saves the current count value cnt and then clears it to zero and starts counting again for the next round.

[0175] In some embodiments, if the frequency of the reference clock is known to be Fref, the frequency of the input pulse (i.e., the pulse signal to be measured) can be calculated using Fref / cnt or Fref / (cnt+1), where the specific use of cnt or cnt+1 is determined by the initial value of the counter. If the counter starts counting from 0, the input pulse frequency is Fref / cnt; if the counter starts counting from 1, the input pulse frequency is Fref / (cnt+1).

[0176] FIG12 is a waveform diagram of a pulse duty cycle monitoring module according to an embodiment of the present disclosure. As shown in FIG12 , the pulse duty cycle monitoring module involves the following signals:

[0177] Reference clock (ref_clk), input pulse (in_pulse), input pulse synchronization signal (in_pulse_sync), input frequency count flag (in_freq_cnt_flag), input duty cycle count (in_duty_cnt).

[0178] In this embodiment, duty cycle calculation is similar to frequency calculation, both of which calculate pulse length by counting the reference clock. However, the pulse duty cycle monitoring module counts the high level of the pulse, sampling on the rising edge and clearing on the falling edge. The input duty cycle count (in_duty_cnt) is stored in a register. The duty cycle is then calculated based on the reference clock frequency and the input frequency count (in_freq_cnt).

[0179] In an exemplary embodiment, assuming that the frequency count value of a single cycle is data_freq and the duty cycle count value is data_duty, the duty cycle can be expressed as: data_duty / data_freq or (data_duty+1) / (data_freq+1), and whether to add 1 depends on the initial value of the counter.

[0180] Through the embodiments of the present disclosure, the duty cycle of any pulse signal can be calculated, which improves the applicability of the chip monitoring system. At the same time, fault monitoring can be performed by comparing the count values ​​before and after the duty cycle / period of the pulse signal, which increases the stability of the system.

[0181] An embodiment of the present disclosure further provides a chip, which includes the pulse signal monitoring circuit in any one of the above embodiments.

[0182] In some embodiments, the chip can be applied to various scenarios such as automotive electronics, consumer electronics, and communications, but the present disclosure does not impose any restrictions on this.

[0183] An embodiment of the present disclosure further provides an electronic device, which includes the pulse signal monitoring circuit in any one of the above embodiments.

[0184] In some embodiments, the device may further include the chip in the above embodiments.

[0185] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail here.

[0186] The foregoing is merely an exemplary embodiment of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art will readily appreciate that the present disclosure is susceptible to various modifications and variations. Any modifications, equivalent substitutions, improvements, and the like made within the principles of the present disclosure shall be included within the scope of protection of the present disclosure.

Claims

1. A pulse signal monitoring circuit, the circuit comprising a pulse monitoring module, the pulse monitoring module comprising: A pulse cycle monitoring module, used to monitor the cycle of the pulse signal to be measured and the cycle change between two adjacent cycles based on the reference clock signal; A pulse duty cycle monitoring module is used to monitor the duty cycle of the pulse signal to be tested and the duty cycle change between two adjacent cycles based on the reference clock signal.

2. The circuit according to claim 1, wherein The pulse monitoring module also includes: A first synchronizer, used for synchronizing the input pulse signal to be tested to the clock domain of the reference clock signal to output a synchronization pulse signal; The pulse period monitoring module comprises: A rising edge monitoring module, whose input end is connected to the output end of the first synchronizer, is used to monitor the rising edge of the synchronization pulse signal and output a first trigger signal when the rising edge of the synchronization pulse signal arrives; A period calculation module, whose input end is connected to the output end of the rising edge monitoring module, is used to start counting the reference clock signal when the first trigger signal arrives, and end counting when the first trigger signal arrives next time, and output the pulse signal period.

3. The circuit according to claim 2, wherein: The pulse period monitoring module also includes: The period change monitoring module has an input end connected to the output end of the period calculation module and is used to compare whether the periods of two adjacent pulse signals are the same, and output a second trigger signal when the periods of the two adjacent pulse signals are different.

4. The circuit according to claim 3, wherein: The pulse period monitoring module also includes: A change cycle counting module, whose input end is connected to the output end of the period change monitoring module, is used to count the second trigger signal.

5. The circuit according to claim 4, wherein: The pulse cycle monitoring module is also used to compare the number of second trigger signals output by the change cycle counting module with a preset cycle change threshold, and output a cycle change alarm signal when the number of the second trigger signals is greater than the cycle change threshold.

6. The circuit according to claim 2, wherein: The pulse duty cycle monitoring module comprises: A falling edge monitoring module, whose input end is connected to the output end of the first synchronizer, is used to monitor the falling edge of the synchronization pulse signal and output a third trigger signal when the falling edge of the synchronization pulse signal arrives; A duty cycle calculation module, whose input end is connected to the output end of the rising edge monitoring module and the output end of the falling edge monitoring module, is used to start counting the reference clock signal when the first trigger signal arrives, and end counting when the third trigger signal arrives to obtain the number of high-level pulses, determine the ratio of the number of high-level pulses to the pulse signal period as the pulse signal duty cycle, and output the pulse signal duty cycle.

7. The circuit according to claim 6, wherein: The pulse duty cycle monitoring module also includes: The duty cycle change monitoring module has an input end connected to the output end of the duty cycle calculation module and is used to compare whether the duty cycles of two adjacent pulse signals are the same. When the duty cycles of the two adjacent pulse signals are different, a fourth trigger signal is output.

8. The circuit according to claim 7, wherein: The pulse duty cycle monitoring module also includes: A duty cycle change counting module, whose input end is connected to the output end of the duty cycle change monitoring module, is used to count the fourth trigger signal.

9. The circuit according to claim 8, wherein The pulse duty cycle monitoring module is also used to compare the number of fourth trigger signals output by the duty cycle change counting module with a preset duty cycle change threshold, and output a duty cycle change alarm signal when the number of the fourth trigger signals is greater than the duty cycle change threshold.

10. The circuit according to claim 6, wherein In the case where the pulse period monitoring module and the pulse duty cycle monitoring module share an edge monitoring module, the rising edge monitoring module and the falling edge monitoring module are the same edge monitoring module.

11. The circuit according to claim 1, wherein: The circuit further includes a clock monitoring module, and the clock monitoring module includes: A clock frequency deviation monitoring module, used to monitor the frequency and frequency deviation of the clock signal to be measured based on the reference clock signal; The clock presence monitoring module is used to monitor the presence status of the clock signal to be tested based on the reference clock signal.

12. The circuit according to claim 11, wherein The clock monitoring module also includes: A frequency divider, used for dividing the input clock signal to be measured based on a preset frequency division coefficient, and outputting a frequency division signal; A second synchronizer, whose input end is connected to the output end of the frequency divider, is used to synchronize the frequency-divided signal to the clock domain of the reference clock signal and output a synchronized clock signal; A second edge monitoring module, whose input end is connected to the output end of the second synchronizer, is used to monitor the rising edge of the synchronization clock signal and output a fifth trigger signal when the rising edge of the synchronization clock signal arrives; A counting module, whose input end is connected to the output end of the second edge monitoring module, is used to start counting the reference clock signal when the fifth trigger signal arrives, and to end counting when the fifth trigger signal arrives next time, and output the count value.

13. The circuit of claim 12, wherein: The clock frequency deviation monitoring module comprises: The frequency deviation detection module has an input end connected to the output end of the counting module and is used to output a frequency deviation alarm signal when the count value is greater than a preset frequency deviation upper limit or less than a preset frequency deviation lower limit.

14. The circuit of claim 12, wherein: The clock frequency deviation monitoring module comprises: A frequency detection module, whose input end is connected to the output end of the counting module, is used to determine the frequency of the clock signal to be measured according to the counting value, the frequency division coefficient and the reference clock frequency.

15. The circuit of claim 12, wherein: The clock presence monitoring module comprises: The in-place detection module has an input end connected to the output end of the counting module and is used to determine that the in-place state of the clock signal to be measured is a lost state and output an in-place alarm signal when the count value is greater than a preset in-place detection threshold.

16. The circuit of claim 12, wherein: In the case where the clock frequency deviation monitoring module and the clock presence monitoring module share the frequency divider, the second synchronizer, the second edge monitoring module and the counting module, the input end of the clock frequency deviation monitoring module and the input end of the clock presence monitoring module are connected to the output end of the same counting module; When the clock frequency deviation monitoring module and the clock presence monitoring module do not share the frequency divider, the second synchronizer, the second edge monitoring module and the counting module, the clock frequency deviation monitoring module and the clock presence monitoring module respectively include a group of the frequency divider, the second synchronizer, the second edge monitoring module and the counting module.

17. The circuit according to claim 11, the circuit comprising a plurality of the clock monitoring modules, the circuit further comprising a frequency deviation monitoring summary module and an in-position monitoring summary module, wherein: The multiple clock monitoring modules are used to output multiple frequency deviation detection signals and multiple in-place detection signals, wherein each of the clock signals to be measured is input into one of the clock monitoring modules, and a frequency deviation detection signal is output from the clock frequency deviation monitoring module of each of the clock monitoring modules, and a in-place detection signal is output from the clock in-place monitoring module of each of the clock monitoring modules, wherein the frequency deviation detection signal includes a frequency deviation alarm signal and a normal frequency deviation signal, and the in-place detection signal includes an in-place alarm signal and a normal in-place signal; The frequency deviation monitoring and summarizing module, whose input end is connected to the output ends of the multiple clock monitoring modules, receives the input multiple frequency deviation detection signals and a preset frequency deviation detection mask, determines whether each frequency deviation detection signal is output according to the frequency deviation detection mask, and performs an OR operation on the multiple frequency deviation detection signals after mask processing, and outputs a summarized frequency deviation detection result; The in-place monitoring summary module has an input end connected to the output ends of the multiple clock monitoring modules, receives the input multiple in-place detection signals and a preset in-place detection mask, determines whether each of the multiple in-place detection signals is output according to the in-place detection mask, performs an OR operation on the multiple in-place detection signals after mask processing, and outputs a summarized in-place detection result.

18. A chip, comprising the pulse signal monitoring circuit described in any one of claims 1 to 17.

19. An electronic device, comprising the pulse signal monitoring circuit according to any one of claims 1 to 17.

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