Deadtime adjustment method, adaptive ZVS control method and switching power supply

Abstract

The present invention provides a deadtime adjustment method, an adaptive ZVS control method and a switching power supply. The deadtime adjustment method comprises: step 11), acquiring a first duration, collecting a second duration of the current period, and comparing the first duration with the second duration; step 12), if the first duration is greater than the second duration, reducing the on-time of a clamping transistor by a preset duration in the next period; if the first duration is smaller than the second duration, increasing the on-time of the clamping transistor by the preset duration in the next period; and if the first duration is equal to the second duration, maintaining the on-time of the clamping transistor in the next period; and step 13), returning to step 11) to sequentially adjust the deadtime between the clamping transistor in each period and a main switch. The present invention can accurately realize self-adaptive control in the deadtime full-load range between an upper clamping transistor and a main switching transistor, thereby achieving high safety, low loss of the main switching transistor, high system efficiency, and wide application range.

Description

Dead time adjustment method, adaptive ZVS control method and switching power supply Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a dead time adjustment method, an adaptive ZVS control method, and a switching power supply. Background Art

[0002] In transformer-based switching power supplies, the drain terminal of the primary power switch experiences significant switching stress due to the transformer's leakage inductance. Therefore, leakage inductance absorption circuits are often used in engineering to recover the energy in the leakage inductance and reduce the switching stress on the drain terminal of the power switch. Common leakage inductance recovery circuits include RCD (resistance, capacitor, diode) clamping circuits, LCD (inductor, capacitor, diode) clamping circuits, and active clamping circuits. Active clamping circuits utilize active components with lower on-resistance and better switching characteristics to recover leakage inductance energy, reducing stress on the primary power switch while further reducing losses in the clamping circuit. Therefore, compared to passive clamping switching power supplies, active clamping switching power supplies can achieve higher efficiency and higher switching frequencies. Because the energy in the leakage inductance is absorbed, there are no leakage inductance spikes during the primary power switch's turn-on process, resulting in a wider input voltage range and lower EMI noise. Furthermore, the widespread adoption of third-generation GaN semiconductor power devices is driving the development of ACF switching power supplies towards smaller size and higher power density.

[0003] However, the dead time between the clamping transistor and the main switch was fixed and not adjustable, which could easily prevent the system from achieving ZVS (zero voltage switch-on) control across the full load range, resulting in energy loss in the switch. Existing technologies adjust and calculate the dead time based on input and output voltages and parasitic capacitance. However, due to the uniqueness and complexity of parasitic capacitance, it is difficult to accurately determine the specific capacitance value. Consequently, the calculated dead time is not entirely accurate, and there is a risk that the clamping transistor and the main switch will be turned on simultaneously.

[0004] Therefore, how to reduce the energy loss of the switch tube and improve the accuracy of zero voltage turn-on control has become one of the problems that need to be solved urgently by those skilled in the art.

[0005] It should be noted that the above technical background is merely provided to provide a clear and complete description of the technical solutions of the present invention and to facilitate understanding by those skilled in the art. Simply because these solutions are described in the technical background section of the present invention, it should not be assumed that the above technical solutions are well known to those skilled in the art.

[0006] Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the present invention aims to provide a dead time adjustment method, an adaptive ZVS control method, and a switching power supply, which are used to solve the problems in the prior art such as the inability to accurately control the dead time, the narrow adjustable range of the dead time, the inability to achieve ZVS conduction control over the full load range, the increased loss of the main switch tube as the system operating frequency increases, the failure to achieve the ideal system efficiency, and the restriction of the development of active clamping zero voltage turn-on.

[0008] To achieve the above-mentioned and other related objectives, the present invention provides a dead time adjustment method applied to an active clamp converter, the dead time adjustment method at least comprising:

[0009] Step 11) Obtaining the calculated first duration, collecting the second duration of the current cycle, and comparing the first duration with the second duration; the first duration is the preset dead zone duration from the time the clamping tube in the active clamp converter is turned off to the time the main switch tube is turned on; and the second duration is the time duration from the time the clamping tube is turned off to the time the secondary inductor current of the transformer is completely released;

[0010] Step 12) If the first time duration is greater than the second time duration, reducing the on-time of the clamping transistor by a preset time duration in the next cycle; if the first time duration is less than the second time duration, increasing the on-time of the clamping transistor by a preset time duration in the next cycle; if the first time duration is equal to the second time duration, maintaining the on-time of the clamping transistor by a preset time duration in the next cycle;

[0011] Step 13) Return to step 11) and sequentially adjust the dead time between the clamping transistor and the main switch in each cycle.

[0012] Optionally, a turn-off moment of the clamp tube is acquired based on a driving signal of the clamp tube, and a first timing end signal is triggered when the turn-off duration of the clamp tube reaches the first duration.

[0013] Optionally, the turn-off moment of the clamping tube is obtained based on the driving signal of the clamping tube, and when the zero current detection signal is valid, it is determined that the secondary inductor current of the transformer is completely released, and a second timing end signal is triggered.

[0014] More optionally, the order in which the first timing end signal and the second timing end signal arrive is determined to determine the magnitude relationship between the first duration and the second duration.

[0015] To achieve the above objectives and other related objectives, the present invention further provides an adaptive ZVS control method, which at least includes:

[0016] Step 21) Soft-starting the circuit by controlling the on / off of the main switch and the clamp based on the feedback signal of the active clamp converter, so that the main switch and the clamp are complementary to each other;

[0017] Step 22) After the soft start is completed, the on-time of the clamp tube is adjusted based on the above-mentioned dead time adjustment method, and then the first duration is adaptively adjusted to achieve adaptive zero voltage turn-on control; wherein, when the off-time of the clamp tube in the current cycle reaches the set first duration and the zero voltage detection signal is valid, the main switch tube is turned on.

[0018] Optionally, when the output voltage of the active clamp converter is stable, it is determined that the soft start is terminated.

[0019] Optionally, when the output current of the active clamp converter reaches a defined threshold, the main switch tube is driven to be turned off.

[0020] More optionally, after the main switch tube is turned off for a set time, the clamp tube is driven to be turned on.

[0021] To achieve the above objectives and other related objectives, the present invention further provides a switching power supply, comprising: an active clamped converter, wherein the active clamped converter adopts the above dead time adjustment method to achieve adaptive zero voltage turn-on control.

[0022] Optionally, the active clamp converter is a flyback topology structure or a forward topology structure.

[0023] As described above, the dead time adjustment method, adaptive ZVS control method, and switching power supply of the present invention have the following beneficial effects:

[0024] 1. The dead time adjustment method, adaptive ZVS control method, and switching power supply of the present invention can accurately implement adaptive control of the dead time between the upper clamping tube and the main switch tube, so that the main switch tube can implement adaptive ZVS control. The dead time has a wider adjustable range, and adaptive adjustment of ZVS of the system within the full load range is achieved, with high safety, low main switch tube loss, and high system efficiency.

[0025] 2. The dead time adjustment method and the adaptive ZVS control method of the present invention are applicable to flyback and forward active clamp converters and have a wide range of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG1 shows a schematic structural diagram of an active clamp flyback converter.

[0027] FIG2 shows the control operation waveform of the active clamp flyback converter.

[0028] FIG3 is a schematic flow chart showing a dead time adjustment method according to the present invention.

[0029] FIG4 is a schematic structural diagram of an adaptive zero voltage turn-on control module according to the present invention.

[0030] FIG5 is a schematic diagram showing a specific circuit of the adaptive zero voltage turn-on control module of the present invention.

[0031] FIG6 is a flow chart showing the adaptive ZVS control method of the present invention.

[0032] FIG7 is a schematic diagram showing waveforms of key nodes of the adaptive ZVS control method of the present invention.

[0033] FIG8 is a schematic structural diagram of a driving circuit according to the present invention.

[0034] Component Reference Numbers 1 Active Clamp Flyback Converter 2 Driving Circuit 21 Adaptive Zero Voltage Turn-On Control Module 211 Timing Unit 212 Duration Acquisition Unit 212a Controller 212b Frequency Divider 212c Counter 213 Comparison Unit 213a Comparison Sub-Unit 214 Dead Time Adjustment Unit 214a Adjustment Sub-Unit 22 Power-On Reset Module 23 Logic Control Module 24 Oscillator DETAILED DESCRIPTION

[0035] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0036] Please refer to Figures 1 to 8. It should be noted that the figures provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the figures only show components relevant to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, number, and proportion of each component may be varied arbitrarily, and the component layout may also be more complex.

[0037] As shown in FIG1 , the schematic diagram of the active clamp flyback converter 1 is shown, where Nc is the clamping tube, N0 is the main switch tube, R1 is the clamping resistor, and C RD is the clamping capacitor, T is the transformer, Rs is the sampling resistor, Do is the secondary rectifier diode, R L is the load, Co is the output capacitor, Ceq is the drain-source equivalent capacitance of the main switch tube, Coss is the parasitic capacitance of the main switch tube, and C3 is the parasitic capacitance of the clamp tube. To achieve ZVS control, a control mode in which the main switch tube N0 and the clamp tube Nc are complementary turned on is usually adopted. FIG2 is a control waveform diagram of the active clamp flyback converter 1. In the active clamp flyback converter, the main switch tube N0 can be turned on according to its drain-source voltage V DS And the output power is turned on and off. After the main switch N0 is turned on, the transformer primary inductor current i m Flows through the main switch tube N0 (denoted as I P ), showing a linear increasing trend; when the output current sampling signal reaches the preset reference value (the preset reference value is adjustable, and different values ​​correspond to different stages), the control system turns off the main switch tube N0, and the primary inductance L of the transformer M The stored energy is instantly coupled to the secondary side, and the clamp tube Nc is turned on after a delay of TDP_C after the main switch tube N0 is turned off (at this time, the drain-source voltage V DS =Vin+mVo, where Vin is the input voltage, Vo is the output voltage, and m is the turns ratio of the primary winding to the secondary winding in the transformer. After the clamp tube Nc is turned on, the energy in the leakage inductance can be transferred through the clamp resistor R1 and the clamp capacitor C RD To achieve energy recovery, the primary inductance of the transformer L M The current flows through the clamp tube Nc, and the primary inductor current of the transformer is recorded as i clamp , since the clamp tube Nc is opened, the transformer primary inductor current i m It sinks instantly, but under the action of the parasitic capacitance between the drain and source of the main switch tube N0, the transformer capacitance and the capacitance of the secondary rectifier diode Do, the primary inductor current i m There will be an increasing process. According to the above analysis, in order to achieve ZVS control, the following zero voltage start-up conditions need to be met:

[0038] Among them, i clamp- Direction and i clamp The specified currents are in opposite directions and equal in magnitude; i m- Direction and i m The specified currents are in opposite directions and equal in magnitude; due to the leakage inductance L K The leakage inductance energy is very small, and part of the leakage inductance energy has been recovered, so the leakage inductance energy is no longer considered in formula (1). From the above formula, it can be seen that the drain-source equivalent capacitance Ceq of the main switch tube N0 and the clamping capacitance C RD And the parasitic capacitance between the drain and source of the clamp tube Nc is discharged until the ZVS signal is detected. Therefore, in order to achieve ZVS control, the clamp tube Nc needs to be C The on-time of the clamping tube is continuously and adaptively adjusted, thereby adjusting the dead time between the clamping tube turning off and the main switch tube turning on (other active clamping converters also have the above problems).

[0039] As shown in FIG3 , the present invention provides a dead time adjustment method, which is applied to an active clamp converter and is used to adjust the dead time between the clamping transistor and the main switching transistor. The dead time adjustment method includes:

[0040] Step 11) Obtain the calculated first time length T1, and collect the second time length t2 of the current cycle, and compare the first time length T1 with the second time length t2. Wherein, the first time length T1 is the time length of the clamping transistor N in the active clamping converter. C The preset dead zone time between the shut-down and the opening of the main switch N0 is t2, and the second time t2 is the time between the clamping tube N0 and the closing of the clamping tube N1. C The time from shutdown to complete release of the transformer secondary inductor current.

[0041] Step 12) If the first time duration T1 is greater than the second time duration t2, then in the next cycle, the conduction time T of the clamp transistor Nc is reduced to H_ON Reduce the preset time length Δt. If the first time length T1 is less than the second time length t2, then in the next cycle, the conduction time T of the clamp tube Nc is reduced. H_ON Increase the preset time length Δt. If the first time length T1 is equal to the second time length t2, then the conduction time T of the clamp tube Nc is maintained in the next cycle. H_ON .

[0042] Step 13) Return to step 11) and sequentially adjust the dead time between the clamp transistor Nc and the main switch N0 in each cycle.

[0043] Specifically, the first duration T1 of the current cycle is calculated before the clamp transistor Nc of the current cycle is turned off. The actual dead zone duration of the current cycle must be greater than the calculated first duration T1 (i.e., the preset dead zone duration). As an example, in the initial state, the first duration T1 is determined based on the actual dead zone time of the previous cycle, and the first duration T1 corresponding to each subsequent cycle (i.e., the preset dead zone duration) is continuously adjusted through step 2). In this embodiment, the turn-off time of the clamp transistor Nc is obtained based on the drive signal PWM_C of the clamp transistor Nc. Specifically, when the drive signal PWM_C of the clamp transistor Nc transitions to a low level, a timing start signal is triggered, thereby starting to count the first duration T1. A first timing end signal is triggered when the turn-off time of the clamp transistor Nc reaches the (preset) first duration T1.

[0044] Specifically, the second duration t2 of the current cycle is acquired in real time by the acquisition circuit. In this embodiment, the turn-off moment of the clamp transistor Nc is acquired based on the drive signal of the clamp transistor Nc. As described above, when the drive signal PWM_C of the clamp transistor Nc transitions to a low level, a timing start signal is triggered, initiating the timing of the second duration t2. When the zero current detection signal ZCD is asserted, it is determined that the secondary inductor current of the transformer has been fully discharged, and a second timing end signal is triggered. The zero current detection signal ZCD can be obtained by detecting the voltage on the auxiliary winding (not shown in FIG1 ); detailed description thereof is omitted here.

[0045] It should be noted that any method (signal basis) that can obtain the first duration and the second duration is applicable to the present invention, and is not limited to this embodiment; including but not limited to converting the time signal into a voltage signal and representing the length of time by the amplitude of the voltage, which will not be elaborated here.

[0046] Specifically, in this embodiment, the order of arrival of the first timing end signal and the second timing end signal is determined to determine the size relationship between the first duration T1 and the second duration t2. If the first timing end signal arrives before the second timing end signal, it means that the first duration T1 is less than the second duration t2; if the first timing end signal arrives after the second timing end signal, it means that the first duration T1 is greater than the second duration t2; if the first timing end signal and the second timing end signal arrive at the same time, it means that the first duration T1 is equal to the second duration t2. In actual use, any method that can determine the size relationship between the first duration T1 and the second duration t2 is applicable, and they are not described here one by one; if the zero current detection signal ZCD is sampled valid within the first duration T1, it is determined that the first duration T1 is greater than the second duration t2; if the zero current detection signal ZCD is not sampled valid within the first duration T1, it is determined that the first duration T1 is less than the second duration t2; if the zero current detection signal ZCD is sampled valid at the end of the first duration T1, it is determined that the first duration T1 is equal to the second duration t2.

[0047] Specifically, the clamping tube conduction time T of the next cycle is adjusted based on the comparison result of the current cycle. H_ON , satisfying the following relationship:

[0048] Among them, T H_ON (n+1) is the clamping tube conduction time of the (n+1)th cycle, T H_ON (n) is the clamp tube conduction time of the nth cycle. It should be noted that the preset time length Δt is not greater than the clamp tube conduction time. To improve the accuracy of regulation, the preset time length Δt is set to a smaller value. To improve the efficiency of regulation, the preset time length Δt is set to a larger value. The specific value of the preset time length Δt is set according to actual design requirements so as to achieve adaptive changes in the dead time of each cycle. As an example, the preset time length Δt is configured as n working clock cycles, where n is a natural number greater than or equal to 1, including but not limited to 1 to 10.

[0049] As shown in FIG4 , in this embodiment, the dead time adjustment method of the present invention is implemented based on an adaptive zero voltage turn-on control module 21 , and the adaptive zero voltage turn-on control module 21 includes:

[0050] A timing unit 211 , a duration collecting unit 212 , a comparing unit 213 and a dead time adjusting unit 214 .

[0051] As shown in FIG. 4 , the timing unit 211 is connected to the output end of the dead time adjustment unit 214 , and counts the first duration T1 provided by the dead time adjustment unit 214 .

[0052] Specifically, in an initial state, the timing unit 211 obtains the first duration T1 based on the zero voltage detection signal ZVS. In this case, the first duration T1 is the duration from the clamping transistor turning off to the main switching transistor turning on (an actual measured value). Subsequently, the timing unit 211 obtains a continuously updated first duration T1 (a calculated preset value) based on the dead time adjustment unit 214. In this embodiment, the timing unit 211 is implemented as a timer. A count value of the timer is set based on the first duration T1. The timer begins timing from the time the clamping transistor turns off. When the count value is reached, the timer determines that the first duration T1 has expired and outputs a corresponding count-end signal (illustratively, active high). As the dead time adjustment unit 214 continuously adjusts the first duration T1, the set count value of the timer is also continuously updated.

[0053] It should be noted that any circuit structure that can time the first duration T1 and output a corresponding signal is applicable to the present invention, and is not limited to this embodiment.

[0054] As shown in Figure 4, the duration acquisition unit 212 acquires the time duration from the turn-off of the clamping transistor in the active clamp converter to the complete release of the transformer secondary inductor current, obtaining a second duration t2. As shown in Figure 5, in this embodiment, the duration acquisition unit 212 includes a controller 212a, a frequency divider 212b, and a counter 212c.

[0055] Specifically, as shown in FIG5 , in this embodiment, the controller 212 a receives the clamp transistor drive signal PWM_C and the zero current detection signal ZCD. When the clamp transistor is turned off, a timing start signal is triggered. When the zero current detection signal ZCD is valid, a timing end signal is triggered. As an example, the controller 212 a is implemented using an RS flip-flop. The set terminal s of the RS flip-flop is connected to the clamp transistor drive signal PWM_C, and the reset terminal is connected to the zero current detection signal ZCD. The controller 212 a outputs timing start and end control signals. When the clamp transistor drive signal PWM_C transitions to a low level, the output signal CTR of the RS flip-flop transitions to a high level (i.e., a timing start signal). When the zero current detection signal ZCD transitions to a high level, the output signal CTR of the RS flip-flop transitions to a low level (i.e., a timing end signal). In actual use, any circuit structure that satisfies the aforementioned logic is applicable to the present invention, and is not limited to this embodiment.

[0056] Specifically, as shown in FIG5 , in this embodiment, the frequency divider 212b is connected to the output terminal of the controller 212a and receives the working clock OSC. When the timing start signal is valid, the working clock OSC is divided into two parts in sequence. i Multiple frequency division is performed to obtain a counting clock; wherein, i=1, 2…n, n is the number of bits of the output signal of the duration acquisition unit 212, which is set to a natural number greater than 2. In actual use, the corresponding value can be set as needed. As an example, the frequency divider 212b includes n stages of D flip-flops cascaded in sequence, the data input terminal D of each D flip-flop is connected to the inverting output terminal Q-, and the positive output terminal Q+ outputs the divided frequency signal, wherein the first stage D flip-flop outputs a divided-by-two signal 2clk, the second stage D flip-flop outputs a divided-by-four signal 4clk, and so on, the nth stage D flip-flop outputs 2clk. n Frequency division signal 2 n clk; the clock terminal clk of the first-stage D flip-flop is connected to the working clock OSC, and the clock terminal clk of the subsequent-stage D flip-flop is connected to the inverting output terminal Q- of the previous-stage D flip-flop; the asynchronous reset terminal Clr of the first-stage D flip-flop is connected to the output terminal of the controller 212a, and the asynchronous reset terminal Clr of the second to n-th stage D flip-flops is connected to the inverted signal ZCD_N of the zero current detection signal; when the output signal CTR of the RS flip-flop jumps to a high level and the inverted signal ZCD_N of the zero current detection signal is a high level, the frequency divider 212b starts frequency division; when the output signal CTR of the RS flip-flop jumps to a low level and the inverted signal ZCD_N of the zero current detection signal is a low level, the frequency divider 212b is reset; in actual use, any circuit structure that can meet the above logic is applicable to the present invention, and is not limited to this embodiment.

[0057] Specifically, as shown in FIG5 , in this embodiment, the counter 212c is connected to the output terminals of the controller 212a and the frequency divider 212b. When the timing start signal is valid, timing is started based on the counting clock, and when the timing end signal is valid, timing is stopped. As an example, the counter 212c includes n stages of D flip-flops cascaded in sequence, with the asynchronous reset terminal Clr of each D flip-flop connected to the delayed signal CTR_D of the controller output signal, and the clock terminal of the D flip-flop in the i-th stage connected to the 2 i The counting clock with multiple frequency (i.e. the clock end of the first-stage D flip-flop receives the divided-by-two signal 2clk, the clock end of the second-stage D flip-flop receives the divided-by-four signal 4clk, and so on, the clock end of the n-stage D flip-flop receives the divided-by-two signal 2clk n Frequency division signal 2 nclk); the data input terminal D of the first-stage D flip-flop is connected to the preset voltage LV, and the data input terminal D of the subsequent D flip-flop is connected to the positive-phase output terminal Q+ of the previous-stage D flip-flop; the negative-phase output terminal Q- of each D flip-flop outputs the timing result, and each D flip-flop outputs a one-bit signal (t 2_DET1 , t 2_DET2 …t 2_DETn ), an n-bit signal constitutes the timing result (as an example, a high level is valid); when the delay signal CTR_D of the controller output signal jumps to a high level and receives the corresponding counting clock, the counter 212c starts counting; when the delay signal CTR_D of the controller output signal jumps to a low level or does not receive the corresponding counting clock, the counter 212c stops working; in actual use, any circuit structure that can meet the above logic is applicable to the present invention, and is not limited to this embodiment.

[0058] As shown in FIG. 4 , the comparison unit 213 is connected to the output terminals of the timing unit 211 and the duration acquisition unit 212 , and compares the first duration T1 with the second duration t2 .

[0059] Specifically, as shown in FIG5 , in this embodiment, the comparison unit 213 includes n comparison subunits 213a, each of which includes an exclusive OR gate XOR, a first NAND gate nand1, a second NAND gate nand2, and a third NAND gate nand3. The input ends of the exclusive OR gate XOR are respectively connected to the output signal of the timing unit 211 and the corresponding bit output signal of the timer 212c (respectively denoted as t 2_DET1 , t 2_DET2 …t 2_DETn), the input ends of the first NAND gate nand1 are respectively connected to the corresponding bit output signal of the timer 212c and the output signal of the exclusive OR gate XOR, and output first comparison results (respectively denoted as P11, P12...P1n); the input ends of the second NAND gate nand2 are respectively connected to the output signal of the timing unit 211 and the output signal of the exclusive OR gate XOR, and output second comparison results (respectively denoted as P21, P22...P2n); the input ends of the third NAND gate nand3 are respectively connected to the output signal of the timing unit 211 and the corresponding bit output signal of the timer, and output third comparison results (respectively denoted as P31, P32...P3n); Among them, when the duration represented by the corresponding bit output signal of the timer 212c is less than the first duration T1, the first comparison result of the corresponding comparison subunit 213a jumps to a low level; when the duration represented by the corresponding bit output signal of the timer 212c is greater than the first duration T1, the second comparison result of the corresponding comparison subunit 213a jumps to a low level; when the duration represented by the corresponding bit output signal of the timer 212c is equal to the first duration T1, the third comparison result of the corresponding comparison subunit 213a jumps to a low level; in this example, taking the nth comparison unit 213a as an example, the first duration T1 and the nth bit output signal t of the timer 212c are equal. 2_DETn The one with a high level, that is, the one that arrives first, is the one that is detected first with a shorter time. Combining the comparison results P11, P12...P1n, P21, P22...P2n, P31, P32...P3n, we can know which of the first time length T1 and the second time length t2 is longer or shorter. The corresponding truth table is as follows:

[0060] In actual use, any circuit structure that can compare two signals representing durations and obtain a comparison result is applicable to the present invention, and is not limited to this embodiment.

[0061] As shown in FIG4 , the dead time adjustment unit 214 is connected to the output end of the comparison unit 213 , and adjusts the on-time of the clamp tube and the first duration in the next cycle based on the comparison result of the current cycle, thereby realizing adaptive zero voltage turn-on control.

[0062] Specifically, as shown in FIG5 , in this embodiment, the dead time adjustment unit 214 includes a time adjustment subunit 214b and n control subunits 214a. Each control subunit 214a is connected to the output end of each comparison subunit 213a in a one-to-one correspondence. Each control subunit 214a includes a first enabling transistor M1, a second enabling transistor M2, a third enabling transistor M3, a first transistor M4, a second transistor M5, and a third transistor M6. One end of each enabling transistor is connected to a preset voltage LV, and the other end is connected to the control end of each transistor. When the enable signal TSSE When invalid, each enable tube is turned on to control each transistor to be turned off respectively; wherein, the first enable tube M1 is connected to the control end of the first transistor M4, the second enable tube M2 is connected to the control end of the second transistor M5, and the third enable tube M3 is connected to the control end of the third transistor M6. As an example, each enable tube and transistor is a PMOS tube. When the enable signal T SSE When the enable signal T is low (invalid), each enable transistor is turned on, so that the control terminal of each transistor is connected to the preset voltage LV (high level) and turned off. At this time, the dead time adjustment unit 214 does not work; when the enable signal T SSE When it jumps to high level (valid), each enabling transistor is turned off, and the control terminal of each transistor is connected to the corresponding comparison result. At this time, the dead time adjustment unit 214 is in working state. One end of the first transistor M4 is connected to the preset voltage LV, the control terminal is connected to the corresponding first comparison result, and the other end generates a voltage to reduce the conduction time T of the clamping transistor. H_ON One end of the second transistor M5 is connected to the preset voltage LV, the control end is connected to the corresponding second comparison result, and the other end generates a voltage that increases the conduction time T of the clamp tube. H_ON One end of the third transistor M6 is connected to the preset voltage LV, the control end is connected to the corresponding third comparison result, and the other end generates a voltage to maintain the clamp tube conduction time T H_ON When the corresponding comparison result jumps to a low level, the corresponding transistor is turned on and a control signal for adjusting the on-time of the clamping tube is output. The time adjustment subunit 214b is connected to the output end of each control subunit 214a and receives the working clock OSC. According to the control signal output by each control subunit 214a, the working clock OSC is used to generate a counting time, thereby achieving the on-time T of the clamping tube. H_ON adjustments.

[0063] It should be noted that, in this embodiment, when the circuit is in the startup phase, the enable signal T SSE Invalid, the adaptive zero voltage start control module 21 does not work; when the circuit is started, the enable signal T SSE In addition, any circuit structure that can adjust the on-time of the clamp tube and the first duration based on the output signal of the comparison unit 213 is applicable to the present invention, and is not limited to this embodiment.

[0064] As shown in FIG6 , the present invention further provides an adaptive ZVS control method, which includes:

[0065] Step 21) The circuit is soft-started, and the main switch tube and the clamp tube are controlled to be turned on and off based on the feedback signal of the active clamp converter, and the main switch tube and the clamp tube are turned on in a complementary manner.

[0066] Specifically, upon power-up, the circuit (i.e., the active clamp converter) adjusts the on / off timing of the main switch and the clamp based on real-time feedback signals. In this embodiment, the feedback signals include, but are not limited to, the main switch's current sampling signal Vcs and the zero voltage detection signal ZVS. The main switch N0 is turned on based on the zero voltage detection signal ZVS. As the circuit starts up, the main switch's current sampling signal Vcs gradually increases. The main switch's on-time is gradually adjusted based on a comparison between the main switch's current sampling signal Vcs and a preset value (for example, the preset value is set to the overcurrent protection point (OCP)). The clamp is then turned on a predetermined time after the main switch N0 has been off. In practice, any signal or control logic that reflects the operating state of the active clamp converter and, through feedback, controls the complementary conduction of the main switch and the clamp is applicable to the present invention, and is not limited to this embodiment. It should be noted that the complementary conduction mentioned in the present invention means that the main switch tube and the clamp tube are not turned on at the same time, and there is a dead time.

[0067] Specifically, in this embodiment, the soft start is determined to be finished when the output voltage of the active clamp converter is stable. In actual use, any method that can reflect the completion of power-on of the active clamp converter can be used to determine the end of the soft start.

[0068] Step 22) After the soft start is completed, the conduction time T of the clamp tube Nc is adjusted based on the dead time adjustment method. H_ON Adjustment is performed to adaptively adjust the first duration T1 to achieve adaptive zero voltage turn-on control; wherein, when the off time of the clamp tube Nc in the current cycle reaches the set first duration T1 and the zero voltage detection signal ZVS is valid, the main switch tube N0 is turned on.

[0069] Specifically, as shown in FIG7 , in this embodiment, when the off-time of the clamp tube Nc in the current cycle reaches the set first duration T1 and the zero voltage detection signal ZVS is valid, the main switch tube N0 is turned on; if the zero voltage detection signal ZVS is detected within the first duration T1, the main switch tube N0 must wait until the first duration T1 ends before being turned on; if the zero voltage detection signal ZVS is not detected within the first duration T1, the main switch tube N0 is turned on after the zero voltage detection signal ZVS is detected; if the zero voltage detection signal ZVS is detected at the end of the first duration T1, the main switch tube N0 is turned on when both conditions are met. When the output current of the active clamp converter reaches a defined threshold (for example, during the circuit startup phase, the output current is determined to have reached the defined threshold when the output current sampling signal Vcs reaches the overcurrent protection point; after the circuit startup, the output current is determined to have reached the defined threshold when the output current sampling signal Vcs reaches a preset reference value, at which point the output current sampling signal Vcs reaches its maximum value Vcsmax; the defined thresholds for the two phases are different and are set as needed), the main switch N0 is driven to turn off. After the main switch N0 is turned off for a set period of time, the clamping transistor Nc is turned on. When the conduction time of the clamping transistor Nc reaches the period determined by the dead time adjustment method of the present invention, the clamping transistor Nc is turned off. The first duration T1 and the second duration t2 are measured at the falling edge of the clamp transistor Nc's turn-off. The first duration T1 is determined based on the on-time of the clamp transistor Nc in the previous cycle. That is, for the current cycle, the first duration T1 corresponds to a set value, and the first timing end signal T1_end is generated by counting to the set value. The second duration t2 is a real-time acquired signal, and the timing of the second duration t2 ends when the zero current detection signal ZCD (equivalent to the second timing end signal) is valid during the current cycle. The on-time of the clamp transistor Nc in the next cycle is adjusted based on the comparison result of the first duration T1 and the second duration t2. Accordingly, the first duration T1 corresponding to the next cycle is also adjusted, thereby achieving adaptive zero voltage turn-on control of the main switch. The specific adjustment relationship is described above and is not further described here. In this example, it is assumed that the zero voltage detection signal ZVS, the zero current detection signal ZCD, and the first timing end signal T1_end are all active high. In actual use, they can also be set to active low, without being limited to this embodiment.

[0070] As shown in FIG8 , in this embodiment, the adaptive ZVS control method of the present invention is implemented based on the driving circuit 2 of the present invention. The driving circuit 2 includes: an adaptive zero voltage turn-on control module 21 , a power-on reset module 22 and a logic control module 23 .

[0071] As shown in FIG8 , the adaptive zero-voltage turn-on control module 21 adjusts the dead time between the next cycle when the clamping transistor turns off and the main switching transistor turns on based on the clamping transistor drive signal PWM_C and the zero-current detection signal ZCD. The structure and operating principle of the adaptive zero-voltage turn-on control module 21 are described above and are not further elaborated here.

[0072] As shown in FIG8 , the power-on reset module 22 is used to reset the logic control module 23 when the active clamp converter is powered on.

[0073] As shown in FIG8 , the logic control module 23 is connected to the output terminals of the adaptive zero-voltage turn-on control module 21 and the power-on reset module 22, and receives the zero-voltage detection signal ZVS and the output current sampling signal Vcs from the active clamp converter to generate the drive signal PWM_C for the clamp transistor and the drive signal PWM_P for the main switch transistor. The logic control module 23 can control the switching of the clamp transistor and the main switch transistor according to various strategies based on the feedback signals from the active clamp converter, which are not described in detail here.

[0074] As shown in FIG8 , as another implementation of the present invention, the driving circuit 2 further includes an oscillator 24, which provides a working clock for the driving circuit 2 (including a clock with at least one frequency, and clocks with different frequencies can meet the needs of different circuits). The uses of the working clock include but are not limited to counting, adjusting the conduction time of the clamp tube, and adjusting the first duration. The clock signals required in the driving circuit 2 can all be provided by the oscillator 24, which will not be elaborated here.

[0075] The present invention also provides a switching power supply, wherein the active-clamped flyback converter employs the dead-time adjustment method of the present invention to achieve adaptive zero-voltage turn-on control. The active-clamped converter includes, but is not limited to, a flyback topology and a forward topology. Any active-clamped converter structure is applicable, and a detailed description thereof is omitted here. As an example, when the active-clamped converter employs a flyback topology, the circuit structure shown in FIG1 may be employed.

[0076] In summary, the present invention provides a dead time adjustment method, an adaptive ZVS control method, and a switching power supply, comprising: step 11) obtaining a calculated first duration, collecting a second duration of a current cycle, and comparing the first duration with the second duration; the first duration is a preset dead time duration between the turn-off of a clamping transistor and the turn-on of a main switch in the active clamp converter, and the second duration is a duration between the turn-off of the clamping transistor and the complete release of the secondary inductor current of the transformer; step 12) if the first duration is greater than the second duration, reducing the on-time of the clamping transistor by a preset duration in the next cycle; if the first duration is less than the second duration, increasing the on-time of the clamping transistor by a preset duration in the next cycle; if the first duration is equal to the second duration, maintaining the on-time of the clamping transistor in the next cycle; and step 13) returning to step 11) to sequentially adjust the dead time between the clamping transistor and the main switch in each cycle. The dead time adjustment method, adaptive ZVS control method, and switching power supply of the present invention accurately and adaptively control the dead time between the upper clamping transistor and the main switching transistor, enabling adaptive ZVS control of the main switching transistor. This method provides a wider adjustable dead time range, enabling adaptive ZVS adjustment of the system across the full load range. This method offers high safety, minimizes main switching transistor losses, and increases system efficiency. Furthermore, the dead time adjustment method and adaptive ZVS control method of the present invention are applicable to flyback and forward active clamping converters, thus possessing a wide range of applications. Therefore, the present invention effectively overcomes various shortcomings of the prior art and possesses high industrial value.

[0077] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A dead time adjustment method, applied to an active clamp converter, characterized in that: The dead time adjustment method at least comprises: Step 11) obtaining the calculated first duration, collecting the second duration of the current cycle, and comparing the first duration with the second duration; the first duration is the preset dead zone duration from the closing of the clamping tube to the opening of the main switch tube in the active clamping converter, and the second duration is the duration from the closing of the clamping tube to the complete release of the secondary inductor current of the transformer; Step 12) if the first time length is greater than the second time length, then in the next cycle, the on-time of the clamp tube is reduced by a preset time length; if the first time length is less than the second time length, then in the next cycle, the on-time of the clamp tube is increased by a preset time length; if the first time length is equal to the second time length, then in the next cycle, the on-time of the clamp tube is maintained; Step 13) Return to step 11) and sequentially adjust the dead time between the clamping tube and the main switch in each cycle.

2. The dead time adjustment method according to claim 1, characterized in that: The turn-off moment of the clamp tube is acquired based on the driving signal of the clamp tube, and the first timing end signal is triggered when the turn-off time of the clamp tube reaches the first time.

3. The dead time adjustment method according to claim 2, characterized in that: The turn-off moment of the clamp tube is obtained based on the driving signal of the clamp tube, and when the zero current detection signal is valid, it is determined that the secondary inductance current of the transformer is completely released, and a second timing end signal is triggered.

4. The dead time adjustment method according to claim 3, characterized in that: The order in which the first timing end signal and the second timing end signal arrive is determined to determine the magnitude relationship between the first duration and the second duration.

5. The dead time adjustment method according to claim 1, characterized in that: The preset time length is not greater than the conduction time of the clamping tube.

6. The dead time adjustment method according to claim 1, characterized in that: The preset duration is configured as n working clock cycles, where n is a natural number greater than or equal to 1.

7. An adaptive zero voltage turn-on control module for implementing the dead time adjustment method according to any one of claims 1 to 6, characterized in that: The adaptive zero voltage turn-on control module includes: a timing unit, a duration acquisition unit, a comparison unit and a dead time adjustment unit.

8. The adaptive zero voltage turn-on control module according to claim 7, characterized in that: The timing unit is used to obtain a first duration, and the duration acquisition unit is used to obtain a second duration.

9. The adaptive zero voltage turn-on control module according to claim 8, characterized in that: The comparison unit is connected to the output ends of the timing unit and the duration acquisition unit, and is used to compare the first duration with the second duration.

10. An adaptive ZVS control method, characterized in that: The adaptive ZVS control method at least comprises: Step 21) The circuit is soft-started, and the on-off of the main switch tube and the clamp tube is controlled based on the feedback signal of the active clamp converter, and the main switch tube and the clamp tube are complementary to each other; Step 22) After the soft start is completed, the conduction time of the clamp tube is adjusted based on the dead time adjustment method as described in any one of claims 1 to 6, and then the first duration is adaptively adjusted to achieve adaptive zero voltage start-up control; wherein, when the turn-off time of the clamp tube in the current cycle reaches the set first duration and the zero voltage detection signal is valid, the main switch tube is turned on.

11. The adaptive ZVS control method according to claim 10, characterized in that: When the output voltage of the active clamp converter is stable, it is determined that the soft start is ended.

12. The adaptive ZVS control method according to claim 10, characterized in that: When the output current of the active clamp converter reaches a defined threshold, the main switch tube is driven to be turned off.

13. The adaptive ZVS control method according to claim 10 or 12, characterized in that: After the main switch tube is turned off for a set time, the clamp tube is driven to be turned on.

14. A switching power supply, characterized in that: The switching power supply comprises: an active clamped converter, wherein the active clamped converter adopts the dead time adjustment method according to any one of claims 1 to 6 to realize adaptive zero voltage turn-on control.

15. The switching power supply according to claim 14, characterized in that: The active clamp converter is a flyback topology structure or a forward topology structure.

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