Chip production simulation method and system based on digital twin technology

Abstract

The present invention relates to the technical field of semiconductor chip production, and provides a chip production simulation method and system based on digital twin technology. The method comprises: collecting a processing task of a target chip and retrieving a corresponding test data set; constructing a corresponding design parameter domain and design function; performing optimization, using digital twin technology to construct a twin chip, testing the twin chip, and calculating the design fitness; performing iterative optimization to acquire an optimal design parameter; constructing an optimal twin chip, calculating the similarity between the optimal twin chip and the existing family chips, and performing verification; and carrying out design and production of the target chip. The technical problems of incapability of considering possible hardware faults and anomalies, and incapability of guaranteeing the performance and reliability of the chip due to the uncertainty of the chip production process are solved. More accurate simulation and prediction are carried out on the chip design, and potential hazards are repaired in advance. Moreover, a more detailed and accurate simulation result is provided, so that the technical effects of improving the design efficiency, reducing the costs, and improving the performance and reliability of the chip are achieved.

Description

A chip production simulation method and system based on digital twin technology Technical Field

[0001] The present invention relates to the technical field related to semiconductor chip production, and in particular to a chip production simulation method and system based on digital twin technology. Background Art

[0002] During the chip production process, physical experiments and tests are often used to evaluate chip performance and reliability. For example, logic simulation is performed to model the behavior of module-level logic and then partition the simulation software into blocks to verify the SoC (System on Chip) to confirm whether the chip functions as expected. However, this requires a large number of experiments and tests, which is not only time-consuming but also makes it difficult to guarantee the reliability and stability of the chip.

[0003] In summary, the existing technology has technical problems such as the inability to take into account possible hardware failures and abnormal situations, the uncertainty in the chip production process, and the inability to guarantee chip performance and reliability.

[0004] Summary of the Invention

[0005] This application provides a chip production simulation method and system based on digital twin technology, aiming to solve the technical problems in the existing technology that possible hardware failures and abnormal conditions cannot be taken into account, there is uncertainty in the chip production process, and the chip performance and reliability cannot be guaranteed.

[0006] In view of the above problems, the present application provides a chip production simulation method and system based on digital twin technology.

[0007] The first aspect disclosed in the present application provides a chip production simulation method based on digital twin technology, wherein the method includes: collecting processing tasks of the target chip to be designed and produced, and retrieving a test data set of the processing task; according to the processing task, constructing a design parameter domain of a chip that also performs the processing task, and constructing a design function for designing and producing the target chip; within the design parameter domain, optimizing the design parameters, and constructing a twin chip based on the digital twin, using the test data set to test the twin chip, and combining the design function to calculate the design fitness; performing iterative optimization to obtain the optimal design parameters, wherein the optimal design parameters are obtained by optimizing through the leadership optimization rule; according to the optimal design parameters, constructing an optimal twin chip, calculating the similarity between existing chips of the same family and the optimal twin chip, and using the similar chips obtained by matching for verification to obtain a verification result; when the verification result is qualified, using the optimal design parameters to design and produce the target chip.

[0008] Another aspect disclosed in the present application provides a chip production simulation system based on digital twin technology, wherein the system includes: a processing task acquisition module for acquiring processing tasks of a target chip to be designed and produced, and retrieving a test data set for the processing tasks; a design function construction module for constructing a design parameter domain of a chip that also performs the processing tasks based on the processing tasks, and constructing a design function for designing and producing the target chip; an optimization module for performing optimization of design parameters within the design parameter domain, and constructing a twin chip based on the digital twin, testing the twin chip using the test data set, and calculating and obtaining the design fitness in combination with the design function; an iterative optimization module for performing iterative optimization to obtain optimal design parameters, wherein the optimal design parameters are obtained by optimization through the leadership optimization rule; a verification module for constructing an optimal twin chip based on the optimal design parameters, calculating the similarity between existing chips of the same family and the optimal twin chip, and verifying with the similar chips obtained by matching to obtain verification results; a design and production module for designing and producing the target chip using the optimal design parameters when the verification results are qualified.

[0009] One or more technical solutions provided in this application have at least the following technical effects or advantages:

[0010] The process of collecting the processing tasks of the target chip and retrieving the corresponding test data set is adopted; then the corresponding design parameter domain and design function are constructed according to the processing tasks. Optimization is performed within the parameter domain, and a twin chip is constructed using digital twin technology. The twin chip is tested with a test data set, and the design fitness is calculated in combination with the design function. The optimal design parameters are obtained through iterative optimization, the optimal twin chip is constructed, the similarity with existing chips of the same family is calculated, and the target chip is designed and produced after verification. This creates a virtual model that reflects the actual working conditions of the physical chip, simulates and predicts the chip design more accurately, and repairs potential hidden dangers before the chip is produced. At the same time, the digital twin model can provide more detailed and accurate simulation results, thereby better supporting chip design and production decisions, improving design efficiency, reducing costs, and improving chip performance and reliability.

[0011] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG1 is a schematic diagram of a possible process flow of a chip production simulation method based on digital twin technology provided by an embodiment of the present application;

[0013] FIG2 is a schematic diagram of a possible process for determining a test data set in a chip production simulation method based on digital twin technology according to an embodiment of the present application;

[0014] Figure 3 is a possible structural schematic diagram of a chip production simulation system based on digital twin technology provided in an embodiment of the present application.

[0015] Explanation of the reference numerals: processing task collection module 100, design function construction module 200, optimization module 300, iterative optimization module 400, verification module 500, design and production module 600. DETAILED DESCRIPTION

[0016] The following description of exemplary embodiments of the present invention is provided in conjunction with the accompanying drawings, in which various details of the embodiments of the present invention are included to facilitate understanding. These details should be considered as merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present invention. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0017] Example 1

[0018] As shown in FIG1 , an embodiment of the present application provides a chip production simulation method based on digital twin technology, wherein the method includes:

[0019] Step-1: Collect the processing tasks of the target chip to be designed and produced, and retrieve the test data set of the processing tasks;

[0020] Step 2: Based on the processing task, construct a design parameter domain for a chip that also performs the processing task, and construct a design function for designing and producing the target chip;

[0021] Step-3: Optimize the design parameters within the design parameter domain, build a twin chip based on the digital twin, test the twin chip using the test data set, and calculate the design fitness based on the design function;

[0022] A processing task refers to the specific operation or function that the target chip to be designed and produced needs to perform, such as data processing, signal processing, calculation, etc.; a test data set is a set of data used to test the processing tasks of the target chip, usually including various types of data (data type, operation type, execution efficiency) to evaluate the performance of the chip under various conditions.

[0023] The design parameter domain refers to the range or field of suitable design parameters selected according to the processing task, such as the processor architecture, memory size, computing power, etc.; the design function is a function that evaluates the generation of a specific chip design scheme (such as circuit diagram, layout and routing, etc.) based on given design parameters.

[0024] A data set for testing the processing capability of the target chip is obtained from the test framework. The data set may be predefined or customized based on the specific functions and processing tasks of the target chip. Appropriate design parameters are selected based on the processing tasks of the target chip to form the design parameter domain. For example, if the target chip is an image processing chip, the design parameter domain may include processor architecture, memory size, computing power, etc.

[0025] Based on the design parameter domain of the target chip, a design function is constructed to generate the actual chip design solution. The design function can output the fitness of the corresponding chip design solution based on the input design parameters. Within the pre-defined design parameter domain, the optimal design parameters are found through optimization algorithms (such as gradient descent and genetic algorithms) to find the design parameters that achieve the best performance for a specific task.

[0026] A twin chip is a virtual model of a physical system that can simulate its performance in a real environment. In the embodiment of the present application, a model is trained based on the design parameters of chips with different sample design parameters and the test results of a test data set. The model is used as a digitally simulated twin chip, and the design parameters are input to obtain test results.

[0027] The digital twin chip is simulated and tested using the previously collected test data set to evaluate its performance in a real-world environment. Combined with the previously constructed design function, the design fitness is calculated based on the simulation test results. The design fitness can reflect the performance level of the design scheme in actual applications.

[0028] By simulating and testing chips in digital twins and calculating design fitness, potential design problems can be discovered and resolved before actual manufacturing, thereby reducing failures and waste in the manufacturing process. At the same time, chip design plans can be evaluated and optimized in advance to avoid problems that may be encountered after actual manufacturing, thereby improving the performance and efficiency of the chip on specific tasks.

[0029] Step-4: Perform iterative optimization to obtain the optimal design parameters, wherein the optimal design parameters are obtained through the leadership optimization rule;

[0030] Step 5: Based on the optimal design parameters, an optimal twin chip is constructed. The similarity between the existing chips of the same family and the optimal twin chip is calculated. The similar chips obtained by matching are used for verification to obtain verification results.

[0031] Step-6: When the verification result is qualified, the optimal design parameters are used to design and produce the target chip.

[0032] During the chip design process, the chip design parameters are optimized to achieve optimal performance: by repeatedly modifying the candidate solutions to approach or reach the optimal solution, iterative optimization is performed. The design parameters gradually approach the optimal solution in the repeated optimization process, and iterative calculations are performed through some optimization rules (such as gradient descent method, genetic algorithm, etc.) to obtain the design parameters with the best performance in specific processing tasks.

[0033] The optimal design parameters are a set of parameters obtained through iterative optimization, resulting in the best chip performance on a specific task. The optimal design parameters are obtained through the leadership optimization rule, including: The leadership optimization rule (empire competition algorithm) can be used in chip design and production simulation. The empire competition algorithm is a heuristic optimization algorithm that simulates population competition to find the optimal solution, in which each possible design parameter is regarded as an empire, and each empire has its own fitness value.

[0034] The leadership optimization rule described in this application is a variation of the Imperial Competition algorithm. Specifically, the Imperial Competition algorithm has been partially modified to suit specific scenarios, removing its revolution mechanism, among other things, to better adapt to the needs of chip design optimization. In chip design optimization, the goal is to find an optimal set of design parameter combinations that enable the chip to perform optimally on a specific task. Conversely, the revolution mechanism of the Imperial Competition algorithm introduces excessive perturbations, affecting the algorithm's convergence speed and accuracy. Therefore, removing the revolution mechanism and focusing on the selection and updating of the leader empire can better achieve this goal. In summary, the modified leadership optimization rule can better adapt to chip design optimization scenarios and improve the algorithm's efficiency and accuracy.

[0035] During the iterative optimization process, a set of initial design parameters, called "solutions," are randomly generated. These solutions are then tested in a simulation environment, and the fitness of each solution is calculated based on the test results. The solution with the highest fitness value is selected as the leader, leading the subsequent iterative optimization process.

[0036] In each iteration, the algorithm generates new solutions based on the leader's position and fitness value using a specific strategy (such as random search, local search, or genetic algorithm). These new solutions are tested again in the simulation environment and their fitness values ​​are calculated. A new leader is then selected to lead the next round of iterative optimization.

[0037] The above steps are repeated until a preset number of iterations is reached or a certain stopping criterion is met (for example, the fitness value reaches a certain threshold). Finally, the optimal design parameters obtained will be used in the design and production of actual chips, helping to improve chip performance and reliability while reducing costs and risks.

[0038] Based on the optimal design parameters found, a corresponding virtual chip (twin chip) is constructed through digital twin technology, which can be performed on a computer, allowing simulation and testing of the actual operation of the chip; the optimal twin chip refers to a virtual chip model generated by digital twin technology based on the optimal design parameters; the existing chips of the same family and the optimal twin chip are compared in terms of similarity in design parameters and expected performance. Similarity refers to the evaluation of the similarity between the two chips in design parameters and expected performance. During the chip design process, chips with high similarity have similar performance in actual applications.

[0039] The similar chips obtained by matching are existing chips of the same family that are highly similar to the optimal twin chip, and can be used to verify the rationality of the optimal design parameters; based on the calculated similarity, chips of the same family with high similarity are selected for actual operation tests to verify whether their performance in actual applications is similar to that of the optimal twin chip.

[0040] Verification results refer to the performance evaluation results obtained after actual operation testing of the matched similar chips. If the verification results show that the performance of the selected similar chips meets expectations, the actual design and production of the target chip can be carried out according to the optimal design parameters. This completes the entire optimization and design production process.

[0041] Improve the efficiency and accuracy of chip design and production while reducing costs and risks. Through iterative optimization and digital twin technology, chip performance can be predicted and optimized before actual manufacturing, ensuring that the final designed and produced chip has the best performance for specific tasks.

[0042] Furthermore, as shown in FIG2 , the test data set of the processing task is retrieved, and Step-1 includes:

[0043] Acquiring processing tasks of a target chip, wherein the processing tasks include different image processing tasks;

[0044] According to the processing task, sample processing data for executing the processing task is retrieved and obtained as the test data set.

[0045] The processing task of the target chip refers to the processing task that the target chip needs to perform, including different image processing tasks; the test data set refers to the sample processing data selected according to the processing task, which is used to test and verify the processing effect and performance of the target chip.

[0046] According to the processing task, sample processing data of the processing task is obtained and used as a test data set. Representative data is selected to simulate the actual processing task. The test data set can cover a variety of different image processing tasks and can verify the performance and performance of the target chip in these tasks, including:

[0047] Determine the primary functions and application scenarios of the target chip, such as image classification, segmentation, and enhancement. For each processing task, clarify its specific goals and requirements. Select appropriate image processing tasks based on the functions and application scenarios of the target chip. For example, if the target chip is primarily used for image segmentation, then select some classic image segmentation algorithms as processing tasks, such as K-means clustering and region growing.

[0048] For each selected image processing task, it is necessary to collect the corresponding image dataset, preprocess and enhance it to make it more suitable for the actual application scenario. For example, if the processing task is image classification, it is necessary to collect image datasets containing various categories, and label and preprocess these data.

[0049] After data collection and processing for each image processing task is completed, it needs to be combined into a comprehensive test dataset that can comprehensively cover various possible image processing scenarios and requirements. Finally, each image processing task in the test dataset is executed using the target chip, and the processing results are recorded, including various indicators such as processing time, accuracy, and performance.

[0050] By optimizing and verifying the target chip in a simulation environment, the cost and risk of direct testing on the physical device are avoided, improving the efficiency and accuracy of chip design and production. Furthermore, the application of digital twin technology makes the simulation process more accurate and efficient.

[0051] Furthermore, a design function for designing and producing the target chip is constructed. Step-2 includes:

[0052] According to the processing task, query the historical record data of chip design and production to obtain multiple sample design parameters of chips that also perform the processing task;

[0053] constructing the design parameter domain according to a plurality of sample design parameters;

[0054] Construct a design function for designing and producing the target chip:

[0055] Where des is the design fitness, w1, w2, w3 are weights, m is the cost of producing the target chip according to the design parameters, k is the yield rate of the target chip according to the design parameters, T is the number of test data in the test data set, S i is the processing time for the i-th group of test data after the target chip is produced according to the design parameters.

[0056] According to the processing task, a query is conducted in the historical record data of chip design and production to obtain multiple sample design parameters of chips with the same processing task. Specifically, the following steps are included: filtering out data with the same processing task as the target chip from the historical record data, including different design parameters, processing time, cost, yield rate and other information;

[0057] Sample design parameters refer to the design parameters of chips that perform the same processing task as the target chip in the historical record data of chip design and production. From the screened historical data, multiple sample design parameters of chips that perform the same processing task are extracted, including performance indicators, design rules, process parameters, etc. of the processing task;

[0058] The design parameter domain refers to a set of design parameters consisting of multiple sample design parameters. Based on multiple sample design parameters, a design parameter domain can be constructed, including various possible design parameter combinations, and each combination is assigned a corresponding weight. It is a multidimensional space, where each dimension represents a design parameter, and the weight indicates the quality of the parameter value.

[0059] The design function is used to predict the performance of the target chip based on the given design parameters; to construct the design function for the design and production of the target chip, Where des is the design fitness, w1, w2, and w3 are weights, m is the cost of producing the target chip according to the design parameters, k is the yield rate of the target chip produced according to the design parameters (the proportion of products that meet the quality standards among the target chips produced according to the given design parameters), T is the number of test data sets in the test data set, and S i The processing time for the i-th group of test data after the target chip is produced according to the design parameters:

[0060] By querying historical data for chip design parameters related to similar processing tasks and using these parameters to construct design parameter domains and design functions, we can more efficiently predict the performance of the target chip and optimize its design and production processes. Optimizing and verifying the target chip in a simulation environment makes the simulation process more accurate and efficient, while also avoiding the expense and risks associated with direct testing on physical devices, thereby improving the efficiency and accuracy of chip design and production.

[0061] Furthermore, the twin chip is tested using the test data set, and the design fitness is calculated and obtained in combination with the design function. Step-3 includes:

[0062] Randomly generating a plurality of first design parameters within the design parameter domain;

[0063] Acquire multiple sample chip design parameters of the multiple sample chips, and acquire multiple sample test result sets based on the test data set, each sample test result including a processing time;

[0064] Using multiple sample chip design parameters and multiple sample test result sets, multiple sample twin chips are trained to build a chip twin simulator;

[0065] Based on the digital twin, using the multiple first design parameters, constructing multiple twin chips in the server through a chip twin simulator;

[0066] Based on multiple twin chips and in combination with the design function, multiple first design fitnesses are calculated and obtained.

[0067] A set of parameters is randomly selected from the design parameter domain as initial or first design parameters; the sample chip design parameters are the design parameters of a chip that has already been produced, which can be used to understand the performance and characteristics of the chip; the design parameters of some sample chips and corresponding test result data are collected, and the test result data is usually obtained through historical records or experiments. Each sample test result includes processing time, which refers to the time it takes the chip to process a task;

[0068] The sample test result set is a set of results obtained after testing a sample chip, usually including performance indicators such as processing time; the sample twin chip refers to a virtual chip obtained by training using digital twin technology and the design parameters and test result set of the sample chip, which can simulate the performance of a real chip;

[0069] The chip twin simulator can be used to generate virtual twin chips; the collected sample data is used to train the digital twin model to simulate the real chip behavior. By training the model, the model is used as a digital twin chip to perform the processing function of the current processing task to analyze the advantages and disadvantages of the design parameters. Through these methods, the simulator can learn the relationship between the design parameters and performance of the real chip.

[0070] A digital twin model is used to generate a virtual or twin chip. In an embodiment of the present application, the first design parameters previously randomly generated need to be input into the digital twin model to obtain the corresponding twin chip.

[0071] The design fitness can judge the quality of the first design parameter and thus optimize it; evaluate the fitness of the first design parameter, and for each generated twin chip, combined with its corresponding design function, its corresponding performance prediction value can be calculated, and the performance prediction value can be regarded as the fitness of the design parameter.

[0072] The simulator allows for extensive design and optimization experiments in a virtual environment, eliminating the high costs and risks of experimenting on physical chips. Simultaneously, simulation and optimization methods allow for efficient generation and optimization of design parameters for multiple twin chips within the server, thus avoiding the high costs and risks of physical experiments and improving the efficiency and accuracy of chip design and production.

[0073] Furthermore, the optimal design parameters are obtained by optimizing the leading optimization rules. Step-4 includes:

[0074] Selecting M first design parameters corresponding to the largest M first design fitnesses among the multiple first design fitnesses as M first leading solutions, and selecting the other first design parameters as N first following solutions, where M and N are integers greater than 1;

[0075] According to the sizes of the M first design fitnesses and the size of N, M numbers of followers are allocated and obtained, wherein the size of the number of followers is positively correlated with the size of the first design fitness;

[0076] Taking the M first-leading solutions as the center, cluster the N first-following solutions to obtain M group clusters;

[0077] Within the M clusters, the solution within each cluster is iteratively updated and optimized until the preset optimization conditions are met and the optimal design parameters are obtained.

[0078] The first design fitness refers to the performance of a specific design scheme on a specific task among all design schemes; the first leading solution is the best design scheme selected according to the first design fitness among all design schemes. These solutions are regarded as "leaders" because they guide other solutions; the first following solution is the other design schemes except the first leading solution among all design schemes. These solutions are regarded as "followers" because they follow the first leading solution; M first design parameters corresponding to the largest M first design fitnesses among multiple first design fitnesses are selected as M first leading solutions, and the other several first design parameters are regarded as N first following solutions, where M and N are integers greater than 1.

[0079] After randomly generating and testing design parameters, the best performing parameters are selected as leading solutions. Specifically, the M design parameters with the highest first design fitness are selected as leading solutions, while the remaining design parameters serve as follower solutions. The first design fitness refers to a performance metric, such as processing time or cost, that evaluates design performance.

[0080] Based on the M first design fitnesses and the size of N, M followers are allocated. The number of followers refers to the number of first follower solutions associated with or influenced by each first leader solution, and is positively correlated with the first design fitness of the first leader solution. The first design fitness may represent solution performance, so better-performing leader solutions receive more followers. Simply put, this is the process of allocating a follower number to each leader solution based on the performance evaluation results of the leader and follower solutions. The number of followers is positively correlated with the first design fitness, meaning that better-performing leader solutions receive more followers.

[0081] Clustering refers to grouping similar data into "clusters" to make the patterns and structures of data more apparent. In the embodiment of the present application, it is used to group the first follower solutions into groups corresponding to the first leader solutions; clustering the N first follower solutions with the M first leader solutions as the center to obtain M group clusters: using the clustering algorithm, the follower solutions are classified into the corresponding leader solutions to form M group clusters, where each group cluster contains a leader solution and the corresponding follower solution;

[0082] Iterative optimization is a process of improving design performance by repeatedly adjusting design parameters. In this embodiment, the design solutions within each cluster are updated and optimized according to preset optimization conditions until these conditions are met. Within the M clusters, the solutions within each cluster are iteratively optimized until the preset optimization conditions are met and the optimal design parameters are obtained.

[0083] Iterative optimization is performed within each cluster until the preset optimization conditions are met. The design parameters within each cluster are updated and optimized based on some performance indicators (such as processing time, cost, etc.). When the preset conditions are met (such as achieving a certain performance improvement or reaching a preset number of iterations), the solution within the cluster is considered to be the optimal design parameter.

[0084] Using optimization methods such as multi-objective optimization algorithms or genetic algorithms, it is possible to identify the best leading and following solutions from a set of design proposals and group them into distinct clusters. The designs within each cluster are then iteratively updated and optimized based on pre-set optimization criteria to achieve better performance. This approach is commonly used to solve complex multi-objective optimization problems, effectively identifying a set of design parameters that optimizes multiple objectives. It leverages existing design information and iteratively optimizes to find the optimal solution. This approach effectively finds a set of designs that perform well across multiple objectives, thereby improving the efficiency and accuracy of chip design and production.

[0085] Furthermore, within the M clusters, the solution within each cluster is iteratively updated and optimized until the preset optimization conditions are met and the optimal design parameters are obtained, which also includes:

[0086] Within each of the M clusters, the target direction is set as the M first leading solutions. The N first following solutions are adjusted and updated according to the update step size toward the target direction to obtain N second following solutions.

[0087] Based on the digital twin, a twin chip is constructed and tested according to the second design parameters in the N second follow-up solutions, and N second design fitnesses are calculated;

[0088] Determine whether the N second design fitnesses are greater than the first design fitnesses of the corresponding M first leader solutions. If so, update the first leader solution. If not, do not update it, and obtain M updated group clusters.

[0089] Continue to update the M update group clusters according to the update step size;

[0090] Continue iterative update optimization until the preset number of updates is reached, and obtain and calculate the M total design fitness of all solutions in the M final group clusters;

[0091] The final leader solution in the final group cluster corresponding to the maximum total design fitness is taken as the optimal solution, and the optimal solution includes the optimal design parameters.

[0092] By adjusting the design parameters to try to approach or reach the performance of the first leading solution, the update step size may be a preset fixed value or may be dynamically determined based on the performance of the first leading solution.

[0093] The first follower solution is the first design parameter other than the first leader solution. The second follower solution is the solution after adjusting and updating the first follower solution within each group cluster, with the first leader solution as the target direction. The second design fitness is a performance evaluation obtained after testing the second follower solution, representing processing time, accuracy, or cost-effectiveness, etc. Based on the digital twin, a twin chip is constructed and tested according to the second design parameters within the second follower solution, and the second design fitness is calculated. Digital twin technology is used again, but this time to build and test a virtual chip based on the design parameters. The test result (second design fitness) is an approximation of the actual chip performance, such as processing time and cost.

[0094] Determine whether the second design fitness is greater than the first design fitness of the corresponding M first leading solutions. The purpose of the comparison is to determine whether the performance of the second follower solution has exceeded that of the first leading solution. If so, the first leading solution needs to be updated. Otherwise, the first leading solution remains unchanged. In simple terms, if the fitness of the updated follower solution is greater than the fitness of the leading solution, it will be replaced (if there are multiple solutions that are greater than the fitness of the leading solution, the largest one will be used as the replacement). In the next update, the new leading solution will be used as the target direction; otherwise, no update will be performed.

[0095] Updated cliques are re-formed after some solutions are updated. Based on the comparison results, M cliques are updated: if the first leading solution is updated, the corresponding clique will also be updated accordingly. The above update process involves the recalculation and optimization of the entire clique. According to the update step size, the M updated cliques continue to be updated. The iterative update process will continue until the preset number of updates is reached.

[0096] After reaching a preset number of updates, the total design fitness of all solutions within the M final clusters is calculated. This total design fitness is the sum of the design fitness of all solutions within each final cluster. For these M total design fitnesses, it is possible that the optimal design parameters are not the solution corresponding to the maximum fitness, but the overall fitness of the cluster in which it resides is the highest. This indicates that the design parameters within that cluster are generally stable, improving the stability of chip simulation design production. The optimal solution is the solution with the maximum total design fitness during the iterative update optimization process, which includes the optimal design parameters. The final leading solution within the final cluster corresponding to the maximum total design fitness is considered the optimal solution.

[0097] By updating and optimizing the first follower solution within each clique, targeting the first leading solution, we can attempt to find a new solution that approaches or exceeds the performance of the first leading solution. Using digital twin technology, we can build and test chips in a virtual environment, reducing the cost and risk of conducting experiments on physical objects. Through an iterative update process, we can continuously optimize solutions within the clique over multiple update cycles, improving the efficiency and accuracy of chip design and production. Finally, by finding the optimal solution with the maximum overall design fitness, we can effectively identify a set of design parameters that perform well across multiple objectives, providing a reference for actual chip design and production. In short, through iterative updates, we can gradually optimize the design solution and improve chip performance.

[0098] Furthermore, similar chips obtained through matching are used for verification to obtain verification results. Step-5 includes:

[0099] Retrieving multiple design parameters of multiple chips of the same family that execute the processing task;

[0100] Calculating the similarity between the optimal design parameter and multiple design parameters of the same family, and selecting the design parameter of the same family corresponding to the greatest similarity as the matching design parameter and the similar chip;

[0101] Using the test data set to test the similar chip, and calculating the test fitness based on the design function;

[0102] The similarity between the test fitness and the optimal fitness of the optimal design parameters is calculated, and whether a similarity threshold is met is determined to obtain a verification result.

[0103] A chip family refers to a class of chips with similar characteristics or functions, which may be from the same series, manufactured by the same manufacturer, or targeted at the same application. Design parameters for the same family refer to parameters used to configure or design chips within the same family, such as processing speed, memory size, and power consumption. These design parameters are extracted from a storage or database to identify multiple chips of the same type that perform a specific task. These design parameters may include, but are not limited to, processing power, memory size, and power consumption.

[0104] Similarity is used to evaluate the similarity between the optimal design parameters and other design parameters of the same family; matching design parameters and similar chips means selecting the design parameters and corresponding chips of the same family that are most similar to the optimal design parameters among many chips of the same family as the similar chips that are most likely to have similar performance. Generally, the ratio of design parameters of different categories is calculated, and the closer to 1, the more similar; find the design parameters of the same family that are closest to the optimal design parameters. The design parameters of the same family can be regarded as an approximation of the optimal design parameters, and the corresponding chips can be regarded as an approximation of the optimal chip.

[0105] Test fitness is calculated using a test data set and a design function, reflecting the performance evaluation scores of similar chips in actual application scenarios. In the actual operating environment, a specific test data set is used to evaluate the performance of similar chips. An evaluation index is calculated based on the chip's design characteristics and test results. This index can reflect the chip's adaptability to a specific task. The similarity between the test fitness and the optimal fitness of the optimal design parameters is calculated by comparing the similarity between the fitness of the test chip and the fitness of the optimal chip.

[0106] The verification result is determined by comparing the similarity between the test fitness and the optimal fitness of the optimal design parameters to determine whether a similarity threshold is met. The similarity between the fitness of the test chip and the fitness of the optimal chip reaches a preset threshold. If the threshold is reached or exceeded, the performance of the test chip is considered acceptable and is used as the verification result.

[0107] By accessing multiple design parameters from multiple chips of the same family that perform processing tasks, the chip design with the best performance for a specific task is found. This design is then optimized or manufactured based on this design, thereby improving the chip's performance and efficiency for that specific task. Furthermore, by testing similar chips with a test dataset and calculating test fitness based on the design function, the performance of similar chips in real-world applications can be effectively evaluated, providing a reference for practical applications.

[0108] In summary, the chip production simulation method and system based on digital twin technology provided by the embodiments of the present application have the following technical effects:

[0109] 1. Through digital twin technology, problems can be discovered and solved in the early stages of design, avoiding rework and waste in later production.

[0110] 2. By simulating actual working conditions during the simulation phase, the demand and cost of hardware testing can be greatly reduced.

[0111] 3. Through real-time monitoring and prediction, potential hardware problems can be discovered and repaired in a timely manner, improving product reliability and stability.

[0112] 4. By acquiring processing tasks for the target chip, including various image processing tasks, and retrieving sample processing data from these tasks as a test dataset, the target chip can be optimized and verified within a simulation environment, eliminating the expense and risks associated with direct testing on physical devices and improving the efficiency and accuracy of chip design and production. Furthermore, the application of digital twin technology makes the simulation process more accurate and efficient.

[0113] Example 2

[0114] Based on the same inventive concept as the chip production simulation method based on digital twin technology in the aforementioned embodiment, as shown in FIG3 , the embodiment of the present application provides a chip production simulation system based on digital twin technology, wherein the system includes:

[0115] The processing task acquisition module 100 is used to acquire the processing tasks of the target chip to be designed and produced, and to retrieve the test data set of the processing tasks;

[0116] A design function construction module 200 is used to construct a design parameter domain of a chip that also performs the processing task according to the processing task, and to construct a design function for designing and producing the target chip;

[0117] An optimization module 300 is used to optimize the design parameters within the design parameter domain, build a twin chip based on the digital twin, test the twin chip using the test data set, and calculate the design fitness in combination with the design function;

[0118] Iterative optimization module 400 is used to perform iterative optimization to obtain optimal design parameters, wherein the optimal design parameters are obtained by optimizing the leadership optimization rule;

[0119] Verification module 500 is used to construct an optimal twin chip based on the optimal design parameters, calculate the similarity between existing chips of the same family and the optimal twin chip, and perform verification using the matched similar chips to obtain verification results;

[0120] The design and production module 600 is used to design and produce the target chip using the optimal design parameters when the verification result is qualified.

[0121] Furthermore, the processing task collection module 100 is configured to perform the following steps:

[0122] Acquiring processing tasks of a target chip, wherein the processing tasks include different image processing tasks;

[0123] According to the processing task, sample processing data for executing the processing task is retrieved and obtained as the test data set.

[0124] Furthermore, the design function building module 200 is used to perform the following steps:

[0125] According to the processing task, query the historical record data of chip design and production to obtain multiple sample design parameters of chips that also perform the processing task;

[0126] constructing the design parameter domain according to a plurality of sample design parameters;

[0127] Construct a design function for designing and producing the target chip:

[0128] Where des is the design fitness, w1, w2, w3 are weights, m is the cost of producing the target chip according to the design parameters, k is the yield rate of the target chip according to the design parameters, T is the number of test data in the test data set, S i is the processing time for the i-th group of test data after the target chip is produced according to the design parameters.

[0129] Furthermore, the optimization module 300 is configured to perform the following steps:

[0130] Randomly generating a plurality of first design parameters within the design parameter domain;

[0131] Acquire multiple sample chip design parameters of the multiple sample chips, and acquire multiple sample test result sets based on the test data set, each sample test result including a processing time;

[0132] Using multiple sample chip design parameters and multiple sample test result sets, multiple sample twin chips are trained to build a chip twin simulator;

[0133] Based on the digital twin, using the multiple first design parameters, constructing multiple twin chips in the server through a chip twin simulator;

[0134] Based on multiple twin chips and in combination with the design function, multiple first design fitnesses are calculated and obtained.

[0135] Furthermore, the optimization module 300 is further configured to perform the following steps:

[0136] Selecting M first design parameters corresponding to the largest M first design fitnesses among the multiple first design fitnesses as M first leading solutions, and selecting the other first design parameters as N first following solutions, where M and N are integers greater than 1;

[0137] According to the sizes of the M first design fitnesses and the size of N, M numbers of followers are allocated and obtained, wherein the size of the number of followers is positively correlated with the size of the first design fitness;

[0138] Taking the M first-leading solutions as the center, cluster the N first-following solutions to obtain M group clusters;

[0139] Within the M clusters, the solution within each cluster is iteratively updated and optimized until the preset optimization conditions are met and the optimal design parameters are obtained.

[0140] Furthermore, the optimization module 300 is further configured to perform the following steps:

[0141] Within each of the M clusters, the target direction is set as the M first leading solutions. The N first following solutions are adjusted and updated according to the update step size toward the target direction to obtain N second following solutions.

[0142] Based on the digital twin, a twin chip is constructed and tested according to the second design parameters in the N second follow-up solutions, and N second design fitnesses are calculated;

[0143] Determine whether the N second design fitnesses are greater than the first design fitnesses of the corresponding M first leader solutions. If so, update the first leader solution. If not, do not update it, and obtain M updated group clusters.

[0144] Continue to update the M update group clusters according to the update step size;

[0145] Continue iterative update optimization until the preset number of updates is reached, and obtain and calculate the M total design fitness of all solutions in the M final group clusters;

[0146] The final leader solution in the final group cluster corresponding to the maximum total design fitness is taken as the optimal solution, and the optimal solution includes the optimal design parameters.

[0147] Furthermore, the verification module 500 is configured to perform the following steps:

[0148] Retrieving multiple design parameters of multiple chips of the same family that execute the processing task;

[0149] Calculating the similarity between the optimal design parameter and multiple design parameters of the same family, and selecting the design parameter of the same family corresponding to the greatest similarity as the matching design parameter and the similar chip;

[0150] Using the test data set to test the similar chip, and calculating the test fitness based on the design function;

[0151] The similarity between the test fitness and the optimal fitness of the optimal design parameters is calculated, and whether a similarity threshold is met is determined to obtain a verification result.

[0152] Any step of the method described above can be stored as a computer instruction or program in an unlimited computer memory, and can be called and recognized by an unlimited computer processor to implement any method in the embodiments of the present application, without any unnecessary restrictions.

[0153] Furthermore, the terms "first" or "second" as described above may not only represent an order relationship but may also represent a specific concept and / or refer to the selection of multiple elements individually or collectively. Obviously, those skilled in the art may make various modifications and variations to this application without departing from the scope of this application. Thus, if such modifications and variations fall within the scope of this application and its equivalents, this application is intended to include such modifications and variations.

Claims

1. A chip production simulation method based on digital twin technology, It is characterized in that The method comprises: Collecting processing tasks of the target chip to be designed and produced, and retrieving test data sets of the processing tasks; According to the processing task, construct a design parameter domain of a chip that also performs the processing task, and construct a design function for designing and producing a target chip; In the design parameter domain, the design parameters are optimized, and a twin chip is constructed based on the digital twin. The twin chip is tested using the test data set, and the design fitness is calculated and obtained in combination with the design function. Perform iterative optimization to obtain the optimal design parameters, wherein the optimal design parameters are obtained through the leadership optimization rule; According to the optimal design parameters, an optimal twin chip is constructed, the similarity between the existing same-family chips and the optimal twin chip is calculated, and a similar chip obtained by matching is used for verification to obtain a verification result; When the verification result is qualified, the optimal design parameters are used to design and produce the target chip.

2. The method according to claim 1, It is characterized in that The method comprises: Acquire a processing task of a target chip, wherein the processing task includes different image processing tasks; According to the processing task, sample processing data for executing the processing task is retrieved and obtained as the test data set.

3. The method according to claim 1, It is characterized in that The method comprises: According to the processing task, query the historical record data of chip design and production to obtain multiple sample design parameters of chips that also perform the processing task; constructing the design parameter domain according to a plurality of sample design parameters; Construct a design function for designing and producing the target chip: Among them, des is the design fitness, w 1 、w 2 、w 3 is the weight, m ​​is the cost of producing the target chip according to the design parameters, k is the yield rate of the target chip according to the design parameters, T is the number of test data in the test data set, S i is the processing time for the i-th group of test data after the target chip is produced according to the design parameters.

4. The method according to claim 1, It is characterized in that The method comprises: Randomly generate a plurality of first design parameters in the design parameter domain; Acquire multiple sample chip design parameters of multiple sample chips, and acquire multiple sample test result sets according to the test data set, each sample test result including a processing time; Use multiple sample chip design parameters and multiple sample test result sets to train multiple sample twin chips and build a chip twin simulator; Based on the digital twin, using the plurality of first design parameters, a plurality of twin chips are constructed in the server through a chip twin simulator; Based on the multiple twin chips and in combination with the design function, multiple first design fitnesses are calculated and obtained.

5. The method according to claim 4, It is characterized in that The method comprises: Select the M first design parameters corresponding to the largest M first design fitnesses among multiple first design fitnesses as the M first leading solutions, and the other several first design parameters as the N The first follow-up solution, M and N are integers greater than 1; According to the sizes of the M first design fitnesses and the size of N, M numbers of followers are allocated and obtained, wherein the size of the number of followers is positively correlated with the size of the first design fitnesses; Taking the M first leader solutions as the center, cluster the N first follower solutions to obtain M group clusters; In the M clusters, the solution in each cluster is iteratively updated and optimized until the preset optimization conditions are met and the optimal design parameters are obtained.

6. The method according to claim 5, It is characterized in that The method comprises: In each of the M group clusters, the target direction is to approach the M first leading solutions, and the N first following solutions are adjusted and updated according to the update step size toward the target direction to obtain N second following solutions; Based on the digital twin, according to the second design parameters in the N second follow-up solutions, a twin chip is constructed and tested, and N second design fitness is calculated; Determine whether the N second design fitnesses are greater than the first design fitnesses of the corresponding M first leader solutions. If so, update the first leader solution. If not, do not update it, and obtain M updated group clusters. Continue to update the M update group clusters according to the update step length; Continue iterative update optimization until the preset number of updates is reached, and obtain and calculate the M total design fitness of all solutions in the M final group clusters; The final leader solution in the final group cluster corresponding to the maximum total design fitness is taken as the optimal solution, and the optimal solution includes the optimal design parameters.

7. The method according to claim 1, It is characterized in that The method comprises: Retrieving multiple same-family design parameters of multiple same-family chips that execute the processing task; Calculating the similarity between the optimal design parameter and multiple design parameters of the same family, and selecting the design parameter of the same family corresponding to the greatest similarity as the matching design parameter and the similar chip; Using the test data set to test the similar chip, and calculating and obtaining the test fitness based on the design function; The similarity between the test fitness and the optimal fitness of the optimal design parameters is calculated, and whether a similarity threshold is met is determined to obtain a verification result.

8. A chip production simulation system based on digital twin technology, It is characterized in that A chip production simulation method based on digital twin technology for implementing any one of claims 1 to 7, comprising: A processing task acquisition module is used to acquire processing tasks of the target chip to be designed and produced, and to retrieve a test data set of the processing tasks; A design function construction module is used to construct a design parameter domain of a chip that also performs the processing task according to the processing task, and to construct a design function for designing and producing a target chip; An optimization module is used to optimize the design parameters within the design parameter domain, build a twin chip based on the digital twin, test the twin chip using the test data set, and calculate and obtain the design fitness in combination with the design function; Iterative optimization module, used for iterative optimization to obtain the optimal design parameters, wherein the optimal design parameters are obtained through the leadership optimization rule; A verification module is used to construct an optimal twin chip according to the optimal design parameters, calculate the similarity between the existing same-family chips and the optimal twin chip, and use the matched similar chips for verification to obtain a verification result; The design and production module is used to design and produce the target chip using the optimal design parameters when the verification result is qualified.

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