Ingan vcsel by means of coalesced epitaxial lateral overgrowth in combination with electrochemical etching

Abstract

The invention relates to a method for producing an electronic component. The method comprises: forming a first semiconductor layer of a first material on a substrate of a second material, wherein the first material differs from the second material; forming a dielectric structure on the first semiconductor layer, wherein the dielectric structure has a plurality of openings, and in the openings the first semiconductor layer is exposed; epitaxially forming a second semiconductor layer on the first semiconductor layer, which in the openings is exposed, and at least in a region above the dielectric structure, wherein the second semiconductor layer comprises or is formed from the first material; and forming a third semiconductor layer on or above the second semiconductor layer in a first region above the openings of the dielectric structure and in a second region above the dielectric structure. The method also comprises: forming a sacrificial structure on the second semiconductor layer; forming the third semiconductor layer on the sacrificial structure; and removing the sacrificial structure such that the third semiconductor layer is separated from the second semiconductor layer.

Description

[0001] InGaN VCSEL via coalesced epitaxial lateral

[0002] OVERGROWTH IN COMBINATION WITH ELECTROCHEMICAL ETCHING

[0003] Description

[0004] This disclosure relates to surface emitters and

[0005] Process for their production .

[0006] It is known to grow surface emitters (vertical cavity surface emitting lasers, VCSELs) made of indium gallium nitride (InGaN) on substrates made of gallium nitride (GaN), for example 2" GaN wafers. GaN substrates with a low defect density make it possible to manufacture components with a long lifetime. However, these substrates are very cost-intensive and the size limitation of these substrates makes it difficult to scale this technology for mass-market applications.

[0007] It is an object of this invention to be able to form an electronic component that is more substrate-independent and / or can be formed using a wider variety of substrates. This allows GaN-based surface emitters to be formed on more cost-effective substrates.

[0008] In one aspect, a method for manufacturing an electronic component is provided.The method comprising: forming a first semiconductor layer made of a first material on a substrate made of a second material, the first material being different from the second material; forming a dielectric structure on the first semiconductor layer, the dielectric structure having a plurality of openings, the first semiconductor layer being exposed in the openings; epitaxially forming a second semiconductor layer on the first semiconductor layer exposed in the openings and at least in a region above the dielectric structure, the second semiconductor layer comprising or being formed from the first material; and forming a third semiconductor layer on or above the second semiconductor layer in a first region above the openings of the dielectric structure and in a second region above the dielectric structure.The method further comprises : forming a sacrificial structure on the second semiconductor layer ; forming the third semiconductor layer on the sacrificial structure ; and removing the sacrificial structure such that the third semiconductor layer is separated from the second semiconductor layer .

[0009] The third semiconductor layer and the second semiconductor layer may still be connected to one another in one or more non-active regions, for example in a wafer peripheral region and / or in the region of support structures provided in the active region. A laser lift-off process of the substrate may, for example, be performed over the entire surface. Alternatively, the substrate may be broken off or torn away from one or more regions, for example in the region of the wafer peripheral region or the support structures.

[0010] The third semiconductor layer can have a much lower defect density in the second region than in the first region, for example, less than 1% of the defect density of the first region. The second region can have a lateral dimension of more than 20 pm. This makes it easy to form the third semiconductor layer with a lower defect density on or above a cost-effective substrate.

[0011] For example, a less expensive sapphire substrate can be used instead of a more expensive GaN substrate. The dielectric structure is epitaxially overgrown laterally by the second semiconductor layer in the second region (epitaxial lateral overgrowth, ELOG).

[0012] The third semiconductor layer can therefore have a lower defect density in the second region than in the first region. The third semiconductor layer can be separated from the second semiconductor layer, for example by means of a removable sacrificial structure, for example by means of a lift-off process of the sacrificial structure, for example by means of an electrochemical etching (ECE), in order to separate the third semiconductor layer from the second semiconductor layer. Alternatively or additionally, the second semiconductor layer can be separated from the third semiconductor layer by means of removal of the second semiconductor layer (optionally without a sacrificial structure), for example by means of a back-side thinning process, for example grinding or polishing the second semiconductor layer away from the third semiconductor layer. The sacrificial structure can optionally function as a stop layer.

[0013] The second semiconductor layer enables a high-quality surface, for example with improved or low surface roughness, for the formation of the third semiconductor layer.

[0014] Alternatively or additionally, the method enables the precise formation of an optical cavity in a surface emitter, wherein the third semiconductor layer is part of the optical cavity. This is made possible by a low defect density at the position of the optical aperture or the current aperture of the active region in the third semiconductor layer in a surface emitter.

[0015] In the drawings, like reference characters generally refer to the same parts throughout the several views. The drawings are not necessarily to scale, emphasis generally being placed upon illustrating the principles of the invention. In the following description, various aspects of the invention are described with reference to the following drawings, in which:

[0016] FIG. 1A to FIG. 1L are schematic cross-sectional views of structures in the method for producing a surface emitter;

[0017] FIG. 2A to FIG. 2F are schematic cross-sectional views of structures in the method for producing a surface emitter;

[0018] FIG. 3A and FIG. 3B are schematic cross-sectional views of structures in the method for producing a surface emitter;

[0019] FIG. 4 shows a schematic cross-sectional view of a structure in the method for producing a surface emitter;

[0020] FIG. 5A and FIG. 5B are schematic cross-sectional views of structures in the method for producing a surface emitter;

[0021] FIG. 6 is a schematic plan view of a structure in the process for producing a surface emitter;

[0022] FIG. 7 shows a schematic cross-sectional view of a structure in the method for producing a surface emitter;

[0023] FIG. 8A is a schematic plan view of a structure in the process for manufacturing a surface emitter; and

[0024] FIG. 8B is a schematic cross-sectional view of a structure in the process for

[0025] Fabricating a surface emitter .

[0026] The following detailed description refers to the accompanying drawings which, for purposes of illustration, show specific details and aspects in which the disclosure may be practiced. One or more aspects are described in sufficient detail to enable those skilled in the art to put the disclosure into practice. Other aspects may be used, and structural, logical, and electrical changes may be made without departing from the scope of the disclosure. The various aspects described herein are not necessarily mutually exclusive, as some aspects may be combined with one or more other aspects to form new aspects. Various aspects are described in connection with methods, and various aspects are described in connection with devices.It should be understood, however, that aspects described in connection with methods may also apply to devices, and vice versa. In the drawings, it is noted that identical or similar elements, features, and structures are represented by identical reference numerals. In the drawings, it should be noted that proportions need not be to scale and that the size of features may be exaggerated for clarity.

[0027] FIG. 1A to FIG. 1L illustrate schematic cross-sectional views of a structure in a method for manufacturing an electronic component using the example of a GaN surface emitter.

[0028] FIG. 1A illustrates a first semiconductor layer 116 on a carrier 114. The first semiconductor layer 116 can be formed from a first material, for example GaN, for example undoped GaN or weakly n-doped GaN. The substrate 114 can be formed from a second material, for example a sapphire wafer. The second material can be process-specific, for example transparent to a laser lift-off process (see FIG. 1D). A dielectric structure 112 is arranged on the first semiconductor layer 116. The dielectric structure 112 has openings 112. An opening can, for example, be larger than 1 pm and smaller than 20 pm.

[0029] The dielectric structure 112 may be spaced from an edge of the substrate 114, for example, at a distance 130 therefrom. The distance 130 may, for example, be 1 mm or more.

[0030] The dielectric structure 112 may have a lateral dimension greater than 10 pm, for example in a range from 10 pm to 200 pm, for example in a range from 20 pm to 100 pm.

[0031] A second semiconductor layer 108 is arranged on or above the dielectric structure 112 - and in the openings 102 of the dielectric structure 112 - on the first semiconductor layer 116. The second semiconductor layer 108 can be grown or formed epitaxially. The second semiconductor layer 108 can, for example, be formed from the first material or comprise this. The first semiconductor layer 116 can clearly function as a seed layer in the openings 102 of the dielectric structure 112 for the second semiconductor layer 108. The first material and the second material can have different material structures, such that the defect density in the first semiconductor layer 116 can be high.

[0032] The second semiconductor layer 108 can laterally reshape or overgrow the dielectric structure 112, for example by means of epitaxial lateral overgrowth (ELOG). As a result, a cavity 140 can be formed (as viewed from the substrate 114) on the rear side of the dielectric structure 112 between the second semiconductor layer 108 and the dielectric structure 112, which cavity opens into a coalescence region 104 (also referred to as a third region). The second semiconductor layer 108 can laterally enclose the cavity 140 with increasing layer thickness (with increasing distance from the dielectric structure 112).

[0033] The cavity 140 causes defects in the structure of the material of the second semiconductor layer 108 to be compensated or relaxed.

[0034] As a result, the region 106 (also referred to as second region) of the second semiconductor layer 108 above the dielectric structure 112 (laterally between the first region and the third region) can have a significantly lower defect density in the material structure than the region (also referred to as first region) of the second semiconductor layer in or above the openings 102 of the dielectric structure 112 and in the third region 104.

[0035] A third semiconductor layer 120 is formed on or above the second semiconductor layer 108. The third semiconductor layer 120 can have a much lower defect density, for example, less than approximately 1% to 10%, in the regions corresponding to the second regions of the second semiconductor layer (illustrated in FIG. 1A by means of points 106), than in the first region and third region.

[0036] A second region between a first region and a third region can be a region for the aperture of a surface emitter. The diameter of an aperture for a surface emitter can be smaller than 15 pm, for example, a few pm.

[0037] The third semiconductor layer 120 may be formed from the first material, comprise the first material, or comprise a material with a compatible or comparable lattice structure. As illustrated in FIG. 1A, a portion of the cavity 140 may extend into the third semiconductor layer 120. In this third region, the third semiconductor layer 120 may have a high defect density.

[0038] Depending on the application, a sacrificial structure 118 may be provided between the third semiconductor layer 120 and the second semiconductor structure 108. The sacrificial structure 118 may have one or more layers. The sacrificial structure 118 may have a material structure (for example, a lattice structure) corresponding to the second semiconductor layer 108 and / or the third semiconductor layer 120. The sacrificial structure 118 may be formed from one or more semiconductor materials.

[0039] The material of the sacrificial structure 118 may, for example, have a greater chemical etching rate with respect to a chemical etching medium than the first material.

[0040] The sacrificial structure 118 can be formed epitaxially on the second semiconductor layer 108. As a result, the cavity 140 can extend into the sacrificial structure 118. The cavity 140 enables lateral access to the sacrificial structure 118, for example, for an etching medium.

[0041] In the example of a surface emitter, a light-emitting, for example electroluminescent, structure 124, for example a multi-quantum well (MQW) structure, can be formed on or above the third semiconductor layer 120.

[0042] In the coalesced regions (second regions), the light-emitting structure may have an optical aperture and / or a current aperture.

[0043] The second region can have a lateral dimension (illustrated in FIG. 1A by means of the arrow 132) in the third semiconductor layer 120 and in the corresponding regions in the layers grown thereover, for example in a range from 5 pm to 100 pm, for example in a range from 10 pm to 50 pm - depending on the lateral width of the dielectric structure between adjacent openings 102 and the layer thickness of the second semiconductor layer 108.

[0044] A contact layer 126, for example a p-doped semiconductor layer in the case of an n-doped third semiconductor layer 120, can be formed on or above the light-emitting structure 124. The contact layer 126 can, for example, comprise the first material or be formed therefrom.

[0045] Illustratively, the layers or structures can be grown epitaxially on or above the substrate 114 and form an epitaxial layer stack 128.

[0046] Still referring to a surface emitter, a mirror structure 200 may be formed on or above the epitaxial layer stack 128, as illustrated in FIG. 1B. The mirror structure 200 may, for example, comprise a distributed Bragg mirror (DBR) 204 and a gold layer 208 on the DBR 204. The DBR 204 may extend in the edge region of the substrate 114 beyond the sacrificial structure 118 into the second semiconductor layer 108 (illustrated in FIG. 1B by means of arrow 202). For example, the epitaxial layer stack 128 may be appropriately patterned beforehand.

[0047] Between the contact layer (not illustrated), i.e. the last layer on the layer stack 128, and the DBR 204, an insulating layer (illustrated as a thick black line in FIG. 1B) and a functional structure 206 can be provided depending on the application. The insulating layer can be, for example, an optical aperture and / or an electrical aperture. As illustrated in FIG. 1C, a carrier 308 can be applied on or above the mirror structure 200, for example by means of a conductive planarization layer 302. The carrier 308 can be electrically conductive, for example a Ge or Si wafer. An electrical contact structure 306 can be provided on or above the carrier 308, which is electrically conductively connected to the epitaxial layer stack 128.

[0048] Using a lift-off process, for example, a laser lift-off through the substrate 114, the connection between the first semiconductor layer 116 and the substrate 114 can be released, as illustrated in FIG. 1D. In FIG. 1D, the lift-off is shown as structure 400, which illustrates that laser light is absorbed at this interface. As a result, the substrate 114 can be detached from the first semiconductor layer 116, as illustrated in FIG. 1E.

[0049] A trench structure 604 can be formed from the exposed rear side or surface of the first semiconductor layer 116, for example, in the first region and / or in the third region. The trench structure can have one or more through-openings. The trench structure 604 can, for example, extend through the first semiconductor layer 116, the openings 102 in the dielectric structure 112, or the dielectric structure 112 at least as far as the sacrificial structure 118, such that the sacrificial structure 118 is laterally exposed in the trench structure 604, as illustrated in FIG. 1F by means of the access 606. Furthermore, in the peripheral edge region, a lateral access (illustrated in FIG. 1F by means of the arrow 600) to a cavity 140 can form a lateral access to the sacrificial structure 118.

[0050] An etch stop structure 702 may optionally be provided on or above the trench structure 604. The etch stop structure 702 may be configured as an etch stop for an etching medium for removing the sacrificial structure 118, as further illustrated in FIG. 1G. The material of the etch stop structure 702 may, for example, have a lower solubility in the etching medium than the material of the sacrificial structure 118. The etch stop structure 702 may be formed in the third semiconductor layer 120.

[0051] On the DBR 804, which laterally surrounds the third semiconductor layer 120, a sealing structure 802 may be arranged, which encloses at least the first semiconductor layer 116, the dielectric structure 112 and the second semiconductor layer 108, as illustrated in FIG. 1H.

[0052] An etching medium can be supplied through the previously described trench structures or lateral accesses of the sacrificial structure 118, for example by means of ultrasound assistance. As a result, the sacrificial structure 118 can be removed, as illustrated in FIG. 1i by means of the arrow 902. This enables a separation of the second semiconductor layer 108 from the third semiconductor layer 120. As a result, a surface 1002 (also referred to as the front side or light-emitting side) of the third semiconductor layer 120 can be exposed, as illustrated in FIG. 1J. The exposed surface of the third semiconductor layer can have a lower or improved roughness as a result of the etching process than when the second semiconductor layer is removed by means of a laser lift-off process.

[0053] On or from the exposed surface 1002 of the third semiconductor layer (see FIG. 1J), a further mirror structure 1102, for example a further DBR 1102, may be formed on or above the second regions of the third semiconductor layer 120, as illustrated in FIG. 1K. It is further illustrated that a front-side contact 1104 of the third semiconductor layer 120 and a singulation trench structure 1106 in the third

[0054] Semiconductor layer 120.

[0055] The formed structures may subsequently be tested and singulated, as illustrated in FIG.1L by means of the dashed lines 1202, for example along the etch stop structures 702 (see also FIG. 1G) and / or along the singulation trench structure 1106 (see also FIG.1K).

[0056] FIG.2A to FIG.2F illustrate an alternative to forming the surface emitter by removing the sacrificial structure 118 through the trench structure 604, as illustrated in FIG.1F to FIG.1L. Following the removal of the substrate 114 in FIG.1E, a lateral access 600 to the sacrificial structure 118 in the edge region and / or the cavities can be used as access for the etching medium to the sacrificial structure 118, as illustrated in FIG.2A.

[0057] Analogous to FIG.1H, sealing structure 802 can then be arranged, which encloses at least the first semiconductor layer 116, the dielectric structure 112 and the second semiconductor layer 108, as illustrated in FIG.2B.

[0058] Analogous to FIG. 11, the sacrificial structure 118 can be removed through the one or more accesses 600, as illustrated in FIG. 2C by means of the arrow 902.

[0059] Analogous to FIG. 1J, the surface 1002 of the third semiconductor layer 120 may be exposed, as illustrated in FIG. 2D.

[0060] Analogous to FIG. 1K, a further mirror structure 1102 may be formed on or above the second regions of the third semiconductor layer 120, a front-side contact 1104 of the third semiconductor layer 120, and a singulation trench structure 1106 in the third semiconductor layer 120, as illustrated in FIG. 2E. Analogous to FIG. 1L, the formed structures may subsequently be tested and singulated, as illustrated in FIG. 2F by means of the dashed lines 1202.

[0061] As illustrated in FIG. 3A, in addition to the previously described examples, an electrode structure 1902 may be formed in the epitaxial layer stack 128. The electrode structure 1902 may serve as an electrical contact for electrochemical etching (ECE) of the sacrificial structure 118. For this purpose, an electrical voltage may be applied between the electrode structure 1902 and the sacrificial structure 118. The electrode structure 1902 may, for example, be formed by means of an electrically conductive trench structure in the epitaxial layer stack 128, which is electrically conductively connected to the backside contact 306 (see also FIG. 1C).

[0062] The electrode structure 1902 can, for example, be an n-type contact pad that is electrically connected to the third semiconductor layer 120. The electrode structure 1902 is clearly an n-type via, and the region of the third semiconductor layer 120 with the electrode structure 1902 can also be referred to as a "dummy chip." The dummy chip can be separated from the other components during singulation, as illustrated in FIG. 3B by the arrow 2002.

[0063] The electrode structure 1902 may optionally be isolated from the other layers of the active region of the epitaxial layer stack 128, but is not limited thereto.

[0064] The electrode structure 1902 may be arranged in a second region, but is not limited thereto. For example, the electrode structure 1902 may be arranged in a singulation region. FIG. 4 illustrates a schematic cross-sectional view of the epitaxial layer stack 128. Furthermore, an inclination of the surface of the third semiconductor layer 120 and the layers formed thereabove is illustrated by means of the arrows 2100. The inclination 2100 may result from the lateral overgrowth (ELOG). The inclination 2100 may, for example, have an amount less than or equal to 1°.

[0065] Even if both surfaces of the third semiconductor layer 120 are (slightly) inclined, a surface emitter formed by the method is functional, since the resonator or the optical cavity of the surface emitter also has this inclination.

[0066] FIG. 5A and FIG. 5B illustrate an alternative for forming the surface emitter. FIG. 5A illustrates a portion 2228 of the epitaxial layer stack of FIG. 1A after the second semiconductor layer 118 has laterally overgrown the dielectric structure 112 and before the sacrificial structure 118 has been formed.

[0067] The surface of the second semiconductor layer 108 can be polished, for example, by means of chemical-mechanical polishing, to form a polished surface 2202. The superstructure 118 and the further layers and structures of the epitaxial layer stack 128 can be formed on the polished surface 2202 of the second semiconductor layer 108. The epitaxial layer stack 128 can then be further processed as described above to form the surface emitter (or another corresponding electronic component).

[0068] FIG. 6 illustrates a schematic top view of the epitaxial layer stack 128. As illustrated, the dielectric structures and openings can be strip-shaped. As a result, the coalescence region, or the second region 106 and the third region 104, can be strip-shaped. Also illustrated are the initial regions 2302, from which the lateral overgrowth of the dielectric structure by the second semiconductor layer occurs.

[0069] For example, the peripheral edge region of the substrate is sealed or encapsulated by the second semiconductor layer, leaving no exposed cavities (see FIG. 1A). This prevents any contamination from chemical-mechanical polishing or other processes.

[0070] FIG. 7 illustrates a schematic cross-sectional view of an alternative in which trench structures 2402 were formed for the wet-chemical removal of the sacrificial structure 118 from the side of the epitaxial layer stack 128 opposite the substrate 114. In other words, the trench structures 2402 can be formed in the epitaxial layer stack 128 before the substrate 114 is removed from the first semiconductor layer 116. The etching medium can be configured to be selectively etching for the sacrificial structure 118 and non-etching or weakly etching for the epitaxial layers on the sacrificial structure 118.

[0071] FIG. 8A illustrates a schematic top view of the epitaxial layer stack 128. As illustrated, an electronic device may have a plurality of active regions, for example, a cluster of 2502 active regions (a 4x4 chip is illustrated in FIG. 8A). FIG. 8B illustrates the structure corresponding to FIG. 1L and FIG. 2F, respectively, wherein each device has a plurality of active regions, as illustrated in FIG. 8A.

[0072] In a first direction 2504 (see FIG.8A), the epitaxially grown layers, for example the third semiconductor layer 108, can be arranged below the light-emitting

[0073] Layer 124 may be connected by means of a front-side contact 1104. The epitaxially grown layers 126 above the light-emitting layer 124 may be connected by means of a common back-side contact 208, 300 (see also FIG. 1B and FIG. 1C).

[0074] In a second direction 2506 (see FIG. 8A), the epitaxially grown layers, for example the third semiconductor layer 108, below the light-emitting layer 124 can be connected by means of the coalescence and the front-side contact 1104. The epitaxially grown layers 126 above the light-emitting layer 124 can be connected by means of a common back-side contact 208, 300.

[0075] Access to the sacrificial structure, for example, the trench structure (see, for example, FIG. 1F or FIG. 7), may be arranged below the coalescence region 104 in a device with a plurality of active regions and may be wider than in a device with only a single active region. For example, the trench structure may be formed substantially across the entire chip width or wider than a plurality of rows of active regions, as illustrated in FIG. 8B.

[0076] Even if a dielectric etch stop is required for etching the ECE trench structure, the openings may still have common anode and cathode connections 1104, 208 through metal.

[0077] Even odd numbers of active areas per component are possible, since the separation can occur at the coalescence area 104, the ELOG start area 2302 or elsewhere.

[0078] In other words, referring to FIGS. 1A to 8B, a method for manufacturing an electronic component is provided. The electronic component can be formed with one active region or a plurality of active regions. An active region can be, for example, an electroluminescent region. For example, the electronic component can be a vertical cavity surface emitting laser (VCSEL).

[0079] The method may include forming a first semiconductor layer 116 of a first material on a substrate 114 of a second material.

[0080] The first material may be different from the second material. The first material may be or comprise gallium nitride. The second material may be substantially transparent to the wavelength of a laser. The laser may be used for a laser lift-off process for removing the substrate 114 from the first semiconductor layer 116. The second material may be or comprise an aluminum oxide, for example, a sapphire.

[0081] The method may further comprise forming a dielectric structure 112 on the first semiconductor layer 116. The dielectric structure 112 may have a plurality of openings 102. The first semiconductor layer 116 may be exposed in the openings 102.

[0082] The method may further comprise epitaxially forming a second semiconductor layer 108 on the first semiconductor layer 116 exposed in the openings 102, at least in a region above the dielectric structure 112. The second semiconductor layer 108 may comprise or be formed from the first material. The method may further comprise forming a third semiconductor layer 120 on or above the second semiconductor layer 108 in a first region 102 above the openings 102 of the dielectric structure 112 and in a second region 106 above the dielectric structure 112. The third semiconductor layer 120 may have a much lower defect density in the second region 106 than in the first region 102, for example less than 1% of the defect density of the first region 102. The second region 106 may have a lateral dimension of more than 20 pm.This makes it possible to easily form the third semiconductor layer 120 with a lower defect density on or above a cost-effective substrate 114.

[0083] The third semiconductor layer 120 may be epitaxially deposited on or over the second semiconductor layer 108. The third semiconductor layer 120 may comprise or be formed from the first material.

[0084] The method may further comprise forming a sacrificial structure 118 on the second semiconductor layer 108. The method may further comprise forming the third semiconductor layer 120 on the sacrificial structure 118.

[0085] The method may further comprise removing the sacrificial structure 118 such that the third semiconductor layer 120 is separated from the second semiconductor layer 108. The sacrificial structure 118 may be removed by electrochemical etching (ECE). The sacrificial structure 118 may be removed through one or more lateral accesses 600, 606. The sacrificial structure 118 may be removed by an ultrasound-assisted etching process.

[0086] The sacrificial structure 118 may include one or more layers. The sacrificial structure 118 may include or be formed from one of the following materials: AlN, AlInN, AlGaN, InGaN, AlInGaN, or a combination thereof, for example in one or more layers, for example AlN / AlInN or AlN / AlGaN. The sacrificial structure 118 may include or be one or more n+ or n++ doped layers, for example.

[0087] The dielectric structure 112 may comprise or be formed from a silicon oxide. The openings 102 in the dielectric structure 112 may each have a lateral extent in a range from 1 pm to 20 pm. The dielectric structure 112 may have a lateral dimension of more than 20 pm between adjacent openings 102. The dielectric structure 112 may be configured such that the openings 102 each have a stripe shape. The dielectric structure 112 may be configured such that the regions between adjacent openings 102 each have a stripe shape.

[0088] The dielectric structure 112 can be configured such that a peripheral region of the substrate 114 is substantially free of dielectric structure, such that the second semiconductor layer 108 substantially covers the substrate 114 in the peripheral edge region. The second semiconductor layer can laterally encapsulate the dielectric structure 112 in the peripheral edge region. The peripheral region can have a lateral dimension from an edge of the substrate 114 of at least 1 mm.

[0089] The method may further comprise forming one or more electrical contacts 1902 on or in the third semiconductor layer 120. At least one electrical contact may be formed in the second region 106 of the third semiconductor layer 120. The electrical contact 1902 may function as an electrode for electrochemical etching. The method may further comprise forming an etch stop structure 702 on or in the second region 106 of the third semiconductor layer 120. The etch stop structure 702 may be configured as an etch stop for exposing the sacrificial structure 118.

[0090] The method may further include polishing the exposed surface of the second semiconductor layer 108 before forming the third semiconductor layer 120. The polishing may be chemical mechanical polishing. The sacrificial structure 118 may be formed on the polished surface 2202 of the second semiconductor layer 108. The third semiconductor layer 120 may be formed on the sacrificial structure 118.

[0091] The method may further comprise applying a carrier 308 on or over the third semiconductor layer 120.

[0092] The method may further comprise removing the substrate 114 from the first semiconductor layer 116, for example by means of a laser lift-off process 400.

[0093] The method may further comprise forming trench structures 604, 2402 in the first semiconductor layer 116 and / or the second semiconductor layer 108 in the region of the openings 102 of the dielectric structure 112. The trench structures 604, 2402 may be formed such that the sacrificial structure 118 is laterally exposed in the trench structure 604, 2402. The trench structures 604, 2402 may be formed by means of electrochemical etching. The sacrificial structure 118 may, for example, be removed 902 through the trench structures, for example after the carrier 308 has been applied.

[0094] The method may further comprise singulating 1202 the electronic component. During singulating 1202, at least the third semiconductor layer 120 in the first region 102 may be removed. The method may further comprise forming one or more electrical contacts 1104 on or above the exposed surface of the third semiconductor layer 120 after the second semiconductor layer 108 has been removed to expose the third semiconductor layer 120.

[0095] The functional semiconductor region 124 of the electronic component can be formed on or in the second region 106 of the third semiconductor layer 120. The second region 106 of the third semiconductor layer 120 can thus be configured as an active region of the component. For example, a light-emitting, for example electroluminescent, structure 124 can be formed on or in the second region 106 of the third semiconductor layer 120.

[0096] The word "for example" is used herein to mean "serving as an example, instance, or illustration." Any example or design described herein as "for example" is not necessarily to be construed as preferred or advantageous over other examples or designs.

[0097] The words "plurality" and "multiple" in the description or claims expressly refer to a quantity greater than one. The terms "group (of)" and the like in the description or claims refer to a quantity equal to or greater than one, i.e., one or more. Any term expressed in the plurality that is not expressly stated to be "plurality" or "multiple" also refers to a quantity equal to or greater than one.

[0098] The term "connected" can be understood in the sense of a (e.g. mechanical, optical and / or electrical) , e.g. direct or indirect, connection and / or interaction. For example, several elements can be connected mechanically so that they are physically held ( e . g . a plug connected to a socket ), and electrically so that they have an electrically conductive path ( e . g . signal paths exist along a communicative chain ).

[0099] While the above descriptions and accompanying illustrations depict the components of the optical device as separate elements, those skilled in the art will appreciate the various ways to combine or integrate discrete optical functions into a single element. This may include combining two or more components from a single component. Conversely, those skilled in the art will recognize the possibility of dividing a single element into two or more separate elements, such as splitting a single component into two or more separate components.

[0100] It is understood that the methods described herein are exemplary and may therefore be implemented in a corresponding device. Likewise, it is understood that implementations of the devices described herein may be implemented as a corresponding method. It is therefore understood that a device corresponding to a method described herein may include one or more components configured to perform any aspect of the corresponding method.

[0101] Some examples are described below which relate to what is described and shown in the figures.

[0102] Example 1 is a method for manufacturing an electronic component, the method comprising: forming a first

[0103] A semiconductor layer made of a first material on a substrate made of a second material, the first material being different from the second material; forming a dielectric structure on the first semiconductor layer, the dielectric structure having a plurality of openings, the first semiconductor layer being exposed in the openings; epitaxially forming a second semiconductor layer on the first semiconductor layer exposed in the openings and at least in a region above the dielectric structure, the second semiconductor layer comprising or being formed from the first material; and forming a third semiconductor layer on or above the second semiconductor layer in a first region above the openings of the dielectric structure and in a second region above the dielectric structure.The method further comprises : forming a sacrificial structure on the second semiconductor layer ; forming the third semiconductor layer on the sacrificial structure ; and removing the sacrificial structure such that the third semiconductor layer is separated from the second semiconductor layer .

[0104] In Example 2, the subject matter of Example 1 can optionally comprise that the first material is or comprises a gallium nitride, and wherein the second material is or comprises an aluminum oxide, in particular a sapphire.

[0105] In Example 3, the subject matter of Example 1 or 2 can optionally comprise that the second material is configured to be substantially transparent to the wavelength of a laser, wherein the laser is used for a laser lift-off process for removing the substrate from the first semiconductor layer.

[0106] In Example 4, the article of any of Examples 1 to 3 can optionally comprise that the second region has a lateral dimension of more than 20 pm.

[0107] In Example 5, the subject matter of any of Examples 1 to 4 can optionally include the third semiconductor layer being epitaxially deposited on or over the second semiconductor layer.

[0108] In Example 6, the subject matter of any of Examples 1 to 5 can optionally include that the third semiconductor layer comprises or is formed from the first material.

[0109] In Example 7, the article of any of Examples 1 to 6 can optionally comprise removing the sacrificial structure by means of an electrochemical etch.

[0110] In Example 8, the subject matter of any of Examples 1 to 7 can optionally include removing the sacrificial structure through one or more lateral accesses.

[0111] In Example 9, the subject matter of any of Examples 1 to 8 can optionally include removing the sacrificial structure using an ultrasonic-assisted etching process.

[0112] In Example 10, the subject matter of any one of Examples 1 to 9 can optionally include that the sacrificial structure comprises a material selected from the group consisting of: AIN, AlInN, AlGaN, InGaN, or a combination thereof.

[0113] In Example 11, the subject matter of any of Examples 1 to 10 can optionally comprise that the sacrificial structure comprises one or more layers

[0114] In Example 12, the subject matter of any of Examples 1 to 11 can optionally include that the dielectric structure comprises or is formed from a silicon oxide.

[0115] In Example 13, the subject matter of any one of Examples 1 to 12 can optionally comprise that the openings in the dielectric structure each have a lateral extent in a range of 1 pm to 20 pm. In Example 14, the subject matter of any one of Examples 1 to 13 can optionally comprise that the dielectric structure between adjacent openings has a lateral dimension of more than 20 pm.

[0116] In Example 15, the subject matter of any one of Examples 1 to 14 can optionally include that the dielectric structure is configured such that the openings each have a stripe shape.

[0117] In Example 16, the subject matter of any of Examples 1 to 15 can optionally include that the dielectric structure is configured such that the regions between adjacent openings each have a stripe shape.

[0118] In Example 17, the subject matter of any one of Examples 1 to 16 can optionally include that the dielectric structure is configured such that a peripheral region of the substrate is substantially free of dielectric structure, such that the second semiconductor layer substantially covers the substrate in the peripheral edge region.

[0119] In Example 18, the subject matter of any one of Examples 1 to 17 can optionally include that the second semiconductor layer laterally encapsulates the dielectric structure in the peripheral edge region.

[0120] In Example 19, the article of any of Examples 1 to 17 can optionally include, as dependent on Example 18, that the peripheral region has a lateral dimension from an edge of the substrate of at least 1 mm.

[0121] In Example 20, the subject matter of any one of Examples 1 to 19 can optionally comprise the method: forming one or more electrical contacts on or in the third semiconductor layer, wherein the electrical contact functions as an electrode for electrochemical etching. In Example 21, the subject matter of any one of Examples 1 to 20 can optionally comprise the method: forming an etch stop structure on or in the second region of the third semiconductor layer, wherein the etch stop structure is configured as an etch stop for exposing the sacrificial structure.

[0122] In Example 22, the subject matter of any one of Examples 1 to 21 can optionally comprise the method of polishing the exposed surface of the second semiconductor layer before forming the third semiconductor layer.

[0123] In Example 23, the subject matter of Example 22 can optionally include that the polishing is chemical mechanical polishing.

[0124] In Example 24, the subject matter of any of Examples 1 to 23 can optionally include, as dependent on Example 23, the sacrificial structure is formed on the polished surface of the second semiconductor layer, and the third semiconductor layer is formed on the sacrificial structure.

[0125] In Example 25, the subject matter of any one of Examples 1 to 24 can optionally comprise the method of: applying a carrier on or over the third semiconductor layer.

[0126] In Example 26, the subject matter of any one of Examples 1 to 25 may optionally comprise the method: removing the substrate from the first semiconductor layer, in particular by means of a laser lift-off process.

[0127] In Example 27, the subject matter of any one of Examples 1 to 26 may optionally include the method: forming trench structures in the first semiconductor layer and the second semiconductor layer in the region of the openings of the dielectric structure. In Example 28, the subject matter of Example 27 may optionally include forming the trench structures such that the sacrificial structure is laterally exposed in the trench structure.

[0128] In Example 29, the subject matter of any one of Examples 27 to 28 can optionally include that the trench structures are formed by means of an electrochemical etching.

[0129] In Example 30, the article of any of Examples 1 to 19 can optionally include, depending on Example 25, the sacrificial structure being removed after the carrier is applied.

[0130] In Example 31, the subject matter of any one of Examples 1 to 30 may optionally comprise the method of singulating the electronic component, wherein at least the third semiconductor layer in the first region is removed.

[0131] In Example 32, the subject matter of any one of Examples 1 to 31 can optionally comprise the method of forming one or more electrical contacts on or over the exposed surface of the third semiconductor layer after the second semiconductor layer has been removed to expose the third semiconductor layer.

[0132] In Example 33, the subject matter of any of Examples 1 to 32 can optionally include forming at least one electrical contact in the second region of the third semiconductor layer.

[0133] In Example 34, the subject matter of any one of Examples 1 to 33 can optionally comprise the method: forming a functional semiconductor region on or in the second region of the third semiconductor layer. In Example 35, the subject matter of any one of Examples 1 to 34 can optionally comprise configuring the second region of the third semiconductor layer as an active region of the device.

[0134] In Example 36, the subject matter of any one of Examples 1 to 35 can optionally include forming the electronic component with a plurality of active regions.

[0135] In Example 37, the subject matter of any one of Examples 1 to 36 can optionally comprise forming a light-emitting structure on or in the second region of the third semiconductor layer.

[0136] In Example 38, the subject matter of any of Examples 1 to 37 can optionally include that the electronic device is a vertical surface emitter, VCSEL.

[0137] In Example 38, the subject matter of any one of Examples 1 to 37 can optionally comprise a cavity formed between the second semiconductor layer and the dielectric structure, the second semiconductor layer laterally enclosing the cavity with increasing layer thickness such that a part of the cavity extends into the third semiconductor layer.

[0138] All acronyms defined in the above description also apply to all claims contained herein.

[0139] Although the disclosure has been particularly shown and described with reference to certain embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the disclosure as defined by the appended claims. The scope of the disclosure is therefore indicated by the appended claims, and all changes which come within the meaning and range of equivalence of the claims are therefore intended to be embraced.

[0140] LIST OF REFERENCE SYMBOLS

[0141] 102 Opening / first area

[0142] 104 Coalescen c area / third area

[0143] 106 second area / aperture area

[0144] 108 2 . Semiconductor layers

[0145] 112 dielectric structure

[0146] 114 Substrat

[0147] 116 1 . Semiconductor layers

[0148] 118 victims structure

[0149] 120 , 3 . Semiconductor layers

[0150] 124 light-emitting layer

[0151] 126 Semiconductor layers / Contact layer

[0152] 128 epitaxial layer stack

[0153] 132 Width of the second area

[0154] 140 cavity

[0155] 200 mirror structure

[0156] 202 Overhang over victim structure

[0157] 204 DBR

[0158] 206 optical / electrical aperture

[0159] 208 metal mirror (gold layer)

[0160] 300 back contact

[0161] 302 Adhesive layer / planarization layer

[0162] 306 electrical contact structure

[0163] 308 carriers

[0164] 400 Laser Li ft of f

[0165] 600 Access to the victim structure

[0166] 604 Trench structure

[0167] 606 Access to the victim structure

[0168] 702 Etch stop structure

[0169] 802 Sealing structure

[0170] 804 DBR in the peripheral edge area

[0171] 902 Separation area without Operf structure

[0172] 1002 exposed surface

[0173] 1102 DBR

[0174] 1104 electrical contact

[0175] 1106 Separation trench structure 1202 Separation / separation area

[0176] 1902 electrical contact

[0177] 2002 I isolation area

[0178] 2100 incline

[0179] 2202 polished surface

[0180] 2228 Intermediate structure

[0181] 2302 ELOG start area

[0182] 2402 Trench structure

[0183] 2502 clusters

[0184] 2504 , 2506 direction

Claims

PATENT CLAIMS 1 . A method for manufacturing an electronic component, the method comprising: forming a first semiconductor layer made of a first material on a substrate made of a second material, wherein the first material is different from the second material; Forming a dielectric structure on the first semiconductor layer, the dielectric structure having a plurality of openings, the first semiconductor layer being exposed in the openings; Epitaxially forming a second semiconductor layer on the first semiconductor layer exposed in the openings and at least in a region above the dielectric structure, the second semiconductor layer comprising or being formed from the first material; Forming a third semiconductor layer on or above the second semiconductor layer in a first region above the openings of the dielectric structure and in a second region above the dielectric structure; and forming a sacrificial structure on the second semiconductor layer; forming the third semiconductor layer on the sacrificial structure ; and removing the sacrificial structure such that the third semiconductor layer is separated from the second semiconductor layer .

2. Method according to claim 1, wherein the first material is or comprises a gallium nitride, and wherein the second material is or comprises an aluminum oxide, in particular a sapphire.

3. The method according to claim 1 or 2, wherein the third semiconductor layer is deposited epitaxially on or over the second semiconductor layer, and wherein the third semiconductor layer comprises or is formed from the first material.

4. Method according to one of claims 1 to 3, wherein the sacrificial structure is removed by means of electrochemical etching.

5. The method according to any one of claims 1 to 4, wherein the sacrificial structure comprises a material from the group of materials: AIN, Al InN, AlGaN, InGaN or a combination thereof.

6. The method according to any one of claims 1 to 5, wherein the openings in the dielectric structure each have a lateral extent in a range of 1 pm to 20 pm.

7. Method according to one of claims 1 to 6, wherein the dielectric structure between adjacent openings has a lateral dimension of more than 20 pm.

8. Method according to one of claims 1 to 7, wherein the dielectric structure is arranged such that a peripheral region of the substrate is substantially free of dielectric structure, so that the second semiconductor layer substantially covers the substrate in the peripheral edge region, wherein the second semiconductor layer laterally encapsulates the dielectric structure in the peripheral edge region.

9. The method according to any one of claims 1 to 8, the method further comprising: forming one or more electrical contacts on or in the third semiconductor layer, wherein the electrical contact acts as an electrode for electrochemical etching .

10. Method according to one of claims 1 to 9, the method further comprising: forming an etch stop structure on or in the second region of the third semiconductor layer, wherein the etch stop structure is configured as an etch stop for exposing the sacrificial structure.

11. The method according to any one of claims 1 to 10, the method further comprising: polishing the exposed surface of the second semiconductor layer before the third semiconductor layer is formed.

12. The method according to any one of claims 1 to 11, the method further comprising: wherein the sacrificial structure is formed on the polished surface of the second semiconductor layer, and the third semiconductor layer is formed on the sacrificial structure.

13. The method according to any one of claims 1 to 12, the method further comprising: applying a carrier on or over the third semiconductor layer.

14. Method according to one of claims 1 to 13, the method further comprising: forming trench structures in the first semiconductor layer and the second semiconductor layer in the region of the openings of the dielectric structure, wherein the trench structures are formed such that the sacrificial structure is laterally exposed in the trench structure.

15. A method according to any one of claims 1 to 14, the method further comprising: Separating the electronic component , wherein at least the third semiconductor layer in the first region is removed .

16. A method according to any one of claims 1 to 15, the method further comprising: Forming a functional semiconductor region on or in the second region of the third semiconductor layer , wherein the second region of the third semiconductor layer is configured as an active region of the component .

17. The method according to claim 16, wherein the electronic component is formed with a plurality of active regions.

18. Method according to one of claims 1 to 17, wherein a light-emitting structure is formed on or in the second region of the third semiconductor layer.

19. Method according to one of claims 1 to 18, wherein the electronic component is a vertical surface emitter, VCSEL.

20. Method according to one of claims 1 to 19, wherein a cavity is formed between the second semiconductor layer and the dielectric structure, the second semiconductor layer laterally enclosing the cavity with increasing layer thickness such that a part of the cavity extends into the third semiconductor layer.

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