Latch circuit, dynamic latch, dynamic d flip-flop, and related apparatus

Abstract

The present disclosure relates to a latch circuit, a dynamic latch, a dynamic D flip-flop, and a related apparatus. A latch circuit comprises a first transistor group of a first conductivity type, a second transistor group of the first conductivity type, a third transistor group of a second conductivity type, and a fourth transistor group of the second conductivity type, that are sequentially connected in series between a power supply and ground. A node between the second and third transistor groups is connected to an output terminal. A control terminal of one of the first and second transistor groups and a control terminal of one of the third and fourth transistor groups are jointly connected to an input terminal. The other of the first and second transistor sets receives a first clock signal. The other of the third and fourth transistor sets receives an inverted second clock signal. A transistor of the first conductivity type is turned on when the control terminal thereof is at a low level. A transistor of the second conductivity type is turned on when the control terminal thereof is at a high level. At least one of the first to fourth transistor groups comprises multiple transistors connected in series.

Description

Latching circuits, dynamic latches, dynamic D flip-flops, and related devices

[0001] Cross-reference to Related Applications

[0002] This application is based on and claims priority to CN application No. 202410758098.0, filed on June 13, 2024, the disclosure of which is incorporated herein in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates generally to the field of integrated circuit technology, and more specifically, to latching circuits, dynamic latches, dynamic D flip-flops, registers, processors, and computing devices. BACKGROUND

[0004] With the wide application of high-performance computing in exploration, climate change, transportation, artificial intelligence, etc., the requirements for power consumption, operation speed, and area (cost) of computing chips are becoming higher and higher. Computing chips need to use latches for data latching, and the more computing is required, the more latches are used by the computing chips. Therefore, the performance of the latches directly affects the performance of the computing chips. SUMMARY

[0005] According to a first aspect of the present disclosure, a latching circuit is provided, the latching circuit comprising: an input terminal; an output terminal; and a first transistor group having a first conductivity type, a second transistor group having the first conductivity type, a third transistor group having a second conductivity type different from the first conductivity type, and a fourth transistor group having the second conductivity type, which are connected in series in sequence between a power supply and a ground. A node between the second transistor group and the third transistor group is connected to the output terminal. Control terminals of one of the first transistor group and the second transistor group and control terminals of one of the third transistor group and the fourth transistor group are commonly connected to the input terminal. A control terminal of the other of the first transistor group and the second transistor group is configured to receive a first clock signal. A control terminal of the other of the third transistor group and the fourth transistor group is configured to receive a second clock signal which is inverted from the first clock signal. The first conductivity type is configured such that a transistor is turned on when its control terminal is at a low level. The second conductivity type is configured such that a transistor is turned on when its control terminal is at a high level. At least one of the first transistor group to the fourth transistor group comprises a plurality of transistors connected in series.

[0006] According to a second aspect of the present disclosure, there is provided a dynamic latch comprising: a data input configured to receive a data signal; a data output configured to output the data signal; a clock control configured to receive a clock signal; and a latch unit and an inverting driving unit connected in series between the data input and the data output. The latch unit is configured to latch or transmit the data signal from the data input under control of the clock signal. The inverting driving unit is configured to invert and transmit the data signal from the latch unit. The latch unit comprises the latch circuit according to the first aspect of the present disclosure.

[0007] According to a third aspect of the present disclosure, there is provided a dynamic D flip-flop comprising: a data input configured to receive a data signal; a data output configured to output the data signal; a clock control configured to receive a clock signal; and a first latch unit, a second latch unit and an inverting driving unit connected in series between the data input and the data output. The first latch unit is configured to latch or transmit the data signal from the data input under control of the clock signal. The second latch unit is configured to latch or transmit the data signal from the first latch unit under control of the clock signal. The inverting driving unit is configured to invert and transmit the data signal from the second latch unit.

[0008] In some embodiments, the first latch unit comprises the latch circuit according to the first aspect of the present disclosure.

[0009] In some embodiments, the second latch unit comprises the latch circuit according to the first aspect of the present disclosure.

[0010] According to a fourth aspect of the present disclosure, there is provided a register comprising: a plurality of data inputs configured to receive data signals; a plurality of data outputs configured to output the data signals; a clock control configured to receive a clock signal; a clock buffer configured to buffer the clock signal received by the clock control and provide the clock signal to a plurality of register units; and the plurality of register units connected in parallel between the plurality of data inputs and the plurality of data outputs and configured to perform at least one of writing data and reading data under control of the clock signal. A register unit in the plurality of register units is the dynamic latch according to the second aspect of the present disclosure, or the dynamic D flip-flop according to the third aspect of the present disclosure.

[0011] According to a fifth aspect of the present disclosure, there is provided a processor comprising the dynamic latch according to the second aspect of the present disclosure, or the dynamic D flip-flop according to the third aspect of the present disclosure, or the register according to the fourth aspect of the present disclosure.

[0012] According to a sixth aspect of the present disclosure, there is provided a computing device comprising a processor according to the fifth aspect of the present disclosure.

[0013] Other features of the present disclosure, which are evident from the above description, and advantages thereof will become apparent from the following detailed description of exemplary embodiments of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0014] The accompanying drawings, which constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, explain the principles of the present disclosure. The present disclosure can be understood more readily by reference to the following detailed description of exemplary embodiments, and the appended drawings, of which:

[0015] FIG. 1 shows a circuit schematic of a dynamic latch according to a comparative example of the present disclosure;

[0016] FIG. 2 shows a dynamic latch according to some embodiments of the present disclosure;

[0017] FIG. 3 shows a clock buffer according to some embodiments of the present disclosure;

[0018] FIG. 4 shows a dynamic latch and its associated clock circuit according to some embodiments of the present disclosure;

[0019] FIGS. 5 to 18 show circuit schematics of dynamic latches according to some embodiments of the present disclosure, respectively;

[0020] FIG. 19 shows a dynamic D flip-flop according to some embodiments of the present disclosure;

[0021] FIGS. 20 to 25 show circuit schematics of dynamic D flip-flops according to some embodiments of the present disclosure, respectively;

[0022] FIG. 26 shows a register according to some embodiments of the present disclosure;

[0023] FIG. 27 shows an example timing diagram of the circuit of the dynamic latch shown in FIG. 7;

[0024] FIG. 28 shows an example timing diagram of the circuit of the dynamic latch shown in FIG. 10.

[0025] Note that, in the following embodiments, the same reference numerals are sometimes used across different drawings to denote the same or similar parts or parts having the same function, and repeated description thereof is omitted. In the present specification, like numbers and letters refer to like items unless something different is specifically stated. Thus, once an item is defined in one drawing, it need not be discussed further in other drawings unless otherwise stated.

[0026] For ease of understanding, the positions, sizes, ranges, and the like of the structures shown in the drawings and the like are sometimes not actual ones. Therefore, the disclosed application is not limited to the positions, sizes, ranges, and the like disclosed in the drawings and the like. Further, the drawings are not necessarily drawn to scale, and some features can be exaggerated to show details of specific components. DETAILED DESCRIPTION

[0027] Various exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the relative arrangement of the components and steps, numerical expressions, and numerical values set forth in these embodiments are not limiting to the scope of the present disclosure unless otherwise specifically stated.

[0028] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the scope of the present disclosure and its applications or uses. That is, the structures and methods herein are shown by way of example in the drawings and are illustrative of the various embodiments in the present disclosure. However, those skilled in the art will appreciate that they are merely illustrative of exemplary manners in which the present disclosure can be carried out and is not exhaustive. Further, the drawings are not necessarily drawn to scale, and some features can be exaggerated to show details of specific components.

[0029] In addition, techniques, methods, and apparatus known to those of ordinary skill in the relevant art can not be discussed in detail herein, but should be considered as part of the specification, where appropriate.

[0030] In all examples shown and discussed herein, any specific values should be interpreted as merely illustrative and not as a limitation. Thus, other examples of the exemplary embodiments can have different values.

[0031] It should be understood that, although metal-oxide-semiconductor (MOS) transistors are mainly exemplified in the drawings herein, the present disclosure is not limited thereto, but can also take any other suitable transistors, including but not limited to bipolar junction (BJT) transistors and the like.

[0032] It should also be understood that, herein, the control terminal of a transistor can refer to a port for controlling the current flow and switching state of the transistor, and the transmission terminal of the transistor can refer to a port for inputting and outputting the current or signal of the transistor. For example, specifically, for MOS transistors, the control terminal is the gate, and the transmission terminal is the source and the drain; for BJT transistors, the control terminal is the base, and the transmission terminal is the emitter and the collector.

[0033] It should also be understood that, herein, the first conductivity type can be configured such that the transistor is turned on when its control terminal is at a low level, and the second conductivity type can be configured such that the transistor is turned on when its control terminal is at a high level. For example, specifically, for a MOS transistor, the first conductivity type is P-type, and the second conductivity type is N-type; for a BJT transistor, the first conductivity type is PNP-type, and the second conductivity type is NPN-type.

[0034] It should also be understood that, herein, the power supply and the ground are relative concepts, which exist relative to each other, and are used to describe the polarity and direction of voltage in a circuit. For example, the power supply can represent a high level, and the ground can represent a low level.

[0035] A dynamic latch is simpler in structure than a static latch, because the feedback circuit for maintaining the working state is reduced, which reduces the chip area and the power consumption. With these advantages, dynamic latches are widely used in computing chips. However, because there is a node with a floating potential in a dynamic latch for part of the time, the parasitic capacitance at the node needs to maintain the correct voltage state during the part of the time.

[0036] In order to avoid the influence of the leakage current of the device on the voltage of the node, the dynamic latch must work at a higher frequency, so as to reduce the leakage time to prevent functional errors. This greatly limits the range of use of the chip. For example, in some states of the processor, such as sleep or idle, the dynamic latch can work at a relatively low frequency, at which time functional errors are likely to occur.

[0037] Figure 1 illustrates a dynamic latch 10 according to a comparative example of the present disclosure. The dynamic latch 10 includes a tri-state gate 11 and an inverter 12 connected in series between a data input D and a data output Q. Specifically, the tri-state gate 11 includes P-type metal-oxide-semiconductor (PMOS) transistors P1, P2, N-type metal-oxide-semiconductor (NMOS) transistors N1 and N2 connected in series between a power supply VDD and a ground VSS. The gates of the PMOS transistors P1 and N2 are commonly connected to form an input of the tri-state gate 11. The drains of the PMOS transistors P2 and NMOS transistors N1 are commonly connected to form an output of the tri-state gate 11. The clock signals received by the gates of the PMOS transistors P2 and NMOS transistors N1 are opposite to each other. The inverter 12 includes PMOS transistors P0 and NMOS transistors N0 connected in series between the power supply VDD and the ground VSS. The gates of the PMOS transistors P0 and NMOS transistors N0 are commonly connected to form an input of the inverter 12, and the drains of the PMOS transistors P0 and NMOS transistors N0 are commonly connected to form an output of the inverter 12. Thus, assuming that the data input D receives a data signal S, when the clock signal CLKP is high and the clock signal CLKN is low, the tri-state gate 11 is turned on, the data signal S is transmitted by the tri-state gate 11 to the inverter 12 and then transmitted by the inverter 12, so that a non-inverted version of the data signal S is output at the data output Q. That is, the dynamic latch 10 is a dynamic latch for providing a non-inverted output.

[0038] As shown in Figure 1, a node A is formed between the tri-state gate 11 and the inverter 12. Data can be temporarily stored at the node A by a parasitic capacitance of the inverter 12. However, during a part of a clock cycle, the potential of the node A can be floating in the operation of the dynamic latch 10. Dynamic leakage will cause the data stored at the node A to be lost.

[0039] Specifically, when CLKP is high and CLKN is low, the tri-state gate 11 is turned on, so that an inverted version of the data from the data input D is transmitted to the node A to write the inverted version of the data into the parasitic capacitance C of the node A. When CLKP becomes low and CLKN becomes high, the tri-state gate 11 is turned off, and the inverted version of the data previously transmitted by the tri-state gate 11 is maintained in the parasitic capacitance C of the node A.

[0040] Ideally, during a period when CLKP is low and CLKN is high (referred to as a shutdown period), the tri-state gate 11 is closed and the output of the dynamic latch 10 remains in its original state, with node A floating. The leakage current of the PMOS transistor P2 and the NMOS transistor Nl themselves can charge and discharge node A while it is floating. When one of the PMOS transistor P2 and the NMOS transistor Nl has a more severe leakage than the other, the voltage state of node A can be discharged to the opposite state (i.e., node A cannot hold the correct voltage state), undesirably changing the output state of the dynamic latch 10 and causing the dynamic latch 10 to malfunction.

[0041] For example, assume that the data input D originally provides a data "1", the tri-state gate 11 is on so that node A holds the data "0", and thus the output of the dynamic latch 10 is "1". Subsequently, CLKP becomes low and CLKN becomes high, causing the PMOS transistor P2 and the NMOS transistor Nl to turn off. If at this time the data input D provides a data "0", the PMOS transistor P 1 is on and the NMOS transistor N2 is off. Ideally, even though the PMOS transistor P 1 is on so that the level at the source terminal of the PMOS transistor P2 is controlled to a high level by the power supply VDD, node A cannot be rewritten to "1" and thus the output state of the dynamic latch 10 cannot be changed because the PMOS transistor P2 is off. However, if the PMOS transistor P2 has leakage and cannot be ideally completely turned off, the power supply VDD is equivalent to charging the parasitic capacitance of node A. On the other hand, ideally, both the NMOS transistors Nl and N2 are off. However, if the NMOS transistors Nl and N2 have leakage and cannot be ideally completely turned off, ground VSS is equivalent to discharging the parasitic capacitance of node A. The charging process and the discharging process compete with each other, and if the leakage of the PMOS transistor P2 is more severe than the leakage of the NMOS transistors Nl and N2 connected in series, node A is gradually rewritten to "1" and the data "0" that node A is supposed to hold is lost, and thus the output of the dynamic latch 10 undesirably becomes "0". In general, the leakage of a single PMOS transistor P2 is more severe than the leakage of the NMOS transistors Nl and N2 connected in series, although it is possible that in some processes the leakage of an NMOS transistor is much more severe than that of a PMOS transistor, resulting in the opposite situation.

[0042] Similarly, assume that the data input D originally provides data "0", the tri-state gate 11 is turned on so that the node A keeps the data "1", and thus the output of the dynamic latch 10 is "0". Subsequently, CLKP becomes low and CLKN becomes high, so that the PMOS transistor P2 and the NMOS transistor N1 are turned off. If the data input D provides data "1" at this time, the PMOS transistor P1 is turned off and the NMOS transistor N2 is turned on. Ideally, even if the NMOS transistor N2 is turned on so that the level at the source end of the NMOS transistor N1 is controlled to a low level by the ground VSS, since the NMOS transistor N1 is turned off, the data of the node A cannot be rewritten to "0", and thus the output state of the dynamic latch 10 will not be changed. However, if the NMOS transistor N1 has leakage and cannot be ideally completely turned off, the ground VSS is equivalent to discharging the parasitic capacitor of the node A. On the other hand, ideally, both the PMOS transistors P1 and P2 are turned off. However, if the PMOS transistors P1 and P2 have leakage and cannot be ideally completely turned off, the power supply VDD is equivalent to charging the parasitic capacitor of the node A. The discharging process and the charging process compete with each other, and once the leakage of the NMOS transistor N1 is more serious than the leakage of the PMOS transistors P1 and P2 connected in series, the data of the node A will be gradually rewritten to "0", causing the data "1" that the node A should keep to be lost, and thus the output of the dynamic latch 10 undesirably becomes "1". Generally, the leakage of a single NMOS transistor N1 will be more serious than the leakage of the PMOS transistors P1 and P2 connected in series, and of course it is possible that in some processes the PMOS transistors leak much more seriously than the NMOS transistors, which can lead to the opposite situation.

[0043] That is, in the state where CLKP is low and CLKN is high, the tri-state gate 11 cannot ideally keep closed, but there is a certain leakage path, especially as the closing period increases, the risk of data loss is higher. However, as the process nodes continue to shrink (for example, 7 nanometers, 5 nanometers, etc.), the leakage of NMOS transistors and PMOS transistors is intensified, and the imbalance of the leakage of the two can also be amplified, which requires the closing period to be shorter and shorter.

[0044] Specifically, assume that the charge stored on the parasitic capacitor C is Q, the capacitance value of the parasitic capacitor C is C, and the voltage across the parasitic capacitor C is V, then Q = C * V. If the leakage current is I leakage , then the leakage time T (corresponding to the closing period) is T = Q / I leakage = C * V / I leakage . The leakage time is in a positive relationship with the clock period, that is, the clock frequency F clk ∝ 1 / T = I leakage(C*V). Therefore, dynamic leakage current limits the minimum operating frequency of the dynamic latch. If the operating frequency of the dynamic latch is too low, functional errors can occur.

[0045] To this end, the present disclosure provides a dynamic latch that can effectively suppress dynamic leakage current, thereby being able to operate normally at a lower operating frequency. This is advantageous for reducing power consumption, and in particular, when such dynamic latches are used in large quantities in a computing chip, it can significantly reduce the overall power consumption of the computing chip. The dynamic latch according to various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that an actual dynamic latch can also include other components, and in order to avoid obscuring the gist of the present disclosure, these other components are not discussed herein and are not shown in the accompanying drawings.

[0046] FIG. 2 shows a dynamic latch 100 according to some embodiments of the present disclosure. The dynamic latch 100 includes a data input terminal 101, a data output terminal 102, a clock control terminal 103, and a latch unit 104 and an inverting drive unit 105 connected in series between the data input terminal 101 and the data output terminal 102. The data input terminal 101 is configured to receive a data signal. The data output terminal 102 is configured to output the data signal. The clock control terminal 103 is configured to receive a clock signal. The latch unit 104 is configured to latch or transmit the data signal from the data input terminal 101 under the control of the clock signal. The inverting drive unit 105 is configured to invert and transmit the data signal from the latch unit 104.

[0047] FIG. 3 shows a clock buffer 200 for providing a clock signal. The clock buffer 200 is composed of two stages of inverters 201, 202. The clock buffer 200 buffers an input clock signal CK and provides clock signals CLKN, CLKP that are complementary to each other. In FIG. 3, only 2 inverters are shown, but the number of inverters is not limited to 2, but can be more. The clock buffer 200 can be used to provide the clock signal for the dynamic latch 100. As shown in FIG. 4, the clock signal CK is buffered by the clock buffer 200 to provide the dynamic latch 100 with clock signals CLKN, CLKP that are complementary to each other. Similarly, the clock buffer 200 can be used to provide the dynamic D flip-flop, register, etc. described later with clock signals CLKN, CLKP that are complementary to each other.

[0048] Exemplarily, the latch unit 104 can include a latch circuit according to various embodiments of the present disclosure. Such a latch circuit can be configured as a latch circuit for providing an inverted output. Specifically, the latch circuit can include: an input terminal; an output terminal; and a first transistor group having a first conduction type, a second transistor group having the first conduction type, a third transistor group having a second conduction type different from the first conduction type, and a fourth transistor group having the second conduction type, which are connected in series in order between a power supply and a ground. As described before, the first conduction type is configured such that a transistor is turned on when its control terminal is at a low level, and the second conduction type is configured such that a transistor is turned on when its control terminal is at a high level.

[0049] A node between the second transistor group and the third transistor group is connected to the output terminal for outputting a data signal. Control terminals of one of the first transistor group and the second transistor group and control terminals of one of the third transistor group and the fourth transistor group are commonly connected to the input terminal for receiving the data signal. Control terminals of the other of the first transistor group and the second transistor group are configured to receive a first clock signal. Control terminals of the other of the third transistor group and the fourth transistor group are configured to receive a second clock signal which is inverted from the first clock signal. Herein, a transistor or a transistor group for receiving a data signal can be referred to as a data transistor or a data transistor group, and a transistor or a transistor group for receiving a clock signal can be referred to as a clock transistor or a clock transistor group. In addition, a circuit portion from the power supply to the output terminal can be referred to as a first sub-circuit including the first transistor group and the second transistor group, and a circuit portion from the ground to the output terminal can be referred to as a second sub-circuit including the third transistor group and the fourth transistor group.

[0050] In particular, at least one of the first to fourth transistor groups includes a plurality of transistors connected in series, thereby being able to reduce leakage at the at least one transistor group, and thus achieve a reduced minimum operating frequency.

[0051] In some embodiments, the at least one transistor group can be a clock transistor group, e.g., comprising one or two clock transistor groups. In some embodiments, the at least one transistor group can be a data transistor group, e.g., comprising one or two data transistor groups. In some embodiments, the at least one transistor group comprises at least one data transistor group and at least one clock transistor group. In most cases, it can be more advantageous to have a clock transistor group comprise a plurality of transistors connected in series than to have a data transistor group comprise a plurality of transistors connected in series, because, as analyzed earlier with respect to FIG. 1, leakage of a clock transistor can more easily cause data loss (a data transistor in a corresponding one of the leakage paths can be in series with a corresponding one of the clock transistors, which in one aspect can be less likely to leak as a result of having more transistors, and in another aspect can be more likely to be in a direction toward the data held by the repair node A than a single clock transistor in another of the leakage paths). Of course, having a clock transistor group comprise a plurality of transistors connected in series can be further advantageous in some aspects in that leakage can be further suppressed, but too many transistors can also cause problems such as too much chip area being occupied, slower operation, etc.

[0052] As a non-limiting example, the control terminals of the first transistor group and the control terminals of the fourth transistor group can be commonly connected to the input terminal, the control terminals of the second transistor group are configured to receive a first clock signal, and the control terminals of the third transistor group are configured to receive a second clock signal. In such embodiments, the first transistor group and the fourth transistor group act as data transistor groups, and the second transistor group and the third transistor group act as clock transistor groups. In some examples, at least one of the second transistor group and the third transistor group comprises a plurality of transistors connected in series. Further, in some examples, at least one of the first transistor group and the fourth transistor group comprises a plurality of transistors connected in series.

[0053] For example, referring to FIG. 5, which illustrates a circuit 300 of the dynamic latch 100, according to some embodiments of the present disclosure. As shown in FIG. 5, the circuit 300 comprises a latch circuit 310 (which acts as the latch cell 104 (specifically, the inverting latch cell) of the dynamic latch 100) and an inverter 330 (which acts as the inverting drive cell 105 of the dynamic latch 100) connected in series between a data input terminal D and a data output terminal Q.

[0054] The inverter 330 includes a PMOS transistor 331 and an NMOS transistor 332 connected in series between the power supply VDD and the ground VSS, the control terminals (here, gates) of the two transistors are commonly connected to form an input terminal of the inverter 330, and the transmission terminals (here, drains) of the two transistors are commonly connected to form an output terminal of the inverter 330. The output terminal of the inverter 330 can directly provide a data output terminal Q of the circuit 300.

[0055] The latch circuit 310 has an input terminal 3101 and an output terminal 3102. The input terminal 3101 of the latch circuit 310 can directly provide a data input terminal D of the circuit 300. The output terminal 3102 of the latch circuit 310 is connected to the input terminal of the inverter 330, and a node A with a floating potential at part of time is formed therebetween.

[0056] As shown in FIG. 5, the latch circuit 310 includes a PMOS transistor group 311, a PMOS transistor group 312, an NMOS transistor group 313, and an NMOS transistor group 314 connected in series between the power supply VDD and the ground VSS. The control terminal (here, gate) of the PMOS transistor group 311 and the control terminal (here, gate) of the NMOS transistor group 314 are commonly connected to the input terminal 3101. The node between the PMOS transistor group 312 and the NMOS transistor group 313 is connected to the output terminal 3102. In particular, the PMOS transistor group 311 includes one PMOS transistor 3111, the PMOS transistor group 312 includes two PMOS transistors 3121, 3122 connected in series, the NMOS transistor group 313 includes one NMOS transistor 3131, and the NMOS transistor group 314 includes one NMOS transistor 3141. Generally, the bulk of these transistors are not suspended, where the bulk of the PMOS transistor can be connected to the power supply, and the bulk of the NMOS transistor can be connected to the ground.

[0057] In the example of FIG. 5, the PMOS transistor group 312 is configured to receive a clock signal CLKN, and the NMOS transistor group 313 is configured to receive a clock signal CLKP which is inverted from the clock signal CLKN. Specifically, the control terminals (here, gates) of the PMOS transistors 3121, 3122 can be commonly connected to receive the clock signal CLKN, and the control terminal (here, gate) of the NMOS transistor 3131 receives the clock signal CLKP.

[0058] Compared with the dynamic latch 10 of FIG. 1, FIG. 5 is equivalent to realizing a channel-extended PMOS transistor for receiving a clock signal by including multiple PMOS transistors connected in series in the PMOS transistor group for receiving the clock signal, thereby reducing the leakage current, and further enabling a reduced minimum operating frequency.

[0059] This is particularly advantageous in digital circuits, because digital circuits cannot arbitrarily design the size of the transistor as analog circuits can, but usually select the transistor in the standard cell library. The size selection of the channel length of the transistor in the standard cell library is limited, and usually can include two grades, one of which is 1 unit length, and the other is 1.2 unit length. The channel lengthening caused by simply replacing the 1 unit length channel transistor with the 1.2 unit length channel transistor cannot sufficiently suppress dynamic leakage. By increasing the threshold voltage V TH It can also reduce its leakage current, but the selection of the threshold voltage of the transistor in the standard cell library is also limited, and the change caused by increasing the threshold voltage is too large, which will also make the transistor more difficult to turn on (for example, the power supply voltage needs to be raised), and cannot achieve precise suppression of dynamic leakage. Therefore, by controlling the number of transistors in series in the transistor group, the desired channel lengthening effect can be achieved according to the specific needs, so as to fully suppress the dynamic leakage. Of course, the number of transistors should not be too many, otherwise it will slow down the speed of the dynamic latch. In some examples, the number of transistors in each of the at least one transistor group in the first to fourth transistor groups is not more than three, for example, two.

[0060] Figure 6 shows a circuit 300 of the dynamic latch 100 according to another embodiment of the present disclosure. Compared with Figure 5, in Figure 6, the PMOS transistor group 312 includes one PMOS transistor 3121, and the NMOS transistor group 313 includes two NMOS transistors 3131, 3132 connected in series. The control end (here the gate) of the PMOS transistor 3121 receives the clock signal CLKN, and the control ends (here the gates) of the NMOS transistors 3131, 3132 can be commonly connected to receive the clock signal CLKP. Compared with the dynamic latch 10 of Figure 1, Figure 6 includes multiple NMOS transistors connected in series in the NMOS transistor group for receiving the clock signal, which is equivalent to realizing the channel lengthening of the NMOS transistor for receiving the clock signal, thereby reducing the leakage current, and further enabling a reduced minimum operating frequency.

[0061] Figure 7 shows a circuit 300 of the dynamic latch 100 according to some other embodiments of the present disclosure. Compared with Figure 5, in Figure 7, the NMOS transistor group 313 includes two NMOS transistors 3131, 3132 connected in series. Compared with the dynamic latch 10 of Figure 1, Figure 7 is equivalent to implementing a channel- lengthened PMOS transistor for receiving the first clock signal and a channel- lengthened NMOS transistor for receiving the second clock signal by including multiple PMOS transistors connected in series in the PMOS transistor group for receiving the clock signal and including multiple NMOS transistors connected in series in the NMOS transistor group for receiving the clock signal, thereby reducing the leakage current, and in turn enabling a reduced minimum operating frequency.

[0062] Figure 8 shows a circuit 300 of the dynamic latch 100 according to some other embodiments of the present disclosure. Compared with Figure 7, in Figure 8, the PMOS transistor group 312 includes three PMOS transistors 3121, 3122, 3123 connected in series, and the NMOS transistor group 313 includes three NMOS transistors 3131, 3132, 3133 connected in series. The control terminals (here, gates) of the PMOS transistors 3121, 3122, 3123 can be commonly connected to receive the clock signal CLKN, and the control terminals (here, gates) of the NMOS transistors 3131, 3132, 3133 can be commonly connected to receive the clock signal CLKP. Compared with Figure 7, in Figure 8, the number of transistors connected in series in each clock transistor group changes from two to three. As previously described, this can result in further suppression of leakage and thus further reduction of the minimum operating frequency.

[0063] Figure 9 shows a circuit 300 of the dynamic latch 100 according to some other embodiments of the present disclosure. Compared with Figure 7, in Figure 9, the PMOS transistor group 311 includes two PMOS transistors 3111, 3112 connected in series, and the NMOS transistor group 314 includes two NMOS transistors 3141, 3142 connected in series. The control terminals (here, gates) of the PMOS transistors 3111, 3112 and the NMOS transistors 3141, 3142 can be commonly connected to the input terminal 3101. Compared with Figure 7, Figure 9 is equivalent to implementing a channel- lengthened PMOS transistor for receiving the data signal and a channel- lengthened NMOS transistor for receiving the data signal by including multiple PMOS transistors connected in series in the PMOS transistor group for receiving the data signal and including multiple NMOS transistors connected in series in the NMOS transistor group for receiving the data signal, thereby reducing the leakage current, and in turn enabling a reduced minimum operating frequency.

[0064] The number of transistors in each of the two groups of transistors can be adjusted as desired. For example, when transistor technology dictates that NMOS transistors leak more than PMOS transistors, the group of NMOS transistors can include more transistors than the group of PMOS transistors. Conversely, when transistor technology dictates that PMOS transistors leak more than NMOS transistors, the group of PMOS transistors can include more transistors than the group of NMOS transistors. Overall, the more balanced the leakage of the first sub-circuit and the second sub-circuit, the less likely the voltage state of the floating node A will be discharged to the opposite state, thereby preventing functional errors.

[0065] Accordingly, in some embodiments, the total number of transistors in the first group of transistors and the second group of transistors can be greater than the total number of transistors in the third group of transistors and the fourth group of transistors. Additionally or alternatively, in some embodiments, the number of transistors in the clock transistor group of the first group of transistors and the second group of transistors can be greater than the number of transistors in the clock transistor group of the third group of transistors and the fourth group of transistors. This is illustrated, for example, in FIG. 5. In such embodiments, the transistors of the first conductivity type can have a more severe degree of leakage than the transistors of the second conductivity type.

[0066] In other embodiments, the total number of transistors in the first group of transistors and the second group of transistors can be less than the total number of transistors in the third group of transistors and the fourth group of transistors. Additionally or alternatively, in some embodiments, the number of transistors in the clock transistor group of the first group of transistors and the second group of transistors can be less than the number of transistors in the clock transistor group of the third group of transistors and the fourth group of transistors. This is illustrated, for example, in FIG. 6. In such embodiments, the transistors of the second conductivity type can have a more severe degree of leakage than the transistors of the first conductivity type.

[0067] In yet other embodiments, the total number of transistors in the first group of transistors and the second group of transistors can be equal to the total number of transistors in the third group of transistors and the fourth group of transistors. Additionally or alternatively, in some embodiments, the number of transistors in the clock transistor group of the first group of transistors and the second group of transistors can be equal to the number of transistors in the clock transistor group of the third group of transistors and the fourth group of transistors. This is illustrated, for example, in FIG. 7 and FIG. 8. In such embodiments, the transistors of the first conductivity type and the transistors of the second conductivity type can have substantially the same degree of leakage. For example, in this context, “substantially the same degree of leakage” can mean that the degree of leakage differs by no more than 20%, or 15%, or 10%, or 5%.

[0068] Although the embodiments shown in FIGS. 5-9 all depict the number of transistors in the P-type data transistor group (e.g., PMOS transistor group 311) and the N-type data transistor group (e.g., NMOS transistor group 314) as being the same, this is merely exemplary and not limiting, and the number of transistors in the data transistor groups can be adjusted individually or in combination with the number of transistors in the clock transistor groups as taught above, without further elaboration here.

[0069] In the circuit 300 described above, the dynamic latch is high-active. For example, in conjunction with FIGS. 7 and 27, initially, the input data at the data input D is "0" and the data output Q provides the same-phase output data "0". Next, the input data at the data input D changes from "0" to "1", but because the latch circuit 310 is off at this time since CLKP is low and CLKN is high, the data output Q remains "0". As CLKP changes to high and CLKN changes to low, the latch circuit 310 turns on, and the input data "1" at the data input D is transmitted through the latch circuit 310 and inverted by the inverter 330, so that the data output Q provides the same-phase output data "1".

[0070] In addition, the application of the clock signals CLKP and CLKN in any of the embodiments herein can be reversed. For example, referring to FIG. 10, which is compared with FIG. 7, the application of the clock signals CLKP and CLKN is reversed, such that the PMOS transistor group 312 receives the clock signal CLKP and the NMOS transistor group 313 receives the clock signal CLKN, thereby implementing a low-active dynamic latch. For example, in conjunction with FIGS. 10 and 28, initially, the input data at the data input D is "0" and the data output Q provides the same-phase output data "0". Next, the input data at the data input D changes from "0" to "1", but because the latch circuit 310 is off at this time since CLKP is high and CLKN is low, the data output Q remains "0". As CLKP changes to low and CLKN changes to high, the latch circuit 310 turns on, and the input data "1" at the data input D is transmitted through the latch circuit 310 and inverted by the inverter 330, so that the data output Q provides the same-phase output data "1".

[0071] As another non-limiting example, the control terminals of the second transistor group and the control terminals of the third transistor group can be commonly connected to the input terminal, the control terminals of the first transistor group are configured to receive a first clock signal, and the control terminals of the fourth transistor group are configured to receive a second clock signal. In such an example, the first transistor group and the fourth transistor group act as clock transistor groups, and the second transistor group and the third transistor group act as data transistor groups. In some examples, at least one of the first transistor group and the fourth transistor group includes a plurality of transistors connected in series. Further, in some examples, at least one of the second transistor group and the third transistor group includes a plurality of transistors connected in series.

[0072] For example, referring to FIG. 11, there is shown a circuit 400 of the dynamic latch 100 according to some embodiments of the present disclosure. As shown in FIG. 11, the circuit 400 includes a latch circuit 410 (which acts as the latch cell 104 (specifically, the inverting latch cell) of the dynamic latch 100) and an inverter 430 (which acts as the inverting drive cell 105 of the dynamic latch 100) connected in series in sequence between a data input terminal D and a data output terminal Q.

[0073] Similar to the inverter 330, the inverter 430 includes a PMOS transistor 431 and an NMOS transistor 432 connected in series in sequence between a power supply VDD and a ground VSS. An output terminal of the inverter 430 can directly provide the data output terminal Q of the circuit 400.

[0074] Similar to the latch circuit 310, the latch circuit 410 has an input terminal 4101 and an output terminal 4102. The input terminal 4101 of the latch circuit 410 can directly provide the data input terminal D of the circuit 400. The output terminal 4102 of the latch circuit 410 is connected to an input terminal of the inverter 430, between which a node A is formed that is floating in potential for part of the time.

[0075] As shown in FIG. 11, the latch circuit 410 includes a PMOS transistor group 411, a PMOS transistor group 412, an NMOS transistor group 413, and an NMOS transistor group 414 connected in series in turn between a power supply VDD and a ground VSS. The control end (here, the gate) of the PMOS transistor group 412 and the control end (here, the gate) of the NMOS transistor group 413 are commonly connected to an input end 4101. A node between the PMOS transistor group 412 and the NMOS transistor group 413 is connected to an output end 4102. The PMOS transistor group 411 includes two PMOS transistors 4111, 4112 connected in series, the PMOS transistor group 412 includes one PMOS transistor 4121, the NMOS transistor group 413 includes one NMOS transistor 4131, and the NMOS transistor group 414 includes one NMOS transistor 4141. Generally, the bulk of each of these transistors is not suspended, where the bulk of the PMOS transistor can be connected to the power supply and the bulk of the NMOS transistor can be connected to the ground.

[0076] In the example of FIG. 11, the PMOS transistor group 411 is configured to receive a clock signal CLKN, and the NMOS transistor group 414 is configured to receive a clock signal CLKP that is inverted from the clock signal CLKN.

[0077] Compared with the dynamic latch 10 of FIG. 1, FIG. 11 is equivalent to implementing a channel-extended PMOS transistor for receiving a clock signal by including multiple PMOS transistors connected in series in the PMOS transistor group for receiving the clock signal, thereby reducing the leakage current, and further enabling a reduced minimum operating frequency.

[0078] FIG. 12 shows a circuit 400 of a dynamic latch 100 according to some other embodiments of the present disclosure. Compared with FIG. 11, in FIG. 12, the PMOS transistor group 411 includes one PMOS transistor 4111, and the NMOS transistor group 414 includes two NMOS transistors 4141, 4142 connected in series. Compared with the dynamic latch 10 of FIG. 1, FIG. 12 is equivalent to implementing a channel-extended NMOS transistor for receiving a clock signal by including multiple NMOS transistors connected in series in the NMOS transistor group for receiving the clock signal, thereby reducing the leakage current, and further enabling a reduced minimum operating frequency.

[0079] Figure 13 shows a circuit 400 of the dynamic latch 100 according to further embodiments of the present disclosure. Compared with Figure 11, in Figure 13, the NMOS transistor group 414 includes two NMOS transistors 4141, 4142 connected in series. Compared with the dynamic latch 10 of Figure 1, Figure 13 is equivalent to implementing a channel- lengthened PMOS transistor for receiving a first clock signal and a channel- lengthened NMOS transistor for receiving a second clock signal by including multiple PMOS transistors connected in series in the PMOS transistor group for receiving the clock signal and including multiple NMOS transistors connected in series in the NMOS transistor group for receiving the clock signal, thereby reducing the leakage current, and in turn enabling a reduced minimum operating frequency.

[0080] Figure 14 shows a circuit 400 of the dynamic latch 100 according to further embodiments of the present disclosure. Compared with Figure 13, in Figure 14, the PMOS transistor group 411 includes three PMOS transistors 4111, 4112, 4113 connected in series, and the NMOS transistor group 414 includes three NMOS transistors 4141, 4142, 4143 connected in series. Compared with Figure 13, in Figure 14, the number of transistors connected in series in each clock transistor group is changed from two to three. As previously described, this enables further suppression of leakage and in turn enables a further reduced minimum operating frequency.

[0081] Figure 15 shows a circuit 400 of the dynamic latch 100 according to further embodiments of the present disclosure. Compared with Figure 13, in Figure 15, the PMOS transistor group 412 includes two PMOS transistors 4121, 4122 connected in series, and the NMOS transistor group 413 includes two NMOS transistors 4131, 4132 connected in series. Compared with Figure 13, Figure 15 is equivalent to implementing a channel- lengthened PMOS transistor for receiving a data signal and a channel- lengthened NMOS transistor for receiving a data signal by including multiple PMOS transistors connected in series in the PMOS transistor group for receiving the data signal and including multiple NMOS transistors connected in series in the NMOS transistor group for receiving the data signal, thereby reducing the leakage current, and in turn enabling a reduced minimum operating frequency.

[0082] Figure 16 shows a circuit 400 of the dynamic latch 100 according to further embodiments of the present disclosure. Compared with Figure 13, the application of the clock signals CLKP and CLKN is changed such that the PMOS transistor group 411 receives the clock signal CLKP and the NMOS transistor group 414 receives the clock signal CLKN, thereby implementing a low-level active dynamic latch.

[0083] As another non-limiting example, the control terminals of the first set of transistors and the control terminals of the third set of transistors can be commonly connected to the input terminal, the control terminals of the second set of transistors are configured to receive a first clock signal, and the control terminals of the fourth set of transistors are configured to receive a second clock signal. In such an embodiment, the second set of transistors and the fourth set of transistors act as a set of clock transistors, and the first set of transistors and the third set of transistors act as a set of data transistors. In some examples, at least one of the second set of transistors and the fourth set of transistors includes a plurality of transistors connected in series. Further, in some examples, at least one of the first set of transistors and the third set of transistors includes a plurality of transistors connected in series.

[0084] For example, referring to FIG. 17, there is shown a circuit 500 of the dynamic latch 100 according to some embodiments of the present disclosure. As shown in FIG. 17, the circuit 500 includes a latch circuit 510 (which acts as the latch cell 104 of the dynamic latch 100, specifically, an inverting latch cell) and an inverter 530 (which acts as the inverting drive cell 105 of the dynamic latch 100) connected in series in sequence between a data input terminal D and a data output terminal Q.

[0085] Similar to the inverter 330, the inverter 530 includes a PMOS transistor 531 and an NMOS transistor 532 connected in series in sequence between the power supply VDD and the ground VSS. The output terminal of the inverter 530 can directly provide the data output terminal Q of the circuit 500.

[0086] Similar to the latch circuit 310, the latch circuit 510 has an input terminal 5101 and an output terminal 5102. The input terminal 5101 of the latch circuit 510 can directly provide the data input terminal D of the circuit 500. The output terminal 5102 of the latch circuit 510 is connected to the input terminal of the inverter 530, between which a node A is formed that is floating in potential for part of the time.

[0087] As shown in FIG. 17, the latch circuit 510 includes a PMOS transistor set 511, a PMOS transistor set 512, an NMOS transistor set 513, and an NMOS transistor set 514 connected in series in sequence between the power supply VDD and the ground VSS. The PMOS transistor set 511 includes one PMOS transistor 5111, the PMOS transistor set 512 includes two PMOS transistors 5121, 5122 connected in series, the NMOS transistor set 513 includes two NMOS transistors 5131, 5132 connected in series, and the NMOS transistor set 514 includes one NMOS transistor 5141. Generally, the bulk of these transistors are not suspended, where the bulk of the PMOS transistors can be connected to the power supply, and the bulk of the NMOS transistors can be connected to the ground.

[0088] In the example of FIG. 17, the PMOS transistor group 512 is configured to receive a clock signal CLKN, and the NMOS transistor group 514 is configured to receive a clock signal CLKP that is inverted from the clock signal CLKN. Compared to the dynamic latch 10 of FIG. 1, FIG. 17 is equivalent to implementing a channel- lengthened PMOS transistor for receiving a clock signal by including a plurality of PMOS transistors connected in series in the PMOS transistor group for receiving the clock signal, thereby reducing the leakage current, which in turn enables a reduced minimum operating frequency.

[0089] As another non-limiting example, the control terminals of the second transistor group and the control terminals of the fourth transistor group can be commonly connected to an input terminal, the control terminals of the first transistor group are configured to receive a first clock signal, and the control terminals of the third transistor group are configured to receive a second clock signal. In such an example, the second transistor group and the fourth transistor group act as data transistor groups, and the first transistor group and the third transistor group act as clock transistor groups. In some examples, at least one of the first transistor group and the third transistor group includes a plurality of transistors connected in series. Further, in some examples, at least one of the second transistor group and the fourth transistor group includes a plurality of transistors connected in series.

[0090] For example, referring to FIG. 18, which illustrates a circuit 500’ of a dynamic latch 100 according to some embodiments of the present disclosure. Compared to the circuit 500 of FIG. 17, the circuit 500’ configures the PMOS transistor group 511 to receive a clock signal CLKN, configures the NMOS transistor group 513 to receive a clock signal CLKP that is inverted from the clock signal CLKN, and configures the PMOS transistor group 512 and the NMOS transistor group 514 to receive a data signal.

[0091] Compared to the circuit 300, the circuits 400, 500, 500’ configure different ones of the first to fourth transistor groups as clock transistor groups and data transistor groups, and are otherwise similar to the circuit 300, so the relevant aspects can be referred to the various embodiments of the circuit 300, which are not repeated here.

[0092] The present disclosure also provides, in another aspect, a dynamic D flip-flop that can effectively suppress dynamic leakage, thereby enabling normal operation at a lower operating frequency. This is advantageous in reducing power consumption, particularly when such dynamic D flip-flops are used in large quantities in a computing chip, which can significantly reduce the overall power consumption of the computing chip. The dynamic D flip-flop according to various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that an actual dynamic D flip-flop can also include other components, which are not discussed herein and not shown in the accompanying drawings in order to avoid obscuring the gist of the present disclosure. It should also be understood that the latch circuit included in the dynamic D flip-flop depicted in the subsequent drawings is merely exemplary and not limiting, and can be replaced by the latch circuit according to any embodiment of the present disclosure.

[0093] FIG. 19 shows a dynamic D flip-flop 600 according to some embodiments of the present disclosure. The dynamic D flip-flop 600 includes a data input terminal 601, a data output terminal 602, a clock control terminal 603, and a first latch unit 604, a second latch unit 605, and an inverting drive unit 606 connected in series between the data input terminal 601 and the data output terminal 602. The data input terminal 601 is configured to receive a data signal. The data output terminal 602 is configured to output the data signal. The clock control terminal 603 is configured to receive a clock signal. The first latch unit 604 is configured to latch or transmit the data signal from the data input terminal 601 under the control of the clock signal. The second latch unit 605 is configured to latch or transmit the data signal from the first latch unit 604 under the control of the clock signal. The inverting drive unit 606 is configured to invert and transmit the data signal from the second latch unit 605.

[0094] Compared with a static D flip-flop, the dynamic D flip-flop has a significantly simplified circuit structure due to the reduction of feedback circuits for maintaining the operating state, which reduces the chip area and power consumption. With these advantages, the dynamic D flip-flop can be used in large quantities in a computing chip. However, due to the presence of nodes with floating potentials (e.g., the node formed between the first latch unit 604 and the second latch unit 605, and the node formed between the second latch unit 605 and the inverting drive unit 606) in the dynamic D flip-flop for part of the time, the parasitic capacitance at the node needs to maintain the correct voltage state during the part of the time. In order to avoid the leakage of the device affecting the voltage of the node, the dynamic D flip-flop must operate at a relatively high frequency, thereby reducing the leakage time to prevent functional errors. This greatly limits the range of use of the chip. For example, in some states such as sleep or idle of a processor, the dynamic D flip-flop can operate at a relatively low frequency, at which time functional errors are likely to occur.

[0095] In some embodiments, the first latch unit 604 can comprise a latch circuit according to any embodiment of the present disclosure. The input of such a latch circuit can be provided directly with the data input 601 of the dynamic D flip-flop, for example. As described above, by employing a latch circuit of the present disclosure in the first latch unit 604, the leakage current can be effectively suppressed, thereby reducing the minimum operating frequency of the dynamic D flip-flop.

[0096] In some examples, the second latch unit 605 can comprise a tri-state gate. For example, referring to FIG. 20, there is shown a circuit 700 of a dynamic D flip-flop 600 according to some embodiments of the present disclosure. As shown in FIG. 20, the circuit 700 comprises a latch circuit 710 (which functions as the first latch unit 604 (specifically, the inverting latch unit) of the dynamic D flip-flop 600), a tri-state gate 720 (which functions as the second latch unit 605 (specifically, the inverting latch unit) of the dynamic D flip-flop 600), and an inverter 760 (which functions as the inverting drive unit 606 of the dynamic D flip-flop 600) connected in series in that order between the data input D and the data output Q. The node A formed between the latch circuit 710 and the tri-state gate 720, and the node B formed between the tri-state gate 720 and the inverter 760 are floating in potential at some time.

[0097] The latch circuit 710 includes PMOS transistors 7111, 7121, 7122 and NMOS transistors 7131, 7132, 7141, which, without limitation, take an example arrangement as shown in FIG. 7. The inverter 760 includes a PMOS transistor 761 and an NMOS transistor 762 connected in series between the power supply VDD and the ground VSS. The tri-state gate 720 includes a PMOS transistor 721, a PMOS transistor 722, an NMOS transistor 723 and an NMOS transistor 724 connected in series between the power supply VDD and the ground VSS. In particular, the NMOS transistors 7131, 7132 and the PMOS transistor 722 receive the clock signal CLKP, and the PMOS transistors 7121, 7122 and the NMOS transistor 723 receive the clock signal CLKN. In this way, the clock signals can be such that the tri-state gate 720 is turned on when the latch circuit 710 is turned off, and the tri-state gate 720 is turned off when the latch circuit 710 is turned on. As a result, when CLKP is high and CLKN is low, the latch circuit 710 is turned on and the tri-state gate 720 is turned off, and data from the data input D is output to the node A (e.g., overwriting the data at the node A) via the latch circuit 710, but cannot continue through the tri-state gate 720. When CLKP goes low and CLKN goes high, the latch circuit 710 is turned off and the tri-state gate 720 is turned on, and data from the data input D cannot pass through the latch circuit 710, and the data at the node A is maintained, and data from the node A is output to the node B (e.g., overwriting the data at the node B) via the tri-state gate 720, and further output to the data output Q via the inverter 760. When CLKP goes high again and CLKN goes low again, the latch circuit 710 is turned on and the tri-state gate 720 is turned off, and data from the data input D is output to the node A (e.g., overwriting the data at the node A) via the latch circuit 710, but cannot continue through the tri-state gate 720, and the data at the node B is maintained. Similarly, the clock signals CLKP and CLKN can be applied in reverse order, and the active levels can be changed accordingly. In addition, the arrangement of the tri-state gate 720 is not limited to this, and can be replaced by the gates of the PMOS transistor 721 and the NMOS transistor 724 receiving the corresponding clock signals, and the gates of the PMOS transistor 722 and the NMOS transistor 723 being commonly connected to receive the data signal. The tri-state gates mentioned elsewhere in this document are similar, and will not be repeated here.

[0098] In some examples, the second latch unit 605 can include a latch circuit according to any embodiment of the present disclosure. For example, referring to FIG. 21, which is compared with FIG. 20, the tri-state gate 720 is replaced by a latch circuit 730, which functions as the second latch unit 605 (specifically, an inverting latch unit) of the dynamic D flip-flop 600. The latch circuit 730 includes PMOS transistors 7311, 7312, 7321 and NMOS transistors 7331, 7341, 7342, which take, without limitation, the example arrangement as shown in FIG. 13. As such, the latch circuit 710 can mitigate the effect of dynamic leakage at node A, and the latch circuit 730 can mitigate the effect of dynamic leakage at node B, such that the lowest operational efficiency of the dynamic D flip-flop is further reduced. The timing control of FIG. 21 is similar to that of FIG. 20, which is not elaborated here.

[0099] In some examples, the second latch unit 605 can include an inverter and a transmission gate connected in series between the first latch unit 604 and the inverting drive unit 606. For example, referring to FIG. 22, which is compared with FIG. 20, the tri-state gate 720 is replaced by a combination of an inverter 740 and a transmission gate 750, which functions as the second latch unit 605 (specifically, an inverting latch unit) of the dynamic D flip-flop 600. The inverter 740 includes a PMOS transistor 741 and an NMOS transistor 742 connected in series between the power supply VDD and the ground VSS. The transmission gate 750 includes an NMOS transistor 751 and a PMOS transistor 752 connected in parallel between the inverter 740 and an inverter 760. The inverter 740 can provide driving capability for the transmission gate 750. The timing control of FIG. 22 is similar to that of FIG. 20, which is not elaborated here.

[0100] In other embodiments, the second latch unit 605 can include a latch circuit according to any embodiment of the present disclosure. In such embodiments, the first latch unit 604 may, for example, include one of: a transmission gate; a tri-state gate; an inverter and a transmission gate connected in series between the data input 601 and the second latch unit 605.

[0101] For example, Figure 23 shows a circuit 800 of dynamic D flip-flop 600 according to some embodiments of the present disclosure. As shown in Figure 23, circuit 800 includes a tri-state gate 810 (which functions as first latching unit 604 (specifically, an inverting latching unit) of dynamic D flip-flop 600), a latch circuit 850 (which functions as second latching unit 605 (specifically, an inverting latching unit) of dynamic D flip-flop 600), and an inverter 860 (which functions as inverting drive unit 606 of dynamic D flip-flop 600) connected in series between data input D and data output Q. Tri-state gate 810 includes PMOS transistor 811, PMOS transistor 812, NMOS transistor 813, and NMOS transistor 814 connected in series between power supply VDD and ground VSS. Latch circuit 850 includes PMOS transistors 8511, 8521, 8522 and NMOS transistors 8531, 8532, 8541, which take, without limitation, the example arrangement as shown in Figure 7. Inverter 860 includes PMOS transistor 861 and NMOS transistor 862 connected in series between power supply VDD and ground VSS. The timing control of Figure 23 is similar to that of Figure 20, which is not elaborated here.

[0102] Figure 24, compared with Figure 23, the tri-state gate 810 is replaced by a combination of inverter 820 and transmission gate 830, which functions as first latching unit 604 (specifically, an inverting latching unit) of dynamic D flip-flop 600. Inverter 820 includes PMOS transistor 821 and NMOS transistor 822 connected in series between power supply VDD and ground VSS. Transmission gate 830 includes NMOS transistor 831 and PMOS transistor 832 connected in parallel between inverter 820 and latch circuit 850. The timing control of Figure 24 is similar to that of Figure 20, which is not elaborated here.

[0103] Figure 25, compared with Figure 24, the combination of inverter 820 and transmission gate 830 is replaced by transmission gate 840, which functions as first latching unit 604 (specifically, a non-inverting latching unit) of dynamic D flip-flop 600. Transmission gate 840 includes NMOS transistor 841 and PMOS transistor 842 connected in parallel between data input D and latch circuit 850. The timing control of Figure 25 is similar to that of Figure 20, which is not elaborated here.

[0104] The present disclosure provides, in another aspect, a register. As shown in FIG. 26, the register 900 includes a plurality of data inputs D[n:0] configured to receive data signals, a plurality of data outputs Q[n:0] configured to output data signals, and a clock control terminal CK configured to receive a clock signal. The register 900 further includes a clock buffer 902 configured to buffer the clock signal received by the clock control terminal CK and provide the clock signal (CLKP, CLKN) to a plurality of register cells 901. The clock buffer 902 is similar to the aforementioned clock buffer 200, which will not be repeated here. The register 900 further includes a plurality of register cells 901 connected in parallel between the plurality of data inputs D[n:0] and the plurality of data outputs Q[n:0] and configured to write and / or read data under the control of the clock signal. In particular, the register cells in the plurality of register cells 901 can be the dynamic latch according to any embodiment of the present disclosure or the dynamic D flip-flop according to any embodiment of the present disclosure.

[0105] Generally, a latch or a D flip-flop needs a clock buffer to generate mutually opposite clock signals for timing control. If a separate clock buffer is configured for each latch or D flip-flop, the clock buffer will consume considerable chip area and power consumption in applications requiring the use of multiple latches or D flip-flops. Therefore, the register according to the embodiments of the present disclosure uses one clock buffer to drive multiple dynamic latches or dynamic D flip-flops at the same time, which can effectively reduce the area and power consumption.

[0106] The present disclosure provides, in another aspect, a processor, which can include the dynamic latch according to any embodiment of the present disclosure or the dynamic D flip-flop according to any embodiment of the present disclosure or the register according to any embodiment of the present disclosure.

[0107] The present disclosure provides, in another aspect, a computing device, which can include the processor according to any embodiment of the present disclosure. Such a computing device can include, for example but not limited to, a computing chip or an electronic device containing such a computing chip used in the fields of exploration, climate change, transportation, artificial intelligence, etc.

[0108] The words "left," "right," "front," "back," "top," "bottom," "over," "under," "upper," "lower," and the like in the description and the claims, if any, are used for description and not necessarily for limiting relative positions. It will be appreciated with understanding that the words so used are interchangeable with respect to the illustrated embodiments and can be used in other orientations. For example, if the device in the drawings were turned upside down, then the depicted feature which is higher than other features would then be lower, and this is applicable regardless of how the described embodiment of this disclosure is designed, claimed, or deployed. The device can also be oriented in other ways (rotated 90 degrees or in other orientations), and the relative spatial relationships would be interpreted accordingly.

[0109] In the description and the claims, when an element is referred to as being "on," "attached," "connected" or "coupled" to another element, it can be directly on, attached, connected, or coupled to the other element or one or more intervening elements can be present. In contrast, when an element is referred to as being "directly on," "directly attached," "directly connected," "directly coupled," or "directly in contact" to another element, there are no intervening elements present. In the description and the claims, a feature can be arranged "adjacent" to another feature, which can mean that the feature has a portion that overlaps the adjacent feature or is positioned above or below the adjacent feature.

[0110] As used herein, the word "exemplary" means "serving as an example, instance, or illustration," and not "preferred" or "advantageous over other implementations." Furthermore, the disclosure is not to be limited to any particular theory of operation by any of the expressed or implied theories presented in the Background, Summary, or Detailed Description of the Invention.

[0111] As used herein, the word "substantially" means including any minor variations as a result of design, manufacturing, or other factors that would not materially affect the character, use, or operation of the device or element. The word "substantially" also allows for differences that are within normal manufacturing or construction tolerances, environmental influences, and / or other factors that can affect the actual implementation of the device or element.

[0112] In addition, the terms "first", "second", and the like, herein can be used merely for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the descriptive terms "first", "second", etc., are to be interpreted, by those skilled in the art, as a structural or functional pertinence but not by sequence or order.

[0113] It is also to be understood that the terminology "comprising" or "comprises" when used in this disclosure is open-ended and includes one or more elements, integers, steps, operations, units, and / or components but does not exclude others. In the disclosure, the term "providing" is used in a broad sense to encompass all means of obtaining an object, and thus "providing an object" includes, but is not limited to, "purchasing", "preparing / manufacturing", "arranging / setting", "installing / fitting", and / or "ordering" the object, etc.

[0114] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0115] Identical or similar parts between various embodiments of the disclosure can be mutually referred to each other, and each embodiment focuses on the difference from other embodiments. In the description of the disclosure, the description of the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", "exemplary" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the disclosure. In the disclosure, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the skilled person in the art can combine and combine the different embodiments or examples described in the disclosure and the features of the different embodiments or examples without contradiction.

[0116] Additionally, as used in the present disclosure, the words "herein," "above," "below," "nowhere," "below," "above," and words of similar meaning should not be interpreted as limiting the present disclosure with regard to any particular part of the present disclosure. Moreover, no condition is implied or required for the performance of any of the elements or components of the present disclosure unless expressly recited in a claim as being claimed. Additionally, the use herein of conditional language, such as, among others, "can," "could," "might," "may," "e.g.," "for example," "such as," and the like, means that certain embodiments include, while other embodiments do not include, certain features, elements, and / or states. Therefore, such conditional language is not generally intended to imply that one or more embodiments require a feature, element, and / or state, or that a feature, element, and / or state is included in or excluded from any particular embodiment. Additionally, unless otherwise stated, no condition is implied or required for the performance of any of the elements or components of the present disclosure unless expressly recited in a claim as being claimed.

[0117] Those skilled in the art will realize that the boundaries between the above described operations merely illustrative. The multiple operations can be combined into a single operation, a single operation can be distributed in additional operations and the operations can be performed at least in part concurrently with one another. Additionally, alternative embodiments can include multiple instances of a particular operation and the order of operations can be altered in other various embodiments. However, other modifications, variations, and alternatives are also possible. The aspects and elements of all such embodiments can be combined in any manner and / or combination with one another without departing from the scope of the present disclosure. It is intended that the description and examples contained herein be considered in a descriptive sense, rather than a limiting sense.

[0118] While certain specific embodiments of the present disclosure have been described in detail herein, the skilled person will appreciate that the above examples are merely illustrative and are not intended to limit the scope of the present disclosure. Embodiments disclosed herein can be combined in any manner without departing from the spirit and scope of the present disclosure. The skilled person will also appreciate that various modifications can be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A latch circuit comprising: an input terminal; an output terminal; and a first transistor group of a first conductivity type, a second transistor group of the first conductivity type, a third transistor group of a second conductivity type different from the first conductivity type, and a fourth transistor group of the second conductivity type, connected in series between a power supply and a ground, a node between the second transistor group and the third transistor group being connected to the output terminal, a control terminal of one of the first transistor group and the second transistor group and a control terminal of one of the third transistor group and the fourth transistor group being commonly connected to the input terminal, a control terminal of the other of the first transistor group and the second transistor group being configured to receive a first clock signal, and a control terminal of the other of the third transistor group and the fourth transistor group being configured to receive a second clock signal inverted from the first clock signal, wherein the first conductivity type is configured such that a transistor turns on when a control terminal thereof is at a low level, and the second conductivity type is configured such that a transistor turns on when a control terminal thereof is at a high level, and wherein at least one of the first transistor group to the fourth transistor group includes a plurality of transistors connected in series. a control terminal of the first transistor group and a control terminal of the fourth transistor group are commonly connected to the input terminal, a control terminal of the second transistor group is configured to receive the first clock signal, and a control terminal of the third transistor group is configured to receive the second clock signal.

2. The latch circuit of claim 1, wherein, at least one of the second transistor group and the third transistor group includes a plurality of transistors connected in series.

3. The latch circuit of claim 2, wherein, at least one of the first transistor group and the fourth transistor group includes a plurality of transistors connected in series.

4. The latch circuit of claim 3, wherein, a control terminal of the second transistor group and a control terminal of the third transistor group are commonly connected to the input terminal, a control terminal of the first transistor group is configured to receive the first clock signal, and a control terminal of the fourth transistor group is configured to receive the second clock signal.

5. The latch circuit of claim 1, wherein, at least one of the first transistor group and the fourth transistor group includes a plurality of transistors connected in series.

6. The latch circuit of claim 5, wherein, at least one of the second transistor group and the third transistor group includes a plurality of transistors connected in series.

7. The latch circuit of claim 6, wherein, a number of transistors in each of the at least one of the first transistor group to the fourth transistor group is two.

8. The latch circuit of claim 1, wherein, 9. The latch circuit according to claim 1, wherein a total number of transistors of the first transistor group and the second transistor group is greater than a total number of transistors of the third transistor group and the fourth transistor group, or a number of transistors of the other of the first transistor group and the second transistor group is greater than a number of transistors of the other of the third transistor group and the fourth transistor group.

10. The latch circuit according to claim 1, wherein ​ a total transistor quantity of the first transistor group and the second transistor group is less than a total transistor quantity of the third transistor group and the fourth transistor group, or a transistor quantity of the other one of the first transistor group and the second transistor group is less than a transistor quantity of the other one of the third transistor group and the fourth transistor group.

11. The latch circuit of claim 1, wherein a total transistor quantity of the first transistor group and the second transistor group is equal to a total transistor quantity of the third transistor group and the fourth transistor group, or a transistor quantity of the other one of the first transistor group and the second transistor group is equal to a transistor quantity of the other one of the third transistor group and the fourth transistor group.

12. The latch circuit of any one of claims 1 to 11, wherein, Transistors in the latch circuit are metal-oxide-semiconductor (MOS) transistors, the first conductivity type is P-type, and the second conductivity type is N-type.

13. A dynamic latch, the dynamic latch comprising: a data input configured to receive a data signal; a data output configured to output a data signal; a clock control configured to receive a clock signal; and a latch cell and an inverting driver cell connected in series between the data input and the data output, the latch cell configured to latch or pass a data signal from the data input under control of the clock signal, the inverting driver cell configured to invert and pass a data signal from the latch cell, wherein the latch cell comprises the latch circuit of any one of claims 1-12.

14. A dynamic D flip-flop, the dynamic D flip-flop comprising: a data input configured to receive a data signal; a data output configured to output a data signal; a clock control configured to receive a clock signal; and a first latch cell, a second latch cell, and an inverting driver cell connected in series between the data input and the data output, the first latch cell configured to latch or pass a data signal from the data input under control of the clock signal, the second latch cell configured to latch or pass a data signal from the first latch cell under control of the clock signal, the inverting driver cell configured to invert and pass a data signal from the second latch cell, wherein the first latch cell comprises the latch circuit of any one of claims 1-12. the second latch cell comprises one of: a tri-state gate; or 15. The dynamic D flip-flop of claim 14, wherein, the latch circuit of any one of claims 1-11; or an inverter and a pass gate connected in series between the first latch cell and the inverting driver cell.

16. A dynamic D flip-flop, the dynamic D flip-flop comprising: a data input configured to receive a data signal; a data output configured to output a data signal; a clock control configured to receive a clock signal; and a first latch cell, a second latch cell, and an inverting driver cell connected in series between the data input and the data output, the first latch cell configured to latch or pass a data signal from the data input under control of the clock signal, the second latch cell configured to latch or pass a data signal from the first latch cell under control of the clock signal, the inverting driver cell configured to invert and pass a data signal from the second latch cell, wherein the first latch cell comprises the latch circuit of any one of claims 1-12. ​ a first latch unit, a second latch unit and an inverting driving unit connected in series between the data input terminal and the data output terminal, the first latch unit being configured to latch or transmit a data signal from the data input terminal under control of a clock signal, the second latch unit being configured to latch or transmit a data signal from the first latch unit under control of a clock signal, the inverting driving unit being configured to invert and transmit a data signal from the second latch unit, wherein the second latch unit comprises the latch circuit according to any one of claims 1 to 12.

17. The dynamic D flip-flop of claim 16, wherein, The first latch unit comprises one of: a transmission gate; or a tri-state gate; or a transmission gate and an inverter connected in series between the data input terminal and the second latch unit.

18. A register, the register comprising: a plurality of data input terminals configured to receive data signals; a plurality of data output terminals configured to output data signals; a clock control terminal configured to receive a clock signal; a clock buffer configured to buffer a clock signal received by the clock control terminal and provide a clock signal to a plurality of register units; and the plurality of register units connected in parallel between the plurality of data input terminals and the plurality of data output terminals and configured to perform at least one of writing data and reading data under control of a clock signal, wherein a register unit of the plurality of register units is a dynamic latch according to claim 13 or a dynamic D flip-flop according to any one of claims 14 to 17.

19. A processor comprising a dynamic latch according to claim 13 or a dynamic D flip-flop according to any one of claims 14 to 17 or a register according to claim 18.

20. A computing device comprising a processor according to claim 19.

21. A computer program product comprising a computer program according to claim 20.

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