A chip packaging method and packaging structure

Abstract

The present invention discloses a chip packaging method and packaging structure. The technical solution of the present invention arranges that the chip to be packaged is located in a plastic packaging layer, the front side of the chip to be packaged is flush with the first surface of the plastic packaging layer, and the plastic packaging material used to form the plastic packaging layer has good plasticity before curing, and can form a first surface and a second surface with good flatness, thereby ensuring the reliability of the packaging structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor process technology, and more particularly to a chip packaging structure and a packaging method. Background Art

[0002] With the continuous development of science and technology, more and more electronic devices are widely used in people's daily life and work, which brings great convenience to people's daily life and work, and becomes an indispensable tool for people. Electronic devices realize various functions through various chips. In order to ensure the service life and safe and stable operation of the chip, the chip needs to be packaged through the packaging process to form a packaging structure and package the chip for protection.

[0003] When the chip is packaged in the prior art, the flatness of the package structure formed is poor, resulting in poor reliability of the package structure after the chip is packaged. Summary of the invention

[0004] In order to solve the above problems, the technical solution of the present invention provides a chip packaging method and packaging structure, which can make the formed packaging structure have better flatness and ensure the reliability of the packaging structure.

[0005] In order to achieve the above object, the present invention provides the following technical solutions

[0006] A chip packaging method, the packaging method comprising:

[0007] Providing at least one chip to be packaged, wherein the chip to be packaged has a front side and a back side opposite to each other, and the front side has a sensing unit and a pad connected to the sensing unit;

[0008] Forming a plastic encapsulation layer covering the back side of the chip to be encapsulated, wherein the plastic encapsulation layer has a first surface and a second surface opposite to each other, the chip to be encapsulated is located in the plastic encapsulation layer, and its front side is flush with the first surface;

[0009] An interconnection structure corresponding to the chip to be packaged is formed on the second surface of the plastic packaging layer; and the bonding pad is connected to an external circuit via the interconnection structure.

[0010] Preferably, in the above packaging method, a plurality of the chips to be packaged are provided, and the front surfaces of all the chips to be packaged are located in the same plane and are flush with the first surface; each chip to be packaged corresponds to one interconnection structure;

[0011] The packaging method further comprises:

[0012] The plastic encapsulation layer is divided into a plurality of packaging structures through a cutting process, and the packaging structure includes at least one chip to be packaged and its corresponding interconnection structure.

[0013] Preferably, in the above packaging method, the step of forming a plastic packaging layer covering the back side of the chip to be packaged comprises:

[0014] Providing a carrier plate, the carrier plate having a temporary bonding surface for carrying the chip to be packaged;

[0015] Laminating the front surface of the chip to be packaged with the temporary bonding surface of the carrier plate;

[0016] The plastic encapsulation layer is formed, and the plastic encapsulation layer covers the chip to be packaged and the temporary bonding surface of the carrier board.

[0017] Preferably, in the above packaging method, the temporary bonding surface of the carrier plate has a plurality of mounting grooves; one mounting groove is used to place one chip to be packaged; there is a gap between two adjacent mounting grooves; the depths of the mounting grooves are the same and less than the thickness of the chip to be packaged;

[0018] The step of bonding the front side of the chip to be packaged to the temporary bonding surface of the carrier plate comprises: placing one chip to be packaged in each mounting groove, with the front side of the chip to be packaged being arranged opposite to the bottom of the mounting groove.

[0019] Preferably, in the above packaging method, forming the plastic encapsulation layer comprises:

[0020] forming a first plastic encapsulation layer, wherein the first plastic encapsulation layer covers the chip to be encapsulated and the temporary bonding surface of the carrier board; the surface of the first plastic encapsulation layer facing away from the chip to be encapsulated is the second surface;

[0021] removing the carrying plate;

[0022] A second plastic encapsulation layer is formed on a side surface of the first plastic encapsulation layer that exposes the front side of the chip to be encapsulated; a side surface of the second plastic encapsulation layer that is away from the first plastic encapsulation layer is the first surface.

[0023] Preferably, in the above packaging method, forming a second plastic packaging layer on a side surface of the first plastic packaging layer that exposes the front side of the chip to be packaged comprises:

[0024] forming a protective layer on the front side of the chip to be packaged;

[0025] forming the second plastic encapsulation layer, wherein the thickness of the second plastic encapsulation layer is greater than the thickness of the chip to be encapsulated exposed from the first plastic encapsulation layer;

[0026] After removing the protective layer, the surface of the second plastic encapsulation layer on one side facing away from the first plastic encapsulation layer is thinned so that the surface is flush with the front side of the chip to be packaged.

[0027] Preferably, in the above packaging method, the temporary bonding surface is a plane;

[0028] The step of bonding the front surface of the chip to be packaged to the temporary bonding surface of the carrier board includes: bonding and fixing the chip to be packaged to the temporary bonding surface using a temporary adhesive film with uniform thickness.

[0029] Preferably, in the above packaging method, after forming the plastic encapsulation layer and before forming the interconnection structure, the carrier board is removed;

[0030] Alternatively, after forming the interconnection structure and before performing the cutting process, the carrier board is removed.

[0031] Preferably, in the above packaging method, forming an interconnection structure corresponding to the chip to be packaged on the second surface of the plastic packaging layer includes:

[0032] A patterned metal circuit layer is formed on the second surface of the plastic packaging layer, wherein the metal circuit layer includes a plurality of interconnect structures corresponding to the chips to be packaged one by one;

[0033] A welding protrusion is formed on the surface of the interconnection structure, and the welding protrusion is used to connect with the external circuit.

[0034] Preferably, in the above packaging method, the step of forming a patterned metal circuit layer on the second surface of the plastic packaging layer comprises:

[0035] forming a metal circuit layer covering the second surface of the plastic encapsulation layer;

[0036] Etching the metal circuit layer to pattern the metal circuit layer to form a plurality of interconnect structures corresponding to the chips to be packaged;

[0037] Preferably, in the above packaging method, the step of forming a patterned metal circuit layer on the second surface of the plastic packaging layer comprises:

[0038] A mask plate with a preset graphic structure is used to form the patterned metal circuit layer through an evaporation process.

[0039] Preferably, in the above packaging method, before the cutting process is performed, a through hole is formed penetrating the first surface and the second surface of the plastic packaging layer;

[0040] Connecting the bonding pad to one end of a metal wire, and connecting the other end of the metal wire to the interconnect structure through the through hole;

[0041] Wherein, in a first direction, the through hole does not overlap with the chip to be packaged; and in the first direction, the through hole is perpendicular to the first surface and the second surface of the plastic packaging layer.

[0042] Preferably, in the above packaging method, the back side of the chip to be packaged has a pad connected to the pad;

[0043] Before forming the metal circuit layer, a through hole is formed on the second surface of the plastic packaging layer; in a first direction, the through hole is arranged opposite to the pad to expose the pad;

[0044] Wherein, the interconnection structure is connected to the pad through the through hole; and the first direction is perpendicular to the first surface and the second surface of the plastic packaging layer.

[0045] Preferably, in the above packaging method, before forming the metal circuit layer, a first through hole penetrating the plastic packaging layer is formed;

[0046] A second through hole is formed in the first through hole, penetrating the front and back sides of the chip to be packaged, wherein the second through hole is arranged opposite to the pad in the first direction to expose the pad;

[0047] Wherein, the metal circuit layer is connected to the pad through the first through hole and the through hole; the first direction is perpendicular to the first surface and the second surface of the plastic packaging layer.

[0048] Preferably, in the above packaging method, before the cutting process is performed, the method further comprises:

[0049] An insulating protection layer is formed to cover the metal circuit layer, and a surface of the insulating protection layer has an opening for arranging the welding protrusion.

[0050] Preferably, in the above packaging method, the chip to be packaged is an image sensor chip;

[0051] After completing the cutting process, the packaging method further includes:

[0052] Using the plastic sealing layer of the packaging structure as a substrate, fixing a bracket on the periphery of the first surface of the plastic sealing layer;

[0053] A transparent cover plate is arranged on the bracket.

[0054] The present invention also provides a chip packaging structure, the packaging structure comprising: a plastic packaging layer, the plastic packaging layer having a first surface and a second surface opposite to each other;

[0055] At least one chip to be packaged is located in the plastic packaging layer, the chip to be packaged has a front side and a back side opposite to each other, and the front side has a sensing unit and a solder pad connected to the sensing unit;

[0056] An interconnection structure located on the second surface of the plastic encapsulation layer and corresponding to the chip to be packaged, wherein the pad is connected to an external circuit via the interconnection structure;

[0057] The plastic encapsulation layer has a first surface and a second surface that are opposite to each other, the chip to be packaged is located in the plastic encapsulation layer, and its front side is flush with the first surface.

[0058] Preferably, in the above packaging structure, the plastic packaging layer contains a plurality of the chips to be packaged; the front faces of all the chips to be packaged are located in the same plane and are flush with the first surface; and each chip to be packaged corresponds to one interconnection structure.

[0059] Preferably, in the above packaging structure, the plastic sealing layer includes: a first plastic sealing layer and a second plastic sealing layer;

[0060] The first plastic encapsulation layer has a plurality of grooves corresponding to the chips to be packaged one by one, the depth of the grooves is less than the thickness of the chips to be packaged, and the back side of the chips to be packaged is arranged opposite to the bottom of the grooves; the surface of the first plastic encapsulation layer away from the chips to be packaged is the second surface;

[0061] The second plastic encapsulation layer covers a surface of the first plastic encapsulation layer facing the chip to be packaged, and a surface of the second plastic encapsulation layer facing away from the first plastic encapsulation layer is the first surface.

[0062] Preferably, in the above packaging structure, the interconnection structure is located in the same patterned metal circuit layer;

[0063] The interconnection structure surface has a welding protrusion, and the welding protrusion is used to connect with the external circuit.

[0064] Preferably, in the above packaging structure, the plastic packaging layer has a through hole penetrating the first surface and the second surface;

[0065] One end of the bonding pad is connected to one end of the metal wire, and the other end of the metal wire is connected to the interconnection structure through the through hole;

[0066] Wherein, in a first direction, the through hole does not overlap with the chip to be packaged; and in the first direction, the through hole is perpendicular to the first surface and the second surface of the plastic packaging layer.

[0067] Preferably, in the above packaging structure, the back side of the chip to be packaged has a pad connected to the pad;

[0068] The second surface of the plastic sealing layer has a through hole; in the first direction, the through hole is arranged opposite to the pad to expose the pad;

[0069] Wherein, the interconnection structure is connected to the pad through the through hole; and the first direction is perpendicular to the first surface and the second surface of the plastic packaging layer.

[0070] Preferably, in the above packaging structure, the plastic packaging layer has a first through hole;

[0071] The back side of the chip to be packaged has a second through hole corresponding to the first through hole one by one, and in the first direction, the second through hole is arranged opposite to the welding pad to expose the welding pad;

[0072] Wherein, the metal circuit layer is connected to the pad through the through hole; and the first direction is perpendicular to the first surface and the second surface of the plastic packaging layer.

[0073] Preferably, in the above packaging structure, the surface of the interconnection structure further has an insulating protective layer, and the surface of the insulating protective layer has an opening for arranging the welding protrusion.

[0074] Preferably, in the above packaging structure, the chip to be packaged is an image sensor chip.

[0075] Preferably, in the above packaging structure, a bracket is further provided on the first surface of the plastic packaging layer;

[0076] A transparent cover plate is installed on the bracket.

[0077] From the above description, it can be seen that in a chip packaging method and packaging structure provided by the technical solution of the present invention, the chip to be packaged is located in the plastic packaging layer, the front side of the chip to be packaged is flush with the first surface of the plastic packaging layer, and the plastic packaging material used to form the plastic packaging layer has good plasticity before curing, and can form a first surface and a second surface with good flatness, thereby ensuring the reliability of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0079] Figure 1 The present invention is a structural schematic diagram of a multi-chip packaging structure;

[0080] Figure 2a-Figure 5cA schematic diagram of a chip packaging method provided by an embodiment of the present invention;

[0081] Figure 6-Figure 13 A schematic diagram of a process for forming a plastic sealing layer provided by an embodiment of the present invention;

[0082] Figure 14-15 A schematic flow chart of another method for forming a plastic encapsulation layer provided in an embodiment of the present invention;

[0083] Figure 16-Figure 17 A schematic flow chart of another chip packaging method provided by an embodiment of the present invention;

[0084] Figure 18-19 A schematic flow chart of another chip packaging method provided by an embodiment of the present invention;

[0085] Fig. 20 A schematic diagram of a packaging structure provided by an embodiment of the present invention;

[0086] Fig.21 A schematic diagram of another packaging structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0087] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0088] Generally, the packaging structure formed by packaging the chip is as follows Figure 1 As shown, Figure 1 The schematic diagram of the structure of a multi-chip packaging structure is shown in FIG. 1 . In the chip packaging structure, the chip 11 is fixed by bonding with the circuit board 13 through the adhesive layer 12. The surface of the circuit board 13 facing away from the chip 11 has a metal circuit and a welding protrusion 14 connected to the metal circuit for connecting with an external circuit. The chip 11 is connected to the metal circuit through a wire bonding process. The surface of the circuit board 13 on one side where the chip 11 is provided is provided with a bracket 15 surrounding the chip 11, and a transparent cover plate 16 is provided on the bracket 15. When the chip 11 is an image sensor chip, the transparent cover plate 16 is a lens element.

[0089] Figure 1In the illustrated embodiment, the circuit board 13 is used as the carrier board of the chip 11, and the chip 11 is bonded and fixed by the adhesive layer 12, and the flatness of the chip packaging structure cannot be guaranteed. Moreover, when multiple chips 11 are packaged as one, the high flatness of each chip 11 cannot be guaranteed. When the bracket 15 is provided, since the bracket 15 needs to be connected to the circuit board 13 separately through the adhesive layer, the height position of the bracket 15 relative to the chip 11 cannot be accurately controlled. For the image sensor chip, the focal length of the lens element cannot be accurately controlled. The above problems will lead to poor reliability of the formed packaging structure.

[0090] In order to solve the above problems, the embodiments of the present invention provide a chip packaging structure and packaging method, wherein the chip is packaged through a plastic sealing layer, and the plastic sealing material has good plasticity before curing, so that the formed packaging structure has good flatness, thereby ensuring the reliability of the packaging structure. At the same time, the plastic sealing layer formed after the plastic sealing material is cured has good mechanical strength and can be reused as a carrier substrate for carrying supporting components, such as for carrying a bracket, and installing components such as a cover plate through the bracket. When the supporting component is set through the plastic sealing layer, since the plastic sealing layer has good flatness, the height of the supporting component relative to the chip can be accurately controlled, thereby effectively ensuring the reliability of the plastic sealing structure.

[0091] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0092] An embodiment of the present invention provides a chip packaging method, the packaging method comprising:

[0093] Step S1: providing at least one chip to be packaged.

[0094] The chip to be packaged has a front side and a back side opposite to each other, and the front side has a sensing unit and a bonding pad connected to the sensing unit.

[0095] Step S2: forming a plastic packaging layer covering the back side of the chip to be packaged.

[0096] The plastic encapsulation layer has a first surface and a second surface that are opposite to each other. The chip to be packaged is located in the plastic encapsulation layer, and its front side is flush with the first surface.

[0097] Step S3: forming an interconnection structure corresponding to the chip to be packaged on the second surface of the plastic packaging layer; the bonding pad is connected to an external circuit via the interconnection structure.

[0098] The encapsulation method described in the embodiment of the present invention directly encapsulates and protects the chip through the plastic encapsulation layer, and the plastic encapsulation layer has a first surface and a second plane relative to each other. The first surface and the second surface are both planes and parallel. The front side of the chip to be encapsulated is flush with the first surface.

[0099] The plastic encapsulation layer can encapsulate and protect the chip to be encapsulated. Moreover, the interconnection structure is directly arranged on the surface of the plastic encapsulation layer and connected to the pad. At this time, the plastic encapsulation layer is reused as a circuit board to facilitate the connection between the chip to be encapsulated and the external circuit. In this way, compared with the conventional method of fixing the chip on the circuit board through the glue layer, the plastic encapsulation layer has the functions of both the circuit board and the glue layer, which greatly simplifies the packaging structure. In addition, the plastic encapsulation layer has a large mechanical strength, and a large mechanical strength can be achieved through a thin thickness, which greatly reduces the thickness of the packaging structure.

[0100] At the same time, the chip is encapsulated by the plastic encapsulation layer, and the good plasticity of the plastic encapsulation material before curing is utilized to make the formed packaging structure have good flatness, thereby ensuring the reliability of the packaging structure. At the same time, the plastic encapsulation layer formed after the plastic encapsulation material is cured has good mechanical strength and can be reused as a carrier substrate for carrying supporting components, such as for carrying a bracket, and installing components such as a cover plate through the bracket. When the supporting component is set through the plastic encapsulation layer, since the plastic encapsulation layer has good flatness, the height of the supporting component relative to the chip can be accurately controlled, thereby effectively ensuring the reliability of the plastic encapsulation structure.

[0101] When multiple chips are packaged at the same time, multiple chips to be packaged are provided, and the front faces of all the chips to be packaged are located in the same plane and are flush with the first surface; each chip to be packaged corresponds to one interconnection structure. At this time, the packaging method further includes: dividing the plastic packaging layer into multiple packaging structures through a cutting process, and the packaging structure includes at least one chip to be packaged and its corresponding interconnection structure.

[0102] When multiple chips are packaged at the same time, the packaging method is as shown in Figure 2- Figure 5a shown.

[0103] Refer to Figure 2- Figure 5c , Figure 2a-Figure 5c A schematic flow chart of a chip packaging method provided in an embodiment of the present invention, the packaging method comprising:

[0104] Step S11: providing a plurality of chips to be packaged.

[0105] The structure of the chip to be packaged is as follows Figure 2a and Figure 2b As shown, Figure 2a is a cross-sectional view of the chip to be packaged, Figure 2bIt is a top view of the front side of the chip to be packaged. The chip 20 to be packaged has a front side 201 and a back side 202 opposite to each other. The front side 201 has a sensing unit 203 and a bonding pad 204 connected to the sensing unit 203 .

[0106] exist Figure 2a and Figure 2b In the illustrated embodiment, the plurality of pads 204 may be divided into two columns, and the sensing unit 203 is located between the two columns of pads 204. In other embodiments, the pads 204 may be evenly arranged around the sensing unit 203, or the plurality of pads 204 may be arranged on the same side of the sensing unit 203.

[0107] In the embodiment of the present invention, there is no limitation on the number of the chips 20 to be packaged, and the number of the chips 20 to be packaged can be specifically set according to the design parameters of the packaging structure. The chips 20 to be packaged are arranged in an array.

[0108] Step S12: Figure 3 As shown, a plastic encapsulation layer 21 is formed to cover the back side of the chip 20 to be packaged.

[0109] The front faces of all the chips 20 to be packaged are located in the same plane; the plastic encapsulation layer 21 has a first surface 211 and a second surface 212 opposite to each other, the chips 20 to be packaged are located in the plastic encapsulation layer 21, and the front faces 201 thereof are flush with the first surface 211. There are gaps between adjacent chips 20 to be packaged, so as to facilitate the subsequent cutting process.

[0110] Step S13: Figure 4 As shown, an interconnection structure 22 corresponding to the chip 20 to be packaged is formed on the second surface 212 of the plastic packaging layer 21 .

[0111] The pad 204 is connected to the external circuit through the interconnection structure 22. The plastic layer 21 has a through hole 41, and the pad 204 and the interconnection structure 22 are connected through a wire located in the through hole 41, or the pad 204 and the interconnection structure 22 can be electrically connected in other ways.

[0112] In this step, an interconnection structure 22 corresponding to the chip 20 to be packaged is formed on the second surface 212 of the plastic encapsulation layer 21, specifically including: forming a patterned metal circuit layer on the second surface 212 of the plastic encapsulation layer 21, the metal circuit layer including a plurality of interconnection structures 22 corresponding one by one to the chip 20 to be packaged; forming a welding protrusion 25 on the surface of the interconnection structure 22, the welding protrusion 25 being used to connect to the external circuit.

[0113] Specifically, the forming of a patterned metal circuit layer on the second surface 212 of the plastic encapsulation layer 21 includes: forming a metal circuit layer covering the second surface of the plastic encapsulation layer; etching the metal circuit layer to pattern the metal circuit layer to form a plurality of interconnect structures corresponding one to one to the chips to be packaged; or, the forming of a patterned metal circuit layer on the second surface 212 of the plastic encapsulation layer 21 includes: using a mask plate with a preset graphic structure to form the patterned metal circuit layer through a vapor deposition process.

[0114] Optionally, before the cutting process is performed, the method further includes: forming an insulating protection layer covering the metal circuit layer, wherein a surface of the insulating protection layer has an opening for arranging the welding protrusion. Figure 4 The insulating protective layer is not shown.

[0115] Step S14: Figure 5a and Figure 5b As shown, the plastic packaging layer 22 is divided into a plurality of packaging structures through a cutting process.

[0116] The packaging structure may include a plurality of the chips to be packaged 20 and their corresponding interconnection structures 22, or may include one chip to be packaged 20 and its corresponding interconnection structure 22. When the packaging structure has a plurality of the chips to be packaged 20, the arrangement of the plurality of chips to be packaged 20 may be arbitrarily set, such as in the packaging structure, the plurality of chips to be packaged 20 may be arranged in an array. The embodiment of the present invention does not limit the number of the chips to be packaged 20.

[0117] exist Figure 5a and Figure 5b In the illustrated embodiment, each packaging structure has three chips 20 to be packaged, and the three chips 20 to be packaged are located in the same straight line. Figure 5c As shown, the three chips 20 to be packaged may also be located at three vertices of a triangle respectively.

[0118] In the packaging method of the embodiment of the present invention, the method of forming the plastic packaging layer 21 covering the back side of all the chips 20 to be packaged is as follows: Figure 6-Figure 13 As shown, Figure 6-Figure 13 A schematic flow chart of a method for forming a plastic encapsulation layer provided in an embodiment of the present invention, the method comprising:

[0119] Step S21: Figure 6 As shown, a carrier plate 23 is provided, and the carrier plate has a temporary bonding surface 231 for carrying the chip 20 to be packaged.

[0120] In this embodiment, the temporary bonding surface 231 of the carrier plate 23 has a plurality of mounting grooves 232; one mounting groove 232 is used to place one chip 20 to be packaged; there is a gap 233 between two adjacent mounting grooves 23; the depths of the mounting grooves 232 are the same and are smaller than the thickness of the chip 20 to be packaged.

[0121] The carrier plate 23 may be a glass plate or a plastic plate. The carrier plate 23 has a plane which is the temporary bonding surface 231. Depending on the material of the carrier plate 23, the mounting groove 232 may be formed by an injection molding process or by an etching process.

[0122] Step S22: Figure 7 As shown, the front side 201 of the chip 20 to be packaged is bonded to the temporary bonding surface 231 of the carrier board 23 .

[0123] When the carrier plate 23 with the mounting grooves 232 is used, in this step, the front surface 201 of the chip to be packaged 20 is bonded to the temporary bonding surface 231 of the carrier plate 23, including: placing one chip to be packaged 20 in each mounting groove 232, and the front surface 201 of the chip to be packaged 20 is arranged opposite to the bottom of the mounting groove 232. Since the depths of the mounting grooves 232 are the same, and the front surface of the chip to be packaged 20 and the bottom of the corresponding mounting groove 232 are in seamless contact, the front surfaces 201 of the chips to be packaged 20 can be located in the same plane.

[0124] Step S23: Figure 8-Figure 13 As shown, the plastic encapsulation layer 21 is formed, and the plastic encapsulation layer 21 covers the chip to be packaged 20 and the temporary bonding surface 231 of the carrier board 23 .

[0125] When the above-mentioned carrier plate 23 with the mounting groove 232 is used, in this step, the step of forming the plastic encapsulation layer 21 includes:

[0126] First, if Figure 8 As shown, a first plastic encapsulation layer 21a is formed. The first plastic encapsulation layer 21a covers the chip to be packaged 20 and the temporary bonding surface 231 of the carrier board 23. The surface of the first plastic encapsulation layer 21a facing away from the chip to be packaged 20 is the second surface 212.

[0127] Then, if Fig. 9 As shown, the carrying plate 23 is removed.

[0128] For example Figure 10-13As shown, a second plastic encapsulation layer 21b is formed on a side surface of the first plastic encapsulation layer 21a that exposes the front surface 201 of the chip to be packaged 20. A side surface of the second plastic encapsulation layer 21b that is away from the first plastic encapsulation layer 21a is the first surface 211. In this embodiment, the method of forming the second plastic encapsulation layer 21b on a side surface of the first plastic encapsulation layer 21a that exposes the front surface 201 of the chip to be packaged 20 includes: first, as Fig.10 As shown, the front side 201 of the chip 20 to be packaged faces upward, and a protective layer 24 is formed on the front side 201 of the chip 20 to be packaged; then, as shown in FIG. Fig.11 As shown, the second plastic encapsulation layer 21b is formed, and the thickness of the second plastic encapsulation layer 21b is greater than the thickness of the chip to be packaged 20 exposed from the first plastic encapsulation layer 21a; Fig.12 As shown, the protective layer 24 is removed, and finally, as shown Fig.13 As shown, the surface of the second plastic encapsulation layer 21 b facing away from the first plastic encapsulation layer 21 a is thinned so that the surface is flush with the front side 201 of the chip 20 to be packaged.

[0129] exist Figure 6-Figure 13 In the embodiment shown, the carrier plate 23 has a mounting groove 232. In other embodiments, a carrier plate 23 with a flat structure can be directly used to form the plastic encapsulation layer 21, such as Figure 14-15 As shown, Figure 14-15 A schematic diagram of a process for forming another plastic encapsulation layer provided by an embodiment of the present invention, wherein the method adopts Fig.14 The support plate 23 of the flat plate structure shown in the figure has a temporary bonding surface 231 of the support plate 23 which is a plane. Fig.15 As shown, the bonding of the front surface 201 of the chip to be packaged 20 with the temporary bonding surface 231 of the carrier board 23 includes: bonding and fixing the chip to be packaged 20 with the temporary bonding surface 231 using a temporary bonding film 25 with uniform thickness. In this method, the chip to be packaged 20 is uniformly bonded and fixed to the temporary bonding surface 231 using a temporary bonding film with uniform thickness. Since the temporary bonding surface 231 is a plane, the chips to be packaged 20 are bonded and fixed using the same layer of bonding film 25, so that the front surfaces 201 of the chips to be packaged 20 can be ensured to be located on the same surface.

[0130] When the temporary bonding surface 231 is a plane, optionally, the packaging method removes the carrier plate 23 after forming the plastic encapsulation layer 21 and before forming the interconnection structure 22; or removes the carrier plate 23 after forming the interconnection structure 22 and before performing a cutting process.

[0131] In the above embodiment, the pad 204 of each chip 20 to be packaged is connected to the corresponding interconnection structure through a wire bonding process. Specifically, before the cutting process is performed, a through hole 41 is formed that penetrates the first surface 211 and the second surface 212 of the plastic encapsulation layer 21, and the through hole 41 can be prepared by a laser drilling process; the pad 204 is connected to one end of a metal wire 42, and the other end of the metal wire 42 is connected to the interconnection structure 22 through the through hole 41; wherein, in the first direction, the through hole 41 does not overlap with the chip 20 to be packaged; and the first direction is perpendicular to the first surface 211 and the second surface 212 of the plastic encapsulation layer 21.

[0132] In another embodiment, the interconnect structure 22 may also be directly connected to the pad on the back of the chip to be packaged 20 through a through hole, and then connected to the pad through the pad. Figure 16-Figure 17 As shown, Figure 16-Figure 17 A schematic flow chart of another chip packaging method provided in an embodiment of the present invention, wherein the back side 202 of the chip 20 to be packaged has a pad 162 connected to the pad 204; before forming the metal circuit layer, a through hole 161 is formed on the second surface 212 of the plastic encapsulation layer 21, and the through hole 161 can be prepared by a laser drilling process; in a first direction, the through hole 161 is arranged opposite to the pad to expose the pad 162; wherein the interconnection structure 22 is connected to the pad 162 through the through hole 161; and the first surface 211 and the second surface 212 perpendicular to the plastic encapsulation layer 21 in the first direction. In this method, it is necessary to form a back-side interconnection structure (not shown in the figure) on the back side of the chip 20 to be packaged by a TSV process, and at this time, the back side 202 of the chip 20 to be packaged has a through hole, and the through hole is used to expose the pad 162 located on the front side 201 thereof, so as to facilitate the connection between the pad 162 and the pad 204 through the back-side interconnection structure. In this method, after cutting, the formed packaging structure is as follows Fig.17 As mentioned above, the number of the chips 20 to be packaged in the package structure formed after cutting is not limited, and can be one or more.

[0133] The back-side interconnection structure includes: an insulating layer covering the back side 202 and the side wall of the through hole, the insulating layer having an opening in the area corresponding to the bottom of the through hole for exposing the solder pad; a rewiring layer covering the insulating layer and the bottom of the through hole; a solder resist layer covering the rewiring layer, the solder resist layer having an opening in the area outside the through hole exposing the rewiring layer, and the opening is used to set the solder pad 161. Fig.16The specific level and structure of the backside interconnection structure are not shown in the figure, and can be formed by referring to the TSV process of the traditional chip, which will not be described here. In this way, each interconnection structure 22 is connected to the pad 162 on the back side 202 of the chip 20 to be packaged through at least one through hole 161, and each through hole 161 corresponds to a pad 162.

[0134] In another embodiment, the interconnection structure may be connected to the pad via a first through hole penetrating the plastic encapsulation layer 21 and a second through hole penetrating the chip. Figure 18-19 As shown, Figure 18-19 A schematic flow chart of another chip packaging method provided in an embodiment of the present invention, before forming the metal circuit layer, a first through hole 171 is formed to penetrate the plastic encapsulation layer 21; a second through hole 172 is formed in the first through hole 171 to penetrate the front side 201 and the back side 202 of the chip 20 to be packaged, and in a first direction, the second through hole 172 is arranged opposite to the welding pad to expose the welding pad; wherein the metal circuit layer is connected to the welding pad through the first through hole 171 and the through hole 172; a first surface 211 and a second surface 212 perpendicular to the plastic encapsulation layer 21 in the first direction. In order to avoid a short circuit between the interconnect structure 22 and the substrate of the chip 20 to be packaged, an insulating layer covering the side walls of the second through hole 172 needs to be formed before forming the interconnect structure 22, and the insulating layer exposes the welding pad at the bottom of the second through hole 172, and the insulating layer can also cover the side walls of the first through hole 171 and the second surface 212. In this way, after cutting, the formed packaging structure is as follows Fig.19 shown.

[0135] In this method, the first through hole 171 and the second through hole 172 correspond to each other, and the second through hole 172 is formed by the mask of the plastic encapsulation layer 21. Since the chip 20 to be packaged does not need to form a back-side interconnection structure through the TSV process, the manufacturing process is simple and the cost is low; since no wire bonding process is required, the area of ​​the packaging structure is reduced.

[0136] In the packaging method described in the embodiment of the present invention, the chip 20 to be packaged is an image sensor chip; after completing the cutting process, the packaging method further includes: using the plastic packaging layer 21 of the packaging structure as a substrate, fixing a bracket on the periphery of the first surface of the plastic packaging layer; and arranging a transparent cover plate on the bracket, and the transparent cover plate can be a lens. Since the front surface 201 of the chip 20 to be packaged is located in the same plane, when the transparent cover plate is arranged, the height tolerance between the chip 20 to be packaged and the transparent cover plate can be avoided. At this time, when the packaging structure has one chip to be packaged, the transparent cover plate corresponds to one chip to be packaged alone, and when the packaging structure has multiple chips to be packaged, the transparent cover plate corresponds to the multiple chips to be packaged at the same time.

[0137] In the packaging method described in the embodiment of the present invention, multiple chips 20 to be packaged are located in the same plastic packaging layer 21, and the front of the chip 20 to be packaged is flush with the first surface 211 of the plastic packaging layer 21. In this way, a preset carrier plate 23 can be used to form the plastic packaging layer 21, so that the first surface 211 of the plastic packaging layer 21 has good flatness, and then the fronts 201 of each chip 20 to be packaged are located in the same plane, ensuring that the fronts 201 of multiple chips 20 to be packaged in the same packaging structure have good flush characteristics, and ensuring the reliability of the packaging structure. Since the plastic packaging material used to prepare the plastic packaging layer 21 has a large hardness after curing, on the one hand, the chip 20 to be packaged can be packaged and protected, and on the other hand, it can be used as a substrate to set other supporting components, such as a bracket for setting a transparent cover plate.

[0138] Based on the above packaging method, another embodiment of the present invention further provides a chip packaging structure, the packaging structure comprising: a plastic packaging layer, the plastic packaging layer having a first surface and a second surface relative to each other; at least one chip to be packaged located in the plastic packaging layer, the chip to be packaged having a front side and a back side relative to each other, the front side having a sensing unit and a solder pad connected to the sensing unit; an interconnection structure located on the second surface of the plastic packaging layer and corresponding to the chip to be packaged, the solder pad being connected to an external circuit through the interconnection structure; wherein the plastic packaging layer has a first surface and a second surface relative to each other, the chip to be packaged is located in the plastic packaging layer, and the front side thereof is flush with the first surface.

[0139] When the package structure has a chip to be packaged, the package structure can be as follows: Fig. 20 As shown, Fig. 20 A schematic diagram of a packaging structure provided in an embodiment of the present invention. The chip 20 to be packaged is located in a plastic layer 21. The chip 20 to be packaged has a whole surface 201 and a back surface 202, and its front side 201 has a solder pad 204 and a sensing unit (not shown). The chip 20 to be packaged can refer to the above embodiment and will not be described here. The plastic layer has a first surface 211 and a second surface 212, and its back side 212 has an interconnection structure 22 corresponding to the chip 20 to be packaged. The plastic layer 21 has a through hole 41, and a metal wire 42 is arranged in the through hole 41 for connecting the interconnection structure 22 and the solder pad 204. Other methods can also be used to connect the interconnection structure 22 and the solder pad 204, including but not limited to the methods described in the above embodiment.

[0140] In the packaging structure of the embodiment of the present invention, when the packaging structure has multiple chips to be packaged, the plastic packaging layer has multiple chips to be packaged; the front faces of all the chips to be packaged are located in the same plane and are flush with the first surface; each chip to be packaged corresponds to one interconnection structure. In this case, the packaging structure can be as follows Fig.21 shown.

[0141] refer to Fig.21 , Fig.21 Another schematic diagram of a packaging structure provided for an embodiment of the present invention includes: a plastic encapsulation layer 21, the plastic encapsulation layer 21 having a first surface 211 and a second surface 212 relative to each other; a plurality of chips 20 to be packaged located in the plastic encapsulation layer 21, the chips 20 to be packaged having a front side 201 and a back side 212 relative to each other, the front side 201 having a sensing unit and a pad connected to the sensing unit; the front sides 201 of all the chips 20 to be packaged are located in the same plane, and the front sides are flush with the first surface 211; a plurality of interconnect structures 22 located on the second surface 212 of the plastic encapsulation layer 21, the interconnect structures 22 corresponding to the chips 20 to be packaged one by one; the pads are connected to an external circuit through the interconnect structures 22. The structure of the chips 20 to be packaged can refer to the structure described in the above embodiment, and will not be repeated here.

[0142] In one embodiment, the plastic encapsulation layer 21 includes: a first plastic encapsulation layer and a second plastic encapsulation layer; the first plastic encapsulation layer has a plurality of grooves corresponding to the chips to be packaged, the depth of the grooves is less than the thickness of the chips to be packaged, and the back of the chips to be packaged is arranged relative to the bottom of the grooves; the surface of the first plastic encapsulation layer away from the chip to be packaged is the second surface; the second plastic encapsulation layer covers the surface of the first plastic encapsulation layer facing the chip to be packaged, and the surface of the second plastic encapsulation layer away from the first plastic encapsulation layer is the first surface. In another embodiment, the plastic encapsulation layer 21 is a single-layer structure formed by a carrier plate with a flat structure. The specific structures and formation processes of the two embodiments can refer to the above embodiments and will not be repeated here.

[0143] In the packaging structure described in the embodiment of the present invention, the interconnection structure 22 is located in the same patterned metal circuit layer; the surface of the interconnection structure 22 has a welding protrusion 25, and the welding protrusion 25 is used to connect to the external circuit. The pad of the front side 201 of the chip 20 to be packaged is connected to the interconnection structure 22, and then connected to the external circuit through the welding protrusion 25. Optionally, the surface of the interconnection structure 22 also has an insulating protective layer, and the surface of the insulating protective layer has an opening for setting the welding protrusion 25. Fig.21 The insulating protective layer is not shown.

[0144] exist Fig.21 In the illustrated embodiment, the plastic encapsulation layer 21 has a through hole 41 penetrating the first surface 211 and the second surface 212; one end of the welding pad is connected to one end of the metal wire 42, and the other end of the metal wire 42 is connected to the interconnection structure 22 through the through hole 41; wherein, in a first direction, the through hole 41 does not overlap with the chip to be packaged 20; and in the first direction, is perpendicular to the first surface 211 and the second surface 212 of the plastic encapsulation layer 21.

[0145] Optionally, the chip to be packaged 22 is an image sensor chip. The first surface 211 of the plastic encapsulation layer 21 is further provided with a bracket 181; a transparent cover plate 182 is mounted on the bracket 181. The transparent cover plate can be a transparent lens, which is used to control the light emitted or collected by the sensor chip.

[0146] As described in the above embodiment, in another implementation manner, the back surface 212 of the chip to be packaged 20 has a pad connected to the pad; the second surface 212 of the plastic encapsulation layer 21 has a through hole; in the first direction, the through hole is arranged opposite to the pad to expose the pad; wherein the interconnection structure is connected to the pad through the through hole. The packaging structure described in this manner can refer to Fig.17 The electrical connection structure can refer to the corresponding implementation of the above packaging method, which will not be described here.

[0147] As described in the above embodiment, in another implementation manner, the plastic encapsulation layer 21 has a first through hole; the back side 202 of the chip to be packaged 20 has a second through hole corresponding to the first through hole, and in the first direction, the second through hole is arranged opposite to the pad to expose the pad; wherein the metal circuit layer is connected to the pad through the through hole. The packaging structure described in this manner can refer to Fig.19 The electrical connection structure can refer to the corresponding implementation of the above packaging method, which will not be described here.

[0148] It can be known from the above description that in the packaging structure described in the embodiment of the present invention, multiple chips 20 to be packaged are located in the same plastic packaging layer 21, and the front of the chip 20 to be packaged is flush with the first surface 211 of the plastic packaging layer 21. In this way, a preset carrier plate 23 can be used to form the plastic packaging layer 21, so that the first surface 211 of the plastic packaging layer 21 has good flatness, and then the fronts 201 of each chip 20 to be packaged are located in the same plane, ensuring that the fronts 201 of multiple chips 20 to be packaged in the same packaging structure have good flush characteristics, and ensuring the reliability of the packaging structure. Since the plastic packaging material used to prepare the plastic packaging layer 21 has a large hardness after curing, on the one hand, the chip 20 to be packaged can be packaged and protected, and on the other hand, it can be used as a substrate to set other supporting components, such as a bracket for setting a transparent cover plate.

[0149] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the packaging structure disclosed in the embodiment, since it corresponds to the packaging method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the packaging method part.

[0150] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A chip packaging method, characterized in that: The packaging method comprises: Providing at least one chip to be packaged, wherein the chip to be packaged has a front side and a back side opposite to each other, and the front side has a sensing unit and a pad connected to the sensing unit; Forming a plastic encapsulation layer covering the back side of the chip to be encapsulated, wherein the plastic encapsulation layer has a first surface and a second surface opposite to each other, the chip to be encapsulated is located in the plastic encapsulation layer, and its front side is flush with the first surface; An interconnection structure corresponding to the chip to be packaged is formed on the second surface of the plastic encapsulation layer; the pad is connected to the external circuit through the interconnection structure; wherein the plastic encapsulation layer is reused as a carrier substrate for carrying a bracket, and a cover plate is installed through the bracket; Wherein, a plurality of the chips to be packaged are provided, and the front faces of all the chips to be packaged are located in the same plane and are flush with the first surface; each chip to be packaged corresponds to one interconnection structure; the packaging method further comprises: dividing the plastic packaging layer into a plurality of packaging structures by a cutting process, and the packaging structure comprises at least one chip to be packaged and its corresponding interconnection structure; The forming of the interconnection structure corresponding to the chip to be packaged on the second surface of the plastic encapsulation layer comprises: forming a patterned metal circuit layer on the second surface of the plastic encapsulation layer, the metal circuit layer comprising a plurality of interconnection structures corresponding one to one to the chip to be packaged; forming a welding protrusion on the surface of the interconnection structure, the welding protrusion being used to connect to the external circuit; The forming of a patterned metal circuit layer on the second surface of the plastic encapsulation layer includes: forming a metal circuit layer covering the second surface of the plastic encapsulation layer; etching the metal circuit layer to pattern the metal circuit layer to form a plurality of interconnect structures corresponding one to one to the chips to be packaged.

2. The packaging method according to claim 1, characterized in that: The forming of a plastic encapsulation layer covering the back side of the chip to be packaged comprises: Providing a carrier plate, the carrier plate having a temporary bonding surface for carrying the chip to be packaged; Laminating the front surface of the chip to be packaged with the temporary bonding surface of the carrier plate; The plastic encapsulation layer is formed, and the plastic encapsulation layer covers the chip to be packaged and the temporary bonding surface of the carrier board.

3. The packaging method according to claim 2, characterized in that: The temporary bonding surface of the carrier plate has a plurality of mounting grooves; one mounting groove is used to place one chip to be packaged; there is a gap between two adjacent mounting grooves; the depths of the mounting grooves are the same and less than the thickness of the chip to be packaged; The step of bonding the front side of the chip to be packaged to the temporary bonding surface of the carrier plate comprises: placing one chip to be packaged in each mounting groove, with the front side of the chip to be packaged being arranged opposite to the bottom of the mounting groove.

4. The packaging method according to claim 3, characterized in that: The forming of the plastic encapsulation layer comprises: forming a first plastic encapsulation layer, wherein the first plastic encapsulation layer covers the chip to be encapsulated and the temporary bonding surface of the carrier board; the surface of the first plastic encapsulation layer facing away from the chip to be encapsulated is the second surface; removing the carrying plate; A second plastic encapsulation layer is formed on a side surface of the first plastic encapsulation layer that exposes the front side of the chip to be encapsulated; a side surface of the second plastic encapsulation layer that is away from the first plastic encapsulation layer is the first surface.

5. The packaging method according to claim 4, characterized in that: The forming of a second plastic encapsulation layer on a surface of the first plastic encapsulation layer that exposes the front surface of the chip to be encapsulated comprises: forming a protective layer on the front side of the chip to be packaged; forming the second plastic encapsulation layer, wherein the thickness of the second plastic encapsulation layer is greater than the thickness of the chip to be encapsulated exposed from the first plastic encapsulation layer; After removing the protective layer, the surface of the second plastic encapsulation layer on one side facing away from the first plastic encapsulation layer is thinned so that the surface is flush with the front side of the chip to be packaged.

6. The packaging method according to claim 2, characterized in that: The temporary bonding surface is a plane; The step of bonding the front surface of the chip to be packaged to the temporary bonding surface of the carrier board includes: bonding and fixing the chip to be packaged to the temporary bonding surface using a temporary adhesive film with uniform thickness.

7. The packaging method according to claim 6, characterized in that: After forming the plastic encapsulation layer and before forming the interconnection structure, removing the carrier plate; Alternatively, after forming the interconnection structure and before performing the cutting process, the carrier board is removed.

8. The packaging method according to claim 1, characterized in that: Before the cutting process is performed, a through hole is formed that penetrates the first surface and the second surface of the plastic encapsulation layer; Connecting the bonding pad to one end of a metal wire, and connecting the other end of the metal wire to the interconnect structure through the through hole; Wherein, in a first direction, the through hole does not overlap with the chip to be packaged; and in the first direction, the through hole is perpendicular to the first surface and the second surface of the plastic packaging layer.

9. The packaging method according to claim 1, characterized in that: The back side of the chip to be packaged has a pad connected to the pad; Before forming the metal circuit layer, a through hole is formed on the second surface of the plastic packaging layer; in a first direction, the through hole is arranged opposite to the pad to expose the pad; Wherein, the interconnection structure is connected to the pad through the through hole; and the first direction is perpendicular to the first surface and the second surface of the plastic packaging layer.

10. The packaging method according to claim 1, characterized in that: Before forming the metal circuit layer, forming a first through hole penetrating the plastic packaging layer; A second through hole is formed in the first through hole, penetrating the front and back sides of the chip to be packaged, wherein the second through hole is arranged opposite to the welding pad in the first direction, so as to expose the welding pad; Wherein, the metal circuit layer is connected to the pad through the first through hole and the through hole; the first direction is perpendicular to the first surface and the second surface of the plastic packaging layer.

11. The packaging method according to claim 1, characterized in that: Before the cutting process, it also includes: An insulating protection layer is formed to cover the metal circuit layer, and a surface of the insulating protection layer has an opening for arranging the welding protrusion.

12. A chip packaging structure prepared by the packaging method according to any one of claims 1 to 11, characterized in that: The packaging structure comprises: a plastic packaging layer, wherein the plastic packaging layer has a first surface and a second surface opposite to each other; At least one chip to be packaged is located in the plastic packaging layer, the chip to be packaged has a front side and a back side opposite to each other, and the front side has a sensing unit and a solder pad connected to the sensing unit; An interconnection structure located on the second surface of the plastic encapsulation layer and corresponding to the chip to be packaged, wherein the pad is connected to an external circuit via the interconnection structure; The plastic encapsulation layer has a first surface and a second surface opposite to each other, the chip to be packaged is located in the plastic encapsulation layer, and its front side is flush with the first surface; the plastic encapsulation layer is reused as a carrier substrate for carrying a bracket, and a cover plate is installed through the bracket; The plastic encapsulation layer contains a plurality of chips to be packaged; the front surfaces of all the chips to be packaged are located on the same plane and are flush with the first surface; each chip to be packaged corresponds to one interconnection structure; The interconnection structure is located in the same patterned metal circuit layer; the surface of the interconnection structure has a welding protrusion, and the welding protrusion is used to connect with the external circuit.

13. The packaging structure according to claim 12, characterized in that: The plastic sealing layer comprises: a first plastic sealing layer and a second plastic sealing layer; The first plastic encapsulation layer has a plurality of grooves corresponding to the chips to be packaged one by one, the depth of the grooves is less than the thickness of the chips to be packaged, and the back side of the chips to be packaged is arranged opposite to the bottom of the grooves; the surface of the first plastic encapsulation layer away from the chips to be packaged is the second surface; The second plastic encapsulation layer covers a surface of the first plastic encapsulation layer facing the chip to be packaged, and a surface of the second plastic encapsulation layer facing away from the first plastic encapsulation layer is the first surface.

14. The packaging structure according to claim 12, characterized in that: The plastic sealing layer has a through hole penetrating the first surface and the second surface; One end of the bonding pad is connected to one end of the metal wire, and the other end of the metal wire is connected to the interconnection structure through the through hole; Wherein, in a first direction, the through hole does not overlap with the chip to be packaged; and in the first direction, the through hole is perpendicular to the first surface and the second surface of the plastic packaging layer.

15. The packaging structure according to claim 12, characterized in that: The back side of the chip to be packaged has a pad connected to the pad; The second surface of the plastic sealing layer has a through hole; in the first direction, the through hole is arranged opposite to the pad to expose the pad; Wherein, the interconnection structure is connected to the pad through the through hole; and the first direction is perpendicular to the first surface and the second surface of the plastic packaging layer.

16. The packaging structure according to claim 12, characterized in that: The plastic sealing layer has a first through hole; The back side of the chip to be packaged has a second through hole corresponding to the first through hole one by one, and in the first direction, the second through hole is arranged opposite to the welding pad to expose the welding pad; Wherein, the metal circuit layer is connected to the pad through the through hole; and the first direction is perpendicular to the first surface and the second surface of the plastic packaging layer.

17. The packaging structure according to claim 12, characterized in that: The interconnection structure surface also has an insulating protection layer, and the surface of the insulating protection layer has an opening for arranging the welding protrusion.

18. The packaging structure according to any one of claims 13 to 17, characterized in that: The chip to be packaged is an image sensor chip.

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