Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for preparing the same, and relates to the field of semiconductor technology. In the manufacturing process of the semiconductor device, a metal pad is formed on the device, and a bonding mark is formed on the metal pad. These bonding marks can be used as marks of positions where bonding connection is required during wire bonding, and the specific position on the device that needs to be connected to an external structure can be determined through the bonding marks, so that the bonding position of the wire on the device during wire bonding can be determined, thereby improving the accuracy of wire bonding.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] During the packaging process, semiconductor devices such as chips require wire bonding to connect the device to the lead frame via wires. However, during wire bonding, the exact location on the device where the connection needs to be made cannot be determined. Summary of the Invention

[0003] In view of this, the present invention provides a semiconductor device and a method for manufacturing the same, which can solve the above problems.

[0004] The technical solutions provided by the present invention are as follows:

[0005] A method for preparing a semiconductor device, the method comprising:

[0006] providing a wafer;

[0007] fabricating a plurality of metal pads on one side of the wafer;

[0008] One or more bonding marks are formed on a side of at least one of the metal pads away from the wafer to form a metal pad with bonding marks.

[0009] Furthermore, the step of manufacturing a plurality of metal pads on one side of the wafer includes:

[0010] forming a first mask layer on one side of the wafer;

[0011] removing the first mask layer corresponding to the position of the metal pad;

[0012] A first metal layer is formed on the side of the wafer where the first mask layer is formed. The first metal layer includes a first portion located on the side of the wafer corresponding to the metal pad and a second portion located on the side of the first mask layer away from the wafer. The first portion forms the metal pad.

[0013] Furthermore, the step of forming a first mask layer on one side of the wafer includes:

[0014] Applying a release adhesive layer on one side of the wafer;

[0015] A photoresist layer is coated on a side of the stripping adhesive layer away from the wafer, so that the stripping adhesive layer and the photoresist layer form the first mask layer.

[0016] Furthermore, the step of removing the first mask layer corresponding to the position of the metal pad includes:

[0017] exposing the side of the wafer coated with the stripping adhesive layer and the photoresist layer;

[0018] The exposed wafer is developed to remove the stripping adhesive layer and the photoresist layer corresponding to the position of the metal pad, wherein the area of ​​the stripping adhesive layer removed at the position of each metal pad is larger than the area of ​​the photoresist layer removed.

[0019] Furthermore, the step of forming a first metal layer on the side of the wafer where the first mask layer is formed includes:

[0020] The first metal layer is formed on the side of the photoresist layer away from the stripping layer, wherein the first metal layer is located on the side of the wafer corresponding to the metal pad to form the first part, and the first metal layer is located on the side of the photoresist layer away from the stripping layer to form the second part.

[0021] Furthermore, the step of making one or more bonding marks to form a metal pad with bonding marks includes:

[0022] removing the stripping adhesive layer and the photoresist layer on one side of the wafer;

[0023] removing a portion of the first metal layer located on a side of the photoresist layer away from the stripping adhesive layer;

[0024] Part of the material of the first portion away from the surface of one side of the wafer is removed to form an external circuit point with a bonding mark.

[0025] Furthermore, the thickness of the first metal layer is smaller than the thickness of the release adhesive layer.

[0026] Furthermore, the step of forming one or more bonding marks on a side of at least one of the metal pads away from the wafer includes:

[0027] forming a second metal layer on the side of the wafer where the metal pad is provided;

[0028] forming a patterned second mask layer on a side of the second metal layer away from the wafer;

[0029] Etching the wafer using the second mask layer as a mask to remove the second metal layer and the second mask layer except for the position of the bonding mark;

[0030] The second mask layer corresponding to the bonding mark position is removed, so that the second metal layer corresponding to the bonding mark position forms the bonding mark.

[0031] The present invention also provides a semiconductor device comprising an active area and a passive area, wherein the active area comprises a substrate, a semiconductor layer and an electrode, and an electron channel is provided in the semiconductor layer; the passive area comprises a substrate and a semiconductor layer; at least one independent metal pad is covered on a side of the semiconductor layer in the passive area away from the substrate, the metal pad is connected to the electrode in the active area, and each independent metal pad comprises at least one bonding mark.

[0032] Furthermore, the metal pad includes at least one row of bonding marks along its length.

[0033] Furthermore, when there are multiple independent metal pads in the passive area, when any two of the metal pads have the same length, the spacing between the bonding marks of the independent metal pads is equal.

[0034] Furthermore, when there are multiple independent metal pads in the passive region, when the lengths of any two independent metal pads are unequal, the spacings between the bonding marks of the independent metal pads are equal or unequal.

[0035] Furthermore, the distance between two adjacent bonding marks ranges from 40 um to 410 um.

[0036] Furthermore, when the independent metal pad has multiple bonding marks, the distances between two adjacent bonding marks are equal.

[0037] Furthermore, the bonding mark is a geometric figure or a letter figure.

[0038] Furthermore, the metal pad further includes a source pad, the source pad is on the same side as the drain pad or the gate pad, and the source pad includes at least one bonding mark.

[0039] The preparation method provided in the embodiments of the present application forms metal pads on the device and bonding marks on the metal pads during the manufacturing process of the semiconductor device. These bonding marks can be used as marks for the locations where bonding connections are required during the wire bonding process. The bonding marks can be used to determine the specific locations on the device where connections to external structures are required, so that the bonding positions of the wires on the device can be determined during wire bonding, thereby improving the accuracy of wire bonding.

[0040] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0042] Figure 1 A schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present invention.

[0043] Figure 2 Schematic diagram of the flow of sub-steps of step S102 in an embodiment of the present invention.

[0044] Figures 3 to 7 Schematic cross-sectional views of a device in each process of a method for manufacturing a semiconductor device provided by an embodiment of the present invention.

[0045] Figure 8 A schematic flow chart of another method for manufacturing a semiconductor device provided in an embodiment of the present invention.

[0046] Figures 9 to 13 Schematic cross-sectional views of a device in each process of a method for manufacturing a semiconductor device provided by an embodiment of the present invention.

[0047] Figures 14 to 16 A schematic diagram of the distribution of bonding marks on metal pads of different shapes provided by an embodiment of the present invention.

[0048] Figure 17 An overall schematic diagram of a semiconductor device provided by an embodiment of the present invention.

[0049] Figure 18 for Figure 17 Schematic diagram of the cross section at the AA' position.

[0050] Figure 19 An overall schematic diagram of a semiconductor device provided by an embodiment of the present invention.

[0051] Figure 20 An overall schematic diagram of a semiconductor device provided by an embodiment of the present invention.

[0052] Icons: 101-wafer; 102-first mask layer; 121-stripping adhesive layer; 122-photoresist layer; 10-undercut structure; 103-first metal layer; 131-first part; 132-second part; 104-metal pad; 105-second metal layer; 106-second mask layer; 107-bonding mark; 108-source; 109-gate; 110-drain; 111-passive area; 112-active area. DETAILED DESCRIPTION

[0053] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. The components of the embodiments of the present invention generally described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention.

[0054] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are used only to distinguish the description and should not be understood as indicating or implying relative importance.

[0055] The inventors have discovered that when performing wire bonding on semiconductor devices such as chips, it is usually impossible to determine the specific location of the metal pad on the device, resulting in the inability to control the specific location of the connection between the wire and the semiconductor device during the wire bonding process. As a result, after the wire bonding is completed, the spacing between the wires is too large or too small, resulting in excessive current in the wires, and even the excessive current in the wires causing the wires to overheat and burn out.

[0056] Example 1

[0057] In view of this, the present application provides a method for preparing a semiconductor device, such as Figure 1 As shown, the method includes the following steps.

[0058] In step S101 , a wafer 101 is provided.

[0059] The size of the wafer 101 can be determined according to actual conditions, and the embodiment of the present application does not limit the specific size of the wafer 101.

[0060] In step S102 , a plurality of metal pads 104 are fabricated in the passive region on one side of the wafer 101 .

[0061] After completing various manufacturing processes, the wafer 101 can be cut into various chips. The metal pads 104 serve as the structure for connecting the chip to the external circuit. The specific position of each metal pad 104 on the wafer 101 can be predetermined. The semiconductor device on the wafer 101 may include an active area and a passive area. The active area is provided with structures such as electrodes. The metal pads 104 can be provided in the passive area and connected to the electrodes in the active area. Figure 2 As shown, the specific method of manufacturing the metal pad 104 may include the following sub-steps.

[0062] In sub-step S121 , a first mask layer 102 is formed in the inactive area on one side of the wafer 101 .

[0063] The process of manufacturing the metal pad 104 can be achieved through a lift-off process. First, a first mask layer 102 is manufactured in the inactive area on one side of the wafer 101 .

[0064] Detailed, such as Figure 3 As shown, a release adhesive layer 121 can be first coated on the inactive area on one side of the wafer 101. A photoresist layer 122 is then coated on the side of the release adhesive layer 121 away from the wafer 101. The release adhesive layer 121 and the photoresist layer 122 form the first mask layer 102. The thickness of the release adhesive layer 121 and the photoresist layer 122 can be determined according to actual conditions, and the embodiment of the present application does not limit the specific thickness of the release adhesive layer 121 and the photoresist layer 122. The specific materials of the release adhesive layer 121 and the photoresist layer 122 can be selected according to the needs of the stripping process, and the embodiment of the present application does not limit the specific materials selected for the release adhesive layer 121 and the photoresist layer 122.

[0065] Sub-step S122 , removing the first mask layer 102 corresponding to the position of the metal pad 104 in the inactive area on both sides of the device electrode.

[0066] After forming the first mask layer 102 , the first mask layer 102 at the location of the metal pad 104 may be removed.

[0067] Detailed, such as Figure 4 As shown, the side of the wafer 101 coated with the stripping adhesive layer 121 and the photoresist layer 122 can be exposed. The exposed wafer 101 is then developed to remove the stripping adhesive layer 121 and the photoresist layer 122 corresponding to the position of the metal pad 104. Since the development characteristics of the stripping adhesive layer 121 and the photoresist layer 122 are different, the area of ​​the stripping adhesive layer 121 removed at the position corresponding to each metal pad 104 is larger than the area of ​​the photoresist layer 122 removed, so that an undercut structure 10 is formed at the position of the metal pad 104. The position and number of the undercut structure 10 can be determined according to actual needs. Figure 4As shown, in the embodiment of the present application, two undercut structures 10 are formed. The embodiment of the present application does not limit the position and number of the undercut structures 10. In each undercut structure 10, the area of ​​the removed stripping adhesive layer 121 is larger than the area of ​​the removed photoresist layer 122.

[0068] In sub-step S123, a first metal layer 103 is formed on the side of the wafer 101 where the first mask layer 102 is formed. The first metal layer 103 includes a first portion 131 located on the side of the wafer 101 corresponding to the metal pad 104 and a second portion 132 located on the side of the first mask layer 102 away from the wafer 101. The first portion 131 of the first metal layer 103 forms the metal pad 104.

[0069] After a first mask layer 102 formed of a release adhesive layer 121 and a photoresist layer 122 is provided on one side of the wafer 101, and after exposure, development and other steps, the first mask layer 102 at the position corresponding to the metal pad 104 is removed, and the metal pad 104 can be manufactured. Figure 5 As shown, the metal pad 104 in the embodiment of the present application is formed by the step of manufacturing the first metal layer 103. The metal material used for the first metal layer 103 is not limited in this application and can be determined according to the specific needs of the metal pad 104 to be manufactured. The first metal layer 103 can be formed by a process such as vacuum sputtering or electron beam evaporation. The embodiment of the present application does not limit the specific manufacturing process of the first metal layer 103. Since the release adhesive layer 121 and the photoresist layer 122 at the position of the metal pad 104 are removed, an opening is formed in the first mask layer 102 at the position corresponding to the metal pad 104. When the first metal layer 103 is manufactured, the first metal layer 103 actually includes two parts, namely a first part 131 located on the side of the wafer 101 corresponding to the metal pad 104, and a second part 132 located on the side of the first mask layer 102 away from the wafer 101. The first part 131 is located in the undercut structure 10, and the second part 132 is the part located on the photoresist layer 122 away from the release adhesive layer 121. Part of the material for making first metal layer 103 is formed on wafer 101 through the opening, directly contacting wafer 101, and forming first portion 131. Preferably, the size of first portion 131 of first metal layer 103 is in the range of 2 / 3 to 4 / 3 of the size of the opening in photoresist layer 122. First portion 131 of first metal layer 103 thus forms metal pad 104.

[0070] As previously mentioned, due to the different development characteristics of the release adhesive layer 121 and the photoresist layer 122 during the exposure and development steps, the area of ​​the release adhesive layer 121 removed from the corresponding location of each metal pad 104 is larger than the area of ​​the photoresist layer 122 removed. During the fabrication of the first metal layer 103, the first portion 131 of the first metal layer 103 will directly fall onto the surface of the wafer 101 through the opening formed in the photoresist layer 122. Furthermore, the first portion 131 of the first metal layer 103 will not contact the release adhesive layer 121. To prevent adhesion between the first metal layer 103 and the photoresist layer 122, during the fabrication of the first metal layer 103, the thickness of the first metal layer 103 can be less than the thickness of the release adhesive layer 121. This prevents the first portion 131 of the first metal layer 103 from contacting the photoresist layer 122, thereby preventing adhesion between the first metal layer 103 and the photoresist layer 122.

[0071] like Figure 6 As shown, the stripping adhesive layer 121 and the photoresist layer 122 on one side of the wafer 101 can be removed, and the second portion 132 of the first metal layer 103 can be removed. When the stripping adhesive layer 121 and the photoresist layer 122 are removed, the second portion 132 of the first metal layer 103 is also stripped at the same time. Figure 7 FIG. 1 is a cross-sectional view of the device after removing the release adhesive layer 121, the photoresist layer 122, and the second portion 132 of the first metal layer 103. After removing the release adhesive layer 121, the photoresist layer 122, and the second portion 132 of the first metal layer 103, the first portion 131 of the first metal layer 103 previously formed in the undercut structure 10 becomes a metal pad 104, and the portion between the metal pads 104 can serve as a bonding mark 107.

[0072] Step S103 : making one or more bonding marks based on the plurality of metal pads to form a metal pad 104 with bonding marks.

[0073] After forming the first metal layer 103 and forming the metal pad 104 through the first portion 131 of the first metal layer 103, a portion of the metal material on the metal pad 104 can be removed to form a bonding mark 107 at the location where the portion of the metal material was removed, thereby forming a metal pad 104 having a bonding mark 107. The embodiments of the present application do not limit the specific process for removing the portion of the metal material.

[0074] In the above embodiment, a release adhesive layer 121 and a photoresist layer 122 are first formed, and then the release adhesive layer 121 and the photoresist layer 122 at the position of the metal pad 104 are removed, and the metal pad 104 is formed through the first part 131 of the first metal layer 103, and a bonding mark 107 is formed on the metal pad 104. In fact, the metal pad 104 and the bonding mark 107 are manufactured and formed in the same process, and there is no need to add a new process step to form the bonding mark 107, thereby improving the manufacturing efficiency of forming the bonding mark.

[0075] Example 2

[0076] In this embodiment, the metal pad 104 may be formed first, and then a bonding mark may be made on the metal pad 104. Figure 8 As shown, the method may include the following steps.

[0077] In step S201 , a wafer 101 is provided.

[0078] In step S202 , a plurality of metal pads 104 are fabricated on one side of the wafer 101 .

[0079] The step of manufacturing the metal pad 104 in step S202 may be different from the manufacturing process in step S102 , and the metal pad 104 may be first formed on one side of the wafer 101 through other processes.

[0080] Step S203, as Figure 9 As shown, a second metal layer 105 is formed on the side of the wafer 101 where the metal pad 104 is provided.

[0081] Step S204, as Figure 10 As shown, a patterned second mask layer 106 is formed on a side of the second metal layer 105 away from the wafer 101 .

[0082] Step S205, as Figure 11 As shown, the wafer 101 is etched using the second mask layer 106 as a mask to remove the second metal layer 105 and the second mask layer 106 except for the position of the bonding mark.

[0083] It can be understood that before the step of removing the second metal layer 105 and the second mask layer 106 outside the position of the bonding mark 107, another mask layer can be made on the side of the second mask layer 106 away from the wafer 101, and the second metal layer 105 and the second mask layer 106 outside the position of the bonding mark 107 can be etched using the newly made mask to remove the second metal layer 105 and the second mask layer 106 outside the position of the bonding mark 107.

[0084] The second metal layer 105 can cover the side of the wafer 101 where the metal pad 104 is provided, and a second mask layer 106 is formed on the side of the second metal layer 105 away from the wafer 101. The second mask layer 106 can be used to determine the specific location of the bonding mark on the metal pad 104. The wafer 101 is then etched, and the second mask layer 106 is used as a mask to block the portion that does not need to be etched. The second metal layer 105 and the second mask layer 106 outside the location of the bonding mark 107 are removed. The second metal layer 105 at the bonding mark location and the second mask layer 106 at the bonding mark location are retained.

[0085] Step S206, as Figure 12 As shown, the second mask layer 106 corresponding to the bonding mark position is removed, so that the second metal layer 105 corresponding to the bonding mark position forms the bonding mark 107.

[0086] After etching with the second mask layer 106, the second metal layer 105 and the second mask layer 106 at the bonding mark 107 are left. At this time, the remaining second mask layer 106 is removed, and the second metal layer 105 left on the metal pad 104 is the bonding mark 107. Figure 13 , which is a cross-sectional view after forming a bonding mark 107 on the metal pad 104, the portion of the second metal layer 105 remaining on the metal pad 104 forms the bonding mark 107. The shape of the remaining second metal layer 105 can be a dot, a cross, or the like, thus forming a dot-shaped or cross-shaped bonding mark 107. This provides an identifiable bonding mark 107 on the metal pad 104, facilitating wire bonding operations during wire bonding.

[0087] It is understandable that if Figures 14 to 16 As shown, the shape of the metal pad 104 can be a long strip, a rectangle or a circle. The distribution of the bonding mark 107 on the metal pad 104 in the embodiment of the present application can be determined according to the position requirements of the wire bonding. For example, the spacing between multiple bonding marks 107 can be equal, and the positions of the bonding marks 107 corresponding to each chip on the wafer 101 can be evenly distributed to ensure that when wire bonding is performed, the bonding mark 107 can be used as an identifier for the bonding operation to form bonding wires with equal spacing.

[0088] Example 3

[0089] After the metal pads 104 and bonding marks 107 are fabricated on the wafer 101 , the wafer 101 may be cut into required chips according to the actual conditions of the wafer 101 .

[0090] The semiconductor device includes an active area 112 and a passive area 111. The active area 112 includes a substrate, a semiconductor layer and an electrode in a direction perpendicular to the paper, and an electron channel is provided in the semiconductor layer. The passive area 111 includes a substrate and a semiconductor layer in a direction perpendicular to the paper. The semiconductor layer of the passive area 111 is covered on a side away from the substrate by at least one independent metal pad 104. The metal pad 104 is connected to the electrode of the active area 112. Each independent metal pad 104 includes at least one bonding mark 107. Figure 17 In the top view of the semiconductor device shown, the electrodes of the active region 112 may include a source 108, a gate 109, and a drain 110. The present application does not limit the number and distribution of the source 108, gate 109, and drain 110. For example, multiple gates 109 may be distributed in a finger-like manner between the source 108 and the drain 110. It is understood that the metal pad 104 connected to the multiple gates 109 can serve as a gate pad, and the metal pad 104 connected to the multiple drains 110 can serve as a drain pad. Depending on the device structure, the metal pad 104 includes at least a drain pad and a gate pad. Each independent pad on the gate 109 pad and / or the drain 110 pad includes at least one bonding mark 107. These bonding marks 107 facilitate connection between the pad and the external circuit. The distribution of the bonding marks 107 on the pad can be determined according to actual needs, and the embodiments of the present application do not limit the number and distribution of the bonding marks 107 on the pad.

[0091] It is understood that the shape of the metal pad 104 can be a strip, a rectangle or a circle. In the length direction of the metal pad 104, Figure 1 As shown, the source electrode 108, gate electrode 109, and drain electrode 110 may be arranged in a crosswise direction, and each independent metal pad 104 may include at least one row of bonding marks 107. If the metal pad 104 is circular, each independent metal pad 104 may include at least one row of bonding marks 107 along the length of the perimeter of the metal pad 104. In practice, the bonding marks 107 can be used to identify the specific location on the device where the external structure needs to be connected, so that the bonding position of the wire on the device can be determined during wire bonding, thereby improving the accuracy of wire bonding.

[0092] In the embodiment of the present application, the distribution of the bonding mark 107 on the metal pad 104 can be determined according to the position requirements of the wire bonding. For example, the spacing between the multiple bonding marks 107 on each independent metal pad 104 can be equal, and the positions of the bonding marks 107 on the metal pad 104 can be evenly distributed, ensuring that when wire bonding is performed, the bonding marks 107, as identifiers of the bonding operation, can form bonding wires with equal spacing. In the case where the bonding position on the chip is not clearly located, the position of the bonding mark 107 is designed so that the spacing between the bonding wires will not be too small or too large, so that the current borne by each wire is consistent, avoiding the risk of chip burning. Therefore, the spacing between two adjacent bonding marks 107 on each independent metal pad 104 ranges from 40um to 410um; preferably, the spacing between two adjacent bonding marks 107 ranges from 85um to 310um.

[0093] The bonding mark 107 is formed to be easy to distinguish and identify, and is preferably a geometric figure or letter figure, which can be a dot-shaped, cross-shaped, X-shaped, etc., thus forming a dot-shaped or cross-shaped bonding mark 107, so that the metal pad 104 has an identifiable bonding mark 107, which can facilitate the bonding operation of the wire during wire bonding. Preferably, the plane line width of the bonding mark 107 figure is 1.5um to 15um. In addition, optionally, the plane space area occupied by the bonding mark 107 figure is within the range of 25um. 2 Up to 1000um 2 Alternatively, the size of the bonding mark 107 may be enlarged or reduced accordingly according to the size of the metal pad 104 on the chip.

[0094] like Figure 18 As shown, Figure 1 In the cross-sectional view at position AA', the bonding mark 107 on the metal pad 104 can be a protrusion from the surface of the metal pad 104, or can be a groove located on the metal pad 104. The actual volume of the bonding mark 107 can be a size that can be distinguished during the bonding process. The embodiment of the present application does not limit the size of the bonding mark 107. It is understandable that if the bonding mark 107 is a raised structure, that is, the second metal layer 105 is covered on the surface of the metal pad 104; if the bonding mark 107 is a recessed structure, that is, a groove is provided on the surface of the metal pad 104, then the depth of the groove is less than or equal to the thickness of the metal pad 104. Preferably, the depth of the groove-type bonding mark 107 is equal to the thickness of the metal pad 104, which can reduce the process difficulty and facilitate industrial implementation.

[0095] Example 4

[0096] like Figure 19FIG. 1 is a top view of a semiconductor device according to this embodiment. Compared to the third embodiment described above, this embodiment differs in that there are at least two metal pads 104 connected to the same type of electrode, i.e., there are metal pads 104 of different lengths. The length L of each independent metal pad 104 can be equal or unequal. It is understood that when there are multiple independent metal pads 104 in the passive region 111, when the lengths L of any two independent metal pads 104 are equal, the spacing between the bonding marks 107 of the independent metal pads 104 is equal; when the lengths L of any two independent metal pads 104 are unequal, the spacing between the bonding marks 107 of the independent metal pads 104 is equal or unequal.

[0097] The length of the independent metal pad 104 affects the spacing between adjacent bonding marks 107. For example, when the drain 110 pad length L1 and the gate 109 pad length L2 are equal, the spacing between the bonding marks 107 on the drain 110 pad and the bonding marks 107 on the gate 109 pad are equal; when the drain 110 pad length L1 and the gate 109 pad length L2 are different, the spacing between the bonding marks 107 on the drain 110 pad and the bonding marks 107 on the gate 109 pad are different; when the gate 109 pad length L2 and the gate 109 pad length L3 are different, the spacing between the bonding marks 107 on the L2 and L3 pads is equal or different. It is understood that in order to ensure that the current carried by each lead is consistent, the risk of chip burning is avoided. Therefore, the distance between two adjacent bonding marks 107 on each independent metal pad 104 ranges from 40 um to 410 um; preferably, the distance between two adjacent bonding marks 107 ranges from 85 um to 310 um.

[0098] Example 5

[0099] like Figure 20 , which is a top view of the semiconductor device according to this embodiment. Compared with the third embodiment, the difference of this embodiment is that multiple sources 108 can be connected to the external circuit through one or more metal pads 104 in the passive area 111, and the metal pads 104 connected to the multiple sources 108 can be used as source 108 pads. The source 108 pad is on the same side as at least one of the drain 110 pad or the gate 109 pad. Each independent source 108 pad includes at least one bonding mark 107. In the length direction of the metal pad 104, each independent metal pad 104 includes at least one row of bonding marks 107. As shown in the attached figure, the source 108 pad is connected to the external circuit through one or more metal pads 104 in the passive area 111. Figure 4As shown, the source 108, gate 109, and drain 110 may be arranged in a crosswise direction, and each gate 109 may include two rows of bonding marks on the independent metal pad 104. In this embodiment, the source 108 pad and the gate 109 pad are on the same side, and the lengths of each independent metal pad 104 are unequal. Therefore, the spacing between the bonding marks 107 of the metal pads 104 may be equal or unequal, and the spacing between two adjacent bonding marks 107 on each independent pad 104 ranges from 40 μm to 410 μm.

[0100] The present application also provides a semiconductor device manufactured using the above-described manufacturing method. One or more bonding marks 107 are prepared using the above-described manufacturing method. These bonding marks 107 facilitate connection between a pad and an external circuit. The distribution of the bonding marks 107 on the pad can be determined based on actual needs, and the embodiments of the present application do not limit the number or distribution of the bonding marks 107 on the pad.

[0101] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Various modifications and variations are readily apparent to those skilled in the art. Any modifications, equivalent substitutions, improvements, and the like made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention. It should be noted that similar reference numerals and letters denote similar items in the following figures. Therefore, once an item is defined in one figure, it need not be further defined or explained in subsequent figures.

[0102] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A method for preparing a semiconductor device, characterized in that: The method includes: providing a wafer; Making a plurality of metal pads in a passive area on one side of the wafer; Based on the plurality of metal pads, one or more bonding marks are made to form a metal pad with bonding marks; The step of making one or more bonding marks on a side of at least one of the metal pads away from the wafer comprises: Fabricating a second metal layer on a side of the wafer where the metal pad is disposed; forming a patterned second mask layer on a side of the second metal layer away from the wafer; Etching the wafer using the second mask layer as a mask to remove the second metal layer and the second mask layer except for the position of the bonding mark; The second mask layer corresponding to the bonding mark position is removed, so that the second metal layer corresponding to the bonding mark position forms the bonding mark.

2. The preparation method according to claim 1, characterized in that: The step of making a plurality of metal pads on one side of the wafer comprises: forming a first mask layer on one side of the wafer; removing the first mask layer corresponding to the position of the metal pad; A first metal layer is formed on the side of the wafer where the first mask layer is formed. The first metal layer includes a first portion located on one side of the wafer corresponding to the metal pad and a second portion located on a side of the first mask layer away from the wafer. The first portion forms the metal pad.

3. The preparation method according to claim 2, characterized in that: The step of forming a first mask layer on one side of the wafer comprises: Applying a release adhesive layer on one side of the wafer; A photoresist layer is coated on a side of the stripping adhesive layer away from the wafer, so that the stripping adhesive layer and the photoresist layer form the first mask layer.

4. The preparation method according to claim 3, characterized in that: The step of removing the first mask layer corresponding to the position of the metal pad comprises: Exposing the side of the wafer coated with the stripping glue layer and the photoresist layer; The exposed wafer is developed to remove the stripping adhesive layer and the photoresist layer corresponding to the position of the metal pad, wherein the area of ​​the stripping adhesive layer removed at the position of each metal pad is larger than the area of ​​the photoresist layer removed.

5. The preparation method according to claim 4, characterized in that: The step of forming a first metal layer on the side of the wafer where the first mask layer is formed comprises: The first metal layer is produced on a side of the photoresist layer away from the stripping glue layer, wherein a portion of the first metal layer located on a side of the wafer corresponding to the metal pad forms the first portion, and a portion of the first metal layer located on a side of the photoresist layer away from the stripping glue layer forms the second portion.

6. The preparation method according to claim 5, characterized in that: The steps of making one or more bonding marks and forming a metal pad with bonding marks include: removing the stripping adhesive layer and the photoresist layer on one side of the wafer; removing a portion of the first metal layer located on a side of the photoresist layer away from the stripping adhesive layer; Part of the material of the first portion away from the surface of one side of the wafer is removed to form an external circuit point with a bonding mark.

7. The preparation method according to any one of claims 3 to 6, characterized in that: The thickness of the first metal layer is smaller than the thickness of the release adhesive layer.

8. A semiconductor device, characterized in that: The semiconductor device is prepared according to the preparation method according to any one of claims 1 to 7, and the semiconductor device includes an active area and a passive area, the active area includes a substrate, a semiconductor layer and an electrode, and there is an electron channel in the semiconductor layer; the passive area includes a substrate and a semiconductor layer; at least one independent metal pad is covered on the side of the semiconductor layer in the passive area away from the substrate, the metal pad is connected to the electrode in the active area, and each of the metal pads includes at least one bonding mark.

9. The semiconductor device according to claim 8, characterized in that When there are multiple independent metal pads in the passive region, when any two of the metal pads are equal in length, the spacings between the bonding marks of the metal pads are equal.

10. The semiconductor device according to claim 8, characterized in that When there are multiple independent metal pads in the passive region, when the lengths of any two of the metal pads are unequal, the spacings between the bonding marks of the independent metal pads are equal or unequal.

11. The semiconductor device according to claim 8, characterized in that The distance between two adjacent bonding marks of the independent metal pad ranges from 40um to 410um.

12. The semiconductor device according to any one of claims 8 to 11, characterized in that: When the independent metal pad has a plurality of bonding marks, the intervals between two adjacent bonding marks are equal.

13. The semiconductor device according to any one of claims 8 to 11, characterized in that: The bonding mark is a geometric figure or a letter figure.

14. The semiconductor device according to any one of claims 8 to 11, characterized in that: The metal pad further includes a source pad, which is on the same side as the drain pad or the gate pad, and the source pad includes at least one bonding mark.

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