Vertical storage device

Abstract

The present application provides a vertical memory device. The vertical memory device includes a gate electrode structure and a channel on a substrate. The gate electrode structure includes gate electrodes spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate. The channel extends through the gate electrode structure in a vertical direction on the substrate. The channel includes: a first portion having an inclined sidewall relative to an upper surface of the substrate, and a second portion contacting an upper surface of the first portion and having an inclined sidewall relative to an upper surface of the substrate. The width of the upper surface of the second portion is smaller than the width of the upper surface of the first portion. An impurity region doped with carbon or p-type impurities is formed on an upper portion of the substrate. The channel contacts the impurity region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2017-0163653 filed on November 30, 2017 in the Korean Intellectual Property Office (KIPO), the contents of which are hereby incorporated by reference in their entirety. Technical Field

[0003] The inventive concept relates to a vertical memory device. Background Art

[0004] As the number of stacked mold structures in a VNAND flash memory device increases, the depth of the channel holes extending through the mold structures may have a distribution. Therefore, in an etching process for forming the channel holes, the mold structure may be over-etched so that all the channel holes may expose the upper surface of the substrate, which may form a recess on the substrate. As an ONO layer may be formed on the recess, a parasitic capacitance may be generated, and thus the electrical characteristics of the VNAND flash memory device may be deteriorated. Summary of the invention

[0005] Example embodiments provide a vertical memory device having excellent characteristics.

[0006] According to one aspect of the inventive concept, a vertical memory device may include a substrate, a gate electrode structure, and a channel. The gate electrode structure may be located on the substrate. The upper portion of the substrate may include an impurity region doped with carbon or p-type impurities. The gate electrode structure may include gate electrodes spaced apart from each other in a vertical direction substantially perpendicular to the upper surface of the substrate. The channel may extend through the gate electrode structure in a vertical direction on the substrate. The channel may include a first portion and a second portion. The first portion may have an inclined sidewall relative to the upper surface of the substrate. The second portion may contact the upper surface of the first portion and may have an inclined sidewall relative to the upper surface of the substrate. The width of the upper surface of the second portion may be less than the width of the upper surface of the first portion. The channel may contact the impurity region.

[0007] According to one aspect of the inventive concept, a vertical memory device may include a substrate, a channel structure, a charge storage structure, and a gate electrode structure. The substrate may include an impurity region doped with carbon or p-type impurities. The channel structure may include a lower channel on the upper surface of the impurity region of the substrate and an upper channel contacting the upper surface of the lower channel. The lower channel may have an inclined sidewall and a columnar shape relative to the upper surface of the substrate. The upper channel may have an inclined sidewall relative to the upper surface of the substrate and may have a hollow cylindrical shape. The charge storage structure may cover the outer sidewall of the upper channel. The gate electrode structure may include gate electrodes spaced apart from each other in a vertical direction substantially perpendicular to the upper surface of the substrate. Each of the gate electrodes may cover the outer sidewall of the channel structure or the outer sidewall of the charge storage structure. The width of the upper surface of the charge storage structure may be less than the maximum width of the lower channel.

[0008] According to one aspect of the inventive concept, a vertical memory device may include: a gate electrode structure on a substrate, which includes an impurity region located at an upper portion of the substrate; and a channel on the substrate. The gate electrode structure may include gate electrodes spaced apart from each other in a vertical direction substantially perpendicular to the upper surface of the substrate. The channel may extend in a vertical direction on the substrate through the gate electrode structure and the upper portion of the impurity region of the substrate. The channel may include a plurality of portions stacked sequentially in a vertical direction and connected to each other. Each of the plurality of portions may have an inclined sidewall relative to the upper surface of the substrate. The width of the upper surface of a first portion of the plurality of portions of the channel arranged at an odd level relative to the upper surface of the substrate may be greater than the width of the upper surface of a second portion of the plurality of portions of the channel directly above the first portion.

[0009] In a vertical memory device according to example embodiments, degradation in transistor characteristics due to bending or misalignment of a channel extending in a vertical direction may be reduced or prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1 to 3 are plan views and cross-sectional views illustrating a vertical memory device according to some example embodiments;

[0011] Figure 5 , Figure 8 , Fig.13 and Fig.15 is a plan view illustrating operations in a method of manufacturing a vertical memory device according to some example embodiments;

[0012] Figure 4 , Figure 6-Figure 7 , Figure 9-12 , Fig.14 and Figure 16-Figure 19 is a cross-sectional view illustrating operations in a method of manufacturing a vertical memory device according to some example embodiments;

[0013] Fig. 20 is a cross-sectional view illustrating a vertical memory device according to some example embodiments;

[0014] Fig.21 is a cross-sectional view illustrating a vertical memory device according to some example embodiments;

[0015] Figure 22 to Figure 25 is a cross-sectional view illustrating a method of manufacturing a vertical memory device according to some example embodiments;

[0016] Fig.26 is a cross-sectional view illustrating a vertical memory device according to some example embodiments;

[0017] Figure 27 to Figure 28 is a cross-sectional view illustrating a method of manufacturing a vertical memory device according to some example embodiments; and

[0018] Fig.29 is a cross-sectional view illustrating a vertical memory device according to some example embodiments. DETAILED DESCRIPTION

[0019] The above and other aspects and features of a vertical memory device and a method of manufacturing the same according to some example embodiments will become readily understood from the following detailed description with reference to the accompanying drawings.

[0020] Figures 1 to 3 2 is a plan view and a cross-sectional view showing a vertical memory device according to some example embodiments. Specifically, Figure 1 It is a floor plan. Figure 2 It is along Figure 1 A cross-sectional view taken along line AA', and Figure 3 It is along Figure 1 A cross-sectional view taken along line BB'.

[0021] Hereinafter, a direction substantially perpendicular to the upper surface of the substrate may be defined as a first direction, and two directions substantially parallel to the upper surface of the substrate and intersecting each other may be defined as a second direction and a third direction, respectively. In some example embodiments, the second direction and the third direction are substantially perpendicular to each other.

[0022] Reference Figures 1 to 3 , the vertical memory device may include a gate electrode structure, an insulating pattern structure, and a second structure extending through the gate electrode structure and the insulating pattern structure. The vertical memory device may also include a first impurity region 102 and a second impurity region 104, a separation layer 240, a second barrier layer 280, a second spacer 340, a common source line (CSL) 350, a contact plug 370, a bit line 390, and first to third interlayer insulating layers 250, 360, and 380. In some embodiments, the third interlayer insulating layer 380 may be omitted.

[0023] The substrate 100 may include a semiconductor such as silicon, germanium, silicon-germanium, or a III-V compound such as GaP, GaAs, GaSb, etc. In some embodiments, the substrate 100 may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0024] The first impurity region 102 may be formed at an upper portion of the substrate 100. The first impurity region 102 may include carbon or p-type impurities such as boron.

[0025] The gate electrode structure may include a plurality of gate electrodes respectively located at a plurality of levels, the plurality of gate electrodes being spaced apart from each other in the first direction on the substrate 100. The gate electrode structure may extend in the second direction, and a plurality of gate electrode structures may be formed in the third direction. That is, gate electrode structures adjacent to each other in the third direction in each level among the gate electrode structures (each of which may extend in the second direction) may be spaced apart from each other by the second opening 260 extending in the second direction.

[0026] In some example embodiments, the CSL 350 may be formed in the second opening 260 to extend in the second direction, and the second spacer 340 may be formed on each of opposite sidewalls of the CSL 350 in the third direction. The second impurity region 104 may be formed at an upper portion of the substrate 100 adjacent to a lower surface of the CSL 350.

[0027] The CSL 350 may include metal, metal nitride, and / or metal silicide. The second spacer 340 may include an insulating material such as oxide (eg, silicon oxide), and the second impurity region 104 may include n-type impurities such as phosphorus, arsenic, or the like.

[0028] Each of the gate electrode structures may include at least one first gate electrode 332 , a plurality of second gate electrodes 334 respectively located at a plurality of levels, and at least one third gate electrode 336 , which may be sequentially stacked in a first direction.

[0029] In some example embodiments, the first gate electrode 332 may serve as a ground selection line (GSL), each of the second gate electrodes 334 may serve as a word line, and the third gate electrode 336 may serve as a string selection line (SSL).

[0030] Figure 2Two first gate electrodes 332, four second gate electrodes 334, and two third gate electrodes 336 are shown, respectively, at two levels; however, the inventive concept is not limited thereto. For example, each of the first gate electrode 332 and the third gate electrode 336 may be formed at one level or at multiple levels, respectively, and more than four second gate electrodes 334 may be formed at more than four levels, respectively. Some of the second gate electrodes 334 adjacent to the first gate electrode 332 and / or the third gate electrode 336 may be used as dummy word lines.

[0031] The first gate electrode 332 may include a first gate conductive pattern 322 extending in the second direction and a first gate barrier pattern 312 covering upper and lower surfaces and sidewalls of the first gate conductive pattern 322. The second gate electrode 334 may include a second gate conductive pattern 324 extending in the second direction and a second gate barrier pattern 314 covering upper and lower surfaces and sidewalls of the second gate conductive pattern 324. The third gate electrode 336 may include a third gate conductive pattern 326 extending in the second direction and a third gate barrier pattern 316 covering upper and lower surfaces and sidewalls of the third gate conductive pattern 326.

[0032] The first to third gate conductive patterns 322 , 324 and 326 may include metal having low resistance such as tungsten, titanium, tantalum, platinum, etc., and the first to third gate barrier patterns 312 , 314 and 316 may include metal nitride such as titanium nitride, tantalum nitride, etc.

[0033] The insulating pattern structure may include a plurality of insulating patterns 115 sequentially stacked in a first direction on the substrate 100. The insulating pattern 115 may be formed between an upper surface of the first impurity region 102 and the first gate electrode 332, between the first to third gate electrodes 332, 334, and 336 adjacent to each other in the first direction, and on the third gate electrode 336.

[0034] In some example embodiments, each of the insulating patterns 115 respectively located at a plurality of levels may extend in the second direction, and the plurality of insulating patterns 115 at each level may be spaced apart from each other in the third direction by the second opening 260. The insulating pattern 115 may include an insulating material such as oxide (e.g., silicon oxide).

[0035] Some of the plurality of insulating patterns 115 may be thicker than other insulating patterns 115 of the plurality of insulating patterns 115. The insulating pattern 115 between the lowermost second gate electrode 334 and the uppermost first gate electrode 332 and / or the insulating pattern between the lowermost third gate electrode 336 and the uppermost second gate electrode 334 may be thicker than other insulating patterns 115. For example, one insulating pattern 115 located at the third level relative to the upper surface of the substrate 100, the uppermost insulating pattern 115, and one insulating pattern 115 located at the third level relative to the upper side of the insulating patterns 115 may be thicker than the insulating patterns 115 located at other levels, respectively; however, the inventive concept is not limited thereto.

[0036] The second structure may include a first structure and a pad 230 sequentially stacked on the first impurity region 102 of the substrate 100 , and may extend in the first direction through the gate electrode structure and the insulating pattern structure.

[0037] The first structure may include a channel 215 extending in a first direction from an upper surface of the first impurity region 102 , a charge storage structure 195 covering an outer sidewall of the channel 215 , and a filling pattern 220 filling an inner space formed by the channel 215 .

[0038] In some example embodiments, the channel 215 may have a hollow cylindrical shape or a cup shape, and the filling pattern 220 may fill a space formed by the channel 215. That is, a lower surface and a sidewall of the filling pattern 220 having a columnar shape may be covered by the channel 215.

[0039] The channel 215 may include a semiconductor such as crystalline silicon, and the filling pattern 220 may include an insulating material such as oxide (eg, silicon oxide).

[0040] In some example embodiments, a plurality of channels 215 may be formed in each of the second direction and the third direction, and thus a channel array may be defined. In some example embodiments, the channel array may include: a first channel column 215a including channels 215 arranged in the second direction; and a second channel column 215b including channels 215 arranged in the second direction and spaced apart from the first channel column 215a in the third direction. The channels 215 included in the first channel column 215a may be arranged to form an acute angle with the second direction or the third direction relative to the channels 215 included in the second channel column 215b.

[0041] The first channel columns 215 a and the second channel columns 215 b may be alternately and repeatedly arranged in the third direction. Figure 1Five first channel columns 215 a and four second channel columns 215 b are alternately arranged in the third direction to form a channel group, however, the inventive concept is not limited thereto.

[0042] Hereinafter, the four channel columns arranged in the third direction in one channel group may be referred to as the first channel column 215a, the second channel column 215b, the third channel column 215c, and the fourth channel column 215d, respectively. In this order, one channel column located in the middle in the third direction in the channel group may be referred to as the fifth channel column 215e, and the other four channel columns arranged in the third direction in the channel group may be referred to as the first channel column 215a, the second channel column 215b, the third channel column 215c, and the fourth channel column 215d, respectively, again in this order. Figure 1 A channel array including one channel group and a portion of another channel group spaced apart from each other in a third direction is shown. Each of the channel groups may include two channel blocks arranged in the third direction, and the fifth channel column 215e may be arranged between the two channel blocks.

[0043] In some example embodiments, the charge storage structure 195 covering the outer sidewall of the channel 215 may have a cup shape whose bottom may be open. The charge storage structure 195 may include a tunnel insulating pattern 185 , a charge storage pattern 175 , and a first barrier pattern 165 sequentially stacked from the outer sidewall of the channel 215 .

[0044] The tunnel insulating pattern 185 and the first barrier pattern 165 may include an insulating material such as oxide (eg, silicon oxide), and the charge storing pattern 175 may include a different insulating material such as nitride (eg, silicon nitride).

[0045] The first structure may have a pillar shape extending in a first direction from an upper surface of the first impurity region 102 at an upper portion of the substrate 100, and the second structure including the first structure and the pad 230 may have a pillar shape. The pad 230 may include, for example, doped crystalline silicon.

[0046] In some example embodiments, the second structure may include a lower portion and an upper portion that may be integrally formed and in contact with each other, each of which may have an inclined sidewall relative to the upper surface of the substrate 100. The upper surface of the lower portion of the second structure may have a first width W1 in a horizontal direction substantially parallel to the upper surface of the substrate 100, and the lower surface of the lower portion of the second structure may have a second width W2 in the horizontal direction that may be smaller than the first width W1. In addition, the upper surface of the upper portion of the second structure may have a third width W3 in the horizontal direction, and the lower surface of the upper portion of the second structure may have a fourth width W4 in the horizontal direction that may be smaller than the third width W3.

[0047] In some example embodiments, the first width W1 may be greater than the third width W3, and the third width W3 may be greater than the second width W2. In some example embodiments, the fourth width W4 may be smaller than the second width W2.

[0048] Since the first width W1 may be greater than the third width W3, when forming a reference Figure 8 and Fig. 9 In the described process of forming the first upper holes 140 , each of the first upper holes 140 may easily expose the upper surface of each of the second sacrificial layers 130 , and thus the second structure may have a desired structure.

[0049] In some example embodiments, a portion of the second structure corresponding to the first gate electrode 332 may have a width in the horizontal direction equal to or less than the third width W3. The second structures are preferably formed close to each other to increase integration, however, if the second structures are too close to each other, then Figures 15 to 18 In the gate replacement process described above, the gate electrode may not fill the gap 270 between the second structures (see Fig.16 ), so that a gap can be formed. Therefore, in the design step, when the second structure has the third width W3, a minimum and / or desired distance between the second structures (where the gate electrode can be formed without a gap) can be ensured, and therefore, it is not necessary to form a gate electrode in a region where the second structure has a width greater than the third width W3.

[0050] The upper surface of the lower portion of the second structure has a first width W1 greater than the third width W3 of the upper surface of the upper portion thereof, however, the width of the lower portion of the second structure may gradually decrease from the top toward the bottom thereof, and thus the gate electrode may be formed only at a height where the width of the lower portion of the second structure is equal to or less than the third width W3, so that no void may be formed in the gate electrode. That is, a portion of the second structure corresponding to the upper surface of the first gate electrode 332 located at the second level relative to the upper surface of the substrate 100 may have a width in the horizontal direction equal to or less than the third width W3.

[0051] Contact plug 370 may be formed on pad 230, and bit line 390 may be formed on contact plug 370. Contact plug 370 may extend through first and second interlayer insulating layers 250 and 360 to contact pad 230, and bit line 390 may extend through third interlayer insulating layer 380 to contact contact plug 370.

[0052] The contact plug 370 and the bit line 390 may include a metal such as copper, aluminum, tungsten, titanium, tantalum, etc. and / or a metal nitride such as titanium nitride, tantalum nitride, tungsten nitride, etc., and the first to third interlayer insulating layers 250, 360 and 380 may include an insulating material such as an oxide (e.g., silicon oxide).

[0053] The separation layer 240 may extend downward in the first direction from the topmost insulating pattern 115 toward a portion of an insulating pattern 115 located at a third level relative to the top, and thus the third gate electrode 336 located at each level higher than the third level relative to the top may be divided into multiple blocks in the third direction.

[0054] In some example embodiments, the partition layer 240 may extend in the second direction between two channel blocks in one channel group and may extend through the channels 215 included in the fifth channel column 215e. The partition layer 240 may extend in the first direction to a portion of one of the insulating patterns 115 on the uppermost one of the second gate electrodes 334.

[0055] The second barrier layer 280 may be formed on the lower and upper surfaces and a portion of the sidewalls of each of the first to third gate electrodes 332, 334, and 336 and the sidewalls of each insulating pattern 115. The second barrier layer 280 may also contact the sidewalls of the charge storage structure 195.

[0056] Figures 4 to 19 are plan views and cross-sectional views illustrating a method of manufacturing a vertical memory device according to some example embodiments. Specifically, Figure 5 , Figure 8 , Fig.13 and Fig.15 is a plan view, and Figure 4 , Figure 6-Figure 7 , Figure 9-12 , Fig.14 and Figure 16-Figure 19 It is a cross-sectional view. Figure 4 , Figure 6-Figure 7 , Figure 9-12 , Fig.14 and Figure 16-Figure 19 are cross-sectional views taken along line AA' of the corresponding plan view, and Fig.14 It is along Fig.13 A cross-sectional view taken along line BB'.

[0057] Reference Figure 4 , the first impurity region 102 may be formed at an upper portion of the substrate 100 , and the insulating layer 110 and the first sacrificial layer 120 may be alternately and repeatedly formed on the first impurity region 102 in a first direction.

[0058] The first impurity region 102 may be formed by doping carbon or one or more p-type impurities (eg, boron) in an upper portion of the substrate 100 .

[0059] In some example embodiments, the insulating layer 110 may be formed at three levels, and the first sacrificial layer 120 may be formed at two levels, however, the present inventive concept is not limited thereto. Figure 4 The insulating layers 110 and the first sacrificial layers 120 formed by the described process may be stacked at a level greater than that which is subsequently referred to as Figure 7 The number of levels at which the respective insulating layers 110 and the respective first sacrificial layers 120 formed by the described process may be stacked is much smaller.

[0060] The uppermost insulating layer 110 may be thicker than the other insulating layers 110 located at lower levels, respectively.

[0061] The insulating layer 110 and the first sacrificial layer 120 may be formed by a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, an atomic layer deposition (ALD) process, etc. The insulating layer 110 may include an insulating material such as an oxide (e.g., silicon oxide), and the first sacrificial layer 120 may include a different insulating material such as a nitride (e.g., silicon nitride).

[0062] Reference Figure 5 and Figure 6 , a second sacrificial layer 130 may be formed through the insulating layer 110 and the first sacrificial layer 120 to contact the first impurity region 102 located at an upper portion of the substrate 100 .

[0063] A photoresist pattern (not shown) may be formed on the uppermost one of the insulating layers 110. The insulating layer 110 and the first sacrificial layer 120 may be etched using the photoresist pattern as an etching mask to form first lower holes exposing the upper surface of the first impurity region 102. The second sacrificial layers 130 may be formed to fill the first lower holes, respectively.

[0064] In some example embodiments, the first impurity region 102 may be used as an etch stop layer in an etching process. The first impurity region 102 may include silicon doped with carbon or one or more p-type impurities, and thus, the first impurity region 102 may have an increased etching selectivity with respect to the insulating layer 110 and the first sacrificial layer 120, which respectively include silicon oxide and silicon nitride, compared to the substrate 100 including silicon. In the etching process for forming the first lower hole, a recess may not be formed on the substrate 100. That is, the first lower hole may be formed to have a uniform depth, and the second sacrificial layer 130 filling the first lower hole may have a uniform thickness.

[0065] In some example embodiments, due to the general characteristics of the etching process, each of the first lower holes may have a width that gradually decreases from the top toward the bottom thereof. Therefore, the sidewall of each of the first lower holes may not be vertical, but may be inclined relative to the upper surface of the substrate 100. Therefore, each of the second sacrificial layers 130 filling each of the first lower holes may also have an inclined sidewall. That is, the upper surface of each of the second sacrificial layers 130 may have a first width W1 in a horizontal direction substantially parallel to the upper surface of the substrate 100, and the lower surface of each of the second sacrificial layers 130 may have a second width W2 that is smaller than the first width W1.

[0066] In some example embodiments, a plurality of first lower holes may be formed in each of the second direction and the third direction to form a lower hole array. The description of the lower hole array may be replaced by the description of the upper hole array to be shown later.

[0067] The second sacrificial layer 130 may include a material having an etch selectivity with respect to the insulating layer 110 and the first sacrificial layer 120 , for example, polysilicon.

[0068] Reference Figure 7 The insulating layer 110 and the first sacrificial layer 120 may be alternately and repeatedly formed again on the second sacrificial layer 130 and the first sacrificial layer 120 previously formed on the second sacrificial layer 130. Figure 5 and Figure 6 On the topmost insulating layer 110 formed in the process.

[0069] Figure 7 It is shown that the insulating layer 110 is formed at seven levels, and the first sacrificial layer 120 is formed at six levels, respectively; however, the inventive concept is not limited thereto. Therefore, the insulating layer 110 and the first sacrificial layer 120 may be formed at another number of levels, respectively.

[0070] One insulating layer 110 on the second sacrificial layer 130 may be merged with one insulating layer 110 covering the sidewall of the second sacrificial layer 130 and may be thicker than other insulating layers 110 at other levels with respect to one insulating layer 110 above. However, the inventive concept is not limited thereto.

[0071] Reference Figure 8 and Fig. 9 A photoresist pattern (not shown) may be formed on the uppermost insulating layer 110, and the insulating layer 110 and the first sacrificial layer 120 may be etched using the photoresist pattern as an etching mask to form first upper holes 140 that respectively expose upper surfaces of the second sacrificial layers 130.

[0072] In some example embodiments, each of the first upper holes 140 may have a width that gradually decreases from its top toward its bottom due to general characteristics of the etching process. Therefore, the sidewall of each of the first upper holes 140 may not be vertical but may be inclined relative to the upper surface of the substrate 100. Therefore, the top of each of the first upper holes 140 may have a third width W3 in the horizontal direction, and the bottom of each of the first upper holes 140 corresponding to the upper surface of each of the second sacrificial layers 130 may have a fourth width W4 that is smaller than the third width W3.

[0073] In some example embodiments, the third width W3 of the top of each of the first upper holes 140 may be smaller than the first width W1 of the upper surface of each of the second sacrificial layers 130, and may be larger than the second width W2 of the lower surface of each of the second sacrificial layers 130. Therefore, the fourth width W4 of the bottom of the first upper hole 140 corresponding to the upper surface of each of the second sacrificial layers 130 may also be smaller than the first width W1. In some example embodiments, the fourth width W4 of the bottom of each of the first upper holes 140 may be smaller than the second width W2 of the lower surface of each of the second sacrificial layers 130.

[0074] Since the first width W1 of the upper surface of each of the second sacrificial layers 130 may be greater than the fourth width W4 of the bottom of each of the first upper holes 140, each of the first upper holes 140 may easily expose the upper surface of each of the second sacrificial layers 130. Each of the first upper holes 140 may extend through a certain number of levels of the insulating layer 110 and the first sacrificial layer 120 and thus may be bent at a lower portion thereof, and each of the first upper holes 140 may not be accurately formed on the upper surface of each of the second sacrificial layers 130 due to misalignment. However, the first width W1 of the upper surface of each of the second sacrificial layers 130 may be greater, and thus each of the first upper holes 140 may easily expose the upper surface of each of the second sacrificial layers 130 even in the presence of the above phenomenon.

[0075] The first upper holes 140 may have a depth distribution such that each of the plurality of first upper holes 140 may expose an upper surface of each of the second sacrificial layers 130 , and thus the bottoms of the first upper holes 140 may have a height distribution in the second sacrificial layers 130 . Fig. 9 The first upper hole 140 having bottoms at first height H1 and second height H2, respectively, is shown. However, the second sacrificial layer 130 may be removed later, and thus even though the first upper hole 140 may have a depth profile, characteristics of a channel that may be formed in the first upper hole 140 may not change.

[0076] In order to increase the integration degree, the number of the first upper holes 140 in each unit area may be increased to form as many channels as possible. However, if the distance between the channels is reduced too much, then Figures 16 to 18 In the gate replacement process described above, the gap 270 (see Fig.16 ) may not allow the gate electrode to be formed well.

[0077] Therefore, the third width W3 of the top of each of the first upper holes 140 may be determined based on the maximum distance between the first upper holes 140 in which the gate electrode is well formed between the channels. In addition, the first width W1 of the upper surface of each of the second sacrificial layers 130 corresponding to each of the first upper holes may be greater than the third width W3, however, each of the second sacrificial layers 130 may have an inclined sidewall having a width that decreases in a horizontal direction from the top toward the bottom thereof, and thus the first sacrificial layer 120 may be formed at a height at which the width of each of the second sacrificial layers 130 in the horizontal direction may be equal to or less than the third width W3, so that the gate electrode may be well formed in the gap 270.

[0078] Therefore, in some example embodiments, a portion of the second sacrificial layer 130 corresponding to an upper surface of one of the first sacrificial layers 120 located at a second level relative to the upper surface of the substrate 100 may have a width in the horizontal direction that is equal to or less than a third width W3 of the top of each of the first upper holes 140.

[0079] A plurality of first upper holes 140 may be formed in each of the second direction and the third direction, and thus may define an upper hole array. In some example embodiments, the upper hole array may include: a first upper hole row 140a including first upper holes 140 arranged in the second direction; and a second upper hole row 140b including first upper holes 140 arranged in the second direction and spaced apart from the first upper hole row 140a in the third direction. The first upper holes 140 included in the first upper hole row 140a may be arranged to have an acute angle with the second direction or the third direction relative to the first upper holes 140 included in the second upper hole row 140b.

[0080] The first upper hole row 140a and the second upper hole row 140b may be alternately and repeatedly arranged in the third direction. In some example embodiments, five first upper hole rows 140a and four second upper hole rows 140b may be alternately arranged in the third direction, thus forming an upper hole group.

[0081] Hereinafter, four upper hole rows arranged in the third direction in one upper hole group may be referred to as the first upper hole row 140a, the second upper hole row 140b, the third upper hole row 140c, and the fourth upper hole row 140d in this order, respectively, an upper hole row in the upper hole group located in the middle in the third direction may be referred to as the fifth upper hole row 140e, and the other four upper hole rows arranged in the third direction in the upper hole group may also be referred to as the first upper hole row 140a, the second upper hole row 140b, the third upper hole row 140c, and the fourth upper hole row 140d in this order. The first to fourth upper hole rows 140a, 140b, 140c, and 140d arranged in the third direction may define an upper hole block.

[0082] Reference Fig.10 , the second sacrificial layer 130 exposed through the first upper hole 140 may be removed, so that the first lower hole may be formed again.

[0083] The first lower hole may be formed by removing the second sacrificial layer 130 previously formed through the insulating layer 110 and the first sacrificial layer 120 , so that the first lower hole is limited by the size of the second sacrificial layer 130 .

[0084] Hereinafter, the first lower hole and the first upper hole 140 may be referred to as a first channel hole 142. The first channel hole 142 may include a lower portion and an upper portion connected to each other, and each of the lower portion and the upper portion of the first channel hole 142 may have an inclined sidewall.

[0085] The charge storage structure layer 190 and the third sacrificial layer 200 may be sequentially formed on the sidewalls of the first channel hole 142 , on the upper surface of the first impurity region 102 , and on the upper surface of the uppermost one of the insulating layers 110 .

[0086] In some example embodiments, the charge storage structure layer 190 may include a first blocking layer 160, a charge storage layer 170, and a tunnel insulating layer 180 that are sequentially stacked. For example, the first blocking layer 160, the charge storage layer 170, and the tunnel insulating layer 180 may include silicon oxide, silicon nitride, and silicon oxide, respectively, and the third sacrificial layer 200 may include, for example, polysilicon.

[0087] Reference Fig.11 , a first spacer layer (not shown) may be formed on the third sacrificial layer 200 , and may be anisotropically etched to form first spacers (not shown) on sidewalls of the first channel holes 142 .

[0088] The third sacrificial layer 200, the tunnel insulating layer 180, the charge storage layer 170, and the first barrier layer 160 may be sequentially etched using the first spacer as an etching mask to form a third sacrificial pattern (not shown), a tunnel insulating pattern 185, a charge storage pattern 175, and a first barrier pattern 165 having a cup shape with its bottom open, respectively, on the sidewall of the first channel hole 142 and the first impurity region 102. The upper portion of the first impurity region 102 may also be removed. The tunnel insulating pattern 185, the charge storage pattern 175, and the first barrier pattern 165 may form a charge storage structure 195.

[0089] After removing the first spacer and the third sacrificial pattern, a channel layer 210 may be formed on the exposed first impurity region 102, the tunnel insulating pattern 185, and the uppermost insulating layer 110. The channel layer 210 may include polycrystalline silicon or amorphous silicon. When the channel layer 210 includes amorphous silicon, a laser epitaxial growth (LEG) process or a solid phase epitaxy (SPE) process may be performed so that the channel layer 210 may include crystalline silicon.

[0090] Reference Fig.12 A filling layer may be formed on the channel layer 210 to fill the first channel hole 142 , and the filling layer and the channel layer 210 may be planarized until the uppermost insulating layer 110 may be exposed, thereby forming a filling pattern 220 filling the first channel hole 142 , and the channel layer 210 may be transformed into a channel 215 .

[0091] Thus, the charge storing structure 195 , the channel 215 , and the filling pattern 220 may be sequentially stacked on the first impurity region 102 in the first channel hole 142 .

[0092] Since the first upper holes 140 included in the first channel holes 142 define first to fifth upper hole columns 140a, 140b, 140c, 140d and 140e, upper hole blocks, upper hole groups and upper hole arrays, the channels 215 in the first channel holes 142 may also define first to fifth channel columns 215a, 215b, 215c, 215d and 215e (see Fig.15 ), channel blocks, channel groups and channel arrays.

[0093] The channel 215 having a hollow cylindrical shape, the charge storage structure 195 covering the outer sidewall of the channel 215 , and the filling pattern filling the inner space defined by the inner sidewall of the channel 215 may form a first structure having a pillar shape.

[0094] An upper portion of the first structure may be removed to form a trench, and a pad 230 may be formed to fill the trench.

[0095] In some example embodiments, the pad 230 may include polysilicon or amorphous silicon doped with impurities, and when the pad 230 includes amorphous silicon, a crystallization process may further be performed.

[0096] Hereinafter, the first structure and the pad 230 thereon may be referred to as a second structure.

[0097] Reference Fig.13 and Fig.14 , the separation layer 240 may be formed through the first sacrificial layer 120 and the insulating layer 110 located at an upper level.

[0098] The separation layer 240 may be formed by forming an etching mask (not shown) on the uppermost insulating layer 110; etching the first sacrificial layer 120 and the insulating layer 110 using the etching mask to form a first opening (not shown) therethrough; and filling the first opening. In some example embodiments, the first opening may extend to a portion of the insulating layer 110 located at a third level relative to the upper side, however, the inventive concept is not limited thereto. The upper level first sacrificial layer 120 may be divided by the separation layer 240.

[0099] In some example embodiments, the separation layer 240 may extend between two channel blocks in one channel group in the second direction, and may extend through upper portions of the channels 215 included in the fifth channel column 215 e .

[0100] Reference Fig.15 and Fig.16 , a first interlayer insulating layer 250 may be formed on the uppermost insulating layer 110, the pad 230 and the separation layer 240, and a second opening 260 may be formed through the first interlayer insulating layer 250, the insulating layer 110, the first sacrificial layer 120 and the first impurity region 102, and a portion of the substrate 100 below the first impurity region 102 may also be removed.

[0101] In some example embodiments, the second openings 260 may extend between the channel groups in the second direction, and a plurality of second openings 260 may be formed in the third direction. That is, one channel group may be arranged between adjacent ones of the second openings 260 in the third direction, and the channel group may include two channel blocks each including four channel columns at each of opposite sides of the fifth channel column 215e in the third direction.

[0102] As the second openings 260 may be formed, the insulating layer 110 may be transformed into the insulating patterns 115 each extending in the second direction, and the first sacrificial layer 120 may be transformed into first sacrificial patterns (not shown) each extending in the second direction.

[0103] The first sacrificial pattern exposed through the second opening 260 may be removed to form a gap 270 between the insulating patterns 115 at each level. A portion of the outer sidewall of the first barrier pattern 165 may be exposed through the gap 270.

[0104] In some example embodiments, the first sacrificial pattern exposed through the second opening 260 may be removed through a wet etching process using an etchant including phosphoric acid and / or sulfuric acid.

[0105] Reference Fig.17 , after a second barrier layer 280 may be formed on the exposed portion of the outer sidewall of the first barrier pattern 165, the inner wall of the gap 270, the surface of the insulating pattern 115, the upper surface of the substrate 100, and the upper surface of the first interlayer insulating layer 250, a gate barrier layer 290 may be formed on the second barrier layer 280, and a gate conductive layer 300 may be formed on the gate barrier layer 290 to fill the remaining portion of the gap 270.

[0106] As described above, the second structures may be spaced apart from each other by a suitable distance, and thus the gate conductive layer 300 may well fill the gap 270 even between the second structures. That is, each of the second structures may include a lower portion and an upper portion, and the gap 270 may be formed only in an area of ​​the lower portion of the second structure whose width is less than the third width W3 (which may be the maximum width of the upper portion of the second structure). When each of the second structures includes a width equal to or less than the third width W3, the gap 270 may be well filled by the gate conductive layer 300; and thus, the gate conductive layer 300 at a lower level may be formed without a void therein.

[0107] In some example embodiments, the second blocking layer 280 may include a metal oxide such as aluminum oxide, hafnium oxide, zirconium oxide, etc., the gate barrier layer may include a metal nitride such as titanium nitride, tantalum nitride, etc., and the gate conductive layer 300 may include a low-resistance metal such as tungsten, titanium, tantalum, etc.

[0108] Reference Fig.18 , the gate conductive layer 300 and the gate barrier layer 290 may be partially removed to form a gate conductive pattern and a gate barrier pattern, respectively, in the gap 270, so that a gate electrode may be formed. In some example embodiments, the gate conductive layer 300 and the gate barrier layer 290 may be removed by a wet etching process, and thus the gate electrode may partially fill the gap 270.

[0109] The gate electrode may extend in the second direction, and a plurality of gate electrodes may be formed in the third direction. Therefore, the gate electrodes each extending in the second direction may be spaced apart from each other by the second opening 260 .

[0110] In some example embodiments, the gate electrodes may be respectively formed at a plurality of levels spaced apart from each other in the first direction, and a gate electrode structure may be formed. The gate electrode structure may include at least one first gate electrode 332, a plurality of second gate electrodes 334, and at least one third gate electrode 336 stacked sequentially. The number of levels at which each of the first to third gate electrodes 332, 334, and 336 is formed may vary.

[0111] Fig.18 Two first gate electrodes 332 are respectively located at two levels, four second gate electrodes 334 are respectively located at four levels, and two third gate electrodes 336 are respectively located at two levels; however, the inventive concept is not limited thereto. For example, the second gate electrodes 334 may be respectively formed at many levels.

[0112] In some example embodiments, the first gate electrode 332 may be used as a ground selection line (GSL), the second gate electrode 334 may be used as a word line, and the third gate electrode 336 may be used as a string selection line (SSL). Some second gate electrodes 334 adjacent to the first gate electrode 332 and / or the third gate electrode 336 may be used as dummy word lines.

[0113] Reference Fig.19 , impurities may be implanted into the upper portion of the substrate 100 through a portion of the second blocking layer 280 exposed as the gate conductive layer 300 and the gate barrier layer 290 are partially removed, thereby forming the second impurity region 104. In some example embodiments, the impurities may include n-type impurities such as phosphorus, arsenic, etc.

[0114] The second spacer layer may be formed on the second barrier layer 280 and may be anisotropically etched to form second spacers 340 on sidewalls of the second opening 260 , and thus may expose a portion of the second barrier layer 280 on the second impurity region 104 .

[0115] The second barrier layer 280 may be etched using the second spacer 340 as an etching mask, and a portion of the second barrier layer 280 on the first interlayer insulating layer 250 may also be removed. An upper portion of the second impurity region 104 of the upper portion of the substrate 100 may also be partially removed.

[0116] A conductive layer may be formed on the upper surface of the second impurity region 104 , the second spacer 340 , and the first interlayer insulating layer 250 , and may be planarized until the upper surface of the first interlayer insulating layer 250 may be exposed to form the CSL 350 .

[0117] In some example embodiments, the CSL 350 may extend in the first direction and also extend in the second direction. A lower surface of the CSL 350 may be covered by the second impurity region 104 .

[0118] Refer to Figures 1 to 3 , a second interlayer insulating layer 360 may be formed on the first interlayer insulating layer 250, the CSL 350, the second spacer 340, and the second barrier layer 280, and a contact plug 370 may be formed through the first interlayer insulating layer 250 and the second interlayer insulating layer 360 to contact the upper surface of the pad 230. A third interlayer insulating layer 380 may be formed on the second interlayer insulating layer 360 and the contact plug 370, and a bit line 390 may be formed through the third interlayer insulating layer 380 to contact the upper surface of the contact plug 370.

[0119] In some example embodiments, the bit line 390 may extend in the third direction, and a plurality of the bit lines 390 may be formed in the second direction.

[0120] A vertical memory device may be manufactured through the above process.

[0121] As shown above, after forming the first impurity region 102 at the upper portion of the substrate 100, the insulating layer 110 and the first sacrificial layer 120 may be alternately and repeatedly formed at several levels, and the first lower hole may be formed through the insulating layer 110 and the first sacrificial layer 120 to expose the first impurity region 102. The first impurity region 102 may serve as an etch stop layer, and thus the first lower hole may have a uniform depth, and thus no recess may be formed on the substrate 100.

[0122] After forming the second sacrificial layers 130 to fill the first lower holes, respectively, the insulating layer 110 and the first sacrificial layer 120 may be alternately and repeatedly formed at a plurality of levels, and the first upper holes 140 may be formed through the insulating layer 110 and the first sacrificial layer 120. The upper surface of each of the second sacrificial layers 130 may have a first width W1 greater than the third width W3 (which may be the maximum width of each of the first upper holes 140); and therefore, even if bending or misalignment may occur in the first upper holes 140, each of the first upper holes 140 may expose each of the second sacrificial layers 130.

[0123] The second sacrificial layer 130 may be removed to form the charge storage structure 195 and the channel 215 in the first channel hole 142 including the first lower hole and the first upper hole 140 , and thus, even if the first upper hole 140 has a depth profile, characteristics of the charge storage structure 195 and the channel 215 may not be deteriorated.

[0124] Fig. 20 is a cross-sectional view illustrating a vertical memory device according to some example embodiments. Fig. 20 It is along Figure 1 A cross-sectional view taken along line AA'.

[0125] In addition to the first gate electrode and the second gate electrode, the vertical memory device may be connected to Figures 1 to 3Therefore, the same reference numerals refer to the same elements, and detailed description thereof is omitted herein.

[0126] Reference Fig. 20 , the first gate electrode 332 in the gate electrode structure of the vertical memory device may be formed at the lowest level relative to the upper surface of the substrate 100 , and the second gate electrode 334 may be formed at a second level relative to the upper surface of the substrate 100 .

[0127] That is to say, in reference Figures 1 to 3 In the vertical memory device described above, the first gate electrode 332 used as the GSL may be formed at two levels with respect to the upper surface of the substrate 100; however, in reference to Fig. 20 In the described vertical memory device, the first gate electrode 332 used as the GSL may be formed only at one level, for example, the lowest level relative to the upper surface of the substrate 100. One of the second gate electrodes 334 at a level directly above that of the first gate electrode 332 may be used as a dummy word line.

[0128] Fig.21 is a cross-sectional view illustrating a vertical memory device according to some example embodiments. Fig.21 It is along Figure 1 A cross-sectional view taken along line AA'.

[0129] In addition to the shape of the second structure, the vertical memory device can be Figures 1 to 3 Therefore, the same reference numerals refer to the same elements, and detailed description thereof is omitted herein.

[0130] Reference Fig.21 , the second structure of the vertical memory device may include a first portion, a second portion, a third portion, and a fourth portion sequentially stacked on the substrate 100 .

[0131] In some example embodiments, the upper surfaces of the first and third portions of the second structure may have substantially the same width as each other, and the lower surfaces of the first and third portions of the second structure may have substantially the same width as each other. In addition, the upper surfaces of the second and fourth portions of the second structure may have substantially the same width as each other, and the lower surfaces of the second and fourth portions of the second structure may have substantially the same width as each other.

[0132] In some example embodiments, the first portion and the second portion of the second structure may have the same Figures 1 to 3 The lower and upper parts of the second structure described in the embodiment of the present invention have substantially the same shape. In addition, the third and fourth parts of the second structure may have substantially the same shape as the reference part. Figures 1 to 3 The shapes of the lower and upper parts of the second structure are described as being substantially the same shape.

[0133] That is to say, Fig.21 The second structure may include sequential stacking of Figure 2 However, the first gate electrode 332 may be formed at a height corresponding to the first portion of the second structure, the second gate electrode 334 may be formed at a height corresponding to the second portion and the third portion and the lower portion of the fourth portion of the second structure, and the third gate electrode 336 may be formed at a height corresponding to the upper portion of the fourth portion of the second structure.

[0134] In the drawings, the second structure includes first to fourth parts stacked sequentially, however, the inventive concept is not limited thereto, and the second structure may include a plurality of parts, for example, an even number of parts stacked sequentially.

[0135] Figure 22 to Figure 25 is a cross-sectional view showing a method of manufacturing a vertical memory device according to some example embodiments. The method may be similar to that described in reference to Figures 4 to 19 The described methods are substantially the same or similar, and thus a detailed description thereof is omitted herein.

[0136] Reference Fig. 22 , executable and reference Figures 4 to 9 Processes substantially the same or similar to those described herein.

[0137] However, the insulating layer 110 and the first sacrificial layer 120 may be formed on the second sacrificial layer 130 only at some levels of all levels where the insulating layer 110 and the first sacrificial layer 120 need to be formed, and the fourth sacrificial layer 150 may be formed in the first upper hole 140 extending through the insulating layer 110 and the first sacrificial layer 120 to expose the upper surface of the second sacrificial layer 130.

[0138] The fourth sacrificial layer 150 may include, for example, polysilicon, and thus may be merged with the underlying second sacrificial layer 130 .

[0139] Reference Fig.23 , can be executed and referenced again Figures 4 to 9 Processes substantially the same or similar to those described herein.

[0140] That is, the insulating layer 110 and the first sacrificial layer 120 may be formed at several levels (e.g., three levels and two levels) on the fourth sacrificial layer 150, respectively, and the fifth sacrificial layer 135 may be formed through the insulating layer 110 and the first sacrificial layer 120 to respectively contact the upper surface of the fourth sacrificial layer 150. The insulating layer 110 and the first sacrificial layer 120 may be formed at other levels on the fifth sacrificial layer 135, and the second upper hole 144 may be formed through the insulating layer 110 and the first sacrificial layer 120 to respectively expose the upper surface of the fifth sacrificial layer 135.

[0141] In some example embodiments, each of the fifth sacrificial layers 135 may have a size and shape substantially the same as or similar to those of each of the second sacrificial layers 130, and a width of a top of each of the second upper holes 144 corresponding to an upper surface of each of the fifth sacrificial layers 135 and a width of a bottom of each of the second upper holes 144 may be substantially the same as or similar to a width of an upper surface of each of the fourth sacrificial layers 150 and a width of a bottom of each of the fourth sacrificial layers 150 corresponding to an upper surface of each of the second sacrificial layers 130. Therefore, each of the second upper holes 144 may be formed to easily expose an upper surface of each of the fifth sacrificial layers 135.

[0142] Reference Fig.24 The fifth sacrificial layer 135 exposed through the second upper hole 144 and the second sacrificial layer 130 and the fourth sacrificial layer 150 thereunder may be removed, so that a second channel hole 146 exposing the first impurity region 102 may be formed at an upper portion of the substrate 100 .

[0143] Reference Fig.25 , executable and reference Figures 10 to 12 Processes substantially the same or similar to those described herein.

[0144] Refer to Fig.21 , executable and reference Figures 13 to 19 and Figures 1 to 3 Processes substantially the same or similar to those described herein may be used to complete the fabrication of the vertical memory device.

[0145] As shown above, after forming the second sacrificial layer 130, instead of forming the insulating layer 110 and the first sacrificial layer 120 at a desired number of layers and forming the upper channel hole therethrough, only some of the insulating layer 110 and the first sacrificial layer 120 may be formed at lower levels, and the upper channel hole may be formed therethrough. Therefore, a bending phenomenon of the upper channel hole that may occur due to formation through many levels may be alleviated. In addition, the process for forming the insulating layer 110 and the first sacrificial layer 120 and forming the upper channel hole may be divided into a plurality of processes, and thus misalignment and positional deviation generated during the process may be corrected between the divided processes.

[0146] The present invention is not limited to the Figure 22 to Figure 24 The number of processes described is small, and when the number of stacked insulating layers 110 and first sacrificial layers 120 is large, the formation of the sacrificial layers and the upper channel holes may be divided into a greater number of formations.

[0147] Fig.26 is a cross-sectional view illustrating a vertical memory device according to some example embodiments. Fig.26 It is along Figure 1A cross-sectional view taken along line AA'.

[0148] In addition to the shape of the second structure, the vertical memory device can be Figures 1 to 3 Therefore, the same reference numerals refer to the same elements, and detailed description thereof is omitted herein.

[0149] Reference Fig.26 The vertical memory device may also include a semiconductor pattern 400 located on the first impurity region 102 at the upper portion of the substrate 100, and a second structure may be formed on the semiconductor pattern 400, the second structure including a first structure having a channel 215, a charge storage structure 195 and a filling pattern 220, and a pad 230.

[0150] The semiconductor pattern 400 may serve as a channel of the first gate electrode 332 , and thus the semiconductor pattern 400 and the channel 215 may be referred to as a lower channel and an upper channel, respectively.

[0151] The fifth width W5 of the upper surface of the semiconductor pattern 400 (which may be the maximum width of the semiconductor pattern 400) may be greater than the seventh width W7 of the upper surface of the second structure. In addition, the eighth width W8 of the bottom of the second structure corresponding to the upper surface of the semiconductor pattern 400 may be smaller than the fifth width W5 of the upper surface of the semiconductor pattern 400. The sixth width W6 of the lower surface of the semiconductor pattern 400 may be smaller than the fifth width W5 of the upper surface of the semiconductor pattern 400.

[0152] The lower surface of the second structure may have a height distribution, however, it may be located between the lower surface and the upper surface of one of the insulating patterns 115 corresponding to the upper surface of the semiconductor pattern 400. Therefore, the characteristics of the transistor may not be deteriorated due to the height distribution. Fig.26 , the second structure includes lower surfaces having fifth and sixth heights H5 and H6, respectively.

[0153] Figure 27 to Figure 28 is a cross-sectional view showing a method of manufacturing a vertical memory device according to some example embodiments. The method may include Figures 4 to 19 The processes described are substantially the same or similar processes, and thus a detailed description thereof is omitted herein.

[0154] Reference Fig. 27 , executable and reference Figures 4 to 6 The processes described are essentially the same or similar processes.

[0155] However, the second sacrificial layer 130 is not formed in each of the first lower holes, but the semiconductor pattern 400 may be formed therein.

[0156] A selective epitaxial growth (SEG) process may be performed using the upper surface of the substrate 100 exposed through the first lower holes as a seed to form a semiconductor pattern 400 in each of the first lower holes. Therefore, the semiconductor pattern 400 may include single crystal silicon or single crystal germanium according to the material of the substrate 100. In some embodiments, n-type or p-type impurities may be implanted into the semiconductor pattern 400.

[0157] In some example embodiments, the semiconductor pattern 400 may be formed such that an upper surface of the semiconductor pattern 400 may be located between a lower surface and an upper surface of an uppermost insulating layer 110. The upper surface of the semiconductor pattern 400 may have a height distribution, however, the height distribution may not be too large.

[0158] When the first lower hole is formed by an etching process, the first impurity region 102 may be used as an etching stop layer, so that a recess may not be formed on the substrate 100, and the first lower hole may have a uniform depth. In addition, the number of the insulating layer 110 and the first sacrificial layer 120 may not be too high, and thus the heights of the upper surfaces of the semiconductor pattern 400 extending through the insulating layer 110 and the first sacrificial layer 120 may be substantially the same or similar to each other. In the drawings, the semiconductor pattern 400 includes upper surfaces having third and fourth heights H3 and H4, respectively, which may be substantially the same as each other.

[0159] However, the first impurity region 102 may not be formed, and in this case, a height distribution of the upper surface of the semiconductor pattern 400 may increase.

[0160] Reference Fig.28 , executable and reference Figures 7 to 9 The processes described are essentially the same or similar processes.

[0161] However, the first upper holes 140 may expose upper surfaces of the semiconductor patterns 400 , respectively.

[0162] In some example embodiments, a fifth width W5 of the upper surface of the semiconductor pattern 400 (which may be the maximum width of the semiconductor pattern 400) may be greater than a seventh width W7 of the top of the first upper hole 140. In addition, an eighth width W8 of the bottom of the first upper hole 140 corresponding to the upper surface of the semiconductor pattern 400 may be smaller than the fifth width W5 of the upper surface of the semiconductor pattern 400. A sixth width W6 of the lower surface of the semiconductor pattern 400 may be smaller than the fifth width W5 of the upper surface of the semiconductor pattern 400.

[0163] The lower surface of the first upper hole 140 may have a height distribution, however, it may be located between the lower surface and the upper surface of one of the insulating layers 110 corresponding to the upper surface of the semiconductor pattern 400. Therefore, the characteristics of the transistor may not be deteriorated due to the height distribution. In the drawings, the first upper hole 140 includes lower surfaces having the fifth height H5 and the sixth height H6, respectively.

[0164] Reference Fig.28 , executable and reference Figures 10 to 19 and Figures 1 to 3 Processes substantially the same or similar to those described herein may be used to complete the fabrication of a semiconductor device.

[0165] Fig.29 is a cross-sectional view illustrating a vertical memory device according to some example embodiments. Fig.29 It is along Figure 1 A cross-sectional view taken along line AA'.

[0166] The vertical storage device is Fig.21 At least some of the concepts of a vertical memory device are applied to Fig.26 Results in a vertical memory device.

[0167] Reference Fig.29 , the vertical memory device may include a second structure on the semiconductor pattern 400, and the second structure may include a second portion, a third portion, and a fourth portion sequentially stacked in the first direction.

[0168] That is to say, Fig.21 The first portion of the second structure may be replaced by the semiconductor pattern 400 .

[0169] Although some example embodiments have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made in the example embodiments without departing from the spirit and scope of the claims.

Claims

1. A vertical storage device, comprising: A substrate, wherein the upper portion of the substrate includes an impurity region doped with carbon or p-type impurities; a gate electrode structure on the substrate, the gate electrode structure comprising gate electrodes spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate; as well as a channel extending through the gate electrode structure in the vertical direction on the substrate, the channel comprising a first portion and a second portion, The first portion has an inclined sidewall relative to an upper surface of the substrate, the second portion contacts an upper surface of the first portion, The second portion has an inclined sidewall relative to an upper surface of the substrate, The width of the upper surface of the second portion is smaller than the width of the upper surface of the first portion, the width of the upper surface of the second portion is greater than the width of the lower surface of the second portion, and The channel contacts the impurity region.

2. The vertical storage device of claim 1 , further comprising: a charge storage structure covering the outer sidewalls of the channel on the substrate, wherein The charge storage structure includes a first portion and a second portion, The first portion has an inclined sidewall relative to an upper surface of the substrate, and the second portion contacts an upper surface of the first portion, The second portion has an inclined sidewall relative to an upper surface of the substrate, and A width of an upper surface of the second portion is smaller than a width of an upper surface of the first portion.

3. The vertical storage device of claim 2, wherein A central lower portion of the first portion of the channel extends through an upper portion of the impurity region, and A lower portion of the first portion of the charge storage structure covers the central lower outer sidewall of the first portion of the channel contacting an upper surface of the impurity region.

4. The vertical storage device of claim 2, wherein The charge storage structure includes a tunnel barrier pattern, a charge storage pattern, and a blocking pattern sequentially stacked from an outer sidewall of the channel in a horizontal direction substantially parallel to an upper surface of the substrate.

5. The vertical storage device of claim 2, further comprising: Fill pattern; as well as The fill pattern, the trench and the pad on the charge storage structure, wherein The channel has a hollow cylindrical shape, and The filling pattern fills an inner space defined by inner sidewalls of the trench.

6. The vertical storage device according to claim 5, wherein: The pad directly contacts an upper surface of the filling pattern, an upper surface of the trench, and an upper surface of the charge storage structure.

7. The vertical storage device according to claim 5, wherein: The gate electrode structure includes at least one first gate electrode, a plurality of second gate electrodes on the at least one first gate electrode, and at least one third gate electrode on the plurality of second gate electrodes.

8. The vertical storage device of claim 7, wherein The at least one first gate electrode includes two first gate electrodes respectively arranged at two levels with respect to the upper surface of the substrate, Each of the two first gate electrodes overlaps the first portion of the channel in a horizontal direction substantially parallel to the upper surface of the substrate, and A maximum width of the charge storage structure corresponding to an upper surface of one of the two first gate electrodes located at an upper level is equal to or smaller than a width of an upper surface of the pad.

9. The vertical storage device of claim 7, wherein The at least one first gate electrode serves as a ground selection line, The plurality of second gate electrodes serve as word lines, and The at least one third gate electrode serves as a string selection line.

10. The vertical storage device of claim 5, wherein The gate electrode structure includes a first gate electrode, a plurality of second gate electrodes on the first gate electrode, and at least one third gate electrode on the plurality of second gate electrodes. The first gate electrode and a lowermost second gate electrode of the plurality of second gate electrodes are respectively arranged at two levels relative to an upper surface of the substrate, Each of the first gate electrode and a lowermost one of the plurality of second gate electrodes overlaps the first portion of the channel in a horizontal direction substantially parallel to an upper surface of the substrate, and A maximum width of the charge storage structure corresponding to an upper surface of a lowermost second gate electrode among the plurality of second gate electrodes is equal to or smaller than a width of an upper surface of the pad.

11. The vertical storage device of claim 1, wherein The channel further includes a third portion and a fourth portion, the third portion contacts an upper surface of the second portion of the channel, The third portion has an inclined sidewall relative to the upper surface of the substrate, The fourth portion contacts an upper surface of the third portion, The fourth portion has an inclined sidewall relative to the upper surface of the substrate, and A width of an upper surface of the fourth portion is smaller than a width of an upper surface of the third portion.

12. The vertical storage device of claim 11, wherein: A width of an upper surface of the third portion of the channel is greater than a width of an upper surface of the second portion of the channel.

13. The vertical storage device of claim 11, wherein The gate electrode structure includes two first gate electrodes, a plurality of second gate electrodes on the two first gate electrodes, and two third gate electrodes on the plurality of second gate electrodes. The two first gate electrodes are arranged at two levels relative to the upper surface of the substrate, respectively. Each of the two first gate electrodes overlaps the first portion of the channel in a horizontal direction substantially parallel to the upper surface of the substrate, The plurality of second gate electrodes are arranged at a plurality of levels on the upper surface of the substrate, The plurality of second gate electrodes overlap the second portion to the fourth portion of the channel in a horizontal direction, The two third gate electrodes are respectively arranged at two levels relative to the upper surface of the substrate, and Each of the two third gate electrodes overlaps the fourth portion of the channel in a horizontal direction.

14. The vertical storage device of claim 13, wherein At least one of the two first gate electrodes is used as a ground selection line, The plurality of second gate electrodes serve as word lines, and At least one of the two third gate electrodes serves as a string selection line.

15. A vertical storage device comprising: a substrate including an impurity region doped with carbon or p-type impurities; a channel structure on the substrate, The channel structure includes a lower channel on an upper surface of the impurity region of the substrate and an upper channel contacting an upper surface of the lower channel, The lower channel has an inclined sidewall relative to the upper surface of the substrate, The lower channel has a columnar shape, The upper trench has an inclined sidewall relative to an upper surface of the substrate, and The upper channel has a hollow cylindrical shape; a charge storage structure covering the outer sidewall of the upper channel, wherein the width of the upper surface of the charge storage structure is smaller than the maximum width of the lower channel; as well as a gate electrode structure on the substrate, The gate electrode structure includes gate electrodes spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, each of the gate electrodes covering an outer sidewall of the channel structure or an outer sidewall of the charge storage structure, Wherein, the width of the upper surface of the upper channel is greater than the width of the lower surface of the upper channel.

16. The vertical storage device of claim 15, further comprising: A plurality of channel structures on the substrate, wherein The plurality of channel structures include the channel structure, and Lower surfaces of upper channels of at least two of the plurality of channel structures are located at different heights from each other.

17. The vertical storage device of claim 16, wherein: Upper surfaces of lower channels included in the plurality of channel structures are substantially coplanar with each other.

18. The vertical storage device of claim 16, further comprising: a filling pattern filling a space defined by the inner sidewalls of the upper trench; as well as The filling pattern, the upper channel and the pad on the charge storage structure, wherein: The gate electrode structure includes at least one first gate electrode, a plurality of second gate electrodes on the first gate electrode, and at least one third gate electrode on the plurality of second gate electrodes. The at least one first gate electrode serves as a ground selection line, The plurality of second gate electrodes serve as word lines, and The at least one third gate electrode serves as a string selection line.

19. The vertical storage device of claim 18, wherein The at least one first gate electrode includes two first gate electrodes respectively arranged at two levels with respect to the upper surface of the substrate, Each of the two first gate electrodes overlaps the lower channel in a horizontal direction substantially parallel to the upper surface of the substrate, and A width of a lower channel corresponding to an upper surface of one of the two first gate electrodes located at an upper level is equal to or smaller than a width of an upper surface of the pad.

20. A vertical storage device comprising: a substrate including an impurity region located at an upper portion of the substrate; a gate electrode structure on the substrate, the gate electrode structure comprising gate electrodes spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate; as well as a channel on the substrate, The channel extends in a vertical direction on the substrate through the gate electrode structure and an upper portion of the impurity region of the substrate, The channel includes a plurality of parts sequentially stacked in a vertical direction and connected to each other, Each of the plurality of portions has an inclined sidewall relative to an upper surface of the substrate, a width of an upper surface of a first portion of the plurality of portions of the channel arranged at an odd level relative to an upper surface of the substrate is greater than a width of an upper surface of a second portion of the plurality of portions of the channel directly above the first portion, The width of the upper surface of the second portion is greater than the width of the lower surface of the second portion.

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