Package substrate

Abstract

Embodiments of the present application relate to a packaging substrate. According to some embodiments of the present application, the packaging substrate includes a packaging unit area and a simulated impedance area. The packaging unit area is arranged with a plurality of packaging units, each of the plurality of packaging units having a first multilayer structure. The simulated impedance area is arranged at the periphery of the packaging unit area, and the simulated impedance area has a second multilayer structure, and the second multilayer structure is configured to simulate the first multilayer structure of at least one of the plurality of packaging units and has an impedance layer and at least one reference layer, wherein the impedance layer includes an impedance line. The packaging substrate provided in the embodiment of the present application can conveniently and quickly perform impedance detection on the packaging unit without damaging it, thereby improving the accuracy and flexibility of impedance detection.

Description

Technical Field

[0001] The embodiments of the present application relate to a packaging substrate, and more particularly to a technology for detecting impedance performance of a packaging substrate. Background Art

[0002] Impedance is a parameter used to evaluate the characteristics of electronic components. It is the total resistance of electronic components to alternating current at a given frequency. In many application scenarios, the design of substrate circuits needs to consider the relationship of impedance matching to achieve the purpose of reducing signal attenuation and smooth transmission.

[0003] With the continuous advancement of packaging technology, electronic products have higher and higher requirements for the impedance circuits inside the packaging substrates used. This requires the impedance values ​​of dense impedance circuits in the packaging substrates to be detected and controlled. However, the existing impedance measurement technology is to detect by destroying a certain packaging unit structure on the corresponding packaging substrate. On the one hand, the production cost is increased due to the structural damage, and on the other hand, there is also the problem of inaccurate detection affecting product quality.

[0004] Therefore, the industry is in urgent need of new packaging substrate impedance performance detection technology. Summary of the invention

[0005] One of the purposes of the embodiments of the present application is to provide a packaging substrate having a dedicated impedance performance detection area without destroying its packaging unit.

[0006] According to some embodiments of the present application, the package substrate includes a package unit area and a simulated impedance area. The package unit area is arranged with a plurality of package units, each of the plurality of package units having a first multilayer structure. The simulated impedance area is arranged at the periphery of the package unit area, and the simulated impedance area has a second multilayer structure, and the second multilayer structure is configured to simulate the first multilayer structure of at least one of the plurality of package units and has an impedance layer and at least one reference layer, wherein the impedance layer includes an impedance line.

[0007] According to some embodiments of the present application, at least one layer in the second multi-layer structure has at least one pair of metal probe points.

[0008] According to some embodiments of the present application, at least one layer in the second multi-layer structure has at least one via.

[0009] According to some embodiments of the present application, the at least one reference layer is configured to be grounded.

[0010] According to some embodiments of the present application, the impedance layer is the top layer in the second multi-layer structure.

[0011] According to some embodiments of the present application, the second multi-layer structure further includes a clearance layer located between the impedance layer and the at least one adjacent reference layer.

[0012] According to some embodiments of the present application, the impedance layer is an inner layer in the second multi-layer structure.

[0013] According to some embodiments of the present application, the impedance layer further includes a shielding line disposed around the impedance line.

[0014] According to some embodiments of the present application, the distance between the impedance line and the shielding line is between 100 μm and 400 μm.

[0015] Compared with the prior art, the packaging substrate provided in the embodiment of the present application has a dedicated impedance performance detection area, and the purpose of impedance performance analysis can be achieved without destroying the packaging unit area of ​​the packaging substrate, thereby saving production costs while ensuring product quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The following will briefly describe the drawings necessary for describing the embodiments of the present application or the prior art to facilitate the description of the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, the drawings of other embodiments can still be obtained according to the structures illustrated in these drawings without the need for creative work. It should be noted that various structures may not be drawn to scale, and the sizes of various structures may be arbitrarily increased or decreased for the sake of clarity of discussion.

[0017] Figure 1 Schematic diagram of a top view of a packaging substrate 10 according to some embodiments of the present application

[0018] Figure 2 FIG. 1 is a schematic cross-sectional view of a second multilayer structure 20 of a simulated impedance region 14 on a package substrate 10 according to some embodiments of the present application.

[0019] Figure 3 FIG. 1 is a schematic cross-sectional view of a second multilayer structure 30 of a simulated impedance region 14 on a package substrate 10 according to some other embodiments of the present application.

[0020] Figure 4 FIG. 1 is a schematic cross-sectional view of a second multilayer structure 40 of a simulated impedance region 14 on a package substrate 10 according to some other embodiments of the present application. DETAILED DESCRIPTION

[0021] The embodiments of the present application will be described in detail below. In the full text of the present application specification, the same or similar components and components with the same or similar functions are represented by similar reference numerals. The embodiments of the accompanying drawings described herein are illustrative, graphical, and are used to provide a basic understanding of the present application. The embodiments of the present application should not be interpreted as limiting the present invention.

[0022] In this specification, unless otherwise specified or limited, relative terms such as "central", "longitudinal", "lateral", "front", "rear", "right", "left", "inner", "outer", "lower", "higher", "horizontal", "vertical", "above", "below", "above", "below", "top", "bottom" and their derivative terms (such as "horizontally", "downwardly", "upwardly", etc.) should be interpreted as referring to the directions described in the discussion or depicted in the drawings. These relative terms are only used for convenience of description and do not require that the present application be constructed or operated in a specific direction.

[0023] In addition, sometimes amounts, ratios and other numerical values ​​are presented in range format herein. It should be understood that such range format is for convenience and brevity, and should be flexibly understood to include not only the numerical values ​​explicitly specified as range limits, but also all individual numerical values ​​or sub-ranges encompassed within the range, as if each numerical value and sub-range were explicitly specified.

[0024] Furthermore, for ease of description, "first", "second", "third", etc. may be used herein to distinguish different components of one figure or a series of figures. Unless otherwise specifically specified or limited, "first", "second", "third", etc. are not intended to describe corresponding components.

[0025] In the detailed description and claims, a list of items connected by the terms "one of," "one of," "a kind of," or other similar terms may mean any of the listed items. For example, if items A and B are listed, the phrase "one of A and B" means only A or only B. In another example, if items A, B, and C are listed, the phrase "one of A, B, and C" means only A; only B; or only C. Item A may include a single element or multiple elements. Item B may include a single element or multiple elements. Item C may include a single element or multiple elements.

[0026] In the detailed description and claims, a list of items connected by the terms "at least one of," "at least one of," "at least one of," or other similar terms may mean any combination of the listed items. For example, if items A and B are listed, the phrase "at least one of A and B" means only A; only B; or A and B. In another example, if items A, B, and C are listed, the phrase "at least one of A, B, and C" means only A; or only B; only C; A and B (excluding C); A and C (excluding B); B and C (excluding A); or all of A, B, and C. Item A may include a single element or multiple elements. Item B may include a single element or multiple elements. Item C may include a single element or multiple elements.

[0027] An embodiment of the present application provides a packaging substrate, on which a simulated impedance area for the impedance line of at least one packaging unit in a simulated packaging unit area is provided. Accordingly, the impedance performance of the corresponding at least one packaging unit can be detected by monitoring the detection data of the impedance of the simulated impedance area without destroying the at least one packaging unit. Therefore, the embodiment of the present application can conveniently and quickly perform impedance detection on the packaging units on the packaging substrate. Even when an impedance abnormality problem is found in at least one packaging unit area being detected, it is only necessary to perform destructive slicing analysis on the impedance line of the simulated impedance area instead of the at least one packaging unit. In addition, when simulating the impedance environment of the packaging unit area to be detected, a dense line similar to the at least one packaging unit can be designed in the simulated impedance area, which reduces the impedance difference between the two and improves the accuracy and flexibility of the impedance detection of the packaging substrate.

[0028] In order to better illustrate the beneficial effects and technical advantages of the impedance line of the packaging unit area of ​​the analog packaging substrate of the present application, it will be further described below in combination with the embodiments of the present application and the drawings in the specification.

[0029] Figure 1 1 is a schematic diagram of a top view of the packaging substrate 10 according to some embodiments of the present application.

[0030] like Figure 1 As shown, the package substrate 10 includes at least one package unit area 12 and at least one simulated impedance area 14. Each package unit area 12 is arranged with a plurality of package units 120 arranged in an array, wherein each package unit 120 has a first multi-layer structure, and the first multi-layer structure may include an impedance layer and at least one reference layer. For details, please refer to the detailed description of the subsequent embodiments and the attached Figure 2-4. The reference layer can also be called a ground layer. The at least one simulated impedance area 14 is arranged on the periphery of the corresponding package unit area 12, such as one or more side edges of the package substrate 10. The simulated impedance area 14 has a second multilayer structure, which is configured to simulate the first multilayer structure of at least one package unit 120 in the package unit area 12. The second multilayer structure has the same number of layers as the simulated first multilayer structure, and the circuit performance of each layer corresponds. As can be understood by those skilled in the art, the simulation only ensures that the second multilayer structure can have the same circuit design performance as the first multilayer structure, but not that the circuit layout on each layer is exactly the same. For example, in some embodiments of the present application, the simulated first multilayer structure has an impedance layer, a clearance layer and a reference layer arranged in sequence from top to bottom. Correspondingly, the second multilayer structure 142 also has an impedance layer, a clearance layer and a reference layer arranged in sequence from top to bottom. However, although the impedance layer of the second multilayer structure has approximately the same impedance performance as the impedance layer of the first multilayer structure, the layout of the impedance line in the second multilayer structure is different.

[0031] The layout of the impedance lines in the impedance layer of the first multilayer structure is more square and dense. The so-called "substantially the same" means completely the same or the same within a tolerance range, and the tolerance range can be well known to those skilled in the art or specially formulated according to application requirements, such as customer customization requirements.

[0032] Figure 2 FIG. 1 is a schematic cross-sectional view of a second multilayer structure 20 of a simulated impedance region 14 on a package substrate 10 according to some embodiments of the present application. The package substrate 10 may be Figure 1 The packaging substrate 10 shown or the packaging substrate 10 according to other embodiments of the present application.

[0033] like Figure 2 As shown, in some embodiments of the present application, the second multilayer structure 20 can be arranged in the simulated impedance area 14 at the edge of the package substrate 10. The second multilayer structure 20 can be a five-layer structure, wherein the upper three layers can include an impedance layer 201, a clearance layer 203 and a reference layer 202, and the other two layers 204 and 205 can be other types of circuit layers. The second multilayer structure 20 can simulate the impedance performance of the corresponding package unit, for example, Figure 2 In the embodiment shown, the second multilayer structure 20 can simulate Figure 1 A first multi-layer structure of at least one packaging unit 120 is shown.

[0034] The impedance layer 201 is disposed on the top layer of the second multi-layer structure 20, i.e., the first layer. The clearance layer 203 is disposed on the next layer of the impedance layer 201, i.e., the second layer. In some embodiments of the present application, the clearance layer 203 is disposed according to the first multi-layer structure simulated in these embodiments, and no circuit lines are disposed therein. The reference layer 202 is disposed on the next layer of the clearance layer 203, i.e., the third layer. That is, the clearance layer 203 is disposed between the impedance layer 201 and the reference layer 202. In some embodiments of the present application, the reference layer 202 may be configured to be grounded.

[0035] At least one layer of the second multilayer structure 20 may be provided with a via hole 240 to achieve circuit connection between different layers. Those skilled in the art should understand that the number, shape and array arrangement of the via holes 240 can be adjusted according to the actual size and shape of the second multilayer structure 20 to meet the requirements of different product sizes and performances, and are not limited by the embodiments illustrated in this application. For example, in this embodiment, the first to fifth layers of the second multilayer structure 20 are all provided with pairs of via holes 240.

[0036] In some embodiments of the present application, the impedance layer 201 may include a differential impedance line 210, a metal probe point 220 and a wire 230. The reference layer 202 forms a capacitive effect with the differential impedance line 210, thereby generating a resistance value. The differential impedance line 210 in the impedance layer 201 is connected to the metal probe point pair 220. The metal probe points 220 may be arranged in pairs corresponding to the differential impedance line 210, and may be connected to an external impedance tester (not shown in the figure) through the wire 230. When testing the impedance characteristics of the package unit 120 of the package substrate 10, the impedance tester may be connected to the wire 230 to perform impedance detection on the second multilayer structure 20, thereby obtaining the impedance value of at least one package unit 120 simulated by the second multilayer structure 20. Those skilled in the art should understand that the number, shape and array arrangement of the metal probe points 220 may be adjusted according to the actual size and shape of the second multilayer structure 20 to meet the requirements of different product sizes and performances, and are not limited by the embodiments exemplified in the present application.

[0037] Figure 3 FIG. 1 is a schematic cross-sectional view of a second multilayer structure 30 of a simulated impedance region 14 on a package substrate 10 according to some embodiments of the present application. The package substrate 10 may be Figure 1 The packaging substrate 10 shown or the packaging substrate 10 according to other embodiments of the present application.

[0038] like Figure 3As shown, in some embodiments of the present application, the second multilayer structure 30 may be disposed in the simulated impedance region 14 at the edge of the package substrate 10. The second multilayer structure 30 may be a four-layer structure, which may include two reference layers. Specifically, the lower three layers of the second multilayer structure 30 may include an impedance layer 302, a first reference layer 301, and a second reference layer 303, and the top layer 304 may be other types of circuit structures. The second multilayer structure 30 may simulate the impedance performance of the corresponding package unit, for example, Figure 3 In the embodiment shown, the second multilayer structure 30 can simulate Figure 1 A first multi-layer structure of at least one packaging unit 120 is shown.

[0039] The first reference layer 301 is disposed on the bottom layer, i.e., the fourth layer, in the second multi-layer structure 30. The impedance layer 302 is disposed on the upper layer, i.e., the third layer, of the first reference layer 301. The second reference layer 303 is disposed on the upper layer, i.e., the second layer, of the impedance layer 302. That is, the impedance layer 302 is disposed between the first reference layer 301 and the second reference layer 303. Both the first reference layer 301 and the second reference layer 303 may be configured to be grounded.

[0040] At least one layer of the second multilayer structure 30 may be provided with a via hole 340 to achieve circuit connection between different layers. Those skilled in the art should understand that the number, shape and array arrangement of the via holes 340 can be adjusted according to the actual size and shape of the second multilayer structure 30 to meet the requirements of different product sizes and performances, and are not limited by the embodiments exemplified in this application. For example, in this embodiment, the first to fourth layers of the second multilayer structure 30 are all provided with pairs of via holes 340.

[0041] In this embodiment of the present application, the impedance layer 302 may include a differential impedance line 310 and shielding lines 350 and 351. The differential impedance line 310 is connected to a pair of vias 340 disposed in the impedance layer 302. The shielding lines 350 and 351 are disposed around the differential impedance line 310, and are made of copper. Generally, a copper block design is adopted to shield external interference signals and improve the electromagnetic shielding effect. The distance between the shielding lines 350 and 351 and the differential impedance line 310 will affect the accuracy of the detection result during the impedance detection process. In this embodiment of the present application, the distance between the shielding lines 350 and 351 and the differential impedance line 310 may range from 100 μm to 400 μm.

[0042] The two reference layers 301, 303 form a capacitive effect with the differential impedance line 310, thereby generating a resistance value. A metal probe point 320 may also be provided on the first reference layer 301, and a wire 330 may be used to lead the metal probe point 320 to an external test circuit. The differential impedance line 310 in the impedance layer 302 is connected to a corresponding via 340, and a circuit connection may be established with the metal probe point 320 of the first reference layer 301 through the via 340. The metal probe point pair 320 may be connected to an external impedance tester (not shown) through the wire 330. When testing the impedance characteristics of the package unit 120 of the package substrate 10, the impedance tester may be connected to the wire 330 to perform impedance detection on the second multilayer structure 30, thereby obtaining the impedance value of at least one package unit 120 simulated by the second multilayer structure 30. Those skilled in the art should clearly understand that the number, shape and array arrangement of the metal probe points 320 can be adjusted according to the actual size and shape of the multilayer structure 30 to meet the requirements of different product sizes and performances, without being limited by the embodiments illustrated in this application.

[0043] Figure 4 FIG. 1 is a schematic cross-sectional view of a second multilayer structure 40 of a simulated impedance region 14 on a package substrate 10 according to some embodiments of the present application. The package substrate 10 may be Figure 1 The packaging substrate 10 shown or the packaging substrate 10 according to other embodiments of the present application.

[0044] like Figure 4 As shown, in some embodiments of the present application, the second multilayer structure 40 may be disposed in the simulated impedance region 14 at the edge of the package substrate 10. The second multilayer structure 40 may be a four-layer structure, which may include two reference layers. Specifically, the lower three layers of the second multilayer structure 40 may include an impedance layer 402, a first reference layer 401, and a second reference layer 403, and the top layer 404 may be other types of line structures. The second multilayer structure 40 may simulate the impedance performance of the corresponding package unit, for example, Figure 4 In the embodiment shown, the second multilayer structure 40 can simulate Figure 1 A first multi-layer structure of at least one packaging unit 120 is shown.

[0045] The first reference layer 401 is disposed on the bottom layer, i.e., the fourth layer, in the second multi-layer structure 40. The impedance layer 402 is disposed on the upper layer, i.e., the third layer, of the first reference layer 401. The second reference layer 403 is disposed on the upper layer, i.e., the second layer, of the impedance layer 402. That is, the impedance layer 402 is disposed between the first reference layer 401 and the second reference layer 403. Both the first reference layer 401 and the second reference layer 403 may be configured to be grounded.

[0046] At least one layer of the second multilayer structure 40 may be provided with a via 440 to achieve circuit connection between different layers. Those skilled in the art should understand that the number, shape and array arrangement of the via 440 can be adjusted according to the actual size and shape of the second multilayer structure 40 to meet the requirements of different product sizes and performances, and are not limited by the embodiments exemplified in this application. For example, in this embodiment, the first to fourth layers of the second multilayer structure 40 are each provided with a single via 440.

[0047] In this embodiment of the present application, the impedance layer 402 includes a characteristic impedance line 410 and shielding lines 450 and 451. The characteristic impedance line 410 is connected to a via 440 provided in the impedance layer 402. The shielding lines 450 and 451 are provided around the characteristic impedance line 410, and are made of copper. Generally, a copper block design is adopted to shield external interference signals and improve the electromagnetic shielding effect. The distance between the shielding lines 450 and 451 and the characteristic impedance line 410 will affect the accuracy of the detection result in the impedance detection process. In this embodiment of the present application, the distance between the shielding lines 450 and 451 and the characteristic impedance line 410 can range from 100 μm to 400 μm.

[0048] The two reference layers 402 and 403 form a capacitive effect with the characteristic impedance line 410, thereby generating a resistance value. A metal probe point 420 may also be provided on the first reference layer 401, and a wire 430 may be used to lead the metal probe point 420 to an external test circuit. The differential impedance line 410 in the impedance layer 402 is connected to a corresponding via 440, and a circuit connection may be established with the metal probe point 420 of the first reference layer 401 through the via 440. The metal probe point pair 420 may be connected to an external impedance tester (not shown in the figure) through the wire 430. When testing the impedance characteristics of the package unit 120 of the package substrate 10, the impedance tester may be connected to the wire 430 to perform impedance detection on the second multilayer structure 40, thereby obtaining the impedance value of at least one package unit 120 simulated by the second multilayer structure 40. Those skilled in the art should clearly understand that the number, shape and array arrangement of the metal probe points 420 can be adjusted according to the actual size and shape of the multilayer structure 40 to meet the requirements of different product sizes and performances, without being limited by the embodiments illustrated in this application.

[0049] Those skilled in the art will appreciate that the number of layers of the first multi-layer structure of at least one packaging unit in the packaging unit area and the positional relationship of each layer can be adjusted according to the customer's requirements for the impedance lines during the actual design and production process to meet the requirements of different product sizes and performances, without being limited by the embodiments illustrated in the present application.

[0050] In some embodiments of the present application, the impedance line in the first multilayer structure can be adjusted according to customer requirements, including, but not limited to, one or more parameters of the impedance line type, line width, line spacing, dielectric and polypropylene thickness. In some embodiments of the present application, one or more parameters of the impedance line type, line width, line spacing, dielectric and polypropylene thickness of the impedance line in the second multilayer structure of the simulated impedance area are the same as the impedance line in the first multilayer structure of at least one package unit.

[0051] In some embodiments of the present application, the lengths of the impedance line in the second multilayer structure of the simulation area and the impedance line in the first multilayer structure of at least one package unit are both greater than 8 mm.

[0052] References to "some embodiments of the present application" or similar terms throughout this specification mean that a particular feature, structure, or characteristic described in conjunction with other embodiments is included in at least one embodiment and may not necessarily be present in all embodiments. Therefore, corresponding appearances of the phrase "an embodiment of the present application" or similar terms throughout this specification do not necessarily refer to the same embodiment. In addition, the particular features, structures, or characteristics of any particular embodiment may be combined with one or more other embodiments in any suitable manner. It should be understood that other variations and modifications of the embodiments described and illustrated herein are possible in view of the teachings herein and are to be considered part of the spirit and scope of the present application.

[0053] The technical content and technical features of this application have been disclosed as above, but those skilled in the art may still make various substitutions and modifications based on the teachings and disclosures of this application without departing from the spirit of this application. Therefore, the protection scope of this application should not be limited to the contents disclosed in the embodiments, but should include various substitutions and modifications that do not depart from this application, and are covered by the claims of this patent application.

Claims

1. A packaging substrate, comprising: a package unit region, in which a plurality of package units are arranged, each of the plurality of package units having a first multi-layer structure; as well as A simulated impedance region is disposed at the periphery of the package unit region, the simulated impedance region has a second multilayer structure, and the second multilayer structure is configured to simulate the first multilayer structure of at least one of the plurality of package units and has: an impedance layer, comprising an impedance line, the impedance layer further comprising a shielding line disposed around the impedance line; and At least one reference layer, wherein the at least one reference layer is configured to be grounded. 2 . The package substrate according to claim 1 , wherein at least one layer in the second multi-layer structure has at least one pair of metal probe points. 3 . The package substrate according to claim 1 , wherein at least one layer in the second multi-layer structure has at least one via. The package substrate according to claim 1 , wherein the impedance layer is a top layer in the second multi-layer structure.

5. The package substrate according to claim 1, wherein the second multilayer structure further comprises: The clearance layer is located between the impedance layer and the at least one adjacent reference layer. The package substrate according to claim 1 , wherein the impedance layer is an inner layer in the second multi-layer structure. 7 . The packaging substrate according to claim 1 , wherein a distance from the impedance line to the shielding line is between 100 μm and 400 μm.

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