Electro-optical active devices

Abstract

A silicon-based electro-optical active device and a method for producing the same. The silicon-based electro-optical active device comprises: a silicon-on-insulator (SOI) waveguide; an electro-optical active waveguide comprising an electro-optical active stack within a cavity of the SOI waveguide; and a lined channel between the electro-optical active stack and the SOI waveguide, the lined channel comprising a lining; wherein the lined channel is filled with a filling material having a refractive index similar to that of a material forming a sidewall of the cavity, thereby forming a bridge waveguide in the channel between the SOI waveguide and the electro-optical active stack.

Description

Technical Field

[0001] The present invention relates to silicon based electro-optical active devices and in particular to electro-optical modulators. Background Art

[0002] 1, a conventional electro-optical active device may include an SOI substrate 101 on which a first passive waveguide 102a and a second passive waveguide 102b are formed. An electro-optical active EPI stack 103 is grown in the gap between the passive waveguides and may include a first facet or curved region 104a and a second facet or curved region 104b.

[0003] These facets or curved regions of the EPI stack can produce significant losses in the device. Summary of the invention

[0004] Generally speaking, the present invention provides an electro-optical active device and method of producing the same, wherein a cutout region is removed and replaced by a filler material.

[0005] Therefore, in a first aspect, the present invention provides a silicon-based electro-optical active device, comprising: a silicon-on-insulator (SOI) waveguide; an electro-optical active waveguide comprising an electro-optical active stack within a cavity of the SOI waveguide; and a lined channel between the electro-optical active stack and the SOI waveguide, the lined channel comprising a lining; wherein the lined channel is filled with a filling material having a refractive index similar to the refractive index of a material forming the side walls of the cavity, thereby forming a bridge waveguide in the channel between the SOI waveguide and the electro-optical active stack.

[0006] In a second aspect, a method for producing a silicon-based electro-optical active device is provided, comprising the following steps: providing a silicon-on-insulator (SOI) waveguide; etching a cavity in a portion of the SOI waveguide through a BOX layer of the SOI waveguide; epitaxially growing an electro-optical active stack in the cavity, and etching the electro-optical active stack to form an electro-optical active waveguide, wherein the epitaxially grown electro-optical active stack has a facet in a region adjacent to a sidewall of the cavity; etching the region to remove the facet and create a channel between the sidewall and the stack; lining the channel with a liner to provide a lined channel; and filling the lined channel with a filling material having a refractive index similar to the refractive index of the material forming the sidewall, thereby forming a bridge waveguide in the channel between the SOI waveguide and the electro-optical active stack.

[0007] By electro-optically active stack, it may be meant that the stack comprises a plurality of functional layers, some of which are electro-optically active. For example, the stack may comprise a buffer layer, a P-doped layer and an N-doped layer, the P-doped layer and the N-doped layer being separated by an intermediate layer, the intermediate layer comprising a spacer layer, a plurality of quantum wells (MQWs) and a barrier layer. These layers may be layered relative to the SOI waveguide on which the stack is formed, i.e., the layers are horizontal layers. The buffer layer serves as a virtual substrate for the MQW layer and may be undoped or P-doped. By similar to, it may be meant that the refractive index of the filling material is such that a substantially barrier-free waveguide formed by: an SOI waveguide, a liner and a filling material may be provided. Similar may mean substantially equal to. The refractive index of the filling material may be equal to or less than the refractive index of the material forming the sidewalls of the cavity. The refractive index of the filling material may be within 10% of the refractive index of the material forming the sidewalls of the cavity. The refractive index of the filling material may be at least 3.2 and not more than 4.0 at a wavelength of 1310 nm. The refractive index of the material forming the sidewalls of the cavity may be at least 3.4 and not more than 3.6 at a wavelength of 1310 nm. The refractive index of the liner may be at least 2.5 and not more than 2.8 at a wavelength of 1310 nm.

[0008] In this way, light is coupled between the SOI waveguide and the electro-optical active stack through the bridge waveguide such that there is no direct contact between the facets of the SOI waveguide in the region adjacent to the sidewalls of the cavity and the sidewalls of the electro-optical active stack.

[0009] Advantageously, by lining the channel with a liner, there is no requirement to provide an insulator layer between the fill material and the substrate of the SOI waveguide.

[0010] Conveniently, the liner provides passivation for the facets after the electro-optical active stack has been etched. When no liner is provided, the facets are exposed to the atmosphere during subsequent processes (e.g., SiO2 deposition, α-silicon deposition, and SiO2 etching), which may add defects to the facets. Therefore, the method of the present invention can provide a higher yield compared to existing methods.

[0011] Advantageously, the above method is easier and simpler than the prior art.In instances where a liner is not used, the chemical mechanical planarization step required after deposition of the insulator is complex.

[0012] Conveniently, the optical coupling efficiency is not reduced compared to a device not including a liner.

[0013] When viewed from the side of the device, the channel can be described as extending vertically downwards (ie, in a direction 90° to the surface of the SOI waveguide) from the uppermost side of the device towards the bottom of the cavity.

[0014] The optional features of the present invention will now be described. These features are applicable individually or in combination with any aspect of the invention.

[0015] The liner may be formed of silicon nitride. For example, the liner may be formed of Si3N4. The liner may have a thickness of at least 200 nm and not more than 280 nm. In some instances, the liner may have a thickness of 240 nm. In some instances, the liner may have dimensions similar to the remaining structure, so its height may vary when viewed in a cross section aligned with the guiding direction of the waveguide. In other instances, the liner may be formed as a substantially uniform wall having a uniform height. The lowermost surface of the sidewall of the channel and the top surface of the portion of the liner located in the bottom of the channel may be aligned with the top surface of the buried oxide layer of the SOI.

[0016] The filling material may be amorphous silicon (α-Si) or SiGe material. There may be a second lined channel between the electro-optical active stack and the second SOI waveguide, the second lined channel comprising a second liner. The second lined channel may be filled with the same material as the first lined channel. The second lined channel may be located on the side of the electro-optical active waveguide opposite to the first lined channel.

[0017] The surface of the stack facing the channel can be described as an etched surface. The etched surface will present an advantage over the grown surface in that the unwanted curved regions at the edge of each grown layer of the stack can be removed by etching. Instead, the interface between the stack and the channel will be a distinct interface; a slice through the stack. Thus, the curved region is replaced by a filling material that forms a straight bridge waveguide aligned with the SOI waveguide and the electro-optically active EPI stack.

[0018] When viewed from above (top view), the electro-optical active stack may have a parallelogram or trapezoidal geometry.

[0019] The electro-optical active device may also include an epitaxial cladding layer located between the silicon substrate of the SOI device and the optically active region forming the electro-optical active waveguide. The epitaxial cladding layer has a refractive index less than the refractive index of the buffer layer in the electro-optical active stack. The epitaxial layer may be referred to as a regenerated cladding layer because it may be formed by etching away a pre-existing cladding region or a portion of a cladding region, such as a buried oxide (BOX) region, and then growing an epitaxial cladding layer in the etched cavity, the epitaxial cladding layer replacing a portion of the original cladding layer.

[0020] The step of filling the channel can be performed by plasma enhanced chemical vapor deposition (PECVD), or low energy plasma enhanced chemical vapor deposition (LEPECVD), or other epitaxial growth methods, at a temperature less than the lowest growth temperature of the stack. The temperature can be in the range of 250° C. and 500° C. In some embodiments, the temperature can be in the range of 300° C. and 350° C. The step of filling the lined channel can be performed by hot wire chemical vapor deposition.

[0021] The method may further include the step of planarizing the fill material by chemical mechanical polishing.

[0022] The epitaxially grown electro-optical active stack may have a second facet in a second region adjacent to the opposite sidewall of the cavity, and the etching step may also remove the second region, thereby removing the second facet and creating a second channel between the opposite sidewall and the stack; the filling step may also fill the second channel with amorphous silicon or SiGe.

[0023] The method may further comprise the step of lining the cavity with a spacer before growing the stack. The thickness of the spacer may be between 5 nm and 35 nm, and may be 20 nm thick. The method may further comprise the step of etching away a portion of the liner, the portion being in the bottom of the cavity, i.e. between the side walls of the cavity.

[0024] The electro-optic active device may be any of an electro-optic modulator, a photodetector, or a laser. In some embodiments, the device is an electro-optic modulator, and in some embodiments, it is an electro-absorption modulator based on the quantum confined Stark effect.

[0025] The electro-optical active stack may include a multi-quantum well region.

[0026] The epitaxially grown stack may include a silicon layer and a buffer layer, and the method may include adjusting the height of the buffer layer so that the optical mode of the modulator matches the optical mode of the SOI waveguide. The silicon layer may be the lowermost layer of the epitaxially grown stack, i.e., the layer closest to the bottom of the cavity.

[0027] In some embodiments, from the layer adjacent to the silicon substrate upward, the stack is: a silicon layer with the same thickness as the BOX layer, a buffer layer including SiGe, a P-doped layer including SiGe, a spacer layer including SiGe, a quantum well multi-quantum well layer including Ge / SiGe, another spacer layer including SiGe, an N-doped layer including SiGe, an N-doped layer including SiGe, and an N+ doped layer including SiGe.

[0028] In some embodiments, from the layer adjacent to the silicon substrate upward, the stack is: a SiGe layer with the same thickness as the BOX layer, a P-doped layer including SiGe, a spacer layer including SiGe, a quantum well multi-quantum well layer including Ge / SiGe, another spacer layer including SiGe, an N-doped layer including SiGe, and an N+ doped layer including SiGe.

[0029] In some embodiments, from the layer adjacent to the silicon substrate upward, the stack is: a silicon layer with the same thickness as the BOX layer, a P-doped layer including SiGe, a spacer layer including SiGe, a quantum well multi-quantum well layer including Ge / SiGe, another spacer layer including SiGe, an N-doped layer including SiGe, and an N+ doped layer including SiGe.

[0030] More specifically, in some embodiments, the stack, from the layer immediately adjacent to the silicon substrate upward, is: a 400 nm silicon layer, a Si 0.28 Ge 0.72 The 400nm buffer layer, including Si 0.28 Ge 0.72 200nm P-doped layer, including Si 0.28 Ge 0.72 50nm (or 20nm) spacer layer, 7 (or 10) quantum wells (each well includes a 10nm Ge well layer and a 12nm Si well layer) 0.23 Ge 0.57 barrier layer), including Si 0.28 Ge 0.72 Another 50nm (or 20nm) spacer layer, including Si 0.28 Ge 0.72 600nm N-doped layer, including Si 0.8 Ge 0.2 The 200nm N-doped layer and the Si 0.8 Ge 0.2 The top 100 nm of N+ doping is heavily doped (e.g., with greater than 1x10 19 cm -3 The 400nm buffer can also be P-doped to reduce series resistance and achieve high speed.

[0031] In some embodiments, the stack, from the layer immediately adjacent to the silicon substrate upward, is: 400 nm Si 0.8 Ge 0.2 layer (which may be referred to as a transition buffer layer), including Si 0.18 Ge 0.82 400nm P-doped layer (can be called buffer layer), including Si0.18 Ge 0.82 15nm (or 50nm) spacer layer, 8 quantum wells (each well includes 10nm Ge well layer and 12nm Si 0.33 Ge 0.67 barrier layer), including Si 0.18 Ge 0.82 Another 15nm (or 50nm) spacer layer, including Si 0.18 Ge 0.82 The 300nm N-doped layer and the Si 0.8 Ge 0.2 The top 80 nm of N+ doping is heavily doped (e.g., with greater than 1x10 19 cm -3 The dopant species in the N-doped layer and the N+-doped layer may be phosphorus.

[0032] In some embodiments, the stack, from the layer immediately adjacent to the silicon substrate upward, is: a 400 nm Si layer (which may be referred to as a transition buffer layer), a Si 0.18 Ge 0.82 400nm P-doped layer (can be called buffer layer), including Si 0.18 Ge 0.82 15nm (or 50nm) spacer layer, 8 quantum wells (each well includes 10nm Ge well layer and 12nm Si 0.33 Ge 0.67 barrier layer), including Si 0.18 Ge 0.82 Another 15nm (or 50nm) spacer layer, including Si 0.18 Ge 0.82 The 300nm N-doped layer and the Si 0.18 Ge 0.82 The top 80 nm of N+ doping is heavily doped (e.g., with greater than 1x10 19 cm -3 The dopant species in the N-doped layer and the N+-doped layer may be phosphorus.

[0033] In another aspect, the present invention provides a silicon-based electro-optical active device comprising:

[0034] Silicon-on-insulator (SOI) waveguides;

[0035] an electro-optic active waveguide comprising an electro-optic active stack within a cavity of said SOI waveguide; and

[0036] a channel between the electro-optical active stack and the SOI waveguide; wherein the channel is filled with a filling material having a refractive index similar to the refractive index of the material forming the sidewalls of the cavity, thereby forming a bridge waveguide in the channel between the SOI waveguide and the electro-optical active stack. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Embodiments of the present invention will now be described by way of example with reference to the accompanying drawings, in which:

[0038] FIG1 shows a device according to the prior art;

[0039] Figure 2 Shows a top perspective view of a device according to the invention;

[0040] FIG. 2A to FIG. 2D Show Figure 2 various cross-sectional views of the device shown; and

[0041] Figure 3(A) to Figure 3(Q)A Various manufacturing steps according to the invention are shown. DETAILED DESCRIPTION

[0042] Figure 2 An apparatus 200 according to the invention is shown. Figure 2A shows a cross-sectional view of the device along line AA', Figure 2B shows a cross-sectional view of the device along line BB', Figure 2C shows a cross-sectional view of the device along line CC', and Figure 2D A cross-sectional view of the device along line DD' is shown.

[0043] Broadly speaking, the device comprises a waveguide formed by ribs disposed on top of a plate extending from one end of the device to the other in the x-direction indicated in the figure. The entire device resides on a silicon substrate 201, which is covered in place by a buried oxide layer 202. The buried oxide layer may be approximately 400 nm thick, measured in the y-direction from the uppermost surface of the silicon substrate.

[0044] Light enters the device through the input port of input waveguide 250. Input waveguide 250 comprises a rib portion 203a on top of a plate portion 207a. In this example, both portions are formed of silicon. Light in the waveguide is guided in the direction x, i.e., to Figure 2B In the plane of Figure 2BAs shown most clearly in FIG, the rib portion 203a has a width of about 2.5 μm measured in the y direction. The rib may have a thickness of about 0.6 μm measured in the y direction from the uppermost portion of the plate portion. The plate may have a thickness of about 0.4 μm measured in the y direction from the uppermost portion of the buried oxide layer. The input waveguide rests on top of the buried oxide layer 202, which in turn is located on top of the silicon substrate 201. The optical mode of the input waveguide is such that most of the light is contained within the rib portion 203a, while a small portion of the light is contained by the plate portion 207a.

[0045] Light is guided from the input port to the output port adjacent to the channel by the input waveguide 250. The channel comprises: a first side wall lining 204a, a filling material 205 and a second side wall lining 204b. Figure 2C A cross-sectional view of the channel along line CC' is shown in . As can be seen, the filling material includes a rib portion 205a and a plate portion 205c. The size of the filling material is roughly matched to the size of the input waveguide, wherein the input waveguide provides an output port. Below the filling material is a first bottom liner 204e, and a second bottom liner is located in a second channel, and the second channel is located on opposite sides of the device, as discussed below. The first and second bottom liners may have a thickness of approximately 400nm. The first sidewall liner, the second sidewall liner and the first bottom liner are all formed of silicon nitride (SiN), such as Si3N4. The length of the channel in the x direction is approximately 3μm. Below the first bottom liner 204e is a layer 242, which forms a part of the optical active stack discussed below.

[0046] The light passes through the channel acting as a bridge waveguide and enters the optically active stack 210. The stack may have a length of about 80 μm measured in the x-direction and from one channel to another. From the bottommost layer to the topmost layer (in the direction away from the silicon substrate 201), the stack in this example includes:

[0047] 242: By Si 0.8 Ge 0.2 A 400nm high transition buffer layer is formed;

[0048] 240: By Si 0.18 Ge 0.82 A 400nm high P-type buffer layer is formed;

[0049] 238: By Si 0.18 Ge 0.82 A 15 nm high spacer layer is formed;

[0050] 236: 188nm high multi-quantum well layer, which includes 8 Ge quantum wells, each 10nm high, with a 12nm barrier layer between each Ge quantum well, the barrier layer is made of Si0.33 Ge 0.67 Formation, there can be 9 barrier layers;

[0051] 234: By Si 0.18 Ge 0.82 A 15 nm high spacer layer is formed;

[0052] 232: By Si 0.18 Ge 0.82 The N layer formed is 300 high and doped to 1×10 18 cm -3 concentration; and

[0053] 230: By Si 0.8 Ge 0.2 The 80nm high N+ layer is doped to >1×10 19 cm -3 concentration.

[0054] The dopant species in the N layer and the N+ layer can be phosphorus. This stack can provide a quantum confined Stark effect at an operating wavelength of 1310nm, at 60°C, 2V bias, with a peak Aα / α of 0.95. The absorption coefficient of the multi-quantum well layer at 1310nm (cm -1 ) may be 320. The multi-quantum well layer may have a refractive index of about 4.0531 at 1310 nm. In contrast, the refractive index of α-silicon filling may be about 3.4.

[0055] The optically active stack may be an electro-optically active stack. For example, the optically active stack may operate as a quantum confined Stark effect modulator.

[0056] The detailed parameters of an example are shown in Table 1 below:

[0057]

[0058] The transition buffer layer 242 extends at least a distance below the channel, such as Figure 2A In addition, the transition buffer layer 242 and the P-type buffer layer extend further in the z direction than the other layers to provide a plate for the optically active region, such as Figure 2D The optically active stack 210 thus provides a waveguide comprising a rib portion formed by layers 238-230 and a slab portion formed by layers 240 and 242. Figure 2D As shown, the width of the rib portion is about 2.5 μm.

[0059] In some examples, the optically active stack is connected to one or more electrodes and can operate as a modulator (eg, an electro-absorption modulator).

[0060] After passing through the optically active stack 210, the light passes through the second channel formed by the third sidewall liner 204c, the second filling materials 205b and 205d, and the fourth sidewall liner 204d. The structure of the second channel is substantially the same as the first channel.

[0061] After passing through the second channel, the light enters the output waveguide 260, which includes a rib portion 203b on top of the plate portion 207b. The light can then leave the device through an output port in the output waveguide. The output waveguide is generally similar to the input waveguide, and the device can be conceptually considered bidirectional (because the input waveguide can be the output waveguide and vice versa).

[0062] FIG. 2A to FIG. 2D In the Figure 2 Not shown is an upper insulating layer 206. This upper insulating layer is formed, for example, of silicon dioxide (SiO2) and may serve to passivate the device. Figure 2 The upper insulating layer is omitted for clarity.

[0063] Figure 3(A) to Figure 3(N) Along with Figure 2A The same AA' plane shows various fabrication steps. FIG3(A) shows a first fabrication step according to the present invention. A silicon-on-insulator wafer is provided, comprising a silicon substrate 201, on top of which is a buried oxide (e.g., SiO2) layer 302. On top of the buried oxide layer is a silicon layer 301, which may be 1.1 μm-1.5 μm high (measured in the y direction from the upper surface of the buried oxide layer to the upper surface of the silicon layer).

[0064] Next, as shown in FIG3(B), a cavity 303 is etched into the device. The cavity extends to the upper surface 304 of the silicon substrate 201 and includes removing at least a portion of the buried oxide layer, thereby producing a first buried oxide layer 202a and a second buried oxide layer 202b located at either side of the cavity. Similarly, a portion of the silicon layer is removed, thereby providing a first silicon portion 401a and a second silicon portion 401b at either side of the cavity 303.

[0065] Next, as shown in FIG. 3 (C), the first precursor optically active stack 310a is epitaxially deposited onto the now etched silicon-on-insulator wafer. Epitaxial deposition occurs in n stages, where n corresponds to the number of layers in the precursor optically active stack. However, during deposition, the precursor optically active stack is epitaxially grown from all exposed surfaces. Therefore, there is not only the required growth from the upper surface 304 of the silicon substrate, but also the growth from the sidewalls of the first silicon portion 401a and the second silicon portion 401b and also from the upper surfaces of these silicon portions. Therefore, facet defects 305a and 305b are generated, which, if left in the device, may cause significant signal loss. These facet regions can be understood as being caused by the bending in each layer of the precursor optically active stack.

[0066] After the step shown in FIG. 3(C), a silicon nitride layer 306 is deposited on the uppermost surface of the first precursor optically active stack 310a. Figure 3D The silicon nitride layer may be formed of Si3N4.

[0067] Next, as shown in FIG3(E), the device undergoes a chemical mechanical planarization process. This removes the portion of the first precursor optically active stack 310a that extends over the previously formed cavity and a portion of each of the silicon portions 401a and 401b. Approximately 20 nm of the silicon nitride layer 307 remains. The planarization process and / or subsequent etching process is performed so that the height of the first silicon portion 401a and the second silicon portion 401b is approximately 1 μm.

[0068] As a next step, a silicon dioxide hard mask 308 is deposited on the upper surface of the device. The result of this step is shown in Figure 3(F).

[0069] Subsequently, as shown in FIG. 3(G), photoresists 309a, 309b and 309c are provided on the upper surface of the device. Above the facet defect regions 305a and 305b, gaps 311a and 311b are provided in the photoresist. From a top view, the photoresist will be a single layer with two rectangular gaps above the corresponding facet defect regions. Such a photoresist will be provided by depositing a single photoresist layer and then removing the necessary material to form the rectangular gaps, for example, by electron beam r optical lithography.

[0070] Fig. 3 (H) shows the result of subsequent steps, wherein the area not covered by photoresist has been etched and the photoresist has been removed subsequently.The depth of this etching step is variable.In the example shown in Fig. 3 (H), etching removes about 240nm of 400nm transition buffer, leaving the first district 242a and the second district 242b of transition buffer, and these two districts have the thickness of reduction relative to remaining transition buffer 242.In the alternative case shown in Fig. 3 (H) (i), etching removes all transition buffers not covered by photoresist and can be etched into silicon substrate 201.In this example, the result is the first exposed area 201a and the second exposed area 201b of silicon substrate.Etching also provides the first channel 312a and the second channel 312b, and these two channels constrain the two surfaces of the precursor optical active stack.Usually, the etching depth depends on the thickness of the silicon nitride liner on the bottom of the channel in the next process step, to ensure that the silicon nitride liner top surface is aligned with the top surface of the BOX layer.

[0071] The first precursor optically active stack 310a is now a second precursor optically active stack 310b, which differs from the first precursor optically active stack in that it no longer includes the facet defect regions 305a and 305b.

[0072] After this etching step, the silicon dioxide hard mask 308 is removed and 240 nm thick silicon nitride (e.g. Si3N4) sidewalls are deposited on all exposed surfaces of the device. This is shown in FIG3(I) and provides a first upper liner 313a, a second upper liner 313b and a third upper liner 313c (to be removed) and also provides sidewall liners 204a-204d and a first bottom liner 204e and a second bottom liner 204f, the top surfaces of the first bottom liner 204e and the second bottom liner 204f being aligned with the top surface of the BOX layer, as shown in FIG3(I). Figure 2A shown.

[0073] Next, as shown in FIG. 3(J), amorphous silicon (also referred to as α-Si) is deposited to fill the remaining portions of the first channel 312a and the second channel 312b. A first bulk filling material 505a and a second bulk filling material 505b are provided, which will provide Figure 2A However, there is a large amount of bulk amorphous silicon that is not contained within channels 312a and 312b and should be removed.

[0074] Thus, as shown in FIG3(K), openings 314a-314c are etched into the amorphous silicon that is not present in channels 312a and 312b. These openings increase the uniformity obtained during a subsequent chemical mechanical planarization (CMP) process, the results of which are shown in FIG3(L). The CMP process is performed such that the upper liner portions 313a-313c are reduced to approximately 20nm and the remaining amorphous silicon is substantially aligned with the upper liner portions 313a-313c.

[0075] Next, as shown in FIG3(M), another etching step is performed to align the uppermost surface of the amorphous silicon with the uppermost surface of the second precursor optically active stack. In addition, the upper liner portions 313a-313c are removed, thus exposing the uppermost surface 230 of the second precursor optically active stack 310b. Thereafter, a second hard mask 315 is deposited on the uppermost surface.

[0076] 3(N) shows the subsequent steps from a top view, omitting the second hard mask 315 for clarity. A second photoresist 316 extending from one edge to the other is provided on a central portion of the uppermost surface of the device. The width of the second photoresist (measured in the z-direction) defines the width of the input waveguide, output waveguide and resulting rib portion of the optically active stack. Figure 3(N)A to Figure 3(N)C Cross-sectional views along lines AA', BB', and CC' in FIG. 3(N) are respectively shown.

[0077] The uncovered portion is then etched and Figure 3(O)A to Figure 3(O)C In FIG. 3(O)A taken along cross section AA' of FIG. 3(N) after etching has been performed, it is shown that the input waveguide now comprises Figure 2B 3(O)B, taken along cross section BB' of FIG. 3(N) after etching, shows that the fill material now includes rib portion 205b and plate portion 205c above first bottom liner 204e. In addition, FIG. 3(O)C, taken along cross section CC' of FIG. 3(N) after etching, shows that the second precursor optically active stack has become Figure 2D An optically active stack 210 is shown.

[0078] To provide Figures 2 to 2D The device is shown with the photoresist 316 removed and bulk silicon dioxide provided to passivate the device.

[0079] also, Figure 3(P) to Figure 3(Q)A An optional step is shown in which one or more electrodes are connected to the corresponding layers of the optically active stack.

[0080] FIG3(P) shows the result of another etching step, in which one side of the optically active stack 210 is etched to remove a portion of the P-type buffer layer 240, exposing the upper surface of the transition buffer 242. This is most clearly shown in FIG3(P)(A), which is a cross-sectional view of FIG3(P) taken along line CC'. The views along cross-sections AA' and BB' remain substantially unchanged.

[0081] In addition, as shown in FIG3(Q), a first electrode 601 and a second electrode 602 are provided. As shown most clearly in FIG3(Q)(A), which is a cross section along line CC' of FIG3(Q), the first electrode 601 extends from a position adjacent to the optically active stack (but separated from the transition buffer layer 242 by the upper insulating layer 206) toward the sidewall of the optically active stack and through a through hole in the upper insulating layer 206 to form an electrical contact with the N+ layer 230. Similarly, the second electrode 602 extends through a second through hole in the upper insulating layer 206 to form an electrical contact with the P-type buffer layer 240.

[0082] When connected to the electrodes, the device can be driven, for example, with a voltage between 0 V and 2 V. The optical losses of the device according to the invention are detailed below in Table 2:

[0083]

[0084] Table 2

[0085] Various dimensions are shown on the drawings and these should be considered as indicative rather than limiting values.

[0086] Although the present invention has been described in conjunction with the above exemplary embodiments, with this disclosure, many equivalent modifications and changes will be apparent to those skilled in the art. Therefore, the exemplary embodiments of the present invention set forth above are considered to be illustrative rather than restrictive. Various changes to the described embodiments may be made without departing from the spirit and scope of the present invention.

[0087] All references mentioned above are hereby incorporated by reference.

Claims

1. A silicon-based electro-optical active device comprising: Silicon-on-insulator SOI waveguide; an electro-optic active waveguide comprising an electro-optic active stack within a cavity of said SOI waveguide; as well as a lined channel between the electro-optical active stack and the SOI waveguide, the lined channel comprising a liner; wherein the lined channel is filled with a fill material having a refractive index similar to the refractive index of a material forming the sidewalls of the cavity, thereby forming a bridge waveguide in the channel between the SOI waveguide and the electro-optical active stack; The liner includes a first sidewall between the SOI waveguide and the filling material, the first sidewall including a material different from that of the SOI waveguide.

2. The silicon-based electro-optical active device of claim 1, wherein the liner is formed of silicon nitride.

3. A silicon-based electro-optical active device as described in claim 1 or claim 2, wherein the lowermost surface of the sidewall of the channel and the top surface of the portion of the liner located in the bottom of the channel are aligned with the top surface of the buried oxide layer of the SOI.

4. A silicon-based electro-optical active device as claimed in claim 1 or claim 2, wherein the liner has a thickness of at least 200 nm and no more than 280 nm.

5. A silicon-based electro-optical active device as claimed in claim 1 or claim 2, wherein the electro-optical active stack comprises a multi-quantum well region.

6. A silicon-based electro-optical active device as claimed in claim 1 or claim 2, wherein the fill material is amorphous silicon.

7. A silicon-based electro-optical active device as claimed in claim 1 or claim 2, wherein the filling material is silicon germanium (SiGe).

8. A silicon-based electro-optical active device as claimed in claim 1 or claim 2, wherein the electro-optical active stack has a parallelogram or trapezoidal geometry.

9. A silicon-based electro-optical active device as described in claim 1 or claim 2, further comprising an epitaxial cladding layer located between the silicon substrate of the SOI device and the optically active region forming the electro-optical active waveguide, and the refractive index of the epitaxial cladding layer is less than the refractive index of the buffer layer in the electro-optical active stack.

10. The silicon-based electro-optical active device of claim 9, wherein the epitaxial material is silicon.

11. The silicon-based electro-optical active device of claim 9, wherein the epitaxial material is silicon germanium (SiGe).

12. A method of producing a silicon-based electro-optical active device, comprising the steps of: Providing silicon-on-insulator SOI waveguides; etching a cavity in a portion of the SOI waveguide through the BOX layer of the SOI waveguide; epitaxially growing an electro-optical active stack within the cavity, and etching the electro-optical active stack to form an electro-optical active waveguide, wherein the epitaxially grown electro-optical active stack has facets in regions adjacent to sidewalls of the cavity; etching the region thereby removing the facet and creating a channel between the sidewall and the stack; lining the passage with a liner to provide a lined passage; as well as filling the lined channel with a fill material having a refractive index similar to the refractive index of the material forming the sidewalls such that the fill material forms a bridge waveguide in the channel between the SOI waveguide and the electro-optical active stack; The liner includes a first sidewall between the SOI waveguide and the filling material, the first sidewall including a material different from that of the SOI waveguide.

13. The method of claim 12, wherein the liner is formed of silicon nitride.

14. A method as claimed in claim 12 or 13, wherein the liner has a thickness of at least 200 nm and no more than 280 nm.

15. The method of claim 12 or 13, wherein the electro-optical active stack comprises a multi-quantum well region.

16. The method of claim 12 or 13, wherein the fill material filling the lined via comprises amorphous silicon.

17. The method of claim 12 or 13, wherein the filling material filling the lined via comprises silicon germanium (SiGe).

18. The method of claim 12 or 13, wherein the step of filling the lined channel is performed by plasma enhanced chemical vapor deposition.

19. The method of claim 12 or 13, wherein the step of filling the lined channel is performed by hot wire chemical vapor deposition.

20. The method of claim 12 or 13, further comprising the step of planarizing the filling material by chemical mechanical polishing.

21. The method of claim 12 or 13, wherein: The epitaxially grown electro-optical active stack has a second facet in a second region adjacent to an opposite sidewall of the cavity, and wherein the etching step also removes the second region, thereby removing the second facet and creating a second channel between the opposite sidewall and the stack; the filling step also fills the second channel with amorphous silicon.

22. The method of claim 21, wherein the silicon-based electro-optical active device is an electro-absorption modulator based on the quantum confined Stark effect.

23. A method as claimed in claim 22, wherein the epitaxially grown stack comprises a buffer layer, and the method comprises adjusting the height of the buffer layer so that the optical mode in the modulator matches the optical mode in the SOI waveguide.

24. A method as claimed in claim 12 or 13, wherein the electro-optical active stack is grown in such a way that it has a parallelogram or trapezoidal geometry in the cavity.

25. The method of claim 12 or 13, wherein the step of etching a cavity in a portion of the SOI waveguide comprises the steps of: The SOI is etched down to or beyond the bottom of its buried oxide BOX layer to form a box-free region.

26. The method of claim 25, further comprising the step of growing a cladding layer within the etched cavity, wherein the epitaxially grown stack includes a buffer layer, the cladding layer having a refractive index less than a refractive index of the buffer layer.

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