Active clamp circuit built into driver IC to protect IGBT
The active clamping circuit in the driver IC addresses the issue of secondary conduction in IGBTs by integrating a comparator and diodes to manage voltage, ensuring safe operation and preventing IGBT damage.
Patent Information
- Application Number
- CN201910627038.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2019-07-12
- Publication Date
- 2024-12-10
- Estimated Expiration
- 2039-07-12
AI Technical Summary
Existing IGBT protection circuits fail to effectively prevent secondary conduction due to varying Miller capacitances among different IGBTs, despite the use of negative power supplies, which can lead to excessive heating and damage.
An active clamping circuit integrated into a driver IC, comprising a comparator, RS latch, AND gate, clamping diode, and active clamping tube, with a negative power supply design, to manage gate-emitter voltage and prevent secondary conduction.
The active clamping circuit effectively maintains the gate-emitter voltage within safe limits, preventing IGBT damage by ensuring it remains off during shutdown, thus providing reliable protection.
Smart Images
Figure CN110289601B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of IGBT driver chips, and in particular to an active clamping circuit built into a driver IC for protecting an IGBT. Background Art
[0002] IGBT combines the advantages of MOSFET and BJT. It has the advantages of MOSFET such as high input impedance, fast operation speed, simple driving, etc., and has the advantages of BJT such as low saturation voltage drop, large current capacity, high withstand voltage, etc. In recent years, IGBT has been widely used in the high-power market.
[0003] Generally speaking, the gate-emitter drive voltage V GE The guaranteed value is ±20V. If it exceeds this range, the IGBT may be damaged. When the IGBT is turned off, the collector voltage will suddenly rise from a low voltage to a very high voltage, and there will be a large dv / dt. However, due to the existence of Miller capacitance between the gate and the collector, a higher glitch voltage will be induced at the gate end. As mentioned earlier, if the voltage exceeds 20V, the IGBT is at risk of damage. Therefore, a gate voltage limiting circuit needs to be set in the IGBT drive circuit. In application, the usual practice is to add a clamping circuit between the gate and emitter of the IGBT, and often a resistor is connected in parallel to eliminate the charge accumulated on the gate capacitance. The corresponding circuit structure is as follows Figure 1 shown.
[0004] However, although this approach can avoid the risk of overvoltage between the gate and emitter of the IGBT, the voltage coupled through the Miller capacitor is enough to turn the IGBT on again. After the IGBT is turned off, the voltage between its collector and emitter is very high. If the IGBT is turned on again, it may cause excessive heating and damage to the IGBT. In application, in order to avoid the IGBT from being turned on again, the usual practice is to use a negative power supply, such as Figure 2 As shown. The left side of the dotted line is the driver IC, and the right side is the IGBT. P1 and N1 in the circuit are the driver tube and the discharge tube respectively. VCC is the positive power pin of the driver IC, OUT is the driver pin of the driver IC, VEE is the negative power pin of the driver IC, and GND is the zero potential pin. When the IGBT is turned off, the discharge tube N1 pulls the OUT voltage to the negative potential VEE. At this time, a large dv / dt appears at the collector of the IGBT. After Miller capacitance coupling, the OUT voltage may rise a certain voltage relative to VEE, but it may still be lower than the voltage of GND, and the IGBT cannot be turned on again.
[0005] However, due to the wide variety of IGBTs on the market, the Miller capacitance of different IGBTs is different, and it is impossible to use negative power supplies with different values for different IGBTs. Although this method can effectively avoid the secondary conduction of IGBT, it cannot fundamentally prevent the occurrence of secondary conduction of IGBT. Summary of the invention
[0006] The purpose of the present invention is to provide an active clamping circuit with a simple structure for protecting IGBT and built into a driver IC. The circuit can prevent the gate-emitter voltage of the IGBT from being too high and avoid the secondary conduction of the IGBT during the shutdown period, thereby achieving effective and reliable protection for the IGBT.
[0007] In order to achieve the above-mentioned purpose, the technical solution adopted by the present invention is an active clamping circuit built into a driver IC for protecting an IGBT, comprising an IGBT driver IC, a comparator arranged inside the IGBT driver IC, an RS latch, an AND gate, a clamping diode, and an active clamping tube. The driver IC adopts a negative power supply design, the gate of the IGBT is connected to the driving pin of the driver IC, the emitter of the IGBT is connected to the zero potential pin of the driver IC, the inverting input terminal of the comparator is connected to the driving pin of the driver IC, the non-inverting input terminal of the comparator is connected to the reference voltage signal, the output terminal of the comparator is connected to the R terminal of the RS latch, the driving signal is connected to the S terminal of the RS latch, the Q output terminal of the RS latch is connected to an input terminal of the AND gate, the inverse signal of the driving signal is connected to the other input terminal of the AND gate, the output terminal of the AND gate is connected to the gate of the active clamping tube, the drain of the active clamping tube is connected to the driving pin of the driver IC, the source of the active clamping tube is connected to the negative power supply pin of the driver IC, and the clamping diode is connected in series between the driving pin and the zero potential pin of the driver IC.
[0008] As an improvement of the present invention, the driver IC is further provided with an upper driver tube, a lower driver tube (or a discharge tube) and a driving logic module, the source of the upper driver tube is connected to the positive power pin of the driver IC, the drain of the upper driver tube is connected to the driving pin of the driver IC, the drain of the discharge tube is connected to the driving pin of the driver IC, the source of the discharge tube is connected to the negative power pin of the driver IC, the gates of the upper driver tube and the discharge tube are connected in common and then connected to the output end of the driving logic module, and the input end of the driving logic module is connected to the driving signal.
[0009] As an improvement of the present invention, a PWM module is further provided in the driver IC, the input end of the PWM module is connected to the input pin of the driver IC, the output end of the PWM module is led out as a drive output end, the drive output end outputs a drive signal, the input pin of the driver IC is connected to a square wave signal, and the timing of the drive signal is consistent with the timing of the square wave signal.
[0010] As an improvement of the present invention, the voltage value of the reference voltage signal is 2V, and the inverse signal of the driving signal is realized by outputting the driving signal through an inverter.
[0011] As an improvement of the present invention, the active clamping tube adopts an NMOS tube.
[0012] As an improvement of the present invention, the upper driving tube adopts a high-voltage PMOS tube, and the discharge tube adopts a high-voltage NMOS tube.
[0013] As an improvement of the present invention, the clamping diode is formed by 2 to 3 Zener diodes connected in series.
[0014] As an improvement of the present invention, the output voltage range of the driving pin of the driving IC is 10-15V.
[0015] Compared with the prior art, the overall structural design of the present invention is ingenious, and the structure is reasonable and stable. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 The invention relates to an IGBT driving circuit with a gate voltage limiting circuit in the prior art.
[0017] Figure 2 The circuit structure diagram of a driver IC for driving an IGBT in the prior art using a negative power supply is shown.
[0018] Figure 3 The active clamping circuit built into the driver IC for protecting the IGBT is a preferred embodiment of the present invention.
[0019] Figure 4 1 is a waveform diagram of the driving signal and driving pin output voltage of the driving IC according to a preferred embodiment of the present invention. DETAILED DESCRIPTION
[0020] In order to deepen the understanding and recognition of the present invention, the present invention is further described and introduced below in conjunction with the accompanying drawings.
[0021] like Figure 3As shown in the figure, an active clamping circuit built into a driver IC for protecting an IGBT according to a preferred embodiment of the present invention includes an IGBT driver IC for controlling the on and off of the IGBT, a comparator CMP, an RS latch, an AND gate, a clamping diode Z1, an active clamping tube N1, an upper driver tube P0, a discharge tube N0, a driver logic module DriverLogic and a PWM module. The driver IC adopts a negative power supply design, and a negative power supply pin VEE is provided on the driver IC. The gate of the IGBT Connect the driving pin OUT of the driver IC, the emitter of the IGBT is connected to the zero potential pin GND of the driver IC, the inverting input terminal of the comparator CMP is connected to the driving pin OUT of the driver IC, the non-inverting input terminal of the comparator CMP is connected to the reference voltage signal, the output terminal of the comparator CMP is connected to the R terminal of the RS latch, the driving signal DRV is connected to the S terminal of the RS latch, the Q output terminal of the RS latch is connected to one input terminal of the AND gate, and the inverted signal DRV_B of the driving signal is connected to the other input terminal of the AND gate. The signal is obtained by outputting the driving signal DRV through the inverter. The output terminal of the AND gate is connected to the gate of the active clamp tube N1, the drain of the active clamp tube N1 is connected to the driving pin OUT of the driver IC, the source of the active clamp tube N1 is connected to the negative power pin VEE of the driver IC, and the clamp diode Z1 is connected in series between the driving pin OUT of the driver IC and the zero potential pin GND. The source of the upper driver tube P0 is connected to the positive power pin VCC of the driver IC, the drain of the upper driver tube P0 is connected to the driving pin OUT of the driver IC, the drain of the discharge tube N0 is connected to the driving pin OUT of the driver IC, the source of the discharge tube N0 is connected to the negative power pin VEE of the driver IC, and the gates of the upper driver tube P0 and the discharge tube N0 are connected in series and connected to the output end of the driver logic module DriverLogic, and the input end of the driver logic module DriverLogic is connected to the drive signal DRV. The input end of the PWM module is connected to the input pin IN of the driver IC, and the output end of the PWM module is led out as the drive output end, and the drive output end outputs the drive signal DRV. The input pin IN of the driver IC is connected to the square wave signal. The PWM module performs PWM processing on the square wave signal input by the input pin IN, thereby obtaining a PWM pulse signal that is consistent with the timing of the square wave signal as the drive signal DRV, such as Figure 4 shown.
[0022] Since the turn-on threshold of IGBT is usually 2~4V, the IGBT will be turned off and a large dv / dt will appear at the collector of the IGBT only when the gate voltage of the IGBT drops below its turn-on threshold voltage. Therefore, the voltage value of the reference voltage signal input to the comparator CMP is set to 2V.
[0023] In addition, the upper driving tube P0 adopts a high-voltage PMOS tube, and the discharge tube N0 adopts a high-voltage NMOS tube. The driving logic module DriverLogic converts the input low-voltage driving signal DRV into a high-voltage signal with strong driving capability after logic processing to control the upper driving tube P0 and the discharge tube N0. When the IGBT is turned on, the upper driving tube P0 will pull up the output voltage of the driving pin OUT of the driving IC to the positive power supply of the driving IC, and when the IGBT is turned off, the discharge tube N0 will pull down the output voltage of the driving pin OUT of the driving IC to the negative power supply of the driving IC. Therefore, the function of the driver logic module DriverLogic is to perform logic processing first and then convert low voltage to high voltage processing. The logic processing refers to the calculation of the drive signal DRV and other various protection signals (such as overvoltage, overcurrent, overtemperature, open circuit protection, short circuit protection, etc.) (under normal circumstances, other various protection signals are all high level) to determine whether to allow the drive signal DRV to be transmitted backward. If a certain protection is triggered, the logic processing will output a low level and turn off the IGBT; and the low voltage to high voltage processing refers to the boost processing of the drive signal DRV transmitted after the logic processing (that is, from low voltage to a voltage that can drive the upper driver tube P0 and the discharge tube N0). The active clamp tube N1 adopts an NMOS tube, and the Ctrl signal output by the AND gate is used as the control signal to control the active clamp tube N1.
[0024] The clamping diode Z1 is a voltage regulator diode. Furthermore, the clamping diode Z1 is formed by connecting 2-3 Zener diodes in series. The clamping diode Z1 can clamp the output voltage of the driving pin OUT of the driving IC within 10V-15V. Figure 4 As shown, ensure that the gate-source voltage of the IGBT is within a reasonable range, which can ensure that the gate-source voltage difference of the IGBT is not too high to avoid the breakdown and damage of the IGBT, and also ensure that the gate-source voltage difference of the IGBT is not too low to avoid the insufficient conduction of the IGBT.
[0025] The circuit working principle of the above preferred embodiment is as follows:
[0026] like Figure 4 As shown, during the IGBT conduction period, that is, during t1~t2, the drive pin OUT output of the driver IC is high level, the drive signal DRV is high level, the inverse signal DRV_B of the drive signal is low level, the active clamp tube N1 is not turned on, and it will not pull down the output voltage of the drive pin OUT of the driver IC. At this time, the RS latch output is low level.
[0027] After the IGBT is turned off, until the output voltage of the driver IC's drive pin OUT drops to 2V, that is, during t2~t3, the drive signal DRV is low level, and the inverse signal of the drive signal DRV_B is high level. Since the output voltage of the driver IC's drive pin OUT is greater than 2V, the comparator outputs a low level, and the RS latch output signal maintains the original state, that is, a low level. At this time, the active clamp tube N1 is still not turned on. During t3~t4, the drive signal DRV turns to a low level, the inverse signal of the drive signal DRV_B is a high level, the output voltage of the driver IC's drive pin OUT is lower than 2V, and the comparator outputs a high level. After that, the RS latch output is latched at a high level, and the active clamp tube N1 will always be turned on. At this time, a large dv / dt appears at the collector of the IGBT, and the output voltage of the driver pin OUT of the driver IC is pulled up through the Maitreya capacitor. Since the active clamp tube N1 is in the on state, the pulled-up output voltage of the driver pin OUT of the driver IC will be immediately discharged by the active clamp tube N1. Therefore, during the IGBT shutdown period, the output voltage of the driver pin OUT of the driver IC will be maintained at the voltage level of the negative power supply, thereby ensuring that the IGBT will not be turned on again.
[0028] The technical means disclosed in the scheme of the present invention are not limited to the technical means disclosed in the above-mentioned implementation mode, but also include technical schemes composed of any combination of the above-mentioned technical features. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications are also regarded as the protection scope of the present invention.
Claims
1. An active clamping circuit built into a driver IC for protecting an IGBT, characterized in that: It includes an IGBT driver IC, a comparator, an RS latch, an AND gate, a clamping diode, an active clamping tube, an upper driving tube, a discharge tube, a driving logic module and a PWM module arranged inside the IGBT driver IC. The driver IC adopts a negative power supply design. The gate of the IGBT is connected to the driving pin of the driver IC, the emitter of the IGBT is connected to the zero potential pin of the driver IC, the inverting input terminal of the comparator is connected to the driving pin of the driver IC, the non-inverting input terminal of the comparator is connected to the reference voltage signal, the output terminal of the comparator is connected to the R terminal of the RS latch, the driving signal is connected to the S terminal of the RS latch, the Q output terminal of the RS latch is connected to an input terminal of the AND gate, the inverse signal of the driving signal is connected to the other input terminal of the AND gate, the output terminal of the AND gate is connected to the gate of the active clamping tube, the drain of the active clamping tube is connected to the driving pin of the driver IC, the source of the active clamping tube is connected to the negative power supply pin of the driver IC, the clamping diode is connected in series between the driving pin and the zero potential pin of the driver IC, and the clamping diode clamps the output voltage of the driving pin of the driver IC within 10V~15V; The source of the upper driving tube is connected to the positive power pin of the driving IC, the drain of the upper driving tube is connected to the driving pin of the driving IC, the drain of the discharge tube is connected to the driving pin of the driving IC, the source of the discharge tube is connected to the negative power pin of the driving IC, the gates of the upper driving tube and the discharge tube are connected in common and then connected to the output end of the driving logic module, and the input end of the driving logic module is connected to the driving signal; the input end of the PWM module is connected to the input pin of the driving IC, the output end of the PWM module is led out as the driving output end, the driving output end outputs the driving signal, the input pin of the driving IC is connected to the square wave signal, the PWM module performs PWM processing on the square wave signal input by the input pin to obtain a PWM pulse signal as the driving signal, and the timing of the driving signal is consistent with the timing of the square wave signal; the driving logic module converts the input low-voltage driving signal into a high-voltage signal after logic processing to control the upper driving tube and the discharge tube, when the IGBT is turned on, the upper driving tube pulls up the output voltage of the driving pin of the driving IC to the positive power supply of the driving IC, and when the IGBT is turned off, the discharge tube pulls down the output voltage of the driving pin of the driving IC to the negative power supply of the driving IC.
2. An active clamping circuit built into a driver IC for protecting an IGBT as claimed in claim 1, characterized in that: The voltage value of the reference voltage signal is 2V, and the inverse signal of the driving signal is realized by outputting the driving signal through an inverter.
3. The active clamping circuit built into a driver IC for protecting an IGBT as claimed in claim 2, characterized in that: The active clamping tube is an NMOS tube.
4. The active clamping circuit built into a driver IC for protecting an IGBT as claimed in claim 3, characterized in that: The upper driving tube is a high-voltage PMOS tube, and the discharge tube is a high-voltage NMOS tube.
5. The active clamping circuit built into a driver IC for protecting an IGBT as claimed in claim 4, characterized in that: The clamping diode is a voltage regulator diode.
6. The active clamping circuit built into a driver IC for protecting an IGBT as claimed in claim 5, characterized in that: The clamping diode is formed by connecting 2 to 3 Zener diodes in series.
7. An active clamping circuit built into a driver IC for protecting an IGBT as claimed in claim 6, characterized in that: The output voltage range of the driving pin of the driving IC is 10~15V.