Method for managing a transaction routed between a source device and a target device

Abstract

Embodiments of the present disclosure relate to methods for managing transactions routed between a source device and a target device. A system-on-chip includes an interconnect circuit that includes at least one input interface and a plurality of output interfaces. The source device is coupled to the input interface. The target device includes a sectorized addressable memory space and a plurality of access ports, which are respectively coupled to the output interfaces. The source device is configured to deliver a transaction containing an address word to the target device.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to French Patent Application No. 1853304, filed on April 16, 2018, which is incorporated herein by reference. Technical Field

[0003] The present disclosure generally relates to routing between devices, and in particular embodiments relates to a method for managing a transaction for routing between a source device and a target device. Background Art

[0004] There is a need to be able to manage such routing, for example according to address priorities and / or Quality of Service (QoS) criteria, and to manage it flexibly according to the envisaged application. Specifically, different applications may employ different devices and / or may require different addressing priority criteria to be assigned depending on the nature of the source device. Summary of the Invention

[0005] According to one aspect, a system-on-chip is proposed, which includes an interconnect circuit that includes at least one input interface and a plurality of output interfaces. At least one source device is coupled to the input interface. At least one target device (e.g., a multi-port memory) has a sectorized addressable space and a plurality of access ports, and the plurality of access ports are respectively coupled to the output interfaces. At least one source device is configured to deliver a transaction (e.g., a read or write transaction) including an address word to at least one target device.

[0006] When multiple source devices are provided, transactions issued by different source devices may be issued sequentially or simultaneously.

[0007] When multiple target devices are provided, all target devices may receive transactions from all source devices, or in fact some of these target devices may only receive transactions from some of the source devices.

[0008] The system-on-chip further includes at least one programmable control module, and the at least one programmable control module is coupled to at least one source device.

[0009] The control module includes a table (lookup table) that is configured to indicate one of the access ports for each sector of the addressable space once the control module is programmed.

[0010] The control module further includes a control circuit that is capable of delivering a control word to the interconnect circuit in the presence of each transaction from at least one source device, and the control word specifies the access port indicated in the table based on the address word included in the transaction.

[0011] Then, the interconnect circuit is configured to route transactions from at least one input interface to an output interface coupled to the access port, and to deliver the transactions to the access port, where the content of each transaction delivered to the access port is the same as the content of the corresponding transaction delivered by the source device, regardless of the access port selected.

[0012] Thus, the interconnect circuit is configured to receive a control word with each transaction and route the transaction to one of the access ports in the access port according to the value of the control word.

[0013] In addition, depending on the envisaged application, i.e., for example, depending on the nature of one or more source devices and on the need to assign priorities to certain addressing transactions originating from one or more source devices, the user will likely program the content of the associated table for each source device in order to assign the access ports of one or more target devices to each sector of the addressing space of the corresponding target device.

[0014] Thus, for each transaction originating from a source device, the control circuit included in the control module will be able to verify which sector the address word included in the transaction is targeted at, and adjust the value of the corresponding control word in order to specify the access port associated with that sector and mentioned in the corresponding table.

[0015] Then, in the presence of such a value of the control word, the interconnect circuit is configured to route the transaction from at least one input interface to an output interface that is coupled to the selected access port.

[0016] In addition, regardless of the access port selected for a transaction originating from a source device, the content of the transaction delivered to the access port is the same as the content of the transaction delivered by the source device. In other words, if for example the target device is a dual-port memory and if the transaction includes a memory write address, the transaction must not be interrupted by the control word, i.e., regardless of the access port of the memory, its content must be the same in order to ensure that the transaction is routed to the same address in the memory space of the memory, regardless of the access port that receives it.

[0017] Thus, the same system-on-chip can be used for various applications, such as those that require the assignment of different priorities and thus the assignment of different access ports.

[0018] According to one implementation, a particularly simple way to ensure that the content of each transaction delivered to the access port is the same as the content of the corresponding transaction delivered by the source device, regardless of the access port selected, is to provide each transaction to be routed to the corresponding output interface together with the control word and an output interface that is configured not to deliver the control word to the corresponding access port.

[0019] According to one embodiment, each transaction is merged into a master word of n bits, and the control word includes m additional bits.

[0020] The value of m is at least equal to 1 and depends on the number of access ports to be selected.

[0021] Thus, if the number of access ports is equal to 2, m will probably be equal to 1. If the number of access ports is equal to 3 or 4, m will be equal to 2.

[0022] Each control circuit is configured to adjust the value of the m bits so as to specify an access port based on the corresponding table and the address word included in the transaction.

[0023] Then, each input interface is configured to receive a total word of n + m bits including the master word and the control word.

[0024] Then, the interconnection circuit is advantageously configured to route the total word to the corresponding output interface, and the corresponding output interface is advantageously configured not to deliver the control word to the access port.

[0025] According to one embodiment, each input interface is coupled to a corresponding source device via an input bus of n tracks and to a corresponding control module via a control bus of m tracks.

[0026] The total word of n + m bits is intended to be routed on an internal network of a bus of n + m tracks within the interconnection circuit.

[0027] Each output interface is configured to receive an internal bus of n + m bits and is coupled to a corresponding access port via an output bus of n tracks. The m tracks of the n + m tracks internal bus leading to the corresponding output interface are not connected to the access port.

[0028] It is possible for the control module to be programmed by at least one source device.

[0029] When multiple source devices are respectively coupled to multiple corresponding control modules and the interconnection circuit then includes multiple input interfaces respectively coupled to the source devices, each control module can be programmed by one of the source devices.

[0030] The source device capable of programming each control module may include a programmable core or a microprocessor.

[0031] The source device may advantageously incorporate a software application that includes instructions intended to program each table included in each control module.

[0032] At least one target device may include a multi-port memory.

[0033] According to another aspect, a method for managing the routing of transactions within a system-on-chip between at least one source device delivering a transaction and at least one target device having a sectorized addressable space and a plurality of access ports is presented, each transaction including an address word.

[0034] The method according to this aspect includes: providing the system-on-chip with an interconnect circuit including at least one input interface and a plurality of output interfaces; coupling the at least one input interface to the at least one source device respectively, and coupling the output interfaces to the access ports respectively; configuring each input interface such that it can receive each transaction originating from the corresponding source device and a control word of a programmable value associated with the transaction; configuring the interconnect circuit such that each transaction and its control word are routed to one of the output interfaces according to the value of the control word; configuring each output interface such that the corresponding transaction is delivered to the access port coupled to the output interface, and the corresponding control word is not limited to the access port; and for each source device, programming a table indicating one of the access ports for each sector of the memory space, and for each transaction, adjusting the value of the control word according to the address word included in the transaction and the content of the table.

[0035] According to one implementation, the method includes: loading a software application including instructions for programming the table into at least one of the source devices, and programming the table by executing the software application.

[0036] According to one implementation, applicable to managing the routing of transactions within a system-on-chip between a plurality of source devices delivering transactions and at least one target device, the method includes: loading a software application including instructions for programming each table associated with each source device into at least one of the source devices, and programming the tables by executing the software application.

[0037] The source device including the software application program may include a programmable core or a microprocessor.

[0038] The at least one target device may include a multi-port memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Other advantages and features of the present invention will become apparent through a complete and non-limiting detailed description of implementations and embodiments, and the drawings, in which:

[0040] Figures 1 to 6 Implementations and embodiments of the present invention are schematically illustrated. DETAILED DESCRIPTION

[0041] The implementation and embodiments of the present invention relate to the routing of transactions between at least one source device and at least one target device (e.g., but not limited to, a multi-port memory) within a system-on-chip (SoC), and more particularly to the routing management of such transactions targeted at addressing the sectorized memory space of the target device.

[0042] In Figure 1 , reference numeral 1 designates a system-on-chip, which includes a plurality of source devices ES1 - ESp that can be of different types / natures.

[0043] Thus, one of the devices (e.g., device ES1) can be an LCD screen controller, another device (e.g., device ES2) can be a processor for signal processing, another source device can be, for example, a decoder, and another source device (e.g., device ESp) can be a microprocessor, such as the microprocessor sold by STMicroelectronics under the number STM32.

[0044] The system-on-chip 1 also includes at least one target device EC, such as a multi-port random access memory, here a memory including three access ports PA0, PA1, and PA2.

[0045] Of course, multiple target devices with different or the same nature can be provided on the system-on-chip 1.

[0046] To circuit-interconnect the source device ESi and the target device EC, the system-on-chip 1 also includes an interconnect circuit ICN.

[0047] The interconnect circuit ICN includes input interfaces IE1 - IEp and output interfaces IS0 - IS2, where the input interfaces IE1 - IEp are respectively coupled to the source devices ES1 - ESp, and the output interfaces IS0 - IS2 are respectively coupled to the access ports PA0 - PA2 of the target device EC.

[0048] Such an interconnect circuit ICN is capable of routing transactions between various source devices and one or more target devices.

[0049] A transaction can be, for example, a write transaction or a read transaction in the memory EC.

[0050] The structure of such an interconnect circuit ICN (usually a multi-layer interconnect circuit) and the protocol allowing the routing and switching of transactions within the interconnect circuit are well-known to those skilled in the art.

[0051] For example, the latter can refer to the article by Venkateswara Rao et al., titled “A Frame work on AMBA bus based Communication Architecture to improve the Real Time Computing Performance in MPSoC”, International Journal of Computer Applications (0975 - 8887), Volume 91 - Issue 5, April 2014; or the general introduction of these interconnect circuits given by A. Gerstlauer in 2015, available at the Internet address: http: / / users.ece.utexas.edu / ~gerstl / ee382v_f14 / lectures / lecture_12.pdf.

[0052] In addition, by way of non - limiting indication, for example, the interconnect sold by the company ARM with the number NIC - 400 (version R0p3) can be used.

[0053] As Figure 1 shown, each input interface IEi of the interconnect circuit ICN is connected to the corresponding source device ESi via an n - bit bus BSi.

[0054] In the example described herein, the bus is a 32 - bit bus.

[0055] Each transaction originating from the source device ESi is merged into an n - bit word called a “master word”, which is transmitted on the bus BSi.

[0056] As is known in the art, a transaction (such as a write transaction) particularly includes an address field, control bits, and a field for the data to be written.

[0057] For example, the address included in a transaction can be encoded in 16 bits.

[0058] In addition, the system - on - chip 1 includes a control module MCMi, for which more details of its structure and function will be given below. The control module MCMi is respectively assigned and coupled to various source devices ES1 - ESp, and is connected to the corresponding input interfaces IE1 - IEp by m - bit control buses BC1 - BCp respectively.

[0059] Thus, each of the input interfaces IE1 - IEp is coupled to an n + m - bit bus.

[0060] The size of m for each bus BCi depends on the number of access ports of one or more target devices EC.

[0061] In the current case, since device EC has three access ports PA0, PA1, and PA2, for device E, m is equal to 2.

[0062] Therefore, each control module delivers 2 bits that form a control word, which will be transmitted together with a 32-bit master word containing a transaction on the corresponding bus BCi.

[0063] As will be seen in more detail below, control module MCMi is programmable.

[0064] In the example described here, the control module is programmed by one of the source devices in the source device, which in the current case is source device ESp, which is here, for example, an STM 32 microprocessor.

[0065] The 32-bit master word and the 2-bit control word form a 34-bit total word.

[0066] Generally, various 34-bit total words BSGi are transmitted to various output interfaces IS0 - IS2 through a network of n + m track internal buses.

[0067] In the example described here (n = 32 and m = 2), various 34-bit total words BSGi are transmitted to various output interfaces IS0 - IS2 through a network of 34-track internal buses.

[0068] Therefore, each output interface is configured to receive an n + m-bit internal bus (in this example, a 34-bit bus), which in the current case is internal bus BSGS0 for interface IS0, internal bus BSGS1 for interface IS1, and internal bus BSGS2 for interface IS2.

[0069] Conversely, as Figure 1 shown, only the n tracks of buses BSGS0, BSGS1, and BSGS2 that are intended to contain transactions (n = 32 in this example) are connected to access ports PA0, PA1, PA2.

[0070] In other words, the m tracks (here, the 33rd and 34th tracks) that transmit the m-bit control word (here, a 2-bit control word) are not connected to the corresponding access ports.

[0071] Therefore, regardless of the access port selected, the transaction delivered to the access port is the same as the transaction originating from the source device.

[0072] Depending on the value of the control word delivered by the corresponding control module MCMi, a transaction originating from the corresponding source device will be routed to output interface IS0 and thus to access port PA0, or to output interface IS1 and thus to access port PA1, or to output interface IS2 and thus to access port PA2.

[0073] Thus, as a non-limiting example, in the case of m = 2, if the value of the control word is equal to the bit sequence 00, the transaction will be routed to access port PA0, and if the value of the control word is equal to the bit sequence 01, the transaction will be routed to access port PA1, and if the value of the control word is equal to the bit sequence 10, the transaction will be routed to access port PA2.

[0074] In practice, for example, the control bits are the two most significant bits in the address word included in the transaction.

[0075] Therefore, if the address word included in the transaction is a 16-bit word, the address word transmitted on the network of the internal bus of the interconnection circuit ICN is an 18-bit word. Thus, the interconnection circuit ICN interprets the 18-bit word as an 18-bit address. Then, the interconnection circuit ICN is configured to route the 18-bit word to output interface IS0 or output interface IS1 or output interface IS2 according to the value of the two most significant bits.

[0076] The interconnection circuit ICN is configured in a conventional manner, for example in VHDL. Then, the VHDL is converted into a hardware circuit that includes a control circuit, switches, and buses, and the various paths of the hardware circuit are defined by the configuration of the interconnection circuit ICN.

[0077] Now refer more specifically to Figures 2 to 5 for an example of the management of the routing of transactions in detail.

[0078] The target element EC (in the current case a multi-port memory) includes an addressable memory space EMM that is sectorized or partitioned. Thus, in Figure 2 the example shown, the memory space EMM includes sectors SCT0 - SCTk. The number of sectors depends on the size of the memory space.

[0079] Depending on the envisaged application and / or the nature of one or more source elements, one or more sectors can be assigned a high priority relative to other sectors that are assigned a low priority. The priority order can depend, for example, on the content stored in the sectors. Thus, if one or more sectors include program code that must always be accessible by one or more source elements (such as a microprocessor), then regardless of the traffic density inside the interconnection circuit ICN, one or more sectors of the memory space will be assigned a high priority.

[0080] In addition, one of the access ports in the access ports of the target device EC will be assigned to these priority sectors, for example, while the other sectors will be associated with other access ports.

[0081] As Figure 3 shown, this correspondence between the sectors and the access ports is stored in a table (lookup table) TBi. In practice, each source device has a table TBi. The content of the table can vary from table to table or be the same between at least some of the tables.

[0082] As Figure 4 shown, the table TBi belongs to the control module MCMi, and the control module MCMi is associated with and coupled to the source element ESi.

[0083] The table TBi can be programmed by one of the source devices in the source device (in this case, the source device ESp), which is a programmable core or a microprocessor.

[0084] The control module MCMi also includes a control circuit CCMi, which is generated using, for example, a logic circuit and is configured to communicate with the table TBi and receive the address word ADRi included in each transaction Ti originating from the source element ESi.

[0085] In addition, as Figure 5 shown, based on the address word ADRi, the control circuit CCMi determines which sector of the memory space EMM the address word ADRi corresponds to and thus determines the access port that the transaction Ti is intended for.

[0086] Knowing the destination access port (for example, the access port PA2), the control circuit CCMi is then configured to generate the value of the control word MCi that will be delivered on the control bus BCi.

[0087] In the current case, since the access port PA2 is specified, the value of the control word MCi is equal to the bit sequence 10, allowing the interconnection circuit ICn to route the transaction Ti to the output interface IS2 and thus to the access port PA2.

[0088] Programming the table TBi by the user according to the envisioned application allows the system-on-chip to have great flexibility in use. Therefore, not only can the priority order be changed according to the application, but other applications can also assign, for example, a given access port for all sectors of the memory space EMM of the target device to one or more source devices. Then, this is equivalent to assigning one access port to one source device and routing all transactions originating from that source device to that access port.

[0089] Thus, depending on the nature of the source device, it may be decided to route all transactions from the source device to one access port and, for example, all transactions originating from other source devices to one or more other access ports.

[0090] An example of managing transaction routing is illustrated in Figure 6 .

[0091] In a first step S20, the interconnect circuit ICN is coupled to various source devices ESi, various access ports PAj, and a control module MCMi.

[0092] Next, in step S21, the interconnect circuit ICN is configured such that the routing of transactions to the access ports depends on the logical value of a control word associated with the transaction.

[0093] Although step S21 is shown in Figure 6 after step S20, it will of course be entirely possible to first configure the interconnect circuit ICN so as to produce it in hardware form and then couple the interconnect circuit ICN to the source devices ESi, access ports PAj, and control module MCMi.

[0094] In step S22, a software application containing instructions for programming a table TBi of the control module MCMi is loaded into the source device ESp, which in the current case is a microprocessor.

[0095] Thus, when the software application is executed (step S23), the module MCMi (more particularly, the table TBi) is programmed (step S24).

Claims

1. A system on a chip, comprising: an interconnect circuit including an input interface and a plurality of output interfaces; a source device coupled to the input interface; a target device including a sectorized addressable memory space and a plurality of access ports, the plurality of access ports being respectively coupled to the plurality of output interfaces, the source device being configured to deliver a transaction containing an address word to the target device; and a programmable control module coupled to the source device, and the programmable control module includes: a table configured to indicate, once the programmable control module is programmed, one access port of the plurality of access ports for each sector of the sectorized addressable memory space; and control circuitry configured to, in the presence of the transaction from the source device, deliver a control word to the interconnect circuit, the control word specifying the selected access port indicated in the table based on the address word contained in the transaction, wherein the interconnect circuit is configured to route the transaction from the input interface to the corresponding output interface coupled to the selected access port, and to deliver the transaction to the selected access port; and wherein the content of the transaction delivered to the selected access port is the same as the content of the transaction delivered by the source device, regardless of the selected access port specified by the control word.

2. The system on a chip according to claim 1, wherein the programmable control module is programmable by the source device.

3. The system on a chip according to claim 1, further comprising a plurality of other source devices, the plurality of other source devices being respectively coupled to a plurality of corresponding other control modules, the interconnect circuit including a plurality of other input interfaces, the plurality of other input interfaces being respectively coupled to the plurality of other source devices, wherein each of the plurality of corresponding other control modules is programmable by one of the plurality of other source devices.

4. The system on a chip according to claim 3, wherein one of the plurality of other source devices includes a programmable core or a microprocessor.

5. The system on a chip according to claim 3, wherein one of the plurality of other source devices incorporates a software application, the software application containing instructions for programming each table included in each of the plurality of corresponding other control modules.

6. The system on a chip according to claim 1, wherein the target device includes a multi-port memory.

7. A system on a chip, comprising: an interconnect circuit including an input interface and a plurality of output interfaces; a source device coupled to the input interface; a target device including a sectorized addressable memory space and a plurality of access ports, the plurality of access ports being respectively coupled to the plurality of output interfaces, the source device being configured to deliver a transaction containing an address word to the target device; and a programmable control module coupled to the source device, and the programmable control module includes: A table, configured to indicate, once the programmable control module is programmed, one of the plurality of access ports for each sector of the sectorized addressable memory space; and A control circuit, configured to, in the presence of the transaction from the source device, deliver a control word to the interconnect circuit, the control word specifying the selected access port indicated in the table based on the address word included in the transaction, wherein the interconnect circuit is configured to route the transaction from the input interface to the corresponding output interface coupled to the selected access port, and to deliver the transaction to the selected access port; wherein the content of the transaction delivered to the selected access port is the same as the content of the transaction delivered by the source device, regardless of the selected access port specified by the control word; wherein the transaction is routed to the corresponding output interface together with the control word; and wherein the corresponding output interface is configured not to deliver the control word to the selected access port.

8. The system-on-chip according to claim 7, wherein the transaction is merged within a master word of n bits, and wherein the control word includes m additional bits, the value of m being at least equal to one and depending on the number of the plurality of access ports.

9. The system-on-chip according to claim 8, wherein the control circuit is configured to adjust the value of the m additional bits so as to specify the selected access port based on the address word included in the transaction and based on the table, wherein the input interface is configured to receive a total word of n + m bits including the master word and the control word, wherein the interconnect circuit is configured to route the total word to the corresponding output interface, and wherein the corresponding output interface is configured not to deliver the control word to the selected access port.

10. The system-on-chip according to claim 9, wherein the input interface is coupled to the source device via an input bus of n tracks, and the input interface is coupled to the programmable control module via a control bus of m tracks, wherein the total word of n + m bits is routed within the interconnect circuit on a network of an internal bus of n + m tracks, wherein the corresponding output interface is configured to receive the internal bus of n + m bits and is coupled to the selected access port via an output bus of n tracks, and wherein m tracks of the internal bus of n + m tracks leading to the corresponding output interface are not connected to the selected access port.

11. A method for managing the routing of transactions between a source device and a target device within a system-on-chip, the source device delivering the transactions, the target device including a sectorized addressable memory space and a plurality of access ports, each transaction including a corresponding address word, wherein the system-on-chip is equipped with an interconnect circuit, the interconnect circuit including an input interface and a plurality of output interfaces, and wherein the input interface is coupled to the source device, and the plurality of output interfaces are respectively coupled to the plurality of access ports, the method comprises: at the input interface, receiving a transaction from the source device and a control word of a programmable value associated with the transaction; routing the transaction and the control word to a corresponding one of the plurality of output interfaces according to the value of the control word; delivering the transaction to a selected access port coupled to the corresponding output interface such that the control word is not limited to the selected access port; for the source device, programming a table indicating corresponding access ports for each sector of the sectorized addressable memory space; and for the transaction, adjusting the value of the control word according to the address word included in the transaction and the content of the table.

12. The method according to claim 11, further comprises: loading a software application including instructions for programming the table into the source device; and programming the table by executing the software application.

13. The method according to claim 11, wherein the table is included in a programmable control module, the programmable control module being coupled to the source device and the input interface.

14. The method according to claim 11, further comprises: receiving a plurality of other transactions from a plurality of other source devices, the plurality of other source devices being respectively coupled to a plurality of corresponding other control modules, the interconnect circuit including a plurality of other input interfaces, the plurality of other input interfaces being respectively coupled to the plurality of other source devices, wherein each of the plurality of corresponding other control modules is programmable by one of the plurality of other source devices.

15. The method according to claim 14, wherein one of the plurality of other source devices includes a programmable core or a microcontroller.

16. The method according to claim 14, wherein the target device includes a multi-port memory.

17. The method according to claim 11, further comprises: routing the transaction together with the control word to the corresponding output interface, and wherein the corresponding output interface is configured not to deliver the control word to the selected access port.

18. The method according to claim 17, wherein the transaction is merged within a master word of n bits, and wherein the control word includes m additional bits, the value of m being at least equal to one and depending on the number of the plurality of access ports.

19. The method according to claim 18, further comprises: Adjust the values of the m additional bits so as to specify the selected access port based on the address word included in the transaction and based on the table; Receive at the input interface a total word of n + m bits including the main word and the control word; and Route the total word to the respective output interface without delivering the control word to the selected access port.

20. The method according to claim 19, wherein the input interface is coupled to the source device via an input bus of n tracks, and the input interface is coupled to a programmable control module via a control bus of m tracks, wherein the total word of n + m bits is routed within the interconnect circuit on a network of an internal bus of n + m tracks, wherein the respective output interface is configured to receive the internal bus of n + m bits and is coupled to the selected access port via an output bus of n tracks, wherein m tracks of the internal bus of n + m tracks leading to the respective output interface are not connected to the selected access port.

Images