Semiconductor device including a test structure

Abstract

A semiconductor device including a test structure includes a semiconductor substrate and a plurality of test structures on the semiconductor substrate. The test structure includes a corresponding lower active region and an upper active region, the corresponding lower active region extends from the semiconductor substrate in a vertical direction and has different widths, and the upper active region extends from the corresponding lower active region in a vertical direction. Each lower active region includes a first region and a second region. The first region overlaps with the upper active region and is between the second region, and the second region includes an outer region and an inner region between the outer regions. The outer regions located in the lower active regions with different widths have different widths.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2018-0045988 filed on April 20, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device including a test structure. Background Art

[0004] In order to manufacture semiconductor devices, integrated circuits may be formed on semiconductor wafers. In order to determine the failure or reliability of such integrated circuits, electrical characteristics of the integrated circuits may be measured. For example, a test element group (TEG) having the same structure as that of the integrated circuit may be formed in a scribe area of ​​a semiconductor wafer. Summary of the invention

[0005] An aspect of the inventive concept is to provide a semiconductor device including a test structure configured or used to provide or indicate an optimum or desired area of ​​an active area.

[0006] An aspect of the inventive concept is to provide a semiconductor device including a test structure configured to or used to detect whether a leakage current defect or a reliability defect exists between source / drain regions having different conductivity types.

[0007] According to one aspect of the present invention, a semiconductor device is provided. The semiconductor device includes: a semiconductor substrate; and a plurality of test structures formed on the semiconductor substrate. The test structure includes a lower active region and an upper active region, the lower active region protrudes from the semiconductor substrate in a vertical direction and has different widths, the upper active region protrudes from the corresponding lower active region in a vertical direction, the corresponding lower active region includes a first region and a second region, the first region overlaps with the upper active region and is arranged between the second region, the second region includes an outer region and an inner region between the outer regions, and the outer region located in the lower active region has different widths.

[0008] According to one aspect of the present invention, a semiconductor device is provided. The semiconductor device includes: a semiconductor substrate; and a plurality of test structures formed on the semiconductor substrate, the plurality of test structures including: a lower active region protruding from the semiconductor substrate in a vertical direction perpendicular to the semiconductor substrate and having different widths; an upper active region protruding from each lower active region in a vertical direction and extending in a first horizontal direction; and a gate structure extending in a second horizontal direction perpendicular to the first horizontal direction and having a portion overlapping the lower active region and the upper active region, each lower active region having different widths including a first region overlapping with the upper active region and a second region not overlapping with the upper active region, and the second region including an outer region and an inner region between the outer regions.

[0009] According to one aspect of the present invention, a semiconductor device is provided. The semiconductor device includes: a memory cell array region including a unit memory cell region; and a test region including a unit test region, the plane size of the unit test region being equal to the plane size of the unit memory cell region, the unit memory cell region including: a pair of first memory active lines adjacent to each other while intersecting the unit memory cell region; a pair of second memory active lines adjacent to each other while intersecting the unit memory cell region; a single third memory active line disposed between the pair of first memory active lines and the pair of second memory active lines; and a single fourth memory active line disposed between the pair of first memory active lines and the pair of second memory active lines. The unit test region includes: a pair of first test active lines adjacent to each other while intersecting the unit test region; a pair of second test active lines adjacent to each other while intersecting the unit test region; a single third test active line adjacent to the pair of first test active lines; and a single fourth test active line adjacent to the pair of second test active lines. Each of the third memory active line and the fourth memory active line has an end portion in the unit memory cell region. Each of the third test active line and the fourth test active line intersects the unit test region. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description given in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a plan view showing a semiconductor device according to some example embodiments;

[0012] Figure 2 yes Figure 1 a partial enlarged view of a portion of;

[0013] FIG. 3A to FIG. 3Cis a plan view illustrating an example of a test structure of a semiconductor device according to some example embodiments;

[0014] FIG. 4A to FIG. 5 is a cross-sectional view illustrating an example of a test structure of a semiconductor device according to some example embodiments;

[0015] Figure 6 is a plan view illustrating an example of a test structure of a semiconductor device according to some example embodiments;

[0016] Figure 7 is a plan view illustrating a modified example of a test structure of a semiconductor device according to some example embodiments;

[0017] Fig. 8A is a plan view illustrating a modified example of a test structure of a semiconductor device according to some example embodiments;

[0018] Figure 8B is a plan view illustrating a modified example of a test structure of a semiconductor device according to some example embodiments;

[0019] Fig. 9 is a cross-sectional view illustrating a semiconductor device according to some example embodiments;

[0020] Fig.10 is a process flow chart illustrating an example of a method of forming a semiconductor device according to some example embodiments;

[0021] Fig.11 is a schematic block diagram illustrating a modified example of a semiconductor device according to some example embodiments;

[0022] Fig.12 is a circuit diagram illustrating a portion of a semiconductor device according to some example embodiments;

[0023] Fig.13 is a plan view showing a portion of a semiconductor device according to some example embodiments;

[0024] Fig.14A and Fig. 14B is a cross-sectional view illustrating a portion of a semiconductor device according to some example embodiments;

[0025] Fig.15 is a plan view showing a portion of a semiconductor device according to some example embodiments;

[0026] Fig.16A and Fig. 16B is a cross-sectional view illustrating a portion of a semiconductor device according to some example embodiments;

[0027] Fig.17is a plan view illustrating a modified example of a portion of a semiconductor device according to some example embodiments;

[0028] Fig.18 is a plan view illustrating a modified example of a portion of a semiconductor device according to some example embodiments;

[0029] Fig.19 is a cross-sectional view illustrating a modified example of a portion of a semiconductor device according to some example embodiments;

[0030] Fig. 20 is a plan view illustrating a modified example of a portion of a semiconductor device according to some example embodiments;

[0031] Fig.21 is a plan view illustrating a modified example of a portion of a semiconductor device according to some example embodiments; and

[0032] Fig.22A and Fig. 22B is a cross-sectional view illustrating a portion of a semiconductor device according to some example embodiments. DETAILED DESCRIPTION

[0033] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0034] Figure 1 is a plan view showing a semiconductor device according to some example embodiments, and Figure 2 yes Figure 1 A partial enlarged view of part "A".

[0035] refer to Figure 1 and Figure 2 , the semiconductor device 1 according to some example embodiments may include a plurality of chip areas CA and scribe lane areas SL between the chip areas CA. In one example, each chip area CA may have a quadrilateral shape when viewed in a plan view.

[0036] The semiconductor device 1 according to some example embodiments may include a test area TA. In one example, the test area TA may include a first test area TA1 in the scribe area SL. In another example, the test area TA may include a second test area TA2 in the chip area CA. In another example, the test area TA may include a first test area TA1 in the scribe area SL and a second test area TA2 in the chip area CA. The terms first, second, third, etc., used herein are only to distinguish or differentiate one element (e.g., layer, transistor, etc.) from another element.

[0037] The test area TA may be an area in which a test structure for testing physical and / or electrical characteristics of various elements forming the semiconductor device 1 according to some example embodiments is to be formed. For example, the semiconductor device 1 according to some example embodiments may include elements such as an active region, a gate electrode, a source / drain region, and wirings, and the test area TA may be an area in which a test structure for testing one or more of the above elements is to be formed.

[0038] The semiconductor device 1 according to some example embodiments may be provided as a semi-finished product in a semiconductor wafer state. In addition, the semiconductor device 1 according to some example embodiments may be provided as a semiconductor package or a semiconductor chip, which is processed into a packaged form by performing a packaging process on a semi-finished product in a semiconductor wafer state.

[0039] Hereinafter, an example of a test structure to be formed in the above-mentioned test area TA will be described. A test structure according to the example described below may be formed in the first test area TA1, in the second test area TA2, or in both the first test area TA1 and the second test area TA2.

[0040] refer to Figures 3A to 5 , an example of a test structure of the semiconductor device 1 according to some example embodiments will be described. Figures 3A to 5 middle, Figure 3A is a plan view showing a test structure, Figure 3B It is shown Figure 3A A plan view of the lower active region 10, Figure 3C It is shown Figure 3A A plan view of the active area 20, Figure 4A is along Figure 3A A cross-sectional view of the area cut by line Ia-Ia′, Figure 4B is along Figure 3A A cross-sectional view of the area cut by line Ib-Ib′, Figure 4C is shown along Figure 3A A cross-sectional view of the area cut by line Ic-Ic′, Figure 4D is shown along Figure 3A A cross-sectional view of the area cut by line Id-Id′, Figure 4E is shown along Figure 3A A cross-sectional view of a region cut along line Ie-Ie′, and Figure 5 is shown along Figure 3A A cross-sectional view of the area cut off by line II-II′.

[0041] refer to Figures 3A to 5 ,and Figure 1 and Figure 2Together, the semiconductor device 1 according to some example embodiments may include a plurality of test structures TS. The test structure TS may be formed on the semiconductor substrate 5.

[0042] The test structure TS may include lower active regions 10 extending from the semiconductor substrate 5 in a vertical direction Z, and upper active regions 20 extending from each lower active region 10 in the vertical direction Z and in a first horizontal direction X perpendicular to the vertical direction Z. The vertical direction Z may be a direction perpendicular to the semiconductor substrate 5 .

[0043] In example embodiments, the “upper active region” may be referred to as an “upper active line” or an “upper active fin.” The lower active regions 10 may be different from each other, ie, each lower active region 10 may separately protrude from the substrate 5 .

[0044] Each test structure TS may include a single lower active region 10 formed on the semiconductor substrate 5 and extending from the semiconductor substrate 5 in the vertical direction Z, and a plurality of upper active regions 20 extending from the single lower active region 10 in the vertical direction Z. As shown, in some embodiments, each lower active region 10 may include the same number or quantity of upper active regions 20.

[0045] The test structure TS may include a lower active region 10 having different sizes (e.g., different widths), and each lower active region 10 having different widths may include a first region 11, and second regions 12 and 13. It should be understood that the different widths and / or other sizes described herein refer to measurable differences that exceed the production tolerance of the corresponding lower active region 10. Specifically, the variation of the different widths of the lower active region 10 of the test structure TS may be outside the acceptable variation range of the width between the lower active regions of the memory cell or other circuit structure as described herein. The first region 11 may overlap with the upper active region 20, and may be disposed between the second regions 12 and 13. The second regions 12 and 13 may include an outer region 13, and an inner region 12 between the outer regions 13. The outer regions 13 located in a single lower active region 10 may have the same width, while the outer regions 13 located in the lower active regions 10 having different sizes may have different widths. That is, the respective widths of the outer regions or edges 13 of each lower active region 10 may be measurably different from each other, and may contribute to the difference in the respective total widths of each lower active region 10.

[0046] In one example, the inner regions 12 located in the lower active regions 10 having different widths may have the same width.

[0047] In one example, the first regions 11 located in the lower active regions 10 having different sizes may have the same width.

[0048] Each of the lower active regions 10 may have first side surfaces ( Figure 3B 10s1) and the second side surface opposite to each other ( Figure 3B In addition, each of the active regions 20 may have first side surfaces ( Figure 3C 20s1) and the second side surface opposite to each other ( Figure 3C The second side surface 20s2 of the upper active region 20 may be aligned with the second side surface 10s2 of the lower active region 10 , and the first side surface 20s1 of the upper active region 20 may be located on the lower active region 10 .

[0049] In an example, the plurality of test structures TS may include a first test structure TSa, a second test structure TSb, a third test structure TSc, a fourth test structure TSd, and a fifth test structure TSe.

[0050] In this specification, for ease of explanation, as an example, a plurality of test structures TS are described as five test structures, such as first to fifth test structures TSa, TSb, TSc, TSd, and TSe. However, the inventive concept described herein is not limited thereto, and the plurality of test structures TS may also include more than five test structures. Therefore, in the following description, the first to fifth test structures TSa, TSb, TSc, TSd, and TSe will be described below, but the inventive concept described herein is not limited thereto.

[0051] The first test structure TSa may include a first lower active region 10a extending from the semiconductor substrate 5 in the vertical direction Z, and an upper active region 20 extending from the first lower active region 10a in the vertical direction Z. The second test structure TSb may include a second lower active region 10b extending from the semiconductor substrate 5 in the vertical direction Z, and an upper active region 20 extending from the second lower active region 10b in the vertical direction Z. The third test structure TSc may include a third lower active region 10c extending from the semiconductor substrate 5 in the vertical direction Z, and an upper active region 20 extending from the third lower active region 10c in the vertical direction Z. The fourth test structure TSd may include a fourth lower active region 10d extending from the semiconductor substrate 5 in the vertical direction Z, and an upper active region 20 extending from the fourth lower active region 10d in the vertical direction Z. The fifth test structure TSe may include a fifth lower active region 10 e extending in the vertical direction Z from the semiconductor substrate 5 , and an upper active region 20 extending in the vertical direction Z from the fifth lower active region 10 e .

[0052] The first to fifth test structures TSa, TSb, TSc, TSd, and TSe having different widths may include first to fifth lower active regions 10a, 10b, 10c, 10d, and 10e having different widths. As described above, each of the first to fifth lower active regions 10a, 10b, 10c, 10d, and 10e may include a first region 11, and second regions 12 and 13.

[0053] In example embodiments, the “first region 11” may be referred to as an “overlapping region 11”, and the “second regions 12 and 13” may be referred to as “non-overlapping regions 12 and 13”. Therefore, the first region 11 of the first to fifth lower active regions 10a, 10b, 10c, 10d, and 10e may be referred to as an overlapping region overlapping with the upper active region 20 (e.g., in a plan view), and the second regions 12 and 13 of the first to fifth lower active regions 10a, 10b, 10c, 10d, and 10e may be referred to as non-overlapping regions that do not overlap with the upper active region 20 (e.g., in a plan view).

[0054] Among the second regions 12 and 13 of the lower active region 10, the upper surface 12S of the inner region 12 may have a curvature in a downward direction. In other words, the upper surface 12S of the inner region 12 may be rounded in a concave form.

[0055] The inner regions 12 of the second regions 12 and 13 located in the lower active region 10 having different widths have the same first width, while the outer regions 13 of the second regions 12 and 13 located in the lower active region 10 having different widths may have different widths within a range greater than 0 and less than the first width.

[0056] One of the lower active regions 10 may have an upper surface of the outer region that forms a first angle with the side surface, and another of the lower active regions 10 may have an upper surface of the outer region that forms a second angle with the side surface, and the first angle may be different from the second angle.

[0057] An upper surface 13s1 of a first outer region 13a of or among the second regions 12 and 13 of the first lower active region 10a may form a first angle θa with a side surface of the first lower active region 10a. An upper surface 13s2 of a second outer region 13b of or among the second regions 12 and 13 of the second lower active region 10b may form a second angle θb with a side surface of the second lower active region 10b. An upper surface 13s3 of a third outer region 13c of or among the second regions 12 and 13 of the third lower active region 10c may form a third angle θc with a side surface of the third lower active region 10c. An upper surface 13s4 of a fourth outer region 13d of or among the second regions 12 and 13 of the fourth lower active region 10d may form a fourth angle θd with a side surface of the fourth lower active region 10d. An upper surface 13s5 of the fifth outer region 13e of or among the second regions 12 and 13 of the fifth lower active region 10e may form a fifth angle θe with a side surface of the fifth lower active region 10e.

[0058] The first to fifth outer regions 13a, 13b, 13c, 13d, and 13e as described above may have different widths. For example, the widths may increase in sequence from the first outer region 13a to the second to fifth outer regions 13b, 13c, 13d, and 13e. In other words, the width of the fifth outer region 13e may be greater than the width of the first outer region 13a.

[0059] The first to fifth angles θa, θb, θc, θd, and θe may be different angles. For example, the angles may decrease in sequence from the first angle θa to the second angle θb, the third angle θc, the fourth angle θd, and the fifth angle θe. For example, the first angle θa and the second angle θb may be obtuse angles, the third angle θc may be close to a right angle, and the fourth angle θd and the fifth angle θe may be acute angles.

[0060] The outer regions 13d and 13e of at least one of the second regions 12 and 13 located in the lower active region 10 having different widths may have ends with different heights. Figure 4D 13d) level at the fourth outer area ( Figure 4D The low area of ​​the upper surface 13s4 of the fifth outer region (13d) gradually increases in the direction toward the second isolation region 37 and increases to the first height H1, while the fifth outer region ( Figure 4E 13e) level at the fifth outer area ( Figure 4E The low area of ​​the upper surface 13s5 of the structure 13e) gradually increases in the direction toward the second isolation region 37 and increases to a second height H2 that is greater than the first height H1.

[0061] The test structure TS may include a gate structure 60, wherein a plurality of gate structures may overlap each lower active region 10, and a source / drain region 40 is formed in an upper active region 20 located adjacent to the gate structure 60. Each gate structure 60 may include a gate electrode 70, and a gate dielectric 65 extending on or covering a lower surface and a side surface of the gate electrode 70.

[0062] The gate structure 60 may include an active gate structure 60a intersecting the upper active region 20 while overlapping the lower active region 10, and a dummy gate structure 60d disposed on both sides of the active gate structure 60a while extending on or covering an end of the upper active region 20. The upper active region 20 may protrude from an upper portion of the first isolation region 35 while passing through the first isolation region 35, and the gate structure 60 may extend on or cover an upper surface and a side surface of the upper active region 20 protruding from an upper portion of the first isolation region 35.

[0063] The gate structure 60 may extend in the second horizontal direction Y in a portion overlapping or adjacent to the lower active region 10, the second horizontal direction Y being perpendicular to the vertical direction Z and perpendicular to the first horizontal direction X. Therefore, the gate structure 60 may extend in a direction intersecting the upper active region 20 (i.e., the second horizontal direction Y) while overlapping the upper active region 20. When an element or layer is referred to herein as being "on" or "adjacent" or "coupled" or "in contact with" another element or layer, there may be an intermediate element or layer. In contrast, the term "directly on" or "directly adjacent" or "directly coupled" or "in direct contact with..." may mean that there are no intermediate elements or layers.

[0064] In example embodiments, the first horizontal direction X may be understood as a longitudinal direction of the upper active region 20 , and the second horizontal direction Y may be understood as a longitudinal direction of the gate structure 60 on the lower active region 10 .

[0065] The source / drain region 40 may be disposed on the upper active region 20 and may be disposed between the gate structures 60 when viewed in a plan view. The source / drain region 40 may be provided as an epitaxial semiconductor layer grown from the recessed region 20r of the upper active region 20.

[0066] Insulating partition walls 75 may be formed on side surfaces of the gate structures 60. Conductive contact plugs 80 electrically connected to the source / drain regions 40 may be formed between the gate structures 60. An interlayer insulating layer 45 may be formed on the second isolation region 37.

[0067] As described above, first to fifth test structures TSa, TSb, TSc, TSd, and TSe may be provided, respectively, but the inventive concepts described herein are not limited thereto. Figure 6 and Figure 7 Each of describes an example of an array or arrangement of first to fifth test structures TSa, TSb, TSc, TSd, and TSe. Figure 6 is a plan view illustrating an example of a test structure of a semiconductor device according to some example embodiments, and Figure 7 is a plan view illustrating a modified example of a test structure of a semiconductor device according to some example embodiments.

[0068] In one example, reference Figure 6 , each of the first to fifth test structures TSa, TSb, TSc, TSd, and TSe may be provided as a plurality of test structures arranged adjacent to each other in the second horizontal direction Y (i.e., the width direction of the active region 20 or the longitudinal direction of the gate structure 60). Therefore, the test structure TS may include a first test structure TSa provided as a plurality of first test structures arranged in the second horizontal direction Y, a second test structure TSb provided as a plurality of second test structures arranged in the second horizontal direction Y, a third test structure TSc provided as a plurality of third test structures arranged in the second horizontal direction Y, a fourth test structure TSd provided as a plurality of fourth test structures arranged in the second horizontal direction Y, and a fifth test structure TSe provided as a plurality of fifth test structures arranged in the second horizontal direction Y.

[0069] In the modified example, refer to Figure 7 , each of the first to fifth test structures TSa, TSb, TSc, TSd, and TSe may be provided as a plurality of test structures arranged adjacent to each other in the first horizontal direction X (i.e., the longitudinal direction of the active region 20). Therefore, the test structure TS may include a first test structure TSa provided as a plurality of first test structures arranged in the first horizontal direction X, a second test structure TSb provided as a plurality of second test structures arranged in the first horizontal direction X, a third test structure TSc provided as a plurality of third test structures arranged in the first horizontal direction X, a fourth test structure TSd provided as a plurality of fourth test structures arranged in the first horizontal direction X, and a fifth test structure TSe provided as a plurality of fifth test structures arranged in the first horizontal direction X.

[0070] exist Figures 3A to 5 , Figure 6 and Figure 7In the illustrated gate structure 60, a single active gate structure 60a is shown between a pair of dummy gate structures 60d extending on or covering the ends of the upper active region 20, but the inventive concepts described herein are not limited thereto. Fig. 8A A modified example of the above-described gate structure 60 is described. Fig. 8A is a plan view illustrating a modified example of a test structure of a semiconductor device according to some example embodiments.

[0071] In the modified example, refer to Fig. 8A , each of the test structures TS according to some example embodiments may include a plurality of active gate structures 60 a disposed between the pair of dummy gate structures 60 d .

[0072] Figures 3A to 5 , Figure 6 and Figure 7 The gate structures 60 shown in FIG. 1 are shown to be spaced apart from each other, but the inventive concepts described herein are not limited thereto. Figure 8B , a modified example of the gate structure 60 will be described. Figure 8B is a plan view illustrating a modified example of a gate structure of a test structure of a semiconductor device according to some example embodiments.

[0073] In the modified example, refer to Figure 8B , a single test structure TS of a semiconductor device according to some example embodiments may include a plurality of gate structures 60 disposed on a single lower active region 10, and a gate connection portion 60i electrically connecting the plurality of gate structures 60 to each other. Therefore, the gate structures 60 overlapping the single lower active region 10 may be connected to each other through the gate connection portion 60i, and thus may operate as a single gate. Figure 3A The gate structures 60 overlapping the single active region 10 shown in FIG. 8 may be electrically connected to each other through the gate connection portion 60i, such as Figure 8B The gate connection portion 60i can increase the detectability of the electrical characteristics of the test structure TS.

[0074] Previous references FIG. 3A to FIG. 8B The test structure TS described in reference can be formed Figure 1 and Figure 2 Test area described ( Figure 2 One or more of the above test structures TS may be formed into the same structure as the circuit structure in the chip area CA. Fig. 9 , will describe the previous reference FIG. 3A to FIG. 8B One of the test structures TS described, and can be formed in reference Figure 1 and Figure 2 The circuit structure in the chip area CA is described. Fig. 9 is a cross-sectional view showing the circuit structure CS in the chip area CA and the previously described test structure TS.

[0075] refer to Fig. 9 , previously referenced FIG. 3A to FIG. 8B The test structure TS described in reference can be formed Figure 1 and Figure 2 Test area described ( Figure 2 The circuit structure CS may include a circuit lower active region 10x, a circuit upper active region 20x disposed on the circuit lower active region 10x, and a gate structure 60x intersecting the circuit upper active region 20x. The gate structure 60x may include a circuit gate electrode 70x, and a circuit gate dielectric 65x extending on or covering the lower portion of the circuit gate electrode 70x.

[0076] The width of the on-circuit active region 20x may be equal to the width of the upper active region 20 of the test structure TS described previously. The separation distance between the on-circuit active regions 20x may be equal to the separation distance between the upper active regions 20 of the test structure TS described previously.

[0077] The structure of the circuit lower active region 10x may be similar to the structure of one of the lower active regions 10 of the test structure TS described previously. For example, the circuit lower active region 10x may have an outer region 13x having a width equal to the width of a single outer region 13 in the lower active region 10. That is, the width of the outer region 13x of the circuit lower active region 10x may be equal to the width of one of the outer regions 13 of different widths in the lower active region 10.

[0078] The lower active regions 10 with various widths of the previously described test structure TS can be used to improve or optimize the planar area of ​​the circuit lower active region 10x. For example, in a product, one of the lower active regions 10 of the previously described test structure TS (e.g., the third lower active region 10c) can be used to form the circuit lower active region 10x, and during or after the production of multiple semiconductor wafers, by testing the electrical characteristics or reliability of the previously described test structure TS, an appropriate one of the lower active regions 10 (e.g., the fourth lower active region 10d) is selected, so that the appropriate one lower active region can be applied to the circuit active region of the next product. Therefore, the test structure TS of the semiconductor device 1 according to the embodiment of the present invention can provide guidance for the optimal width or improved or optimal planar area of ​​the circuit lower active region.

[0079] Next, we will refer to Fig.10 An example of a method for forming the above-mentioned test structure TS is described. Fig.10is a process flow chart describing an example of a method for forming the above-described test structure TS.

[0080] refer to Fig.10 , an upper active line may be formed on a semiconductor substrate (S10). The semiconductor substrate may be a semiconductor wafer. Then, a first isolation region may be provided (S20). The first isolation region may define an upper active line.

[0081] The upper active line and the semiconductor substrate are patterned, thereby providing a plurality of lower active regions. In addition, the upper active line may remain as a plurality of upper active regions on each lower active region, and the lower active region may be provided as a plurality of lower active regions having different widths (S30). Here, the plurality of lower active regions having different widths may be the previously described Figures 3A to 9 The lower active region 10 of the test structure TS described above, and the upper active lines remaining on each lower active region as a plurality of upper active regions may be previously referred to as Figures 3A to 9 An active region 20 is depicted on the test structure TS.

[0082] While the upper active lines and the semiconductor substrate are patterned, the first isolation region is also patterned and thus may remain on each lower active region. Here, the first isolation region remaining on each lower active region may be the first isolation region 35 described previously.

[0083] A second isolation region may be provided (S40). Here, the second isolation region may be the second isolation region 37 described previously. Forming the second isolation region may include: forming an insulating material layer on the result product obtained by patterning the upper active line and the semiconductor substrate; and etching the insulating material layer and the first isolation region until the upper region of the upper active line is exposed. Thus, an isolation region 30 including the first isolation region 35 and the second isolation region 37 described previously may be provided.

[0084] Then, source / drain regions and a gate structure may be provided ( S50 ).

[0085] Next, we will refer to Figures 11 to 22B A semiconductor device according to another example embodiment is described.

[0086] First, refer to Fig.11 and Fig.12 , modified examples of the semiconductor device 1 according to some example embodiments will be described. Fig.11 is a block diagram conceptually illustrating a modified example of a semiconductor device according to some example embodiments, and Fig.12 is a circuit diagram illustrating a portion of a semiconductor device according to some example embodiments.

[0087] and Figure 1 and Figure 2 Reference together Fig.11 and Fig.12 , a semiconductor device according to some example embodiments may include a memory cell array area MCA formed by arranging a unit memory cell area UMC provided as a plurality of unit memory cell areas in a chip area CA, and a test area TSA formed by arranging a unit test area UTC provided as a plurality of unit test areas in a test area TA. The test area TSA may be a reference area. Figure 1 and Figure 2 Describe the test area TA.

[0088] The memory cell array area MCA may be an area in which a memory cell array of a static random access memory (SRAM) is provided, and the unit memory cell area UMC may be an area in which a unit memory cell of the SRAM is provided.

[0089] The SRAM unit memory cell of the unit memory cell region UMC may include a pair of first pull-up transistors TU1 and second pull-up transistors TU2, a pair of first pull-down transistors TD1 and second pull-down transistors TD2, and a pair of first access transistors TA1 and second access transistors TA2. The pair of first pull-down transistors TD1 and second pull-down transistors TD2 and the pair of first access transistors TA1 and second access transistors TA2 may be n-type metal oxide semiconductor (NMOS) transistors, and the pair of first pull-up transistors TU1 and second pull-up transistors TU2 may be p-type metal oxide semiconductor (PMOS) transistors.

[0090] The first pull-down transistor TD1 and the first access transistor TA1 may be connected in series. The source of the first pull-down transistor TD1 may be electrically connected to the ground voltage line VSS, and the drain of the first access transistor TA1 may be electrically connected to the first bit line BL1. In a similar manner thereto, the second pull-down transistor TD2 and the second access transistor TA2 may be connected in series. The source of the second pull-down transistor TD2 may be electrically connected to the ground voltage line VSS, and the drain of the second access transistor TA2 may be electrically connected to the second bit line BL2.

[0091] The source and drain of the first pull-up transistor TU1 may be electrically connected to the power supply voltage line VDD and the drain of the first pull-down transistor TD1, respectively. Similarly, the source and drain of the second pull-up transistor TU2 may be electrically connected to the power supply voltage line VDD and the drain of the second pull-down transistor TD2, respectively.

[0092] A drain of the first pull-up transistor TU1 , a drain of the first pull-down transistor TD1 , and a source of the first access transistor TA1 may correspond to a first node N1 .

[0093] In addition, a drain of the second pull-up transistor TU2 , a drain of the second pull-down transistor TD2 , and a source of the second access transistor TA2 may correspond to the second node N2 .

[0094] The gate electrodes of the first pull-down transistor TD1 and the first pull-up transistor TU1 may be electrically connected to the second node N2, and the gate electrodes of the second pull-down transistor TD2 and the second pull-up transistor TU2 may be electrically connected to the first node N1. In addition, the gate electrodes of the first access transistor TA1 and the second access transistor TA2 may be electrically connected to the word line WL.

[0095] Next, refer to Figures 13 to 14B , the above-mentioned unit memory cell area UMC will be described. Fig.13 , Fig.14A and Fig. 14B is shown formed as reference Fig.12 A diagram of the gates and sources / drains of the six transistors (eg, the first and second pull-up transistors TU1 and TU2, the first and second pull-down transistors TD1 and TD2, and the first and second access transistors TA1 and TA2). Figures 13 to 14B middle, Fig.13 is a plan view showing the previously described unit memory cell region UMC, Fig.14A is shown along Fig.13 A cross-sectional view of a region taken along line IIIa-IIIa′ of Fig. 14B is shown along Fig.13 A cross-sectional view of an area taken along line IVa-IVa′ and line Va-Va′.

[0096] refer to Figures 11 to 14B A pair of first memory active lines 120a adjacent to each other and a pair of second memory active lines 120b adjacent to each other may be provided on the semiconductor substrate 105. Between the pair of first memory active lines 120a and the pair of second memory active lines 120b, a single third memory active line 120c and a single fourth memory active line 120d may be provided.

[0097] When viewed in cross section, the memory active lines 120a to 120d may extend from the semiconductor substrate 105 in a vertical direction Z perpendicular to the semiconductor substrate 105. The memory active lines 120a to 120d may pass through an isolation region 130 on the semiconductor substrate 105. The isolation region 130 may be formed of silicon oxide. The isolation region 130 may be a shallow trench isolation.

[0098] The third memory active line 120c may be closer to the pair of first memory active lines 120a than the pair of second memory active lines 120b. The fourth memory active line 120d may be closer to the pair of second memory active lines 120b than the pair of first memory active lines 120a.

[0099] The pair of first memory active lines 120 a , the pair of second memory active lines 120 b , the third memory active line 120 c , and the fourth memory active line 120 d may have a linear or line shape extending in the first horizontal direction X when viewed in a plan view.

[0100] When viewed in a plan view, the pair of first memory active lines 120 a and the pair of second memory active lines 120 b may intersect the unit memory cell region UMC.

[0101] When viewed in a plan view, the third memory active line 120c and the fourth memory active line 120d may have portions extending from the side of the unit memory cell region UMC, opposite to each other, and overlapping in the second horizontal direction Y perpendicular to the first horizontal direction X, and ends of the portions may be located in the unit memory cell region UMC. Therefore, an end portion of the third memory active line 120c may be located between the fourth memory active line 120d and the pair of first memory active lines 120a, and an end portion of the fourth memory active line 120d may be located between the third memory active line 120c and the pair of second memory active lines 120b.

[0102] A separation distance L1 between the pair of first memory active lines 120 a and a separation distance L1 between the pair of second memory active lines 120 b may be equal to each other.

[0103] The separation distance L2 between the third memory active line 120c and the fourth memory active line 120d, the separation distance L2 between the pair of first memory active lines 120a and the third memory active line 120c, and the separation distance L2 between the pair of second memory active lines 120b and the fourth memory active line 120d may be equal to each other and may be greater than the separation distance L1 between the pair of first memory active lines 120a. For example, the separation distance L2 between the third memory active line 120c and the fourth memory active line 120d may be about twice the separation distance L1 between the pair of first memory active lines 120a.

[0104] When viewed in a plan view, first to fourth memory gate structures MG1, MG2, MG3, and MG4 may be provided, and the first to fourth memory gate structures MG1, MG2, MG3, and MG4 may have a linear or line shape extending in a second horizontal direction Y perpendicular to the first horizontal direction X, or a strip shape elongated in the second horizontal direction X. The first to fourth memory gate structures MG1, MG2, MG3, and MG4 may be spaced apart from each other. Each of the first to fourth memory gate structures MG1, MG2, MG3, and MG4 may include a gate electrode 170, and a gate dielectric 165 extending on or covering the lower surface and side surface of the gate electrode 170. An insulating partition wall 175 may be formed on the side surface of the first to fourth memory gate structures MG1, MG2, MG3, and MG4.

[0105] The first memory gate structure MG1 may intersect the pair of first memory active lines 120a and the third memory active line 120c at the same time. In one example, the first memory gate structure MG1 may extend over or cover the end portion of the fourth memory active line 120d while intersecting the pair of first memory active lines 120a and the third memory active line 120c at the same time.

[0106] The second memory gate structure MG2 may intersect the pair of second memory active lines 120b and the fourth memory active line 120d at the same time. In one example, the second memory gate structure MG2 may extend over or cover the end portion of the third memory active line 120c while intersecting the pair of second memory active lines 120b and the fourth memory active line 120d at the same time.

[0107] An end portion of the third memory gate structure MG3 may be opposite to an end portion of the second memory gate structure MG2 while intersecting the pair of first memory active lines 120 a .

[0108] An end portion of the fourth memory gate structure MG4 may be opposite to an end portion of the first memory gate structure MG1 while intersecting the pair of second memory active lines 120 b .

[0109] In the unit memory cell region UMC, first to tenth memory source / drain regions MSD1, MSD2, MSD3, MSD4, MSD5, MSD6, MSD7, MSD8, MSD9, and MSD10, which are spaced apart from each other, may be disposed therein.

[0110] The first to third memory source / drain regions MSD1, MSD2, and MSD3 may be disposed on a pair of first memory active lines 120a, and may be sequentially arranged in the first horizontal direction X. The second memory source / drain region MSD2 may be disposed between the first memory source / drain region MSD1 and the third memory source / drain region MSD3.

[0111] Each of the first to third memory source / drain regions MSD1 , MSD2 , and MSD3 may be provided as an epitaxial layer grown from each of a pair of first memory active lines 120 a to be connected and merged.

[0112] The first memory source / drain region MSD1 and the second memory source / drain region MSD2 may be formed on both sides of the first memory gate structure MG1, and the second memory source / drain region MSD2 and the third memory source / drain region MSD3 may be formed on both sides of the third memory gate structure MG3. Here, the second memory source / drain region MSD2 may be formed between the first memory gate structure MG1 and the third memory gate structure MG3.

[0113] The fourth to sixth memory source / drain regions MSD4, MSD5, and MSD6 may be disposed on a pair of second memory active lines 120b, and may be sequentially arranged in the first horizontal direction X. The fifth memory source / drain region MSD5 may be disposed between the fourth memory source / drain region MSD4 and the sixth memory source / drain region MSD6.

[0114] Each of the fourth to sixth memory source / drain regions MSD4, MSD5, and MSD6 may be provided as an epitaxial layer grown from each of a pair of second memory active lines 120b to be connected and merged. Thus, each of the first, second, and third memory source / drain regions MSD1, MSD2, and MSD3, as well as the fourth, fifth, and sixth memory source / drain regions MSD4, MSD5, and MSD6 may be provided as a merged epitaxial layer.

[0115] The fourth memory source / drain region MSD4 and the fifth memory source / drain region MSD5 may be formed on both sides of the fourth memory gate structure MG4, and the fifth memory source / drain region MSD5 and the sixth memory source / drain region MSD6 may be formed on both sides of the second memory gate structure MG2. Here, the fifth memory source / drain region MSD5 may be formed between the fourth memory gate structure MG4 and the second memory gate structure MG2.

[0116] The seventh memory source / drain region MSD7 and the eighth memory source / drain region MSD8 may be formed on the third memory active line 120c and may be formed on both sides of the first memory gate structure MG1. The ninth memory source / drain region MSD9 and the tenth memory source / drain region MSD10 may be formed on the fourth memory active line 120d and may be formed on both sides of the second memory gate structure MG2.

[0117] Each of the seventh to tenth memory source / drain regions MSD7 , MSD8 , MSD9 , and MSD10 may be provided as an epitaxial layer grown from a single active line.

[0118] When viewed in a cross section cutting the active lines along the first horizontal direction X, the first to tenth memory source / drain regions MSD1, MSD2, MSD3, MSD4, MSD5, MSD6, MSD7, MSD8, MSD9, and MSD10 may be provided as epitaxial layers filling the recessed regions 120r of the memory active lines 120a to 120d.

[0119] On a pair of first memory active lines 120a, the first memory gate structure MG1, the first memory source / drain region MSD1, and the second memory source / drain region MSD2 may form a reference Fig.12 The first pull-down transistor TD1 described above, while the third memory gate structure MG3, the second memory source / drain region MSD2 and the third memory source / drain region MSD3 may form a reference Fig.12 A first access transistor TA1 is described.

[0120] On a pair of second memory active lines 120b, the second memory gate structure MG2, the fifth memory source / drain region MSD5, and the sixth memory source / drain region MSD6 may form a reference Fig.12 The second pull-down transistor TD2 described above, while the fourth memory gate structure MG4, the fourth memory source / drain region MSD4 and the fifth memory source / drain region MSD5 may form a reference Fig.12A second access transistor TA2 is described.

[0121] On the third memory active line 120c, the first memory gate structure MG1, the seventh memory source / drain region MSD7, and the eighth memory source / drain region MSD8 may form a reference Fig.12 A first pull-up transistor TU1 is described.

[0122] On the fourth memory active line 120d, the second memory gate structure MG2, the ninth memory source / drain region MSD9, and the tenth memory source / drain region MSD10 may form a reference Fig.12 The second pull-up transistor TU2 is described.

[0123] Therefore, in the unit memory cell region UMC, it is possible to set therein the reference Fig.12 The six transistors TD1, TD2, TU1, TU2, TA1 and TA2.

[0124] In the unit memory cell region UMC, the first memory source / drain region MSD1 and the seventh memory source / drain region MSD7 opposite to each other, and the sixth memory source / drain region MSD6 and the tenth memory source / drain region MSD10 opposite to each other should be reliably electrically isolated from each other in a semiconductor device including an SRAM.

[0125] Hereinafter, a test structure for evaluating leakage current characteristics or reliability between the first memory source / drain region MSD1 and the seventh memory source / drain region MSD7 opposite to each other and between the sixth memory source / drain region MS6 and the tenth memory source / drain region MSD10 opposite to each other will be described. The above test structure may be included in the unit test region UTC. Figures 11 to 14B The unit memory cell region UMC will be described together with the reference Figures 15 to 16B describe Fig.11 The unit test zone is UTC. Fig.15 is a plan view showing the unit test area UTC described previously, Fig.16A is shown along Fig.15 A cross-sectional view of a region taken along line IIIb-IIIb′ of Fig. 16B is shown along Fig.13 A cross-sectional view of an area taken along line IVa-IVa′ and line Va-Va′.

[0126] and Figures 11 to 14B Reference together Figures 15 to 16B, a unit test area UTC can be provided having a planar size or a planar view area or an occupied area equal to the planar size or a planar view area or an occupied area of ​​the unit memory cell area UMC (for example, having the same planar area and horizontal (for example, along the Y direction) and vertical (for example, along the X direction) ratios).

[0127] In the unit test region UTC, a pair of first test active lines 220a and a pair of second test active lines 220b may be arranged therein, and the pair of first test active lines 220a and the pair of second test active lines 220b correspond to the pair of first memory active lines 120a and the pair of second memory active lines 120b in the unit memory cell region UMC, respectively. Therefore, the size of the pair of first test active lines 220a may be equal to the size of the pair of first memory active lines 120a, and the size of the pair of second test active lines 220b may be equal to the size of the pair of second memory active lines 120b.

[0128] In the unit test region UTC, between the pair of first test active lines 220 a and the pair of second test active lines 220 b , a single third test active line 220 c and a single fourth test active line 220 d may be disposed.

[0129] Compared with the pair of second test active lines 220b, the third test active line 220c can be closer to the pair of first test active lines 220a, and compared with the pair of first test active lines 220a, the fourth test active line 220d can be closer to the pair of second test active lines 220b. Therefore, the third test active line 220c can be arranged between the pair of first test active lines 220a and the fourth test active line 220d, and the fourth test active line 220d can be arranged between the third test active line 220c and the pair of second test active lines 220d.

[0130] In the unit test region UTC, the shape of the third test active line 220c may be the same as the shape in which the third memory active line 120c in the unit memory cell region UMC is extended to intersect with the unit memory cell region UMC, and the shape of the fourth test active line 220d may be the same as the shape in which the fourth memory active line 120d in the unit memory cell region UMC is extended to intersect with the unit memory cell region UMC. Therefore, when viewed in the second horizontal direction Y, the separation distances L1 and L2 between the test active lines 220a, 220b, 220c, and 220d adjacent to each other in the unit test region UTC may be equal to the separation distances L1 and L2 between the memory active lines 120a, 120b, 120c, and 120d in the unit memory cell region UMC. In this way, further detailed description of the separation distances L1 and L2 will be omitted.

[0131] Furthermore, the test active lines 220a, 220b, 220c, and 220d in the unit test region UTC may pass through the isolation region 130 formed on the semiconductor substrate 105 in a similar manner to the memory active lines 120a, 120b, 120c, and 120d in the unit memory cell region UMC.

[0132] In the unit test region UTC, a first test gate structure TG1 and a second test gate structure TG2 extending in the second horizontal direction Y may be disposed therein.

[0133] In the unit test region UTC, the first test gate structure TG1 may have a shape in which the first memory gate structure MG1 and the fourth memory gate structure MG4 in the unit memory cell region UMC extend in the second horizontal direction Y to be connected to each other, and the second test gate structure TG2 may have a shape in which the second memory gate structure MG2 and the third memory gate structure MG3 in the unit memory cell region UMC extend in the second horizontal direction Y to be connected to each other.

[0134] The structure of each of the first test gate structure TG1 and the second test gate structure TG2 may be the same or similar to the structure of each of the first memory gate structure MG1 and the fourth memory gate structure MG4. For example, each of the first test gate structure TG1 and the second test gate structure TG2 may be provided as a gate dielectric 165 and a gate electrode 170 or defined in other ways by the gate dielectric 165 and the gate electrode 170, thereby forming each of the first memory gate structure MG1 to the fourth memory gate structure MG4. The insulating partition wall 175 may be formed on the side surfaces of the first test gate structure TG1 and the second test gate structure TG2.

[0135] In the unit test area UTC, first to tenth test source / drain regions TSD1, TSD2, TSD3, TSD4, TSD5, TSD6, TSD7, TSD8, TSD9 and TSD10 corresponding to the first to tenth memory source / drain regions MSD1, MSD2, MSD3, MSD4, MSD5, MSD6, MSD7, MSD8, MSD9 and MSD10 in the unit memory cell area UMC, respectively, may be set therein. Since the first to tenth test source / drain regions TSD1, TSD2, TSD3, TSD4, TSD5, TSD6, TSD7, TSD8, TSD9, and TSD10 in the unit test region UTC can be set by position and can be arranged by size, this is different from the first to tenth memory source / drain regions MSD1, MSD2, MSD3, MSD4, MSD5, MSD6, MSD7, MSD8, MSD9, and TSD10 in the unit memory cell region UMC. 9 and MSD10 are the same, so the layout positions and sizes of the first test source / drain region to the tenth test source / drain region TSD1, TSD2, TSD3, TSD4, TSD5, TSD6, TSD7, TSD8, TSD9 and TSD10 can be understood based on the layout positions and sizes of the first memory source / drain region to the tenth memory source / drain region MSD1, MSD2, MSD3, MSD4, MSD5, MSD6, MSD7, MSD8, MSD9 and MSD10. For example, each of the first test source / drain region to the third test source / drain region TSD1, TSD2 and TSD3, the fourth test source / drain region to the sixth test source / drain region TSD4, TSD5 and TSD6, the first memory source / drain region to the third memory source / drain region MSD1, MSD2 and MSD3, and the fourth memory source / drain region to the sixth memory source / drain region MSD4, MSD5 and MSD6 can be provided as an epitaxial layer to be connected and merged grown from a pair of active lines adjacent to each other.

[0136] Compared with the unit memory cell region UMC, the unit test region UTC may further include an eleventh test source / drain region TSD11 and a twelfth test source / drain region TSD12 .

[0137] The eleventh test source / drain region TSD11 may be disposed on the fourth test active line 220d and may be disposed between the seventh test source / drain region TSD7 and the fourth test source / drain region TSD4. The twelfth test source / drain region TSD12 may be disposed on the third test active line 220c and may be disposed between the third test source / drain region TSD3 and the tenth test source / drain region TSD10.

[0138] Each of the seventh to twelfth test source / drain regions TSD7, TSD8, TSD9, TSD10, TSD11 and TSD12 and the seventh to tenth memory source / drain regions MSD7, MSD8, MSD9 and MSD10 may be provided as an epitaxial layer grown from a single active line.

[0139] When viewed in a cross section cutting the test active line along the first horizontal direction X, each of the first to twelfth test source / drain regions TSD1 to TSD12 may be provided as an epitaxial layer filling a recess region 220 r of the test active line.

[0140] In some example embodiments, a pair of first memory active lines 120a, a pair of second memory active lines 120b, a pair of first test active lines 220a, and a pair of second test active lines 220c may have P-type conductivity, and a third memory active line 120c and a fourth memory active line 120d, and a third test active line 220c and a fourth test active line 220d may have N-type conductivity.

[0141] In some example embodiments, the first to sixth memory source / drain regions MSD1, MSD2, MSD3, MSD4, MSD5, and MSD6 and the first to sixth test source / drain regions TSD1, TSD2, TSD3, TSD4, TSD5, and TSD6 may be source / drain regions having N-type conductivity, and the seventh to tenth memory source / drain regions MSD7, MSD8, MSD9, and MSD10 and the seventh to twelfth test source / drain regions TSD7, TSD8, TSD9, TSD10, TSD11, and TSD12 may be source / drain regions having P-type conductivity.

[0142] In some example embodiments, Fig.13As shown, in the unit memory cell area UMC, portions in which source / drain regions having different conductivity types are opposite to each other are provided as a total of four portions, for example, a first memory source / drain region MSD1 and a seventh memory source / drain region MSD7 opposite to each other, a sixth memory source / drain region MSD6 and a tenth memory source / drain region MSD10 opposite to each other, a second memory source / drain region MSD2 and an eighth memory source / drain region MSD8 opposite to each other, and a fifth memory source / drain region MSD5 and a ninth memory source / drain region MSD9 opposite to each other.

[0143] like Fig.15 As shown, in the unit test area UTC, portions in which source / drain regions having different conductivity types are opposite to each other are provided as a total of six portions, for example, a first test source / drain region TSD1 and a seventh test source / drain region TSD7 opposite to each other, a sixth test source / drain region TSD6 and a tenth test source / drain region TSD10 opposite to each other, a second test source / drain region TSD2 and an eighth test source / drain region TSD8 opposite to each other, a fifth test source / drain region TSD5 and a ninth test source / drain region TSD9 opposite to each other, a fourth test source / drain region TSD4 and an eleventh test source / drain region TSD11 opposite to each other, and a third test source / drain region TSD3 and a twelfth test source / drain region TSD12 opposite to each other.

[0144] exist Fig.15 In the embodiment, each of the first test gate structure TG1 and the second test gate structure TG2 may intersect with the test active lines 220a, 220b, 220c, and 220d. However, the inventive concepts described herein are not limited thereto. For example, the first test gate structure ( Fig.15 The TG1) can be divided into a portion ( Fig.17 TG1a), and the portion overlapping with the third test active line 220c and the fourth test active line 220d ( Fig.17 TG1b), and a portion overlapping with a pair of second test active lines 220b ( Fig.17 In a similar manner, the second test gate structure ( Fig.15 TG2) can be divided into a portion ( Fig.17 TG2a), and the portion overlapping with the third test active line 220c and the fourth test active line 220d ( Fig.17 TG2b), and a portion overlapping with a pair of second test active lines 220b ( Fig.17 Here, Fig.17 : is a plan view showing a modified example of the first test gate structure TG1 and the second test gate structure TG2 .

[0145] Next, we will refer to Fig.18 and Fig.19 Describes a modified example of unit testing zone UTC. Fig.18 is a plan view showing a modified example of the unit test area UTC, and Fig.19 is shown along Fig.18 Here, Fig.18 and Fig.19 Only the Fig.15 , Fig.16A and Fig. 16B Therefore, please refer to the reference Fig.15 , Fig.16A and Fig. 16B Some components are described, and only modified examples of the positions or arrangements of such components will be described.

[0146] refer to Fig.18 and Fig.19 In the unit test region UTC, a pair of first test active lines 220a, a third test active line 220c, first to third test source / drain regions TSD1, TSD2, and TSD3, a seventh test source / drain region TSD7, an eighth test source / drain region TSD8, and a twelfth test source / drain region TSD12 may be arranged, with reference to Fig.15 , Fig.16A and Fig. 16B The case described is the same or similar. In the unit test area UTC, a pair of second test active lines 320b and fourth test active lines 320d may be set. A pair of second test active lines 320b may be set between the third test active line 220c and the fourth test active line 320d. Therefore, due to Fig.18 and Fig.19 A pair of the second test active line 320b and the fourth test active line 320d in the unit test region UTC can be understood as having ( Fig.15 , Fig.16A and Fig. 16B In the configuration of FIG. 1 , the positions of a pair of the second test active line 220 b and the fourth test active line 220 d are switched, and further detailed description of the arrangement relationship and the separation distance thereof will be omitted.

[0147] Fig.15 , Fig.16A and Fig. 16B shown with a second test active line in a pair ( Fig.15The fourth test source / drain region to the sixth test source / drain region (220b) formed on Fig.15 The fourth test source / drain region to the sixth test source / drain region (TSD4, TSD5 and TSD6) corresponding to Fig.18 TSD4, TSD5 and TSD6) can be set on a pair of second test active lines ( Fig.18 In a similar manner, with reference to Fig.15 , Fig.16A and Fig. 16B The fourth test active line described ( Fig.15 The ninth test source / drain region, the tenth test source / drain region and the eleventh test source / drain region (220d) are formed on the Fig.15 The ninth test source / drain region, the tenth test source / drain region and the eleventh test source / drain region (TSD9, TSD10 and TSD11) corresponding to the Fig.18 TSD9, TSD10 and TSD11) can be set on the fourth test active line ( Fig.18 320d).

[0148] As mentioned earlier, in Fig.13 In the unit memory cell region UMC, the portion where source / drain regions having different conductivity types face each other may include a total of four portions. Fig.18As shown, in the unit test region UTC, the portions where the source / drain regions with different conductivity types are opposite to each other may include a total of nine portions. For example, the seventh test source / drain region TSD7 may be opposite to two test source / drain regions (e.g., the first test source / drain region TSD1 and the fourth test source / drain region TSD4), the eighth test source / drain region TSD8 may be opposite to two test source / drain regions (e.g., the second test source / drain region TSD2 and the fifth test source / drain region TSD5), the twelfth test source / drain region TSD12 may be opposite to two test source / drain regions (e.g., the third test source / drain region TSD14 and the fifth test source / drain region TSD15), and the twelfth test source / drain region TSD16 may be opposite to two test source / drain regions (e.g., the third test source / drain region TSD17 and the fifth test source / drain region TSD18). The eleventh test source / drain region TSD11 may be opposite to a single test source / drain region (e.g., the fourth test source / drain region TSD4), the ninth test source / drain region TSD9 may be opposite to a single test source / drain region (e.g., the fifth test source / drain region TSD5), and the tenth test source / drain region TSD10 may be opposite to a single test source / drain region (e.g., the sixth test source / drain region TSD6). As described above, the number of test source / drain regions that are opposite to each other and have different conductivity types and are arranged in the unit test region UTC may be larger than the number of memory source / drain regions that are opposite to each other and have different conductivity types and are arranged in the unit memory cell region UMC. Therefore, a test structure may be provided that is configured to or used to more accurately check the leakage current characteristics and reliability between source / drain regions that are opposite to each other and have different conductivity types.

[0149] exist Fig.18 In the embodiment, each of the first test gate structure TG1 and the second test gate structure TG2 may intersect with the test active lines 220a, 320b, 220c, and 320d. However, the inventive concepts described herein are not limited thereto. For example, the first test gate structure ( Fig.18 The TG1) can be divided into a portion ( Fig. 20 TG1a), and the portion overlapping with the third test active line 220c ( Fig. 20 TG1b′), and the portion overlapping with a pair of second test active lines 320b ( Fig. 20 TG1c′) and the portion overlapping with the fourth test active line 320d ( Fig. 20 In a similar manner, the second test gate structure ( Fig.18 TG2) can be divided into a portion ( Fig. 20 TG2a), and the portion overlapping with the third test active line 220c ( Fig. 20TG2b′), and the portion overlapping with a pair of second test active lines 320b ( Fig. 20 TG2c′) and the portion overlapping with the fourth test active line 320d ( Fig. 20 TG2d′).

[0150] Next, refer to Fig.21 , Fig.22A and Fig. 22B , examples of semiconductor devices according to some example embodiments will be described. Fig.21 is a plan view showing the unit test area UTC, Fig.22A is shown along Fig.21 A cross-sectional view of a region taken along line IIId-IIId′, and Fig. 22B is shown along Fig.21 A cross-sectional view of an area intercepted by line IVd-IVd′ and line Vd-Vd′. Fig.21 , Fig.22A and Fig. 22B It is shown in Fig.15 , Fig.16A and Fig. 16B FIG. 1 is a diagram of an example of a device configured to apply a current or voltage to test source / drain regions having different conductivity types while being opposite to each other. Therefore, hereinafter, in reference to reference Fig.15 , Fig.16A and Fig. 16B While describing the structure, a wiring structure configured or used to apply current or voltage to test source / drain regions having different conductivity types will be described. Fig.21 , Fig.22A and Fig. 22B When describing, references to Fig.15 , Fig.16A and Fig. 16B A detailed description of some of the components described.

[0151] refer to Fig.21 , Fig.22A and Fig. 22B ,and Fig.15 , Fig.16A and Fig. 16B Together, the contact plug 185 may be disposed on each of the first to twelfth test source / drain regions TSD1 to Twelfth test source / drain regions TSD12 .

[0152] A wiring may be provided that connects the test source / drain regions arranged in the longitudinal direction of the test active line, ie, the first horizontal direction X. The wiring may include first to fourth wirings 190a, 190b, 190c, and 190d.

[0153] The first wiring 190a may overlap with the first test source / drain region TSD1, the second test source / drain region TSD2, and the third test source / drain region TSD3 arranged in the first horizontal direction X on a pair of first test active lines 220a, and the first wiring 190a may be electrically connected to the first test source / drain region TSD1, the second test source / drain region TSD2, and the third test source / drain region TSD3 through the contact plug 185.

[0154] The second wiring 190 b may overlap with the seventh test source / drain region TSD7, the eighth test source / drain region TSD8, and the twelfth test source / drain region TSD12 arranged in the first horizontal direction X on the third test active region 220 c, and the second wiring 190 b may be electrically connected to the seventh test source / drain region TSD7, the eighth test source / drain region TSD8, and the twelfth test source / drain region TSD12 through the contact plug 185.

[0155] The third wiring 190 c may overlap with the ninth, tenth, and eleventh test source / drain regions TSD9, TSD10, and TSD11 arranged in the first horizontal direction X on the fourth test active region 220 d, and the third wiring 190 c may be electrically connected to the ninth, tenth, and eleventh test source / drain regions TSD9, TSD10, and TSD11 through the contact plug 185.

[0156] The fourth wiring 190d may overlap with the fourth test source / drain region TSD4, the fifth test source / drain region TSD5, and the sixth test source / drain region TSD6 arranged in the first horizontal direction X on the pair of second test active lines 220b, and the fourth wiring 190d may be electrically connected to the fourth test source / drain region TSD4, the fifth test source / drain region TSD5, and the sixth test source / drain region TSD6 through the contact plug 185. A lower insulating layer 178 and an upper insulating layer 180 on the lower insulating layer 178 may be provided, the lower insulating layer 178 being formed on the isolation region 130 and between the contact plugs 185. A portion of the upper insulating layer 180 may extend on or cover the test gate structures TG1 and TG2.

[0157] As described above, in the unit test region UTC, more source / drain regions that are opposite to each other and have different conductivity types are placed compared to the unit memory cell region UMC, thereby providing a test structure configured or used to evaluate leakage current characteristics or reliability between source / drain regions that are opposite to each other and have different conductivity types.

[0158] As described above, according to example embodiments of the inventive concepts, a semiconductor device may include a test structure configured to or used to provide an optimal lower active region for application to a circuit structure.

[0159] Furthermore, the semiconductor device may include a test structure configured or used to detect whether a leakage current defect or a reliability defect exists between source / drain regions having different conductivity types.

[0160] Embodiments are described herein with reference to cross-sectional and / or perspective views that are schematic illustrations of idealized embodiments (and intermediate structures). Thus, variations from the shapes of the illustrations due, for example, to manufacturing techniques and / or tolerances are expected. Thus, the embodiments should not be construed as limited to the specific shapes of regions shown herein, but rather include deviations in shapes resulting, for example, from manufacturing.

[0161] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: Semiconductor substrate; as well as a plurality of test structures on the semiconductor substrate, The test structure includes a corresponding lower active region and an upper active region, wherein the corresponding lower active region protrudes from the semiconductor substrate in a vertical direction and has different widths, and the upper active region protrudes from the corresponding lower active region in a vertical direction. Wherein, the corresponding lower active region includes a first region and a second region, wherein the first region overlaps with the upper active region and is located between the second regions, wherein the second region includes an outer region and an inner region between the outer regions, and wherein the outer regions of the respective lower active regions have respective widths that are different from one another, wherein each of the respective widths is uniform in the outer regions, The respective lower active regions have the same number of upper active regions protruding therefrom, and the upper active regions protrude between the outer regions having the respective uniform widths.

2. The semiconductor device according to claim 1, wherein The inner regions of the respective lower active regions have the same width.

3. The semiconductor device according to claim 1, wherein An upper surface and a side surface of one of the outer regions of one of the corresponding lower active regions define a first angle, wherein an upper surface and a side surface of one of the outer regions of the other lower active region of the corresponding lower active region define a second angle, and Wherein, the first angle is different from the second angle.

4. The semiconductor device according to claim 1, wherein: An upper surface of one of the outer regions of one of the corresponding lower active regions defines an acute angle with a side surface, and Wherein, an upper surface and a side surface of one of the outer regions of the other lower active region of the corresponding lower active region define an obtuse angle.

5. The semiconductor device according to claim 1, wherein The width of each of the inner regions is greater than the corresponding width of each of the outer regions, and Wherein, the corresponding lower active regions are discontinuous between the test structures.

6. The semiconductor device according to claim 1, wherein The test structure also includes a gate structure and a source / drain region, wherein the gate structure overlaps the corresponding lower active region and an upper active region protruding from the corresponding lower active region, and The source / drain region is located on the upper active region and between the gate structures in a plan view.

7. The semiconductor device according to claim 6, wherein: The source / drain region includes an epitaxial semiconductor layer extending from a recessed region of the upper active region.

8. The semiconductor device according to claim 6, further comprising: a first isolation region located on the second region of the corresponding lower active region; as well as The second isolation region extends in a vertical direction along a side surface of the corresponding lower active region and is adjacent to the upper active region and the first isolation region.

9. The semiconductor device according to claim 8, wherein: The upper active region protrudes in a vertical direction between the first isolation regions, and The gate structure extends on the upper surface and the side surface of the upper active region.

10. The semiconductor device according to claim 1, further comprising: A plurality of circuit structures on the semiconductor substrate, The circuit structure includes a corresponding circuit lower active region protruding from the semiconductor substrate in a vertical direction, and a circuit upper active region protruding from the corresponding circuit lower active region, and The variation between different widths of the corresponding lower active regions is greater than the variation between widths of the corresponding lower circuit active regions.

11. A semiconductor device comprising: Semiconductor substrate; as well as a plurality of test structures on the semiconductor substrate, Wherein, the multiple test structures include: a lower active region protruding from the semiconductor substrate in a vertical direction perpendicular to the semiconductor substrate, the lower active region having different widths; an upper active region protruding from each of the lower active regions in a vertical direction, the upper active region extending in a first horizontal direction; and a gate structure extending in a second horizontal direction perpendicular to the first horizontal direction, the gate structure having a portion overlapping the lower active region and the upper active region, Each of the lower active regions includes a first region overlapping with the upper active region and a second region not overlapping with the upper active region, and wherein the second area includes an outer area and an inner area between the outer areas; and a plurality of circuit structures on the semiconductor substrate, wherein the plurality of circuit structures include a circuit lower active region extending from the semiconductor substrate in a vertical direction, a circuit upper active region on the circuit lower active region, and a circuit gate structure including a portion overlapping the circuit lower active region and the circuit upper active region, wherein the variation between different widths of the lower active regions of the plurality of test structures is greater than the variation between corresponding widths of the lower circuit active regions of the plurality of circuit structures, and Wherein, the lower active regions of the plurality of test structures are rectangular in shape.

12. The semiconductor device according to claim 11 in, At least one of the under-circuit active areas includes an outer region, and a width of the outer region is equal to a width of one of the outer regions of the plurality of test structures.

13. The semiconductor device according to claim 11, wherein An upper surface and a side surface of one of the outer regions of one of the lower active regions define an acute angle.

14. The semiconductor device according to claim 11, wherein: The respective first widths of the inner regions of the lower active regions having different widths are equal to each other; The outer regions of the lower active region having different widths have respective widths throughout the outer regions that are different from each other and smaller than the respective first widths, and The respective lower active regions are discontinuous between the test structures.

15. The semiconductor device according to claim 11, wherein Respective ends of the outer regions of at least two of the lower active regions having different widths have different heights.

16. The semiconductor device according to claim 11, further comprising a gate connection portion, in, The plurality of test structures include a first test structure, wherein the first test structure includes a first lower active region, a first upper active region extending from the first lower active region in a vertical direction, and a first gate structure including a portion overlapping the first lower active region and the first upper active region, and Wherein, the gate connecting portion is electrically connected to the first gate structure.

17. The semiconductor device according to claim 11, wherein Each of the lower active regions has an equal number of upper active regions protruding therefrom.

18. The semiconductor device according to claim 11, wherein At least one test structure of the plurality of test structures is in a scribe lane region of the semiconductor device.

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