Control circuit, drive circuit, LED lamp system and control method for controlling power transistor

Abstract

The present invention discloses a control circuit, a driving circuit, an LED lamp system and a control method for controlling a power transistor, wherein the control circuit receives an adjustment signal, and the control circuit is used to adjust the current amplitude flowing through the power transistor based on the adjustment signal when the characterization value of the adjustment signal is greater than a first threshold value; the control circuit is used to adjust the time for the current to flow through the power transistor based on the adjustment signal when the characterization value of the adjustment signal is less than a second threshold value; wherein the second threshold value is less than or equal to the first threshold value. The control circuit, the driving circuit, the LED lamp system and the control method proposed in the present invention can improve the control accuracy and efficiency. The present invention improves the control accuracy when the characterization value (such as the duty cycle) of the adjustment signal (such as a PWM signal) is a lower value; at the same time, the drive circuit of the present invention has a smaller loss and a higher efficiency. When the present invention is applied to an LED driving scheme, the dimming accuracy of the LED driving circuit is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of control circuits, and in particular relates to a control circuit, a drive circuit, an LED lamp system and a control method for controlling a power transistor. Background Art

[0002] Linear LED driving circuits are gradually being accepted by the market due to their simple and convenient design, but there are problems with the prior art. Figure 1 FIG. 1 is a circuit diagram of an existing linear LED driving circuit. Figure 2 This is a schematic diagram of the relationship between duty cycle and Io in an existing linear LED driving circuit; please refer to Figure 1 , Figure 2 In the prior art, a reference generation unit generates Vref through PWM control, obtains the sampling voltage and Vref through an operational amplifier, and outputs a control signal to control the current flowing through transistor Q, thereby realizing the dimming of the LED driving circuit. The current flowing through transistor Q is adjusted to a smaller value D2. In the process of the current from the smaller value D2 to zero, the reference Vref is also smaller. However, due to the bias at the input end of the operational amplifier, the control accuracy is affected. Figure 2 As shown, when the PWM duty cycle D1 is a large value, the reference voltage Vref changes linearly during the process of D1 decreasing to D2, so the current flowing through the transistor Q changes linearly. When the duty cycle D2 is further reduced, the control accuracy of the LED circuit is affected due to the bias at the input of the operational amplifier.

[0003] Figure 3 Schematic diagram of some signal waveforms of existing linear LED driving circuit; Figure 3 It can be seen that the loss flowing through the transistor Q is (Vin-VF)*Io. The loss of the transistor Q is large, and the efficiency of its LED driving circuit is relatively low.

[0004] It can be seen that the linear LED driving circuit of the prior art cannot be precisely regulated when the duty cycle of PWM is at a low value, which affects the dimming accuracy of the LED driving circuit. In addition, the linear LED driving circuit of the prior art has a relatively low efficiency.

[0005] In view of this, there is an urgent need to design a driving circuit to overcome the above-mentioned defects of the existing driving circuit. Summary of the invention

[0006] The present invention provides a control circuit, a drive circuit, an LED lamp system and a control method for controlling a power transistor, which can improve control accuracy and control efficiency.

[0007] To solve the above technical problem, according to one aspect of the present invention, the following technical solution is adopted:

[0008] A control circuit for controlling a power transistor, wherein the power transistor and a load are connected in series, the first end of the series-connected power transistor and the load is coupled to an input voltage, and the second end of the series-connected power transistor and the load is coupled to a ground. The control circuit provides a driving current for the load by controlling the conduction state of the power transistor. The control circuit receives an adjustment signal. When the characteristic value of the adjustment signal is greater than a first threshold, the control circuit is used to adjust the current amplitude flowing through the power transistor based on the adjustment signal; when the characteristic value of the adjustment signal is less than a second threshold, the control circuit is used to adjust the time for the current to flow through the power transistor based on the adjustment signal; wherein the second threshold is less than or equal to the first threshold.

[0009] As an implementation mode of the present invention, when the duty cycle of the adjustment signal is greater than the first threshold value, the control circuit is used to adjust the current amplitude flowing through the power transistor and ensure that the on-time of the power transistor remains unchanged or the change amplitude is lower than the set threshold range;

[0010] When the duty cycle of the adjustment signal is less than the second threshold, the control circuit is used to adjust the time for the current to flow through the power transistor and ensure that the amplitude of the current flowing through the power transistor remains unchanged or the variation amplitude is lower than the set threshold range.

[0011] As an embodiment of the present invention, the regulating signal is a pulse width modulation (PWM) signal, and when the duty cycle of the regulating signal is greater than a first threshold value, the control circuit is used to regulate the current amplitude flowing through the power transistor, so that the current amplitude flowing through the power transistor increases with the increase of the duty cycle;

[0012] When the duty cycle of the adjustment signal is less than the second threshold, the control circuit is used to adjust the time for the power transistor to flow current, so that the time for the power transistor to flow current increases with the increase of the duty cycle.

[0013] As an embodiment of the present invention, the regulating signal is a pulse width modulation (PWM) signal, and when the duty cycle of the regulating signal is greater than a first threshold, the control circuit controls the power transistor to be in an on state during a period when the input voltage is greater than the load driving voltage;

[0014] When the duty cycle of the adjustment signal is less than the second threshold, the control circuit controls the power transistor to be turned on part of the time and turned off part of the time during a period when the input voltage is greater than the load driving voltage.

[0015] As an embodiment of the present invention, the control circuit, in the process of adjusting the current amplitude flowing through the power transistor, controls the current amplitude flowing through the power transistor to show a downward trend in the first part of the conduction time during each cycle of the power transistor being turned on, and to show an upward trend in the second part of the conduction time.

[0016] As an embodiment of the present invention, the conduction time of the power transistor is Ton; in the process of adjusting the current amplitude flowing through the power transistor, the control circuit controls the current amplitude flowing through the power transistor to show a downward trend in the first half of the conduction time Ton / 2, and to show an upward trend in the second half of the conduction time Ton / 2.

[0017] As an implementation mode of the present invention, when the duty cycle of the regulation signal PWM is greater than the set threshold m, the on time in one cycle T of the input line voltage is Ton;

[0018] In the first half of the Ton time, the control circuit controls the current flowing through the power transistor to reach the maximum current value Imax and then starts to decrease;

[0019] In the second half of the Ton time, the control circuit controls the current flowing through the power transistor to start to rise and finally reach the maximum current value Imax.

[0020] As an embodiment of the present invention, the control circuit includes:

[0021] A reference generation unit having an input terminal and an output terminal, wherein the input terminal of the reference generation unit receives the adjustment signal, and the output terminal of the reference generation unit provides a current reference signal, and the reference generation unit intermittently sets the current reference signal to a zero value when the representative value of the adjustment signal is less than a second threshold value, so as to turn off the power transistor, wherein the zero value time of the current reference signal is longer when the representative value of the adjustment signal is smaller; and

[0022] The current regulating unit has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the current regulating unit is coupled to the output terminal of the reference generating unit, the second input terminal of the current regulating unit is coupled to a sampling signal representing the current flowing through the power transistor, and the output terminal of the current regulating unit is coupled to the control terminal of the power transistor.

[0023] As an implementation mode of the present invention, it includes: a first reference generation unit A, an average current control compensation unit, a second reference generation unit B and a current adjustment unit;

[0024] The input terminal of the first reference generating unit A receives a PWM signal, and the first reference generating unit A outputs a first reference voltage Vref according to the received PWM signal;

[0025] The output terminal of the second reference generating unit B is coupled to the first input terminal of the current regulating unit, the second input terminal of the current regulating unit is coupled to the sampling voltage Vcs; the output terminal of the current regulating unit is coupled to the control terminal of the power transistor;

[0026] The average current control compensation unit receives the sampling voltage Vcs and the first reference voltage Vref, and obtains the compensation voltage Vcomp at the output end of the average current control compensation unit through operational amplification processing; the output end of the average current control compensation unit is coupled to the second reference generation unit B, and obtains the second reference voltage Vth through processing by the second reference generation unit B;

[0027] The current regulating unit receives the sampling voltage Vcs and the second reference voltage Vth, and outputs a control signal to the power transistor through operational amplification processing to control the state of the power transistor.

[0028] As an implementation mode of the present invention, when the duty cycle of the regulation signal PWM is greater than the set threshold m, the on time in a cycle T is Ton;

[0029] In the first half of the Ton time, the control circuit controls the current flowing through the power transistor to reach the maximum current value Imax and then starts to decrease;

[0030] In the second half of the Ton time, the control circuit controls the current flowing through the power transistor to start to rise and finally reach the maximum current value Imax;

[0031] The maximum current value Imax is controlled by the compensation voltage Vcomp; when the PWM duty cycle decreases, the first reference voltage Vref decreases, and Imax controlled by the compensation voltage Vcomp decreases; when the first reference voltage Vref increases, the maximum current value Imax controlled by the compensation voltage Vcomp increases.

[0032] As an implementation manner of the present invention, the average current control compensation unit includes a first error amplifier EA1, and the current regulation unit includes a second error amplifier EA2.

[0033] As an implementation manner of the present invention, the average current control compensation unit further includes a capacitor, and the capacitor is coupled to the output end of the first error amplifier EA1.

[0034] As an embodiment of the present invention, the load has a forward voltage VF when being driven;

[0035] When the PWM duty cycle is less than the set threshold m, when the input voltage Vin> forward voltage VF, the time for the control transistor Q to flow current decreases as the PWM duty cycle decreases;

[0036] When the PWM duty cycle is greater than the set threshold m, when the input voltage Vin> the forward voltage VF, the control transistor Q always flows current, and the average value of the flowing current increases with the increase of the PWM duty cycle.

[0037] As an embodiment of the present invention, the load has a forward voltage VF when being driven; when the PWM duty cycle is less than the set threshold m, when the input voltage Vin> the forward voltage VF, the transistor Q remains closed during the hold-off time Tz, and after the hold-off time Tz ends, and when the input voltage Vin> the forward voltage VF, the transistor Q begins to flow current, and the conduction time is Ton';

[0038] Alternatively, when the input voltage Vin>forward voltage VF, transistor Q starts to flow current, and after the on-time Ton', transistor Q remains off during the off-time Tz, waiting for the next cycle.

[0039] As an embodiment of the present invention, the first reference generating unit A includes a third resistor R3 and a third capacitor C3; a first end of the third resistor R3 is coupled to the PWM signal, and a second end of the third resistor R3 is coupled to a first end of the third capacitor C3.

[0040] As an embodiment of the present invention, the second reference generating unit B includes a first comparator, a second comparator, a multiplier, a second transistor Q2, a third transistor Q3, a current source and a second capacitor;

[0041] The first comparator compares the input voltage Vin and the forward voltage VF, the output terminal of the first comparator is coupled to the gate of the third transistor Q3, and the source of the third transistor Q3 is grounded; the current source is respectively coupled to the drain of the third transistor Q3, the first terminal of the second capacitor, and the non-inverting input terminal of the second comparator;

[0042] The compensation voltage Vcomp is respectively coupled to the inverting input terminal of the second comparator, the drain of the second transistor Q2, and the non-inverting input terminal of the multiplier; the inverting input terminal of the multiplier is coupled to the reference voltage V(t); the output terminal of the second comparator is coupled to the gate of the second transistor Q2, and the source of the second transistor Q2 is grounded; the output terminal of the multiplier outputs the second reference voltage Vth.

[0043] As an implementation mode of the present invention, the second reference generating unit B includes a first resistor R1, a second resistor R2, a first comparator, a second comparator, a multiplier, a second transistor Q2, a third transistor Q3, a current source, and a second capacitor;

[0044] The non-inverting input terminal of the first comparator is coupled to the input voltage Vin, the inverting input terminal of the first comparator is coupled to the forward voltage VF, the output terminal of the first comparator is coupled to the gate of the third transistor Q3, and the source of the third transistor Q3 is grounded; the current source is respectively coupled to the drain of the third transistor Q3, the first end of the second capacitor, and the non-inverting input terminal of the second comparator;

[0045] The compensation voltage Vcomp is respectively coupled to the first end of the first resistor R1 and the inverting input end of the second comparator; the second end of the first resistor R1 is respectively coupled to the first end of the second resistor R2, the drain of the second transistor Q2, and the non-inverting input end of the multiplier; the inverting input end of the multiplier is coupled to the reference voltage V(t); the second end of the second resistor R2 is grounded; the output end of the second comparator is coupled to the gate of the second transistor Q2, and the source of the second transistor Q2 is grounded; the output end of the multiplier outputs the second reference voltage Vth.

[0046] As an implementation mode of the present invention, the second reference voltage Vth=k*Vcomp-V(t), wherein V(t)=k'*sin(ωt), the frequency corresponding to ω is positively correlated with the grid frequency, k and k' are constants, thereby obtaining a saddle-shaped second reference voltage Vth output.

[0047] As an embodiment of the present invention, when the PWM duty cycle is less than the set threshold m, when the input voltage Vin> forward voltage VF, the third transistor Q3 is turned on, at this time the current source charges the capacitor, the capacitor voltage VA gradually increases, when the capacitor voltage VA is greater than the compensation voltage Vcomp, the second transistor Q2 is turned on, at this time, the second reference voltage Vth is zero, so the transistor Q is turned off.

[0048] According to another aspect of the present invention, the following technical solution is adopted: a driving circuit, the driving circuit includes the above-mentioned control circuit and a power transistor; the control circuit is coupled to the control end of the power transistor.

[0049] According to another aspect of the present invention, the following technical solution is adopted: an LED lamp system, the LED lamp system includes the above-mentioned driving circuit.

[0050] As an embodiment of the present invention, the LED lamp system includes at least two LED lamps; the at least two LED lamps have LED lamps of different colors;

[0051] The control circuit is coupled to at least one LED lamp and adjusts the current of at least one LED lamp to achieve color adjustment.

[0052] According to another aspect of the present invention, the following technical solution is adopted: a control method for controlling the current flowing through a power transistor, the power transistor and the load are connected in series, the power transistor is used to provide a driving current for the load, and the control method includes: when the characterization value of the adjustment signal is greater than a first threshold, adjusting the current amplitude flowing through the power transistor; when the characterization value of the adjustment signal is less than a second threshold, adjusting the time for the current to flow through the power transistor; wherein the second threshold is less than or equal to the first threshold.

[0053] As an implementation mode of the present invention, when the duty cycle of the adjustment signal is greater than the first threshold, the current amplitude flowing through the power transistor is adjusted, and the on-time of the power transistor is ensured to remain unchanged or the variation amplitude is lower than the set threshold;

[0054] When the duty cycle of the adjustment signal is less than the second threshold, the time for the current to flow through the power transistor is adjusted to ensure that the amplitude of the current flowing through the power transistor remains unchanged or the variation amplitude is lower than the set threshold.

[0055] As an implementation mode of the present invention, when the duty cycle of the adjustment signal is greater than a threshold value, the current amplitude flowing through the power transistor is adjusted so that the current amplitude flowing through the power transistor increases as the duty cycle increases;

[0056] When the duty cycle of the adjustment signal is less than the second threshold, the time for the current to flow through the power transistor is adjusted, so that the time for the current to flow through the power transistor increases as the duty cycle increases.

[0057] As an embodiment of the present invention, in the process of adjusting the current amplitude flowing through the power transistor, the current amplitude flowing through the power transistor is controlled to show a downward trend in the first part after the power transistor is turned on, and to show an upward trend in the second part of the conduction time.

[0058] As an embodiment of the present invention, the on-time of the power transistor is Ton; in the process of adjusting the current amplitude flowing through the power transistor, the current amplitude flowing through the power transistor is controlled to show a downward trend in the first half of the on-time Ton / 2, and to show an upward trend in the second half of the on-time Ton / 2.

[0059] As an implementation mode of the present invention, when the duty cycle of the regulation signal PWM is greater than the set threshold m, the on time in the period T is Ton;

[0060] In the first half of the Ton time, the current flowing through the power transistor is controlled to reach the maximum current Imax and then begins to decrease;

[0061] In the second half of the Ton time, the current flowing through the power transistor starts to rise and finally reaches the maximum current Imax.

[0062] As an implementation mode of the present invention, the control method specifically includes:

[0063] Obtaining a compensation voltage Vcomp according to the current sampling voltage Vcs and the adjustment signal;

[0064] Obtaining a second reference voltage Vth according to the compensation voltage Vcomp, wherein when the compensation voltage Vcomp is less than a threshold, the second reference voltage Vth is intermittently set to zero;

[0065] The sampling voltage Vcs and the second reference voltage Vth are received, and a control signal is output to the power transistor after being processed by operational amplification to control the state of the power transistor.

[0066] As an implementation mode of the present invention, when the duty cycle of the regulation signal PWM is greater than the set threshold m, the on time in the period T is Ton;

[0067] In the first half of the Ton time, the current flowing through the power transistor is controlled to reach the maximum current Imax and then begins to decrease;

[0068] In the second half of the Ton time, the current flowing through the power transistor starts to rise and finally reaches the maximum current Imax;

[0069] The maximum current value Imax is controlled by the compensation voltage Vcomp; when the PWM duty cycle decreases, the first reference voltage Vref decreases, and Imax controlled by the compensation voltage Vcomp decreases; when the first reference voltage Vref increases, the maximum current value Imax controlled by the compensation voltage Vcomp increases.

[0070] As an embodiment of the present invention, the load has a forward voltage VF when being driven, and the transistor and the load connected in series are powered by the input voltage Vin. When the duty cycle of the adjustment signal is less than the set threshold m, when the input voltage Vin> the forward voltage VF, the average value of the current flowing through the transistor Q is controlled to decrease within half a power frequency cycle, and the time for the current to flow through the transistor Q is controlled to decrease as the duty cycle of the adjustment signal decreases;

[0071] When the duty cycle of the regulation signal is greater than the set threshold m, when the input voltage Vin> the forward voltage VF, the control transistor Q always flows current, and the average value of the current flowing through the transistor Q increases with the increase of the duty cycle of the regulation signal.

[0072] As an embodiment of the present invention, when the load has a forward voltage VF when being driven, and the PWM duty cycle is less than a set threshold value m, when the input voltage Vin> the forward voltage VF, the transistor Q remains closed during the hold-off time Tz, and after waiting for the hold-off time Tz to end, and when the input voltage Vin> the forward voltage VF, the transistor Q begins to flow current, and the conduction time is Ton';

[0073] Alternatively, when the input voltage Vin>forward voltage VF, transistor Q starts to flow current, and after the on-time Ton', transistor Q remains off during the off-time Tz, waiting for the next cycle.

[0074] As an embodiment of the present invention, the control method further includes controlling at least one LED lamp among the at least two LED lamps to adjust the current of the at least one LED lamp to achieve color adjustment.

[0075] The beneficial effect of the present invention is that the control circuit, drive circuit, LED lamp system and control method for controlling the power transistor proposed in the present invention can improve the control accuracy and control efficiency.

[0076] The present invention improves the control accuracy when the characteristic value (such as duty cycle) of the adjustment signal (such as PWM signal) is a low value; at the same time, the drive circuit of the present invention has low loss and high efficiency. The present invention is applied to the LED drive solution to improve the dimming accuracy of the LED drive circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] Figure 1 It is a circuit diagram of an existing linear LED driving circuit.

[0078] Figure 2 Schematic diagram of the relationship between duty cycle and Io in an existing linear LED driving circuit.

[0079] Figure 3 Schematic diagram of some signal waveforms of an existing linear LED driving circuit.

[0080] Figure 4 Schematic diagram of a signal waveform for controlling the current amplitude and flow time of a power transistor in one embodiment of the present invention.

[0081] Figure 5 FIG. 4 is a circuit diagram of a driving circuit in an embodiment of the present invention.

[0082] Figure 6 FIG. 1 is a schematic diagram of a waveform of a current flowing through a transistor during the conduction time of the transistor in an embodiment of the present invention.

[0083] Figure 7 FIG. 1 is a schematic diagram of a waveform of a voltage Vth during the conduction time of a transistor in an embodiment of the present invention.

[0084] Figure 8 FIG. 4 is a schematic diagram showing the relationship between the average current flowing through the transistor and Vref according to an embodiment of the present invention.

[0085] Fig. 9 FIG. 4 is a circuit diagram of a first reference generating unit according to an embodiment of the present invention.

[0086] Fig.10 FIG. 4 is a circuit diagram of a second reference generating unit according to an embodiment of the present invention.

[0087] Fig.11 FIG. 4 is a circuit diagram of an LED system in one embodiment of the present invention. DETAILED DESCRIPTION

[0088] The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0089] In order to further understand the present invention, preferred embodiments of the present invention are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of the present invention, rather than limiting the claims of the present invention.

[0090] The description in this section is only for several typical embodiments, and the present invention is not limited to the scope of the embodiments. The same or similar prior art means and some technical features in the embodiments are mutually replaced within the scope of the present invention.

[0091] The term "coupling" or connection in the specification includes both direct connection and indirect connection, such as connection through some active devices, passive devices or electrically conductive media; it may also include connection through other active devices or passive devices known to those skilled in the art on the basis of achieving the same or similar functional purposes, such as connection through circuits or components such as switches and follower circuits.

[0092] The present invention discloses a control circuit, which is coupled to a power transistor; the control circuit is used to adjust the current amplitude flowing through the power transistor when the characterization value of the adjustment signal is greater than a first threshold; the control circuit is used to adjust the time for the current to flow through the power transistor when the characterization value of the adjustment signal is less than a second threshold; wherein the second threshold is less than or equal to the first threshold.

[0093] In one embodiment of the present invention, the control circuit is used to control a power transistor, the power transistor and the load are connected in series, the first end of the series-connected power transistor and the load is coupled to an input voltage, and the second end of the series-connected power transistor and the load is coupled to ground. The control circuit provides a driving current to the load by controlling the conduction state of the power transistor. The control circuit receives an adjustment signal, and the control circuit is used to adjust the current amplitude flowing through the power transistor based on the adjustment signal when the characterization value of the adjustment signal is greater than a first threshold; the control circuit is used to adjust the time for the current to flow through the power transistor based on the adjustment signal when the characterization value of the adjustment signal is less than a second threshold; wherein the second threshold is less than or equal to the first threshold.

[0094] In one embodiment, the regulating signal is a pulse width modulation (PWM) signal, and the characteristic value of the regulating signal is the duty cycle of the PWM signal. In another embodiment, the regulating signal is an analog signal, and its characteristic value is the amplitude of the analog signal. Preferably, the regulating signal is a dimming signal, which is used to adjust the brightness of the LED.

[0095] In one embodiment of the present invention, the second threshold may be greater than the first threshold; in another embodiment of the present invention, the second threshold is equal to the first threshold.

[0096] In one embodiment of the present invention, when the duty cycle of the adjustment signal is greater than the first threshold, the control circuit is used to adjust the current amplitude flowing through the power transistor, and ensure that the on-time of the power transistor remains unchanged or the change amplitude is lower than the set threshold interval (the on-time of the power transistor remains unchanged or changes slightly). When the duty cycle of the adjustment signal is less than the second threshold, the control circuit is used to adjust the time when the power transistor flows through the current, and ensure that the current amplitude flowing through the power transistor remains unchanged or the change amplitude is lower than the set threshold interval (the current amplitude remains unchanged or changes slightly).

[0097] Figure 4 Schematic diagram of a signal waveform for controlling the current amplitude and flow time of a power transistor in an embodiment of the present invention; please refer to Figure 4 In one embodiment of the present invention, when the duty cycle of the dimming signal (or other adjustment signal) is greater than the first threshold value (D2) (the duty cycle of the dimming signal is from D1 to D2), the control circuit is used to adjust the current amplitude flowing through the power transistor, so that the current amplitude flowing through the power transistor increases with the increase of the duty cycle. When the duty cycle of the dimming signal is less than the second threshold value (D1), the control circuit is used to adjust the time for the current to flow through the power transistor, so that the time for the current to flow through the power transistor increases with the increase of the duty cycle. In the 0-D2 interval, the current is shown in the form of a pulse, which does not mean that the current is zero at certain duty cycles, but it can represent that in this interval, when the input voltage is greater than the load driving voltage (forward voltage), the current is intermittently controlled to be zero, which is used to reduce the current average value on the basis of maintaining a certain current amplitude. In one embodiment of the present invention, the control circuit of the present invention is applied to an LED driving circuit, such as Figure 4 As shown, the duty cycle of the dimming signal changes from D2 to D1, changing the current amplitude flowing through the LED, while the time of the current flowing through the LED (i.e., the conduction time of the LED) remains unchanged or changes slightly (the change amplitude is lower than the set threshold range). The duty cycle of the dimming signal changes from D2 to 0, changing the time of the current flowing through the LED, while the current amplitude flowing through the LED remains unchanged or changes slightly.

[0098] In one embodiment of the present invention, when the duty cycle is less than a specific value (such as D2), the current amplitude flowing through the LED remains unchanged or changes slightly, and the bias offset at the input of the operational amplifier has little effect on the dimming accuracy. In the prior art, as the duty cycle gradually decreases, the current amplitude flowing through the LED decreases to a lower value, and the bias offset at the input of the operational amplifier has a greater error effect, thus having a greater impact on the dimming accuracy.

[0099] In one embodiment of the present invention, when the duty cycle of the adjustment signal changes from D2 to 0, when the current amplitude is controlled to be 100mA and the output current duty cycle is 50%, the average current flowing through the LED is 50mA; when the output current duty cycle is 20%, the average current flowing through the LED is 20mA. That is, the time of the current flowing through the LED is changed, while the current amplitude flowing through the LED remains unchanged or changes slightly, thereby achieving the adjustment of the average current flowing through the LED and realizing precise dimming.

[0100] In one embodiment of the present invention, the control circuit controls the current amplitude flowing through the power transistor to show a downward trend in the first part after the power transistor is turned on, and to show an upward trend in the second part of the conduction time. For example, in one embodiment of the present invention, the conduction time of the power transistor is Ton; in the process of adjusting the current amplitude flowing through the power transistor, the control circuit controls the current amplitude flowing through the power transistor to show a downward trend in the first half of the conduction time Ton / 2, and to show an upward trend in the second half of the conduction time Ton / 2, such as Figure 6 shown.

[0101] In one embodiment of the present invention, when the duty cycle of the regulation signal PWM is greater than the set threshold value m, the on-time in the period T is Ton; in the first half of the Ton time, the control circuit controls the current flowing through the transistor Q to reach the maximum current value Imax and then starts to decrease; in the second half of the Ton time, the control circuit controls the current flowing through the transistor Q to start to increase and finally reach the maximum current value Imax, such as Figure 6 shown.

[0102] Figure 5 Schematic diagram of a driving circuit in one embodiment of the present invention. In one embodiment of the present invention, a power transistor Q is connected in series with an LED load, one end of the power transistor Q and the load connected in series receives an input voltage Vin, and the other end is grounded, and a driving current is provided to the LED load under the action of the power transistor Q. In one embodiment, when the duty cycle of the regulating signal PWM is greater than a threshold m1, the power transistor Q is controlled to be always in an on state during a period when the input voltage Vin is greater than the load driving voltage (or forward voltage VF); when the duty cycle of the regulating signal PWM is less than a second threshold m2, the power transistor Q is controlled to be on part of the time and off part of the time during a period when the input voltage Vin is greater than the forward voltage VF, wherein m2 is less than or equal to m1.

[0103] In an embodiment of the present invention, the power transistor Q may include a field effect transistor, such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or a JFET (Junction Field Effect Transistor).

[0104] In one embodiment, Figure 5 As shown, the load includes an LED and a capacitor connected in parallel with the LED.

[0105] In one embodiment of the present invention, the control circuit includes a reference generation unit and a current adjustment unit. The reference generation unit has an input end and an output end, wherein the input end of the reference generation unit receives the adjustment signal, and the output end of the reference generation unit provides a current reference signal. When the characteristic value of the adjustment signal is less than the second threshold, the reference generation unit intermittently sets the current reference signal to zero value, so as to turn off the power transistor, wherein the smaller the characteristic value of the adjustment signal is, the longer the zero value time of the current reference signal is. In one embodiment, the reference generation unit includes a comparison circuit (see Fig.10 The comparison circuit 22) and the switch coupled to the comparison circuit (see Fig.10 The switch Q2 in the circuit is connected to the ground at one end and the output end of the reference generation unit at the other end. The comparison circuit is used to intermittently turn on the switch to set the reference signal Vth to zero when the representative value of the adjustment signal is less than a threshold value. The current adjustment unit has a first input end, a second input end and an output end, wherein the first input end of the current adjustment unit is coupled to the output end of the reference generation unit, the second input end of the current adjustment unit is coupled to the sampling signal representing the current flowing through the power transistor, and the output end of the current adjustment unit is coupled to the control end of the power transistor.

[0106] See also Figure 5 In one embodiment of the present invention, the control circuit includes: a first reference generation unit A, an average current control compensation unit 2, a second reference generation unit B and a current adjustment unit 4.

[0107] In one embodiment of the present invention, the input terminal of the first reference generation unit A receives a PWM signal, and the first reference generation unit A outputs a first reference voltage Vref according to the received PWM signal; the output terminal of the first reference generation unit A is coupled to the first input terminal of the average current control compensation unit 2, the second input terminal of the average current control compensation unit 2 is coupled to the sampling voltage Vcs, and the output terminal of the average current control compensation unit 2 is coupled to the second reference generation unit B. The output terminal of the second reference generation unit B is coupled to the first input terminal of the current adjustment unit 4, the second input terminal of the current adjustment unit 4 is coupled to the sampling voltage Vcs; the output terminal of the current adjustment unit 4 is coupled to the control terminal of the power transistor. In one embodiment of the present invention, the average current control compensation unit 2 receives the sampling voltage Vcs and the first reference voltage Vref, and obtains the compensation voltage Vcomp at the output terminal of the average current control compensation unit after operational amplification processing; the output terminal of the average current control compensation unit 2 is coupled to the second reference generation unit B, and the second reference generation unit B processes to obtain the second reference voltage Vth, also called the current reference signal Vth. In one embodiment of the present invention, the current regulating unit 4 receives the sampling voltage Vcs and the second reference voltage Vth, and outputs a control signal to the power transistor through operational amplification to control the state of the power transistor.

[0108] Figure 6 FIG. 1 is a schematic diagram of a waveform of a current flowing through a transistor during the on-time of a transistor in an embodiment of the present invention; please refer to FIG. Figure 6 In one embodiment of the present invention, when the duty cycle of the regulation signal PWM is greater than the set threshold value m, the conduction time in the steamed bun wave period T is Ton; in the first half of the Ton time, the control circuit controls the current flowing through the transistor Q to reach the maximum current value Imax and then begins to decrease; in the second half of the Ton time, the control circuit controls the current flowing through the transistor Q to start to rise and finally reach the maximum current value Imax. The maximum current value Imax is controlled by the compensation voltage Vcomp; when the PWM duty cycle decreases, the first reference voltage Vref decreases, and the Imax controlled by the compensation voltage Vcomp will decrease; when the first reference voltage Vref increases, the maximum current value Imax controlled by the compensation voltage Vcomp will increase.

[0109] In an embodiment of the present invention, the average current control compensation unit 2 includes a first error amplifier EA1; in an embodiment of the present invention, the current regulation unit 4 includes a second error amplifier EA2. In an embodiment of the present invention, the average current control compensation unit 2 may further include a second capacitor C2, and the second capacitor C2 is coupled to the output terminal of the first error amplifier EA1. Of course, the average current control compensation unit 2 can also be implemented by other methods, and this capacitor may not exist or the error amplifier EA may not be used.

[0110] In an embodiment of the present invention, the current regulation unit 4 is used to control the magnitude and time of the current flowing through the transistor Q. In an embodiment of the present invention, when the PWM duty cycle is less than the set threshold m, and when the input voltage Vin > forward voltage VF, the current regulation unit 4 controls the average value of the current flowing through the transistor Q to decrease within half of the power frequency cycle, and controls the time for the transistor Q to conduct current to decrease as the PWM duty cycle decreases. When the PWM duty cycle is greater than the set threshold m, and when the input voltage Vin > forward voltage VF, the current regulation unit 4 controls the transistor Q to always conduct current, and the average value of the current flowing through it increases as the PWM duty cycle increases.

[0111] In an embodiment of the present invention, the current flowing through the power transistor (such as transistor Q) includes two states:

[0112] State (1): When the PWM duty cycle PWM Duty of the regulation signal < m (m is the threshold, that is, when the PWM duty cycle is a smaller value, corresponding to the process of the duty cycle from D2 to 0), and when the input voltage Vin > forward voltage VF, the current flowing through the transistor Q not only decreases in average value (within half of the power frequency cycle), but also the time for the transistor Q to conduct current decreases.

[0113] State (2): When the PWM duty cycle PWM Duty of the regulation signal > m, and when the input voltage Vin > forward voltage VF, the transistor Q always conducts current, and the average value of the current flowing through it increases (as the duty cycle Duty increases, the average value increases).

[0114] In an embodiment of the present invention, when the power transistor is in state (2), the PWM duty cycle PWM Duty of the regulation signal can be 100%.

[0115] In an embodiment of the present invention, when the power transistor is in state (2), such as Figure 6As shown, the conduction time in the steamed bun wave period T is Ton. When the input voltage Vin>forward voltage VF, the current flowing through transistor Q has the following characteristics (the current flowing through transistor Q is saddle-shaped): ① In the first half of the Ton time, the current flowing through transistor Q reaches the maximum current Imax and then begins to decline; ② In the second half of the Ton time, the current flowing through transistor Q begins to rise and finally reaches the maximum current Imax.

[0116] Since the loss flowing through transistor Q is (Vin-VF)*I0 when the input voltage Vin>forward voltage VF, the current that meets this characteristic reduces the loss of transistor Q.

[0117] In addition, in one embodiment of the present invention, in order to maintain The maximum current value Imax is controlled by the compensation voltage Vcomp. When the PWM Duty decreases, the first reference voltage Vref decreases, and the maximum current value Imax under the control of the compensation voltage Vcomp decreases; when the comparison voltage Vref increases, the opposite is true. This is a method to achieve a constant average current. The compensation voltage Vcomp can also achieve this purpose by controlling other signals.

[0118] In one embodiment of the present invention, when the power transistor is in the above state (1), the current flowing through the transistor Q has the following characteristics: when Vin>VF, the transistor Q remains closed within Tz, and after waiting for Tz to end, and when Vin>VF, the transistor Q starts to flow current, and the conduction time is Ton'. Or when Vin>VF, the transistor Q starts to flow current, and after the conduction time Ton', the transistor Q remains closed within Tz, waiting for the next cycle.

[0119] In one embodiment of the present invention, during the entire process, the average current flowing through the transistor Q is still equal to Vref / R, so the final dimming curve is as follows: Figure 8 shown.

[0120] In one embodiment, the control circuit includes a reference generation unit and a current adjustment unit 4. The reference generation unit may include Figure 5The first reference generation unit A, the average current control compensation unit 2 and the second reference generation unit B are shown. In one embodiment of the present invention, the input end of the reference generation unit receives the adjustment signal PWM, and the output end of the reference generation unit provides a current reference signal Vth (i.e., a second reference voltage Vth). The reference generation unit intermittently sets the current reference signal Vth to zero when the characterization value of the adjustment signal PWM, such as the duty cycle, is less than the second threshold value, so as to turn off the power transistor Q. In one embodiment of the present invention, when the characterization value of the adjustment signal is less than the threshold value, the smaller the characterization value of the adjustment signal, such as the smaller the duty cycle of the PWM signal, the longer the zero value time of the current reference signal Vth. The first input end of the current adjustment unit 4 is coupled to the output end of the reference generation unit for receiving the current reference signal Vth, the second input end of the current adjustment unit 4 is coupled to the sampling signal CS representing the current flowing through the power transistor, and the output end of the current adjustment unit 4 is coupled to the control end of the power transistor Q.

[0121] Fig. 9 FIG. 1 is a circuit diagram of a first reference generating unit according to an embodiment of the present invention; please refer to FIG. Fig. 9 In one embodiment of the present invention, the first reference generating unit A includes a third resistor R3 and a third capacitor C3; a first end of the third resistor R3 is coupled to the PWM signal, and a second end of the third resistor R3 is coupled to a first end of the third capacitor C3.

[0122] In one embodiment of the present invention, the second reference generation unit B includes a first comparator, a second comparator, a multiplier, a second transistor Q2, a third transistor Q3, a current source, and a second capacitor C2. The non-inverting input terminal of the first comparator is coupled to the input voltage Vin, the inverting input terminal of the first comparator is coupled to the forward voltage VF, the output terminal of the first comparator is coupled to the gate of the third transistor Q3, and the source of the third transistor Q3 is grounded; the current source is respectively coupled to the drain of the third transistor Q3, the first end of the second capacitor C2, and the non-inverting input terminal of the second comparator. The first reference generation unit A outputs a compensation voltage Vcomp, and the compensation voltage Vcomp is respectively coupled to the inverting input terminal of the second comparator, the drain of the second transistor Q2, and the non-inverting input terminal of the multiplier; the inverting input terminal of the multiplier is coupled to the voltage V(t); the output terminal of the second comparator is coupled to the gate of the second transistor Q2, and the source of the second transistor Q2 is grounded; the output terminal of the multiplier outputs the second reference voltage Vth.

[0123] Fig.10 is a circuit diagram of a second reference generating unit in an embodiment of the present invention; please refer to Fig.10In one embodiment of the present invention, the second reference generating unit B comprises a first resistor R1, a second resistor R2, a first comparator 21, a second comparator 22, a multiplier 23, a second transistor Q2, a third transistor Q3, a current source 24, and a second capacitor C2. In one embodiment of the present invention, the non-inverting input terminal of the first comparator 21 is coupled to the input voltage Vin, the inverting input terminal of the first comparator 21 is coupled to the forward voltage VF, the output terminal of the first comparator 21 is coupled to the gate of the third transistor Q3, and the source of the third transistor Q3 is grounded; the current source 24 is respectively coupled to the drain of the third transistor Q3, the first end of the second capacitor C2, and the non-inverting input terminal of the second comparator 22. The first reference generating unit A outputs a compensation voltage Vcomp, and the compensation voltage Vcomp is respectively coupled to the first end of the first resistor R1 and the inverting input end of the second comparator 22; the second end of the first resistor R1 is respectively coupled to the first end of the second resistor R2, the drain of the second transistor Q2, and the non-inverting input end of the multiplier 23; the inverting input end of the multiplier 23 is coupled to the voltage V(t); the second end of the second resistor R2 is grounded; the output end of the second comparator 22 is coupled to the gate of the second transistor Q2, and the source of the second transistor Q2 is grounded; the output end of the multiplier 23 outputs the second reference voltage Vth. The second reference voltage Vth=k*Vcomp-V(t), wherein V(t)=k'*sin(ωt), the frequency corresponding to ω is positively correlated with the grid frequency, and k and k' are constants, thereby obtaining a saddle-shaped second reference voltage Vth output.

[0124] In one embodiment of the present invention, when the PWM duty cycle is less than the set threshold m, when the input voltage Vin> forward voltage VF, the third transistor Q3 is turned on, at which time the current source charges the capacitor, and the capacitor voltage VA gradually increases. When the capacitor voltage VA is greater than the compensation voltage Vcomp, the second transistor Q2 is turned on, at which time the second reference voltage Vth is zero, so the transistor Q is turned off.

[0125] In one embodiment of the present invention, the control circuit is a control chip; for example, in one embodiment of the present invention, the control circuit may be a high-efficiency dimming linear control chip.

[0126] The present invention also discloses a driving circuit, the driving circuit comprising the above-mentioned control circuit and a power transistor; the control circuit is coupled to the control terminal of the power transistor. The specific driving method and process of the driving circuit can refer to the above-mentioned description of the control circuit.

[0127] The present invention also discloses an LED lamp system, the LED lamp system comprising the above-mentioned driving circuit. The specific driving method and process of the LED lamp system can refer to the above-mentioned description of the control circuit and the driving circuit.

[0128] Fig.11 is a circuit diagram of an LED system in one embodiment of the present invention; please refer to Fig.11 In one embodiment of the present invention, the LED lamp system includes at least two LED lamps; there are LED lamps of different colors in the at least two LED lamps; the control circuit is coupled to at least one LED lamp, adjusts the current of at least one LED lamp, and realizes color adjustment.

[0129] The present invention further discloses a control method for controlling the current flowing through a power transistor, wherein the power transistor and a load are connected in series, and the power transistor is used to provide a driving current for the load. The control method includes: when the characterization value of the dimming signal is greater than a first threshold, adjusting the current amplitude flowing through the power transistor; when the characterization value of the dimming signal is less than a second threshold, adjusting the time for the current to flow through the power transistor; wherein the second threshold is less than or equal to the first threshold.

[0130] In one embodiment of the present invention, the characterizing value of the adjustment signal is the duty cycle of the dimming signal. In one embodiment of the present invention, when the duty cycle of the dimming signal is greater than a first threshold, the current amplitude flowing through the power transistor is adjusted, and the on-time of the power transistor is ensured to remain unchanged or the change amplitude is lower than the set threshold; when the duty cycle of the dimming signal is less than a second threshold, the time for the current to flow through the power transistor is adjusted, and the current amplitude flowing through the power transistor is ensured to remain unchanged or the change amplitude is lower than the set threshold.

[0131] Figure 4 Schematic diagram of a signal waveform for controlling the current amplitude and flow time of a power transistor in an embodiment of the present invention; please refer to Figure 4 In one embodiment of the present invention, when the duty cycle of the dimming signal is greater than a threshold value, the current amplitude flowing through the power transistor is adjusted so that the current amplitude flowing through the power transistor increases with the increase of the duty cycle; when the duty cycle of the dimming signal is less than a second threshold value, the time for the current to flow through the power transistor is adjusted so that the time for the current to flow through the power transistor increases with the increase of the duty cycle.

[0132] In one embodiment of the present invention, during the process of adjusting the current amplitude flowing through the power transistor, the current amplitude flowing through the power transistor is controlled to show a downward trend in the first part after the power transistor is turned on, and to show an upward trend in the second part of the conduction time.

[0133] In one embodiment of the present invention, the on-time of the power transistor is Ton; in the process of adjusting the current amplitude flowing through the power transistor, the current amplitude flowing through the power transistor is controlled to show a downward trend in the first half of the on-time Ton / 2, and to show an upward trend in the second half of the on-time Ton / 2.

[0134] In one embodiment of the present invention, when the duty cycle of the regulation signal PWM is greater than the set threshold value m, the conduction time in the steamed bun wave period T is Ton; in the first half of the Ton time, the current flowing through the power transistor is controlled to reach the maximum current Imax and then begin to decline; in the second half of the Ton time, the current flowing through the power transistor is controlled to start to rise and finally reach the maximum current Imax.

[0135] In one embodiment of the present invention, the control method specifically includes: outputting a first reference voltage Vref according to a received PWM signal, and this step can also be omitted for directly receiving a reference voltage; receiving a sampled voltage Vcs and a first reference voltage Vref, and obtaining a compensation voltage Vcomp through operational amplification; obtaining a second reference voltage Vth according to the compensation voltage Vcomp; receiving a sampled voltage Vcs and a second reference voltage Vth, and outputting a control signal to a power transistor through operational amplification to control the state of the power transistor. When the compensation voltage Vcomp is less than a threshold, the second reference voltage Vth is intermittently set to zero.

[0136] Figure 6 FIG. 1 is a schematic diagram of a waveform of a current flowing through a transistor during the on-time of a transistor in an embodiment of the present invention; please refer to FIG. Figure 6 In one embodiment of the present invention, when the duty cycle of the regulation signal PWM is greater than the set threshold value m, the conduction time in the steamed bun wave period T is Ton; in the first half of the Ton time, the current flowing through the power transistor is controlled to reach the maximum current value Imax and then begin to decrease; in the second half of the Ton time, the current flowing through the power transistor is controlled to start to rise and finally reach the maximum current value Imax. The maximum current value Imax is controlled by the compensation voltage Vcomp; when the PWM duty cycle decreases, the first reference voltage Vref decreases, and the Imax controlled by the compensation voltage Vcomp will decrease; when the first reference voltage Vref increases, the maximum current value Imax controlled by the compensation voltage Vcomp will increase.

[0137] In one embodiment of the present invention, the load has a forward voltage VF when being driven, and the series-connected transistor and the load are powered by the input voltage Vin; when the PWM duty cycle is less than a set threshold value m, when the input voltage Vin>forward voltage VF, the average value of the current flowing through the transistor Q within half a power frequency cycle is controlled to decrease, and the time for which the transistor Q flows the current decreases as the duty cycle of the adjustment signal decreases; when the PWM duty cycle is greater than the set threshold value m, when the input voltage Vin>forward voltage VF, the transistor Q is controlled to always flow the current, and the average value of the current flowing increases as the PWM duty cycle increases.

[0138] In one embodiment of the present invention, the load has a forward voltage VF when being driven, and the series-connected transistor and the load are powered by the input voltage Vin; when the PWM duty cycle is less than the set threshold m, when the input voltage Vin>forward voltage VF, the transistor Q remains closed during the hold-off time Tz, and after waiting for the hold-off time Tz to end, and when the input voltage Vin>forward voltage VF, the transistor Q begins to flow current, and the conduction time is Ton'. In another embodiment of the present invention, when the input voltage Vin>forward voltage VF, the transistor Q begins to flow current, and after the conduction time Ton', the transistor Q remains closed during the hold-off time Tz, waiting for the next cycle.

[0139] In an embodiment of the present invention, the control method further comprises: controlling at least one LED lamp among the at least two LED lamps to adjust the current of the at least one LED lamp to achieve color adjustment.

[0140] The specific process and implementation of the control method can be found in the above description of the control circuit, which will not be elaborated here.

[0141] In summary, the control circuit, drive circuit, LED lamp system and control method for controlling power transistors proposed in the present invention can improve control accuracy and efficiency. The present invention improves control accuracy when the characteristic value (such as duty cycle) of the adjustment signal (such as PWM signal) is a low value; at the same time, the drive circuit of the present invention has low loss and high efficiency. The present invention is applied to the LED drive solution to improve the dimming accuracy of the LED drive circuit.

[0142] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0143] The description and application of the present invention here are illustrative and are not intended to limit the scope of the present invention to the above-described embodiments. The deformation and changes of the embodiments disclosed here are possible, and the replacement of the embodiments and the various components equivalent to those of ordinary skill in the art are well known. It should be clear to those skilled in the art that the present invention can be realized in other forms, structures, arrangements, proportions, and with other components, materials and parts without departing from the spirit or essential characteristics of the present invention. Other deformations and changes can be made to the embodiments disclosed here without departing from the scope and spirit of the present invention.

Claims

1. A control circuit for controlling a power transistor, wherein the power transistor and a load are connected in series, a first end of the power transistor and the load connected in series is coupled to an input voltage, a second end of the power transistor and the load connected in series is coupled to a ground, and the control circuit provides a driving current for the load by controlling the conduction state of the power transistor, characterized in that: The control circuit receives an adjustment signal. When the duty cycle of the adjustment signal is greater than a first threshold, the control circuit adjusts the current amplitude flowing through the power transistor based on the adjustment signal, so that the current amplitude flowing through the power transistor increases with the increase of the duty cycle; when the duty cycle of the adjustment signal is less than a second threshold, the control circuit adjusts the time for the current to flow through the power transistor based on the adjustment signal, so that the time for the current to flow through the power transistor increases with the increase of the duty cycle; wherein the second threshold is less than or equal to the first threshold.

2. The control circuit according to claim 1, characterized in that: The regulating signal is a pulse width modulation (PWM) signal. When the duty cycle of the regulating signal is greater than a first threshold, the control circuit controls the power transistor to be in an on state during a period when the input voltage is greater than the load driving voltage. When the duty cycle of the adjustment signal is less than the second threshold, the control circuit controls the power transistor to be turned on part of the time and turned off part of the time during a period when the input voltage is greater than the load driving voltage.

3. The control circuit according to claim 1, characterized in that: In the process of adjusting the current amplitude flowing through the power transistor, the control circuit controls the current amplitude flowing through the power transistor to show a downward trend in the first part of the conduction time during each cycle when the power transistor is turned on, and to show an upward trend in the second part of the conduction time.

4. The control circuit according to claim 1, characterized in that: The control circuit comprises: a reference generating unit having an input terminal and an output terminal, wherein the input terminal of the reference generating unit receives the regulating signal, and the output terminal of the reference generating unit provides a current reference signal, and the reference generating unit intermittently sets the current reference signal to a zero value when the duty cycle of the regulating signal is less than a second threshold value, so as to turn off the power transistor, wherein the zero value time of the current reference signal is longer when the duty cycle of the regulating signal is smaller; and The current regulating unit has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the current regulating unit is coupled to the output terminal of the reference generating unit, the second input terminal of the current regulating unit is coupled to a sampling signal representing the current flowing through the power transistor, and the output terminal of the current regulating unit is coupled to the control terminal of the power transistor.

5. The control circuit according to claim 1, characterized in that: include: A first reference generation unit A, an average current control compensation unit, a second reference generation unit B and a current adjustment unit; The input terminal of the first reference generating unit A receives a PWM signal, and the first reference generating unit A outputs a first reference voltage Vref according to the received PWM signal; The output terminal of the second reference generating unit B is coupled to the first input terminal of the current regulating unit, the second input terminal of the current regulating unit is coupled to the sampling voltage Vcs; the output terminal of the current regulating unit is coupled to the control terminal of the power transistor; The average current control compensation unit receives the sampling voltage Vcs and the first reference voltage Vref, and obtains the compensation voltage Vcomp at the output end of the average current control compensation unit through operational amplification processing; The output terminal of the average current control compensation unit is coupled to the second reference generation unit B, and the second reference voltage Vth is obtained by the second reference generation unit B; The current regulating unit receives the sampling voltage Vcs and the second reference voltage Vth, and outputs a control signal to the power transistor through operational amplification processing to control the state of the power transistor.

6. The control circuit according to claim 5, characterized in that: When the duty cycle of the regulation signal PWM is greater than the set threshold m, the on time in a cycle T is Ton; In the first half of the Ton time, the control circuit controls the current flowing through the power transistor to reach the maximum current value Imax and then starts to decrease; In the second half of the Ton time, the control circuit controls the current flowing through the power transistor to start to rise and finally reach the maximum current value Imax; The maximum current value Imax is controlled by the compensation voltage Vcomp; when the PWM duty cycle decreases, the first reference voltage Vref decreases, and Imax controlled by the compensation voltage Vcomp decreases; when the first reference voltage Vref increases, the maximum current value Imax controlled by the compensation voltage Vcomp increases.

7. The control circuit according to claim 5, characterized in that: The average current control compensation unit includes a first error amplifier EA1 , and the current regulation unit includes a second error amplifier EA2 .

8. The control circuit according to claim 7, characterized in that: The average current control compensation unit further includes a capacitor coupled to an output terminal of the first error amplifier EA1 .

9. The control circuit according to claim 5, characterized in that: The load has a forward voltage VF when driven; When the PWM duty cycle is less than the set threshold m, when the input voltage Vin> forward voltage VF, the time for the control transistor Q to flow current decreases as the PWM duty cycle decreases; When the PWM duty cycle is greater than the set threshold m, when the input voltage Vin> the forward voltage VF, the control transistor Q always flows current, and the average value of the flowing current increases with the increase of the PWM duty cycle.

10. The control circuit according to claim 9, characterized in that: The second reference generating unit B includes a first comparator, a second comparator, a multiplier, a second transistor Q2, a third transistor Q3, a current source and a second capacitor; The first comparator compares the input voltage Vin and the forward voltage VF, the output terminal of the first comparator is coupled to the gate of the third transistor Q3, and the source of the third transistor Q3 is grounded; the current source is respectively coupled to the drain of the third transistor Q3, the first terminal of the second capacitor, and the non-inverting input terminal of the second comparator; The compensation voltage Vcomp is respectively coupled to the inverting input terminal of the second comparator, the drain of the second transistor Q2, and the non-inverting input terminal of the multiplier; the inverting input terminal of the multiplier is coupled to the reference voltage V(t); The output terminal of the second comparator is coupled to the gate of the second transistor Q2, and the source of the second transistor Q2 is grounded; The output terminal of the multiplier outputs a second reference voltage Vth.

11. The control circuit according to claim 10, characterized in that: The second reference voltage Vth=k*Vcomp-V(t), wherein V(t)=k'*sin(ωt), the frequency corresponding to ω is positively correlated with the grid frequency, and k and k' are constants, thereby obtaining a saddle-shaped second reference voltage Vth output.

12. The control circuit according to claim 10, characterized in that: When the PWM duty cycle is less than the set threshold m, when the input voltage Vin> forward voltage VF, the third transistor Q3 is turned on, at this time the current source charges the capacitor, the capacitor voltage VA gradually increases, when the capacitor voltage VA is greater than the compensation voltage Vcomp, the second transistor Q2 is turned on, at this time, the second reference voltage Vth is zero, so the transistor Q is turned off.

13. A driving circuit, characterized in that: The driving circuit comprises the control circuit and the power transistor according to any one of claims 1 to 12; the control circuit is coupled to the control terminal of the power transistor.

14. An LED lamp system, characterized in that: The LED lamp system comprises the driving circuit according to claim 13.

15. The LED lamp system according to claim 14, characterized in that: The LED lamp system comprises at least two LED lamps; the at least two LED lamps have LED lamps of different colors; The control circuit is coupled to at least one LED lamp and adjusts the current of at least one LED lamp to achieve color adjustment.

16. A method for controlling a current flowing through a power transistor, wherein the power transistor is connected in series with a load, and the power transistor is used to provide a driving current for the load, characterized in that: The control method includes: when the duty cycle of the adjustment signal is greater than a first threshold, adjusting the current amplitude flowing through the power transistor so that the current amplitude flowing through the power transistor increases with the increase of the duty cycle; when the duty cycle of the adjustment signal is less than a second threshold, adjusting the time for the current to flow through the power transistor so that the time for the current to flow through the power transistor increases with the increase of the duty cycle; wherein the second threshold is less than or equal to the first threshold.

17. The control method according to claim 16, characterized in that: In the process of adjusting the current amplitude flowing through the power transistor, the current amplitude flowing through the power transistor is controlled to show a downward trend in the first part after the power transistor is turned on, and to show an upward trend in the second part of the conduction time.

18. The control method according to claim 16, characterized in that: The control method specifically includes: Obtaining a compensation voltage Vcomp according to the current sampling voltage Vcs and the adjustment signal; Obtaining a second reference voltage Vth according to the compensation voltage Vcomp, wherein when the compensation voltage Vcomp is less than a threshold, the second reference voltage Vth is intermittently set to zero; The sampling voltage Vcs and the second reference voltage Vth are received, and a control signal is output to the power transistor after being processed by operational amplification to control the state of the power transistor.

19. The control method according to claim 16, characterized in that: The load has a forward voltage VF when being driven, and the series-connected transistor and the load are powered by the input voltage Vin. When the duty cycle of the regulation signal is less than the set threshold m, when the input voltage Vin> the forward voltage VF, the average value of the current flowing through the transistor Q in half a power frequency cycle is controlled to decrease, and the time for the current to flow through the transistor Q decreases as the duty cycle of the regulation signal decreases; When the duty cycle of the regulation signal is greater than the set threshold m, when the input voltage Vin> the forward voltage VF, the control transistor Q always flows current, and the average value of the current flowing through the transistor Q increases with the increase of the duty cycle of the regulation signal.

20. The control method according to claim 16, characterized in that: The control method further includes controlling at least one LED lamp of the at least two LED lamps to adjust the current of the at least one LED lamp to achieve color adjustment.

Images