A system for increasing the number of effective display digits

Abstract

The present invention discloses a system for increasing the number of effective display bits, and the display system for increasing the number of effective display bits mainly comprises an address / data receiving and processing module, a row and column drive control logic module, a DAC module, a data latch / drive module, an address decoding module, a pixel unit, a common electrode and a module for increasing the number of effective display bits. The display time within the frame period of the pixel unit is controlled by digital data information, thereby realizing the adjustment of grayscale brightness.

Description

Technical Field

[0001] The invention relates to the technical field of digital pixel driving, and in particular to a novel system for increasing the number of effective display bits. Background Art

[0002] With the continuous development of micro-display products such as AR (augmented reality) and projection products, people have begun to focus on the research of improving the performance of micro-display chips. Micro-display chips are mainly divided into micro-display technology and micro-display driving technology. Good driving technology, especially good pixel driving technology, can improve the display effect of micro-display chips.

[0003] At present, pixel driving methods are mainly divided into analog driving and digital driving. Analog-driven displays use analog signals to represent the grayscale information of pixels, but analog signals are prone to noise and it is difficult to achieve high grayscale value accuracy. Digital driving mainly generates grayscale by modulating pulse width. Since digital signals are stable and reliable and have fast switching speeds, digital driving has higher picture quality, low image noise, high grayscale levels, and can display richer colors. Summary of the invention

[0004] In order to overcome the defects in the prior art, the present invention provides a system for increasing the number of effective display bits, which can adjust the grayscale brightness and avoid inter-frame interference displayed by a display device.

[0005] The present invention provides a system for increasing the number of effective display digits, and the content of the invention is as follows:

[0006] The novel digital pixel driving system mainly includes an address / data receiving and processing module, a row and column driving control logic module, a DAC module, a data latch / driving module, an address decoding module, a pixel unit, a common electrode and a module for increasing the number of effective display bits.

[0007] The address / data receiving and processing module extracts and processes the received address and data signals, extracts the address signal and transmits it to the row and column drive control logic module, and extracts the data signal and transmits it to the data latch / drive module;

[0008] The row and column drive control logic module receives the address signal transmitted by the address / data receiving and processing module, encodes the address signal, and generates the corresponding row data control signal, common electrode signal and in-phase / inverted phase selection signal according to the address signal, and sends the row data control signal to the data latch / drive module; sends the address signal to the address decoding module; sends the common electrode signal to the common electrode; and sends the in-phase / inverted phase selection signal to the pixel unit;

[0009] The data latch / drive module latches and sends the data to the pixel unit according to the received row data control signal;

[0010] The DAC module converts the digital signal into a voltage value and transmits it to the pixel unit to realize the display brightness control of the pixel unit;

[0011] The module for increasing the number of effective display bits generates additional data bits based on the received data and sends them to the data latch / driver module.

[0012] Furthermore, the module for increasing the number of effective display bits generates additional data bits in addition to 8 bits of normal pixel data, which are used to compensate for the threshold voltage of the display device in the digital display mode and avoid inter-frame interference displayed by the display device.

[0013] Furthermore, each bit of the normal 8-bit pixel data and the additional data bits generated by the module for increasing the number of effective display bits is divided into multiple bits or displayed continuously at any display time of the same frame according to needs, and the timing of the bits is fixed or random, or different frames use different timings.

[0014] Furthermore, the address / data receiving and processing module can receive data transmitted from interfaces such as the mipi interface and the lvds interface, and the data signal mainly includes a row address and data of the corresponding row.

[0015] One receiving end of the address / data receiving and processing module is connected to the high-speed interface, and receives the address and data signals transmitted from the high-speed interface. The address / data receiving and processing module extracts and processes the received address and data signals, extracts the address signal and transmits it to the row and column drive control logic module, and extracts the data signal and transmits it to the data latch / drive module.

[0016] The row and column drive control logic module receives the address signal transmitted by the address / data receiving and processing module, and sends the row data control signal to the data latch / driving module; and sends the control signal to the address decoding module, the common electrode and the pixel unit.

[0017] All row pixels in the pixel unit share one DAC module, or several row pixels share one DAC module, or each row pixel uses a separate DAC module.

[0018] The DAC (digital-to-analog converter) module can convert digital signals into voltage values ​​and transmit them to pixels, and can control the numerical value of the voltage value, thereby controlling the brightness of the display screen.

[0019] The data latch / drive module receives the control signal sent by the row and column drive control logic module, and latches and sends the data to the pixel according to the control signal. The data can be sent to the pixel row by row or in combination of several rows.

[0020] The address decoding module is composed of a number of input AND gates. Each row selects a corresponding address connection mode and connects to the address bus. The address is driven to the address bus after being encoded.

[0021] The pixel unit includes a storage unit, a logic operation unit, a driving unit, and a display unit. The storage unit receives address signals and data signals, has a storage function, and sends the signals to the logic operation unit. The logic operation unit receives the same-phase and opposite-phase control commands to process the signals sent from the storage unit and send them to the driving unit. The driving unit processes the received driving unit data signal and DAC (digital-to-analog converter) module voltage signal and sends them to the display unit. The display unit displays the corresponding image according to the received image data signal.

[0022] The common electrode is a common terminal electrode to which one end of all pixels is connected. One end of each pixel is connected to the common electrode, and the other end is independently connected to a pixel driving circuit.

[0023] The module for increasing the number of effective display bits generates the required additional data bits according to the input 8-bit pixel data, sends them to the storage unit or the driving unit, and sends them to the corresponding pixel display according to the address selection, so as to achieve the effect of increasing the effective display bits.

[0024] The beneficial effects achieved by the present invention are:

[0025] The present invention adjusts digital data information by increasing the module of effective display bit number to control the length of display time within the frame period of the pixel unit, thereby realizing the adjustment of grayscale brightness and avoiding inter-frame interference displayed by the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a system framework diagram of a first embodiment of a novel digital pixel driving method of the present invention.

[0027] Figure 2 This is a structural diagram of an address decoding module according to the first embodiment of the present invention.

[0028] Figure 3 This is a structural diagram of a pixel unit according to the first embodiment of the present invention.

[0029] Figure 4 FIG. 4 is a structural diagram of a storage unit in a pixel unit according to the first embodiment of the present invention.

[0030] Figure 5 FIG. 4 is a structural diagram of a logic operation unit in a pixel unit according to the first embodiment of the present invention.

[0031] Figure 6 FIG. 4 is a structural diagram of a driving unit in a pixel unit according to the first embodiment of the present invention.

[0032] Figure 7FIG. 4 is a structural diagram of an LCOS display unit in a pixel unit according to the first embodiment of the present invention.

[0033] Figure 8A-8E This is a data display time allocation diagram for increasing the number of effective display bits according to the first embodiment of the present invention.

[0034] Fig. 9 This is a system framework diagram of a second embodiment of a novel digital pixel driving method of the present invention.

[0035] Fig.10 This is a structural diagram of an address decoding module according to the second embodiment of the present invention.

[0036] Fig.11 This is a structural diagram of a pixel unit according to the second embodiment of the present invention.

[0037] Fig.12 FIG. 4 is a structural diagram of a storage unit in a pixel unit according to a second embodiment of the present invention.

[0038] Fig.13 FIG. 4 is a structural diagram of a logic operation unit in a pixel unit according to a second embodiment of the present invention.

[0039] Fig.14 FIG. 4 is a structural diagram of a driving unit in a pixel unit according to a second embodiment of the present invention.

[0040] Fig.15 This is a structural diagram of an OLED display unit in a pixel unit according to the second embodiment of the present invention.

[0041] Figure 16A-16E This is a data display time allocation diagram for increasing the number of effective display bits according to the second embodiment of the present invention.

[0042] Among them: 11, address / data receiving processing module, 12, row and column driving control logic module, 13, DAC module, 14, data latch / driving module, 15, address decoding module, 16, pixel unit, 17, common electrode, 18, storage unit, 19, compilation unit, 20, module for increasing the number of effective display bits, 110, driving unit, 111, LCOS display unit, 1121, 1124, 1125, 1126, 1133, 1134, 1142 are N-type MOS tubes, 1122, 1123, 1131, 1132, 1141 are P-type MOS tubes, 1151, Transparent electrode liquid crystal, 1152, liquid crystal, 1153, metal reflective layer, 1154, silicon substrate, 310, normal pixel data display time, 320, increase effective display bit display time, 311, 312, 313, 314, segmented normal pixel data display time, 321, 322, 323, 324, segmented increase effective display bit display time;

[0043] 21. Address / data receiving processing module, 22. Row and column drive control logic module, 23. DAC (digital-to-analog converter) module, 24. Data latch / drive module, 25. Address decoding module, 26. Pixel unit, 27. Common electrode, 28. Storage unit, 29. Computation unit, 30. Module for increasing the number of effective display bits, 210. Drive unit, 211. LCOS display unit, 2121, 2124, 2125, 2126, 2133, 2134, 2142 are N-type MOS tubes, 2122, 2123, 2131, 2132, 2141 are P-type MOS tubes, 2156. Silicon substrate, 2155. Metal reflective layer, 2154. White light OLED light-emitting layer, 2153. RGB color filter film, 2152. Semi-transparent cathode, 2151. Transparent glass, 410. Normal pixel data display time, 420, increase the display time of the effective display position, 411, 412, 413, 414, segmented normal pixel data display time, 421, 422, 423, 424, segmented increase of the display time of the effective display position. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present invention will be clearly and completely described below in combination with the embodiments of the present invention and the drawings in the specification. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0045] In order to explain this patent in detail, a specific embodiment is described below. Embodiment 1

[0046] The first embodiment is a micro display chip based on LCOS (liquid crystal on silicon) digital pixel drive, the pixel resolution is 1920*1080, and the color display mode is sequential color.

[0047] like Figure 1 As shown, the micro display chip system based on LCOS digital pixel drive mainly includes an address / data receiving and processing module 11, a row and column drive control logic module 12, a DAC module 13, a data latch / drive module 14, an address decoding module 15, a pixel unit 16, a common electrode 17 and a module 20 for increasing the number of effective display bits.

[0048] The high-speed interface can adopt a MIPI interface or an LVDS interface, etc., and each time the row address and the corresponding row data are sent. The address / data receiving processing module 11 receives one end connected to the high-speed interface, receives the address and data signals transmitted from the high-speed interface, and extracts and processes the received address and data signals, extracts the address signal and transmits it to the row and column drive control logic module 12, and extracts the data signal and transmits it to the data latch / drive module 14.

[0049] The row and column drive control logic module 12 receives the address signal transmitted from the address / data receiving and processing module 11, encodes the address signal, and generates the corresponding row data control signal, common electrode signal and in-phase / inverted phase selection signal according to the address signal. The row data control signal is sent to the data latch / drive module 14; the address signal is sent to the address decoding module 15; the common electrode signal is transmitted to the common electrode 17; and the in-phase / inverted phase selection signal is sent to the pixel unit 16. This is because the voltages at both ends of the liquid crystal must always be in an exchanged state, otherwise its characteristics will change.

[0050] The data latch / drive module 14 receives the row data control signal sent by the row and column drive control logic module 12, and latches and sends the data to the pixel unit 16 according to the row data control signal. In this embodiment, 60 columns of data are used, and a total of 32 data lines are used to complete the transmission. The data of the present invention can be sent to the pixel unit row by row, or several rows can be sent together.

[0051] The common electrode 17 is a common terminal electrode connected to one end of all pixel units 16. The common electrode 17 is a semi-transparent conductive electrode, and can be made of ITO, semi-transparent metal element, semi-transparent metal compound or other semi-transparent conductive materials.

[0052] like Figure 2 The address decoding module 15 is shown. The address and the inverted signal of the address form the address bus. For a resolution of 1920*1080, a total of 1080 address decoding modules 15 are required. Each address decoding module 15 is an 11-bit address data, and the address bus has a total of 22 bits. The address decoding module 15 is composed of 6-way input AND gates, and each row selects the corresponding address connection mode to connect to the address bus. The address is driven to the address bus after encoding. For 1080 address bits, four input options are required for each of the lower five bits, and two input options for the highest bit. A total of 22-bit address buses are required to realize the encoding of all 1080 address bits.

[0053] like Figure 3The structure of the pixel unit 16 is shown in FIG. 1 , and the pixel unit 16 includes a storage unit 18, a logic operation unit 19, a driving unit 110, and an LCOS display unit 111. The storage unit 18 receives address signals and data signals, has a storage function, and sends the signals to the logic operation unit 19. The logic operation unit 19 receives the same-phase and opposite-phase control commands to process the signals sent by the storage unit 18, and sends them to the driving unit 110. The driving unit 110 processes the received data signals and the voltage signals of the DAC module 13, and sends them to the LCOS display unit 111. The LCOS display unit 111 displays the corresponding image according to the received image data signal.

[0054] like Figure 4 The structure diagram of the storage unit 18 is shown, wherein 1121, 1124, 1125, 1126 are N-type MOS tubes, 1122, 1123 are P-type MOS tubes, and the specific process of the storage unit 18 realizing the storage function is that when the address signal ADDR sent by the address decoding module 15 is high, 1121 and 1124 are turned on, and the data signals Data 1 and Data 2 enter the storage devices 1122, 1123, 1125, 1126 through 1121 and 1124 respectively. Data 1 and Data 2 are always opposite, and when the data signal enters the storage device, ADDR becomes a low level, 1121 and 1124 are disconnected, and at this time, the storage unit composed of the inverter composed of 1122, 1125 and the inverter composed of 1123, 1126 will store Data 1 and Data 2 in the storage unit without losing them, and at the same time output the output signal 1 and output signal 2 of the storage unit 18 as the input signal 1 and input signal 2 of the logic operation unit 19.

[0055] like Figure 5The structure diagram of the logic operation unit 19 is shown, in which 1133 and 1134 are N-type MOS tubes, 1131 and 1132 are P-type MOS tubes, and the input signal 1 and the input signal 2 are always opposite signals. When the same-phase opposite phase selection signal is high, the input signal 1 is high, and the input signal 2 is low, the inverter composed of 1131 and 1133 works normally, the switch composed of 1132 and 1134 is disconnected, and the output signal is low level. When the same-phase opposite phase selection signal is high, the input signal 1 is low, and the input signal 2 is high, the inverter composed of 1131 and 1133 does not work, the switch composed of 1132 and 1134 is turned on, and the output signal is high level. When the same-phase opposite phase selection signal is low, the input signal 1 is high, and the input signal 2 is low, the inverter composed of 1131 and 1133 works normally, the switch composed of 1132 and 1134 is disconnected, and the output signal is high level. When the inverse phase selection signal is low, the input signal 1 is low, and the input signal 2 is high, the inverters composed of 1131 and 1133 do not work, the switches composed of 1132 and 1134 are turned on, and the output signal is low. The output signal of the logic operation unit 19 is used as the input signal of the driving unit 110.

[0056] like Figure 6 The structure diagram of the driving unit 110 is shown, wherein 1141 is a P-type MOS tube, 1142 is an N-type MOS tube, and 1141 and 1142 form an inverter driving unit. When the input signal of the driving unit 110 is at a high level, the output signal is at a low level after reverse processing by the driving unit 110. The analog voltage values ​​of the high and low levels are determined by the signals Vhigh and Vlow output by the DAC module 13. When the Vhigh output by the DAC module 13 is closer to the circuit high voltage and the Vlow is closer to the circuit low voltage, the brightness displayed by the LCOS display unit 111 is higher; on the contrary, the brightness displayed by the LCOS display unit 111 is lower. The DAC module 13 can set and adjust the brightness of the LCOS display unit 111 according to the brightness of the actual display environment.

[0057] like Figure 7The structure of the LCOS display unit 111 is shown, which includes a silicon substrate 1154, a metal reflective layer 1153 is provided on the silicon substrate 1154, a liquid crystal 1152 is provided on the metal reflective layer 1153, and a transparent electrode 1151 is provided on the liquid crystal 1152. The types of liquid crystal 1152 include parallel-oriented liquid crystal and vertical-oriented liquid crystal. In this embodiment, vertical-oriented liquid crystal is used. One end of the liquid crystal 1152 is connected to the metal reflective layer 1153, and the other end is connected to the silicon substrate 1154 through the metal reflective layer 1153. Under the drive of the driving unit 110, the external light enters the liquid crystal 1152 through the transparent electrode 1151, and is reflected back through the metal reflective layer 1153, the liquid crystal 1152 and the transparent electrode 1151, thereby realizing the display of the image.

[0058] The module 20 for increasing the number of effective display bits can generate additional data bits in addition to the 8-bit normal pixel data to increase the number of effective display bits, compensate for the threshold voltage of liquid crystal in the digital display mode, and avoid inter-frame interference.

[0059] Each bit of the normal 8-bit pixel data and the additional data bits generated by the module 20 for increasing the number of effective display bits can be divided into multiple bits or displayed continuously at any display time of the same frame as required. The timing of the bits can be random, and different frames can use different timings.

[0060] like Figure 8A-8E The figure shows the display time allocation after the LCOS display chip increases the effective display bits, including normal pixel data bit display time 310, increased effective display bit display time 320, normal pixel data bit display time 311 and 312, increased effective display bit display time 321 and 322. The increased effective display bits and normal pixel data bit display time can be matched at will. Fig. 8A As shown, the normal pixel data is first displayed as 310, and then the increased effective display data bit 320 is displayed; it can also be as Figure 8B As shown, the increased effective display data bit 320 is displayed first, and then the normal pixel data is displayed as 310; it can also be as shown in FIG. Figure 8C As shown, the normal pixel data is segmented and displayed as 311 and 312, and the added valid display data bits are inserted in the middle and displayed as 320; Fig.8D As shown, the normal pixel data is segmented into 311 and 312, the added valid display data bits are segmented into 321 and 322, and then their display order is combined arbitrarily; even as shown in FIG. Fig. 8E As shown, the normal pixel data 311, 312, 313, 314 are divided into any number of segments, and the added effective display data bits 321, 322, 323, 324 are divided into any number of segments, and then combined for display. Embodiment 2

[0061] The second embodiment is a micro display chip based on OLED digital pixel drive, the pixel resolution is 1280*540*RGB, and the arrangement of R, G, B sub-pixels is a herringbone arrangement.

[0062] like Fig. 9 As shown, the micro display chip system based on OLED digital pixel drive mainly includes an address / data receiving and processing module 21, a row and column drive control logic module 22, a DAC module 23, a data latch / drive module 24, an address decoding module 25, a pixel unit 26, a common electrode 27 and a module 28 for increasing the number of effective display bits.

[0063] The high-speed interface can adopt a MIPI interface or an LVDS interface, etc., and each time the row address and the corresponding row data are sent. The address / data receiving processing module 21 receives one end connected to the high-speed interface, receives the address and data signals transmitted from the high-speed interface, and extracts and processes the received address and data signals, extracts the address signal and transmits it to the row and column drive control logic module 22, and extracts the data signal and transmits it to the data latch / drive module 24.

[0064] The row and column drive control logic module 22 receives the address signal transmitted from the address / data receiving and processing module 21 , and sends the row data control signal to the data latch / driving module 24 ; sends the address signal to the address decoding module 25 ; and transmits the common electrode to the common electrode 27 .

[0065] The data latch / drive module 24 receives the control signal sent by the row and column drive control logic module 22, and latches and sends the data to the pixel according to the control signal. In this embodiment, 60 columns of data are used, and a total of 96 data lines are used to complete the transmission. The data of the present invention can be sent to the pixel row by row, or several rows can be sent together.

[0066] like Fig.10 The address decoding module 25 is shown. For an OLED display screen with a pixel resolution of 1280*540*RGB, since the arrangement of the R, G, and B sub-pixels is in a herringbone arrangement, the pixel driving data of the display screen is still 1920*1080, and a total of 1080 address decoding modules 15, 11-bit address data, and a total of 22 bits of address bus are required. The address decoding module 15 is composed of 11-input AND gates, and each row selects the corresponding address connection mode to connect to the address bus. The address is driven to the address bus after encoding. The address decoding module 15 is composed of 6-input AND gates. For 1080 address bits, four input selections are required for each of the lower five bits, and two input selections for the highest bit. A total of 22-bit address bus is required to realize the encoding of all 1080 address bits.

[0067] The common electrode 27 is a common terminal electrode connected to one end of all pixel units 26. The common electrode 27 is a semi-transparent conductive electrode, and can be made of ITO, semi-transparent metal element, semi-transparent metal compound or other semi-transparent conductive materials.

[0068] like Fig.11 The structure of the pixel unit 26 is shown in FIG. 2 , and the pixel unit 26 includes a storage unit 28, a logic operation unit 29, a driving unit 210, and an OLED display unit 211. The storage unit 28 receives address signals and data signals, has a storage function, and sends the signals to the logic operation unit 29. The logic operation unit 29 receives the same-phase and opposite-phase control commands to process the signals sent by the storage unit 28, and sends them to the driving unit 210. The driving unit 210 processes the received data signals of the driving unit 210 and the voltage signals of the DAC module 23, and sends them to the OLED display unit 211. The OLED display unit 211 displays the corresponding image according to the received image data signals.

[0069] like Fig.12 The structure diagram of the storage unit 28 is shown, wherein 2121, 2124, 2125, 2126 are N-type MOS tubes, 2122, 2123 are P-type MOS tubes, and the specific process of the storage unit 28 realizing the storage function is that when the address signal ADDR is high, 2121 and 2124 are turned on, and the data signals Data 1 and Data 2 enter the storage devices 2122, 2123, 2125, 2126 through 2121 and 2124 respectively. Data 1 and Data 2 are always opposite, and when the data signal enters the storage device, ADDR becomes a low level, 2121 and 2124 are disconnected, and at this time, the storage unit composed of the inverter composed of 2122, 2125 and the inverter composed of 2123, 2126 will store Data 1 and Data 2 in the storage unit without loss.

[0070] like Fig.13 The structure diagram of the logic operation unit 29 is shown, in which 2133 and 2134 are N-type MOS tubes, 2131 and 2132 are P-type MOS tubes, and the input signal 1 and the input signal 2 are always opposite signals. Because the control signal is always connected to the high voltage of the circuit, when the input signal 1 is high and the input signal 2 is low, the inverter composed of 2131 and 2133 works normally, the switch composed of 2132 and 2134 is disconnected, and the output signal is low level; when the input signal 1 is low and the input signal 2 is high, the inverter composed of 2131 and 2133 does not work, the switch composed of 2132 and 2134 is turned on, and the output signal is high level.

[0071] like Fig.14The structure diagram of the driving unit 210 is shown, in which 2141 is a P-type MOS tube, 2142 is an N-type MOS tube, and 2141 and 2142 form an inverter driving unit. When the input signal of the driving unit 210 is high, the output signal is low after the driving unit 210 performs reverse processing. The magnitude of the analog voltage values ​​of the high and low levels is determined by Vhigh and Vlow output by the DAC module 23. When the Vhigh output by the DAC module 23 is closer to the circuit high voltage, and the Vlow is closer to the circuit high voltage, the brightness displayed by the LCOS display unit 211 is higher; on the contrary, the brightness displayed by the LCOS display unit 211 is lower. The DAC module 23 can set and adjust the brightness of the OLED display unit 211 according to the brightness of the actual display environment.

[0072] like Fig.15 The structure of the OLED display unit 211 is shown, which includes a silicon substrate 2156, a metal reflective layer 2155 is provided on the silicon substrate 2156, a white light OLED light emitting layer 2154 is provided on the metal reflective layer 2155, a color filter film 2153 is provided on the white light OLED light emitting layer 2154, a semi-transparent cathode 2152 is provided on the color filter film 2153, and a transparent glass 2151 is provided on the semi-transparent cathode 2152. The white light OLED light emitting layer 2154 emits white light when driven by electrodes at both ends, and the white light is converted into RGB colors through the color filter film 2153. The OLED display unit 211 displays the corresponding image according to the image data signal sent by the driving unit 210.

[0073] like Figures 16A-16E The figure shows the display time allocation after the LCOS display chip increases the effective display bits, including normal pixel data bit display time 410, increased effective display bit display time 420, normal pixel data bit display time 411 and 412, and increased effective display bit display time 421 and 422. The increased effective display bits and normal pixel data bit display times can be freely matched. Fig.16A As shown, the normal pixel data is first displayed as 410, and then the increased effective display data bit 420 is displayed; it can also be as Fig. 16B As shown, the increased effective display data bit 420 is displayed first, and then the normal pixel data is displayed as 410; it can also be as shown in FIG. Figure 8C As shown, the normal pixel data is segmented and displayed as 411 and 412, and the added valid display data bits are inserted in the middle and displayed as 420; Fig.16D As shown, the normal pixel data is segmented into 411 and 412, the added valid display data bits are segmented into 421 and 422, and then their display order is combined arbitrarily; even as shown in FIG. Fig.16EAs shown, the normal pixel data bit display time 411, 412, 413, 414 is divided into any number of segments, and the added effective display data bit display time 421, 422, 423, 424 is divided into any number of segments, and then combined for display.

[0074] The above two embodiments are only parts of the present invention.

[0075] The above is a detailed introduction to the research on a new method for increasing the number of effective display bits provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A system for increasing the number of effective display digits, characterized in that: It includes an address / data receiving and processing module, a row and column driving control logic module, a DAC module, a data latch / driving module, an address decoding module, a pixel unit, a common electrode and a module for increasing the number of effective display bits; The address / data receiving and processing module extracts and processes the received address and data signals, extracts the address signal and transmits it to the row and column drive control logic module, and extracts the data signal and transmits it to the data latch / drive module; The row and column drive control logic module receives the address signal transmitted by the address / data receiving and processing module, encodes the address signal, and generates the corresponding row data control signal, common electrode signal and in-phase / inverted phase selection signal according to the address signal, and sends the row data control signal to the data latch / drive module; and sends the address signal to the address decoding module; Sending a common electrode signal to a common electrode; sending an in-phase / inverse phase selection signal to a pixel unit; The data latch / drive module latches and sends the data to the pixel unit according to the received row data control signal; The DAC module converts the digital signal into a voltage value and transmits it to the pixel unit to realize the display brightness control of the pixel unit; The module for increasing the number of effective display bits generates additional data bits according to the received data and sends them to the data latch / drive module; the module for increasing the number of effective display bits generates additional data bits in addition to the 8-bit normal pixel data to compensate for the threshold voltage of the display device in the digital display mode; The common electrode is a common terminal electrode connected to one end of all pixel units; the common electrode is a translucent conductive electrode, including ITO, a translucent metal element, a translucent metal compound or a translucent conductive material.

2. The system for increasing the number of effective display digits as claimed in claim 1, characterized in that: Each bit of normal pixel data and the additional data bits generated by the module for increasing the number of effective display bits is divided into multiple bits according to needs or displayed continuously at any display time of the same frame. The timing of the bits is fixed or random, or different frames use different timings.

3. The system for increasing the number of effective display digits as claimed in claim 1, characterized in that: The address / data receiving and processing module receives the data signal transmitted by the mipi interface or the lvds interface. The data signal mainly includes the row address and the data of the corresponding row.

4. The system for increasing the number of effective display digits as claimed in claim 1, characterized in that: The row and column drive control logic module receives the address signal transmitted by the address / data receiving and processing module, and sends the row data control signal to the data latch / drive module; and sends the control signal to the address decoding module, the common electrode and the pixel unit.

5. The system for increasing the number of effective display digits as claimed in claim 1, characterized in that: All rows of pixels in the pixel unit share one DAC module, or several rows of pixels share one DAC module, or each row of pixels uses a separate DAC module.

6. The system for increasing the number of effective display digits as claimed in claim 1, characterized in that: When the data latch / drive module latches and sends the data to the pixel unit, the data is sent row by row or in combination of several rows.

7. The system for increasing the number of effective display digits as claimed in claim 1, characterized in that: The address decoding module is composed of a number of AND gates, each of which generates a pixel write signal for a row; the address is driven to the address bus after being encoded, and the AND gate of each row selects the corresponding address connection mode to connect to the address bus.

8. The system for increasing the number of effective display digits as claimed in claim 1, characterized in that: The pixel unit includes a storage unit, a logic operation unit, a driving unit and a display unit; the storage unit receives and stores address signals and data signals, and sends the signals to the logic operation unit; the logic operation unit receives a frame-by-frame inverted in-phase / inverted-phase control command or a fixed single-phase control command, processes the signal sent from the storage unit, and then sends it to the driving unit; the display unit displays the corresponding image according to the image data signal sent by the driving unit.

Images