Systems, circuits and methods for detecting

Abstract

A system, circuit and method for detection are disclosed. The system includes: a control circuit having a first detector and a second detector coupled to a first node of the control circuit, a first filter and a second filter coupled to the first detector and the second detector, and a logic circuit coupled to the first filter and the second filter; a diode circuit having a first node coupled to the first node of the control circuit; and a switch having a first current node coupled to the second node of the diode circuit, a gate coupled to the second node of the control circuit, and a second current node coupled to a third node of the control circuit, wherein the first detector is used to provide a first event overcurrent signal, and the second detector is used to provide a multi-event overcurrent signal or a warning signal.

Description

Technical Field

[0001] The present invention generally relates to systems and methods for providing a configurable integrated DESAT (de-saturation region) filter for an IGBT or MOSFET. Background Art

[0002] Semiconductor switches such as IGBTs or MOSFETs must be protected against overload conditions due to, for example, overcurrent conditions, otherwise overheating and subsequent damage to the switch may occur.

[0003] Figure 1A is a graph of typical output characteristics of an IGBT at 25°C, where the collector current (I C ) relative to the collector-emitter voltage (V CE Curve 102A defines a first operating region 106 in which the switch exhibits a bulk resistor voltage drop and a second operating region 108 designated as a desaturation region.

[0004] Figure 1B is a graph of typical output characteristics of an IGBT at 175°C, where the collector current (I C ) relative to the collector-emitter voltage (V CE Curve 102B defines a first operating region 106 in which the switch exhibits a bulk resistor voltage drop and a second operating region 108 designated as a desaturation region.

[0005] IGBT as the collector-emitter voltage V CE As the current increases, V CE The voltage increases according to the body resistance multiplied by the collector current. If the collector current increases further, the IGBT desaturates and V CE increases until the current is limited or until V CE The supply voltage (DC link voltage) is reached.

[0006] The MOSFET has a voltage drop across the on-resistance as the drain-source voltage V DS As current increases, the MOSFET saturates until the current is limited or until V DS The supply voltage (DC link voltage) is reached. For simplicity, the following description uses the wording and model of IGBT, but the principles are equally applicable to MOSFET. V CE The voltage is measured via the high voltage blocking element in the IGBT on-state. In the IGBT blocking state, the high voltage blocking element decouples the sense input from the high IGBT blocking voltage. Therefore, the voltage V CEDirectly measure within a voltage range of about 6 volts to 9 volts. Higher voltages are only detected as "high" and may cause desaturation events. DESAT events are the main faults of applications, which usually require time-consuming restarts. Therefore, false detection and erroneous "no detection" of DESAT events should be prevented, which may cause the destruction of the switch. In addition, the driver is often placed in a noisy environment. This results in the need to filter the DESAT input to resist noise, spikes and other interferences. This in turn leads to restrictions on how fast DESAT detection can occur. Due to this limitation in speed, repeated short circuits of shorter duration on pulses cannot be detected. If this situation continues for many consecutive pulses, it may lead to a continuous increase in switch temperature and eventually damage. Summary of the invention

[0007] According to an embodiment of the present invention, a system includes: a control circuit having a plurality of detectors coupled to a first node of the control circuit, a plurality of filters coupled to the plurality of detectors, and a logic circuit coupled to the first filter and the second filter; a diode circuit having a first node coupled to the first node of the control circuit; and a switch having a first current node coupled to the second node of the diode circuit, a gate coupled to the second node of the control circuit, and a second current node coupled to a third node of the control circuit, wherein a first detector of the plurality of detectors is configured to provide a first event overcurrent signal, and at least a second detector of the plurality of detectors is configured to provide a multi-event overcurrent signal or a warning signal. The first detector has a first detection threshold, and the second detector has a second detection threshold equal to or different from the first detection threshold. The first filter has a first time constant, and the second filter has a second time constant equal to or different from the first time constant. A clamp transistor is coupled between the first node and the third node of the control circuit. The diode circuit includes a resistor and a diode coupled in series. The second detector can be configured to provide a tolerance test of a performance standard of the first detector. The first detector and the second detector can be configured to provide an overcurrent signal or a warning signal during a two-stage shutdown platform operating mode of the system.

[0008] According to another embodiment of the present invention, a circuit includes: a plurality of detectors coupled to a first node, wherein a first detector of the plurality of detectors has a first programmable detection threshold and a second detector of the plurality of detectors has a second programmable detection threshold equal to or different from the first detection threshold; a plurality of filters coupled to the plurality of detectors, wherein a first filter of the plurality of filters has a first programmable time constant and a second filter of the plurality of filters has a second programmable time constant equal to or different from the first time constant; and a logic circuit having an input coupled to the plurality of filters and an output coupled to a second node, the second node being coupled to a switch, wherein a first detector of the plurality of detectors is configured to provide a first event overcurrent signal and at least a second detector of the plurality of detectors is configured to provide a multi-event overcurrent signal or a warning signal. At least one of the first detector and the second detector includes a comparator or an ADC coupled to a DAC. The first filter and the second filter may include different filter types.

[0009] According to another embodiment of the present invention, a method includes: using a first threshold to detect an input signal to generate a first detection signal; using a second threshold to detect the input signal to generate a second detection signal; using a first time constant to filter the first detection signal to generate a first filtered signal; using a second time constant to filter the second detection signal to generate a second filtered signal; using the first filtered signal to generate a first event overcurrent signal; and using at least the second filtered signal to generate a multi-event overcurrent signal or a warning signal. The method also includes using the overcurrent signal to control the operating mode of the switch. The method also includes counting multiple overcurrent events associated with the input signal before generating the multi-event overcurrent signal or the warning signal. Filtering the first detection signal includes filtering the first detection signal using a first filtering method, and filtering the second detection signal includes filtering the second detection signal using a second filtering method. The method is performed in a switch system and includes counting multiple overcurrent events associated with the input signal to implement a tolerance test of at least one performance standard of the switch system. The multi-event overcurrent signal or the warning signal can be generated during the two-stage shutdown platform operating mode of the switch system. The method may further include: detecting the input signal using multiple thresholds to generate multiple detection signals; and filtering the multiple detection signals using multiple time constants to generate multiple filtered signals. At least one of the first threshold, the second threshold, the first time constant, and the second time constant is programmable.

[0010] The use of at least one additional DESAT detector according to an embodiment of the present invention allows for additional operating modes for controlling a switch during one or more overcurrent events. As with other parallel DESAT detectors, additional DESAT detectors with lower detection thresholds and filter times can be used as tolerance indicators for evaluating system performance rather than protection elements. The use of additional DESAT detectors can also be used to detect shorter short circuit events, and the number of shorter short circuit events detected within a number of PWM cycles can be counted to determine whether the turn-on operation of the drive switch should be prevented. The use of additional DESAT detectors can be used during a two-stage shutdown platform to generate an overcurrent signal or a warning signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1A and Figure 1B is a graph of typical output characteristics of an IGBT switch at a first operating temperature and a second operating temperature;

[0013] Figures 2 to 4 is a circuit diagram of a DESAT detection and filtering implementation for an IGBT switch suitable for an embodiment of a configurable integrated desaturation filter of the present invention;

[0014] Figure 5A and Figure 5B is a circuit diagram of DESAT detection and filtering implementation for an IGBT switch according to an embodiment of the present invention;

[0015] Figure 6 is a flow chart of a first DESAT detection and filtering method according to an embodiment of the present invention;

[0016] Figure 7 is a timing diagram associated with the DESAT detection and filtering implementation of FIG. 5 according to an embodiment of the present invention;

[0017] Figure 8 is a flow chart of a second DESAT detection and filtering method according to an embodiment of the present invention; and

[0018] Fig. 9 is a graph of output characteristics of an IGBT switch according to an embodiment of the present invention, the graph showing a four-fold reduction in desaturation current. DETAILED DESCRIPTION

[0019] Several different types of DESAT detection and filtering circuits and implementations suitable for use with embodiments of the configurable integrated desaturation filter of the present invention are described below.

[0020] Figure 2 and Figure 3 The circuit uses a high voltage diode as a blocking element. The VCE voltage is measured in the IGBT conducting state (on-state) via a high voltage blocking diode biased by a current. Therefore, the voltage VCE plus the forward voltage of the diode is measured in the voltage range. The threshold voltage for detection is about 6 volts to 9 volts for an IGBT switch and about 2 volts to 9 volts for a MOSFET switch. A higher voltage is an indication of a desaturation event. A comparator detects this condition and reports the event. In the off-state, the high voltage blocking diode decouples the sense input from the high IGBT blocking voltage at the collector.

[0021] The filtering of the DESAT input can be achieved with a small capacitor. The time constant of the filtering determines the time it takes to charge the capacitor at the DESAT pin to the comparator voltage trigger level (defined herein as the "filtering time"). Therefore, the filtering time is affected by changes in the current used to charge the capacitor, changes in the capacitor value, changes in the comparator trip level, and the pre-charge voltage level that the capacitor has at the point in time when the switch short circuit occurs. The pre-charge voltage level depends on the load of the switch and whether the current through the switch (or diode for IGBT) is positive or negative.

[0022] The charging current can be implemented as a simple pull-up resistor (see Figure 2 ), which results in a flat charging curve at the detection threshold due to the RC filtering properties. Therefore, this solution has high sensitivity to noise around the trip point and high sensitivity to filter time variations due to comparator detection level variations. Although low spreading resistors are not expensive, the charging current and filter time are sensitive to supply voltage variations. However, the losses associated with the charging current are dissipated in the resistor.

[0023] Figure 2 A control circuit 202 including a VCC2 pin, a DESAT pin, an OUT pin, and a GND2 pin is shown. The control circuit also includes a comparator 204 for monitoring the voltage on the DESAT pin, and a clamp transistor 206 coupled between the DESAT pin and the GND2 pin, the clamp transistor 206 for clamping the DESAT pin to the GND2 pin voltage. When the switch 208 is turned on, the clamp transistor 206 can be released at the same time or at a determined time after the switch 208 is turned on. When the switch 208 is turned off, the clamp transistor 206 is activated at the same time as the turn-off command. The command signal for turning off the switch 208 appears at the same time as the activation command for the clamp transistor 206. In some embodiments, the turning off of the switch 208 is artificially delayed. Figure 2 Also included is a filter capacitor C coupled between the VCC2 pin and the GND2 pinVCC2 , a gate resistor R coupled between the OUT pin and the gate 214 of the IGBT 208 G The IGBT 208 is also coupled to a recycling diode 210 at a collector node 212 and an emitter node 216. The pull-up resistor R PULLUP Coupled between VCC2 pin and DESAT pin. DESAT resistor R DESAT and DESAT diode D DESAT is coupled between the DESAT pin and the collector 212 of the IGBT 208 .

[0024] The charging current can also be implemented as an integrated current source (see Figure 3 ). The filtering time constant depends on the accuracy of the current source. The constant voltage ramp makes the voltage ramp dv / dt steeper near the comparator trip point compared to the exponential charging in the resistor case described above. The ramp up and settling time of the current source introduces potential errors to the filtering time if it is required to be used directly after the power switch is activated. The current source needs to be robust to voltages above the drive supply and below the emitter potential at the DESAT pin, which could cause latch-up or other disturbances to the circuit operation.

[0025] In addition to adding an integrated current source 232 coupled between the VCC2 pin and the DESAT pin, Figure 3 Including the above Figure 2 The components of the circuit description are basically the same components.

[0026] The capacitance at the DESAT pin consists of a discrete capacitor C DESAT and high voltage diode D DESAT The charge on Figure 3 The current source circuit has limited charging current (up to several hundred μA) and less filtering time (up to several μs), so the DESAT filter capacitor C DESAT Must be small, typically in the range of 50pF to 250pF. The accuracy of the capacitor (and filter) is affected by layout capacitance, environmental effects such as wetting, charge variations of the high voltage diode charge of any protection diodes that may be used, and leakage current of any protection diodes that may be used.

[0027] like Figure 4 As can be seen from the schematic diagram of FIG, an alternative detection and filtering method uses a voltage divider and a clamping diode so that no high voltage diode is used. In addition to using a clamping diode D CLAMP and two separate DESAT resistors R DESAT1 and R DESAT2 outside, Figure 4 Including the above reference Figure 2 and Figure 3 The components of the circuit described are basically the same components. Resistor R DESAT1 and R DESAT2 is coupled between the DESAT pin and the collector 212 of the IGBT 208. CLAMP Coupled between the VCC2 pin and the intermediate node 234 .

[0028] When the IGBT 208 is in the off state, the clamp transistor 206 is activated to clamp the input of the comparator 204 to 0 V. At the same time, depending on the load current direction, the V CE The voltage can be a few volts negative or at a high voltage potential, such as 800V. Depending on the resistor R DESAT1 With R DESAT2 The ratio between V CE Voltage, diode D CLAMP will be forward biased or reverse biased. The resistance needs to be high so that not too much power is dissipated in the resistor in the off state. When the IGBT208 is turned on, V CE The voltage drops to V CE ,SAT voltage. At the same time or shortly thereafter, the clamp transistor releases the clamp on the comparator input (DESAT pin). The filter time is determined by R DESAT1 and R DESAT2 The capacitance at the DESAT pin includes any intentionally placed capacitor C DESAT As well as any additional parasitic capacitance (from the comparator inputs, PCB, etc.), the comparator trip level and the pre-charge voltage level which depends on the load of the switch. Due to the high series resistance from the collector to the comparator input, the total capacitance at the DESAT pin must be very low and therefore any change in parasitic capacitance will have a large impact on the total capacitance.

[0029] If a desaturation event occurs, V CE The voltage will increase to a level above the threshold of comparator 204, and the comparator will trigger and turn off IGBT 208. However, during a desaturation event, V CE The voltage can also become so high that the voltage becomes higher than the gate driver supply voltage (VCC2). In this case, the diode D CLAMP and resistor R DESAT1 The driver will be protected from potentially destructive voltage levels at the collector 212 of the IGBT 208. Diode D CLAMP The resistor R DESAT2 With R DESAT1The node 234 between the two terminals is clamped to the VCC2+Vth voltage of the diode, and the current will flow from the collector 212 through the resistor R DESAT1 And through the diode D CLAMP Flows to the power supply VCC2.

[0030] Due to this resistive property, the resistor can be connected to the capacitor C DESAT placed in parallel with R DESAT1 and R DESAT2 Together they form a resistor divider. In this way, a higher V level than VCC2 can be used CE DESAT level. This may be important if DESAT detection is used for switches that are able to block voltages above, for example, 1700V.

[0031] For each of the above filtering methods, the absolute size of the DESAT capacitor limits the filtering performance against spikes or coupling from noisy environments. Additionally, filtering at one input with one capacitor gives exactly one time constant. It is not possible to perform higher levels of filtering or parallel detection of different threshold or filter time combinations with one blocking structure (high voltage blocking diode or resistor). In addition, the number of different components and configurations that affect the actual filter time results in a large amount of variation in filter time.

[0032] According to an embodiment of the present invention, in order to improve filtering variation (filtering time is independent of the load of the switch just before the short circuit occurs), two or more independent DESAT levels and filter values ​​are used while sharing the same blocking structure. In one embodiment, the filter can be coupled to a comparator output, which in turn is coupled to a logic circuit.

[0033] According to an embodiment of the present invention, a DESAT detection structure or circuit having one or more independently configurable voltage threshold levels and filter times is used to detect various short circuit and overcurrent events, and various signals are provided in response using only one pin, one resistor, and one diode as described herein, thereby decoupling the DESAT pin from the collector potential or drain potential of the drive switch in the off state. For low voltage applications, desaturation detection can be performed without using a diode. Figure 5A A circuit according to an embodiment of the invention is shown in , where the filter is located after the comparator and the reference for the (in this case two) comparators is set by a DAC.

[0034] As previously mentioned Figures 2 to 4 As shown in the circuit shown in Figure 5A Therefore, the VCC2 pin, the DESAT pin, the OFF pin and the GND2 pin, the filter capacitor C VCC2, Gate resistor R G 、DESAT resistor R DESAT 、DESAT diode D DESAT , a clamp transistor 206, an integrated current source 232, and a controller circuit 202 of an IGBT 208 / recirculation diode 210. In addition, Figure 5A The circuit includes a logic circuit 226 including a first filter 228 and a second filter 230, a first comparator 220 and a second comparator 224, and a first DAC 218 and a second DAC 222. Note that the inputs of both comparators 220 and 224 are coupled to the DESAT pin. DAC 218 provides a threshold voltage for comparator 220, and DAC 222 provides a threshold voltage for comparator 224. The output of comparator 220 is coupled to the first filter 228, and the output of comparator 224 is coupled to the second filter 230.

[0035] Having two or more differently configured DESAT detectors with different DESAT filter time / voltage threshold settings increases the level of protection against overload faults in the application. The driver can be set to cover a wider range of DESAT detection situations and increase the detection range from short-circuit protection only to overcurrent detection (even for bipolar devices or IGBTs). Hard short circuits with steep current slopes are handled according to one DESAT filter time / voltage threshold setting. In a typical case, low load inductance, fast desaturation, and high overloads (DC link voltage multiplied by short-circuit current) require a short reaction time of the driver, thus requiring a short DESAT filter time and a relatively high detection voltage. Soft overloads (overcurrents) with slow current rise are handled according to another DESAT filter time / voltage threshold setting. In another typical case, high load inductance, slow current rise, slowly increasing overloads (slightly increased saturation voltage multiplied by short-circuit current) allow longer filter times and lower detection voltages.

[0036] Having an internal filter also enables an implementation with an adjustable DESAT detector (software adjustable), where the parameters of the detector (detection voltage and filter time) can be changed without changing the external circuitry. This feature enables late design changes without corresponding hardware cluster changes. The adjustable filter can be an analog or digital solution. Adjustability may not be specifically required and fixed values ​​may also be used.

[0037] The internal filter also enables the use of different filtering algorithms or filtering orders optimized for each detection situation, for example, for equal distributed noise floor, an up / down counter can be used, and for fastest reaction, an up / reset counter can be used. Other algorithms can also be used to provide other features and functions. The different filter types that can be used according to the embodiment can include but are not limited to passive or active; analog or digital; high pass, low pass, band pass, band stop or all pass; discrete time or continuous time; linear or nonlinear; or infinite impulse response or finite impulse response. Those skilled in the art can classify filter types in many other ways, including transfer function, filter topology, hardware filtering technology, and many other ways.

[0038] Since there is no time-determining filter capacitor, faster and more reliable short-circuit detection times can be achieved without being limited by the minimum external filter capacitor value. With existing technology implementations, the useful minimum filter capacitor is limited by wetting, noise suppression and layout capacitance. Newer switches with smaller short-circuit time specifications (e.g., new IGBT generations and SiC MOSFETs) can be protected.

[0039] You can also use Figure 5A Other implementations than those shown in . For example, instead of an adjustable comparator, a fast analog-to-digital converter ("ADC") is used to measure the voltage measured at the DESAT pin and then a digital filter is applied.

[0040] Figure 5B Therefore, an implementation using two ADCs 236 and 238 with analog inputs coupled to the DESAT pin is shown. The digital output of the ADC 236, designated as DESAT1, is coupled to the input of the first filter 228. The digital output of the ADC 238, designated as DESAT2, is coupled to the input of the second filter 230. The threshold value can be a digital value comparison of the ADC word or the filtered word. The filter can be placed after the ADC before or after the numerical comparison. The comparison level can be programmed by changing the word that the ADC or filter word should be compared with. If the comparison is completed before filtering, the filtering is completed on a single data stream. If the filtering is completed before comparison, the filter is a numerical filter, such as a classic low-pass filter.

[0041] Configuration of the thresholds by the user is only one option. The drive can also be preconfigured to the most relevant use cases and sold as a fully integrated part that reacts to different fault situations.

[0042] By independently using additional DESAT threshold / filter time combinations, previously undetectable over-current faults can be detected. The additional DESAT detector results (described herein as DESAT2) can be used in a variety of different ways compared to conventional DESAT detection (described herein as DESAT1) that turns off the drive switch when desaturation is detected. Depending on the implementation, more than one DESAT detector can be used for slow and fast short circuit detection.

[0043] According to embodiments of the present invention, any of the above-described DESAT detection methods may be used, such as external filtering without sharing a blocking element or shared internal filtering, high voltage diode blocking or a voltage divider and clamping diodes may be used with a blocking element.

[0044] The application design in tolerance testing is one application for embodiments of the present invention and provides a design in support of testing the tolerance of the first DESAT in the system to prevent false triggering simultaneously with the evaluation process. As previously described, the first DESAT detector setting (DESAT1) prevents standard DESAT events. The second / additional DESAT detector (DESAT2) looks at the setting of the first DESAT in the system with reasonable design tolerances during the application evaluation process. The DESAT2 threshold and time are adjusted with tolerances compared to the first DESAT value (e.g., DESAT1 9V threshold and 5μs filter time, DESAT2 7V threshold and / or 3μs filter time). DESAT2 is configured in a way that DESAT2 events will not cause a fault shutdown. DESAT2 is configured to count DESAT2 events in the DESAT2 counter. The counter value can be monitored by the controller without stopping and endangering the system. The counter value together with the set tolerances of the thresholds gives an indication of system stability.

[0045] For example, an indication of system stability related to voltage thresholds is described below. The DESAT1 value is selected to be, for example, 9 volts. DESAT2 is then set to a low value, such as 7 volts, to begin with. If there is a triggered DESAT2 even during application operation, the known tolerance is less than (9 volts-7 volts) / (9 volts)=22.2%. If the DESAT2 value is increased to 7.5 volts and DESAT2 is not triggered during application testing, the tolerance is between 22.2% and (9 volts-7.5 volts) / (9 volts)=16.7%. Of course, the number of DESAT2 triggering events gives an indication of how close or far the DESAT2 level is from the actual tolerance value. If the tolerance is judged to be too high, the DESAT1 level may be reduced. If the tolerance is judged to be too low, the DESAT1 level may be increased. The filter time can be tested and adjusted in a manner similar to that described above.

[0046] Figure 6 A flow chart of the tolerance test method is shown in FIG. The flow chart for tolerance testing according to an embodiment of the present invention starts at 302. Step 304 queries whether the PWM signal used in the switch is high. If not, the method returns to 302. If yes, then in the above-mentioned DESAT1 path, V is measured at 306. CE voltage. At 308, the method determines whether the DESAT1 voltage is greater than the DESAT1 threshold and whether there is a signal at the output of the first filter. If so, it is determined at 310 that a DESAT1 event has occurred. If not, the method returns to 302. If a DESAT1 event has occurred, the switch is turned off at 312 and the PWM signal is set to low. At 314, the method waits for a command to reset the DESAT event. Once the command is given, the method continues to 316, where the DESAT1 event is reset, and the method further continues back to 302. Reviewing step 304, it is queried whether the PWM signal used in the switch is high. If so, while in the above-mentioned DESAT2 path, V is measured at 318. CE At 320, the method determines whether the DESAT2 voltage is greater than the DESAT2 threshold and whether there is a signal at the output of the second filter. If so, it is determined at 322 that a DESAT2 event has occurred. If not, the method returns to 302. If a DESAT2 event has occurred, the DESAT2 counter is incremented at 324. At 326, the method waits for the PWM signal to be set low, and when the PWM signal is actually set low, the method further continues back to 302.

[0047] Another application of embodiments of the present invention is short circuit detection during repetitive short pulse operation (e.g., sinusoidal pulse width modulation). In response to short PWM on-pulses with repetitive DESAT events (e.g., sinusoidal pulse width modulation), the standard DESAT minimum filter time is limited due to noise in the system. PWM on-pulses shorter than the minimum filter time cannot be detected, otherwise false triggering of DESAT events may occur. Although short short circuit events do not usually immediately damage the switch through current destruction, the switch will heat up during the short circuit event. If the switch has a total short circuit rating of 10μs, this means that the switch is damaged after 10μs of the nominal short circuit current. Although short circuit events shorter than 10μs cause the switch to heat up, they do not damage the switch. For example, 10×1μs short circuit events can have a similar thermal impact as one 10μs short circuit event. If the driver detects ten consecutive short circuit events, it can turn off the switch before damage. This means that not every detected DESAT event needs to shut down the driver, but the driver can be made to count a certain number of short repetitive DESAT events until the switch reaches the maximum junction temperature. According to an embodiment of the invention, the counter is prevented from overflowing due to noise by decrementing the counter with N PWM pulses.

[0048] The standard DESAT1 detection uses certain known filter lengths. On the one hand, the filtering must be as short as possible to protect small pulses, on the other hand, it must prevent false triggering. Every detected DESAT1 event results in a fault shutdown. Pulses shorter than the minimum filter time cannot be detected (e.g. DESAT1 9V threshold and 5μs filter time). For the second / additional DESAT setting (referred to here as DESAT2), other rules can be applied. For example, not every detected DESAT2 event results in a fault shutdown. A shorter filter time than DESAT1 can be used (e.g. 9V threshold and 3μs filter time). To prevent false triggering, a second higher level of filtering is added. DESAT2 events are counted in the absence of DESAT events and the counter is decremented after N-PWM pulses (e.g. 4 in Figure 7 DESAT2 is invalid in , as the maximum count is 2 and not decremented). After the maximum number of DESAT2 events, the driver will shut down with a fault shutdown (e.g., 2). In addition, DESAT2 can be configured as a warning only, which means that the fault shutdown is not initiated and the system controller can read the warning bit periodically.

[0049] exist Figure 7 Examples of corresponding waveforms can be seen in the timing diagram of Figure 8The corresponding flowchart can be seen in . If DESAT2 is configured to set warning only, there will no longer be a path from (DESAT2 counter = maximum DESAT2 events) to fault shutdown, and the path should go to the block that sets the warning flag. This will be described in further detail below Figure 8 .

[0050] Now refer to Figure 7 , shows the minimum DESAT1 filter time 402 determined by the system noise. Undetectable pulses occurring during time period 404 associated with PWM waveform 406 are shown. Six such undetectable pulses are shown during time period 404 because the pulse widths of these pulses are less than the pulse width of the DESAT1 filter time. Nevertheless, during time period 404 after the point in time when the short circuit occurs, the operating temperature T J 408 is shown as increasing. A minimum DESAT2 filter time 410 is shown, which is less than the DESAT1 filter time 402. During time period 404, two DESAT2 short circuit events are determined and shown as counted DESAT2 events 414. During time period 412, also associated with PWM waveform 406, two PWM counts 416 associated with undetectable short circuit events occur (filtered by either DESAT1 or DESAT2).

[0051] Reference Figure 8 The flowchart of further illustrates the short circuit detection method according to an embodiment. Note that the DESAT1 path and the DESAT2 path are the same as those previously described with respect to Figure 6 The paths described above for the tolerance test method of FIG. 1 are substantially the same. However, the DESAT2 path includes another step 328 which asks whether the DESAT2 counter has reached the maximum number of DESAT2 events. If so, the method proceeds to 312 in the DESAT1 path as previously described. If not, the method continues to 326 in the DESAT2 path as previously described. The DESAT2 counter for the sub-DESAT2 short circuit event is decremented using the parallel monitoring path. Step 330 is associated with the reset of the DESAT2 event. At startup, all counters and events are in a reset state, and Figure 8 The left process of is entered at 302, and Figure 8 The right process of is entered at 346. The clearing of the DESAT2 event is completed by the right process. In the case where the PWM signal goes low and the DESAT2 event occurs, the event is reset. Figure 8The left and right processes depicted in can be implemented, for example, by two processors working in parallel. Step 332 checks whether the PWM signal has been set to low. Step 334 asks whether the PWM signal is low and whether a DESAT2 event exists. It should be noted that when a signal exists after the comparator and filter have issued a DESAT2 event signal, this is recorded in the DESAT2 event register or trigger, and this is the value from which it can be determined that a DESAT2 event has occurred. Return to Figure 8 , if yes, the method returns to 330, and if no, the method continues to 342. Step 342 increments the No DESAT counter. The method then continues to step 344, which asks whether the No DESAT counter has reached a predetermined limit. If no, the method returns to 332. If yes, the method continues to step 336. Step 336 asks whether the DESAT2 counter is greater than zero. If not, the method returns to 332. If yes, the DESAT2 counter is decremented at 338, and the method returns to 332.

[0052] A third application of embodiments of the present invention is to detect overcurrent events during the two-stage turn-off phase. In the event of an excessively high switching current, it may not be possible to immediately turn off the power switch without risking damage or destruction of the switching device. Therefore, the gate voltage of the power switch is first reduced to a defined level (plateau), and the switch is turned off after a certain time (plateau time). This mechanism is called "two-stage turn-off" (2LTO or TLTOff). In some embodiments, the two-stage turn-off method can be applied to drive an IGBT switch to avoid latching of the switching transistor in high current situations.

[0053] The standard DESAT detection is inactive during the two-level turn-off (TLTOff) for several reasons. The normal DESAT filter time is in most cases longer than the TLTOff plateau time and therefore desaturation cannot be detected during this period, but it is also undesirable to shut down every time the IGBT goes into desaturation during TLTOff. To prevent the normal DESAT detection from reacting to desaturation during the TLTOff event, the input or output of the comparator is blocked during the TLTOff plateau time. The standard DESAT1 detection uses a certain filter length and voltage threshold. And upon detection, a fault shutdown is performed. During the TLTOff plateau, the output of the DESAT1 comparator is blocked. During TLTOff, the IGBT may go into an overload state, resulting in desaturation due to the reduced gate voltage. This means that by reducing the gate voltage from 15V to 10V, the desaturation current is reduced by approximately a factor of 4. See Fig. 9The corresponding voltage in the switch operating characteristic of TLTOff is decremented by 104. DESAT events during TLTOff do not lead to immediate destruction (the maximum collector current is much lower (e.g. 4 times) compared to the nominal short circuit, and the short circuit withstand time is therefore amplified (e.g. 4 times)). Thermal destruction of the IGBT within several PWM cycles is a typical fault condition. In order to protect the switch from such an overload condition, the same measures as described above with reference to the repeated short circuit condition can be taken. Not every detected DESAT2 event will lead to a fault shutdown. A shorter filtering time than DESAT1 can be used (e.g. 9V threshold and 2μs filtering time). In order to prevent false triggering, a second high level filtering is added. Counting DESAT2 events in the absence of DESAT events and decrementing the counter after N-PWM pulses (e.g. 4) is used. After the maximum number of DESAT2 events, the driver will shut down with a fault shutdown (e.g. 2). In addition, DESAT2 can be configured as a warning only. This means that no false shutdown is initiated and the system controller can read out the warning bit regularly.

[0054] Now refer to Figure 8 , if DESAT2 is configured to set warnings only, the path from step 328 (DESAT2 counter = maximum DESAT2 events) to fault shutdown 312 will no longer occur, and instead, the path should go to optional block 340 which sets the warning flag.

[0055] Due to the single pulse overcurrent condition, the first event overcurrent signal is typically a single event signal, but in an embodiment, the first event overcurrent signal may also include a response to a double pulse event or a multi-pulse event or any other overcurrent event. In an embodiment, the multi-event overcurrent signal can be used as a warning signal or a flag or used to generate a warning signal or a flag, or can be used to directly or indirectly turn off the power switch. Therefore, the term "overcurrent signal" used in this article is defined as the detection of an overcurrent condition. Therefore, the action taken once the overcurrent signal is generated may directly or indirectly lead to the turning off of the power switch, a warning signal for notifying a system including the power switch, or any other measures that are considered appropriate in a specific working environment. The detection thresholds described in this article may be equal to or different from each other in an embodiment. Similarly, the time constants described in this article may be equal to or different from each other in an embodiment. The specific voltage value and duration can be changed according to the needs of the specific application.

[0056] Although the present invention has been described with reference to illustrative embodiments, the description is not intended to be interpreted as having a restrictive meaning. Various modifications and combinations of the illustrative embodiments and other embodiments of the present invention will be apparent to those skilled in the art when referenced to the description. As just one example, although the first detector and the second detector and the first filter and the second filter have been shown and described, any number of detectors and filters may be used. As another example, any voltage, time or any other constant is only for illustrative purposes and can certainly be changed according to the needs of a particular application. Flowcharts are provided for illustration only, and fewer or more blocks may be used in the method of operation shown. Additional methods of operation are also possible. Therefore, it is intended that the appended claims cover any such modifications or embodiments.

Claims

1. A system for detection, comprising: A control circuit comprising Multiple Detector, a plurality of filters, each filter being coupled to one of the plurality of detectors, and a logic circuit coupled to the plurality of detectors and the plurality of filters; Diode circuit; as well as a switch having a gate, a first node and a second node, wherein the diode circuit is coupled between the first node of the switch and the plurality of detectors, wherein the logic circuit is coupled to the gate of the switch, wherein the plurality of detectors include at least a first detector and a second detector, each detector being configured to provide a corresponding event overcurrent signal by measuring a signal provided by the diode circuit and comparing the signal with a detection threshold of the detector, wherein each of the plurality of filters is configured to filter an event overcurrent signal of a corresponding detector of the plurality of detectors and provide the filtered event overcurrent signal to the logic circuit, and Wherein, the logic circuit is configured as counting the event overcurrent signals of at least the second detector, generating a multiple event overcurrent signal in the event that a maximum number of event overcurrent signals of the second detector is reached, and At least one of a detection threshold of the first detector and a detection threshold of the second detector is programmed based on the multiple-event overcurrent signal.

2. The system according to claim 1, wherein: The detection threshold of the first detector is different from the detection threshold of the second detector.

3. The system according to claim 1, wherein: The plurality of filters include a first filter having a first time constant and a second filter having a second time constant different from the first time constant.

4. The system according to claim 1, wherein: A detection threshold of the first detector is different from a detection threshold of the second detector, and wherein the plurality of filters include a first filter having a first time constant and a second filter having a second time constant equal to the first time constant.

5. The system according to claim 1, wherein: A detection threshold of the first detector and a detection threshold of the second detector are equal, and wherein the plurality of filters include a first filter having a first time constant and a second filter having a second time constant different from the first time constant.

6. The system according to claim 1, wherein: The second detector is configured to provide a margin test of a performance standard of the first detector.

7. The system according to claim 1, wherein: The first detector and the second detector are configured to provide an over-current signal during a two-level shutdown platform operating mode of the system.

8. The circuit according to claim 1, wherein: At least one of the first detector and the second detector includes a comparator and a digital-to-analog converter DAC, wherein the DAC is coupled to the logic circuit and the comparator.

9. The circuit according to claim 1, wherein: At least one of the first detector and the second detector includes an analog-to-digital converter ADC.

10. The circuit according to claim 3, wherein: The first filter and the second filter comprise different filter types.

11. A method for detection, comprising: measuring the signal provided by the diode circuit; filtering the measured signal; comparing the filtered signal to a threshold of a first detector of a plurality of detectors and a threshold of a second detector of the plurality of detectors; generating a first event overcurrent signal if the filtered signal exceeds a threshold of the first detector; as well as generating a second event overcurrent signal in case the filtered signal exceeds a threshold of the second detector, Wherein, the method further comprises: incrementing a counter in the event that the second event overcurrent signal is generated; generating a multiple event over-current signal in the event that the counter reaches a maximum number of the second event over-current signals, and At least one of a threshold of the first detector and a threshold of the second detector is programmed based on the multiple-event overcurrent signal. 12 . The method of claim 11 , further comprising controlling an operating mode of a switch based at least on the first event overcurrent signal and the multiple event overcurrent signal. 13 . The method of claim 11 , further comprising counting a number of over-current events associated with the filtered signal before generating the multiple-event over-current signal.

14. The method of claim 11, further comprising counting a number of over-current events associated with the filtered signal before generating the warning signal.

15. The method according to claim 11, wherein: Filtering the measured signal includes filtering the measured signal using a first filtering method and filtering the measured signal using a second filtering method.

16. The method according to claim 11, wherein: The method is performed in a switching system.

17. The method of claim 16, further comprising counting a plurality of overcurrent events associated with the filtered signal to enable margin testing of at least one performance criterion of the switching system.

18. The method according to claim 16, wherein: The multiple event over-current signal or warning signal is generated during a two-stage shutdown platform operating mode of the switching system.

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