Synchronous rectifier and wireless charging system

Abstract

A synchronous rectifier and a wireless charging system, the synchronous rectifier comprises: two groups of low-position MOS tubes, respectively connected to the two ends of an AC output, each group of low-position MOS tubes having a plurality of low-position MOS tubes in parallel; two high-position MOS tubes, one end of which is respectively connected to the two ends of the AC output, and the other end is connected to the DC output end of the synchronous rectifier. By setting two groups of low-position MOS tubes, and controlling the on-off state of a plurality of parallel low-position MOS tubes in each group of low-position MOS tubes through a gate voltage control circuit, the plurality of parallel low-position MOS tubes have the following working states: simultaneously closed, the first number of low-position MOS tubes are opened, the second number of low-position MOS tubes are closed, and simultaneously opened, the corresponding synchronous rectifier can work under low current (0-1mA), small current (1mA-5mA) and medium-large current (greater than 5mA), the efficiency can reach up to 95%-99%, and it is suitable for a wide range of output currents, and can perform high-efficiency rectification for AC power in various current value ranges, and has a wide range of application prospects.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of wireless charging and relates to a synchronous rectifier and a wireless charging system. Background Art

[0002] Wireless charging technology originates from wireless power transmission technology, and the most common ones are electromagnetic induction or resonance charging. Since there is no need to use a physical connection line between the charging device and the electrical appliance during the charging process, it is convenient and beautiful. In the field of consumer electronics, such as: smart bracelets, smart phones, smart watches, Bluetooth headsets, tablets, wearable devices, etc., the demand for wireless charging is becoming stronger and stronger. In related fields such as smart homes and industrial fields, it is also gradually moving towards wireless, such as: lighting systems, security systems, theater systems, sweeping robots, and drones, which have the demand for wireless charging. Under the above requirements, the development of wireless charging needs to meet the following requirements: safety, efficiency, and cost reduction.

[0003] In wireless charging or wireless power transmission systems, the transmitter and receiver are physically separated and use coils or inductors to transmit alternating current (AC) power. Therefore, the DC-AC converter is a key component of the transmitter, and the AC-DC converter is a key component of the receiver. In wireless charging systems, the power transmission efficiency of the transmitter (transmitter chip) and the receiver (receiver chip) is very important, and the main factors that determine the efficiency are the conversion efficiency of the power amplifier (DC-AC converter) and the rectifier (AC-DC converter). Normally, the working efficiency of the rectifier is about 70% to 80%, that is, under the same changing current, the power conversion efficiency is low.

[0004] Therefore, there is an urgent need to propose a rectifier structure with higher working efficiency. Summary of the invention

[0005] 1. Technical issues to be resolved

[0006] The present disclosure provides a synchronous rectifier and a wireless charging system to at least partially solve the above-mentioned technical problems.

[0007] (II) Technical solution

[0008] According to one aspect of the present disclosure, a synchronous rectifier is provided, comprising: two groups of low-order MOS tubes, each group of low-order MOS tubes having a plurality of low-order MOS tubes connected in parallel, wherein the source and drain of one group of low-order MOS tubes are respectively connected to: a first AC output terminal and ground, and the source and drain of the other group are respectively connected to: a second AC output terminal and ground; two high-order MOS tubes, wherein the source and drain of one high-order MOS tube are respectively connected to: a first AC output terminal and a DC output terminal of the synchronous rectifier, and the source and drain of the other high-order MOS tube are respectively connected to: a second AC output terminal and a DC output terminal of the synchronous rectifier; wherein in each group of low-order MOS tubes, respective gates of the plurality of parallel low-order MOS tubes are respectively connected in parallel to an external output terminal of a gate voltage control circuit through switches, and the gate voltage control circuit is used to drive the plurality of parallel low-order MOS tubes in a corresponding manner under different current states: all are in an off state, all are in an on state, or one is on and the other is off.

[0009] In one embodiment of the present disclosure, each gate of the two high-level MOS transistors is connected to a gate voltage control circuit on a branch corresponding to another AC input terminal opposite to the AC input terminal connected to the gate via a boost circuit.

[0010] In an embodiment of the present disclosure, in each group of low-level MOS transistors, the external input terminal of the gate voltage control circuit is connected to the first AC input terminal / the second AC input terminal.

[0011] In an embodiment of the present disclosure, in each group of low-bit MOS transistors, the gate voltage control circuit includes: an operational amplifier and a dual reference voltage switch.

[0012] In one embodiment of the present disclosure, one of the two input terminals of the operational amplifier is a first AC input terminal / a second AC input terminal, and the other input terminal is the output of a dual reference voltage switch. The output terminal of the operational amplifier is connected to the input terminal of the dual reference voltage switch, and the output terminal of the operational amplifier serves as an external output terminal of the gate voltage control circuit.

[0013] In one embodiment of the present disclosure, the synchronous rectifier operates in a passive mode, and the passive mode corresponds to a low current default on, and the current I range of the low current is: 0<I≤1mA. In the passive mode, both the high-order MOS tube and the low-order MOS tube are in a closed state, and the corresponding parasitic diodes of each MOS tube work.

[0014] In one embodiment of the present disclosure, the synchronous rectifier operates in a half-open mode, and the half-open mode operates under a small current, and the current I range of the small current is: 1mA<I≤5mA. In the half-open mode, the high-order MOS tubes are all turned on and the low-order MOS tubes are all turned off.

[0015] In one embodiment of the present disclosure, the synchronous rectifier operates in a first fully-on mode, the first fully-on mode operates under a small current, the current I range of the small current is: 1mA<I≤5mA, in the first fully-on mode, all high-order MOS tubes are turned on, a first number of low-order MOS tubes among a plurality of low-order MOS tubes connected in parallel in each group of two groups of low-order MOS tubes are turned on, and a second number of low-order MOS tubes are turned off.

[0016] In one embodiment of the present disclosure, the synchronous rectifier operates in a second fully-on mode, and the second fully-on mode operates at medium to large currents. The current I range of the medium to large currents is: I>5mA. In the second fully-on mode, both high-order MOS tubes are turned on and both low-order MOS tubes are turned on.

[0017] According to another aspect of the present disclosure, a wireless charging system is provided, comprising any one of the synchronous rectifiers mentioned in the present disclosure.

[0018] (III) Beneficial effects

[0019] It can be seen from the above technical solutions that the synchronous rectifier and wireless charging system provided by the present disclosure have the following beneficial effects:

[0020] (1) By arranging two groups of low-order MOS tubes respectively connected to the two ends of the AC output, one end of two high-order MOS tubes respectively connected to the two ends of the AC output, and the other end connected to the DC output end of the synchronous rectifier, and controlling the on-off state of a plurality of low-order MOS tubes in each group of low-order MOS tubes by a gate voltage control circuit, the plurality of low-order MOS tubes in parallel have the following working states: simultaneously closed, a first number of low-order MOS tubes turned on, a second number of low-order MOS tubes turned off, and simultaneously turned on, the corresponding synchronous rectifier can work under low current (0-1mA), small current (1mA-5mA) and medium-large current (greater than 5mA), the efficiency can reach up to 95%-99%, and it is suitable for a wide range of output currents, and can perform high-efficiency rectification for AC power in various current value ranges, and has a wide application prospect;

[0021] (2) The current ranges corresponding to different working modes (half-open mode and first fully-open mode) can also be adjusted by setting the number of MOS tubes turned on and off in the low-bit MOS tubes connected in parallel in each group of low-bit MOS tubes, that is, by setting different ratios of the first number and the second number. Since the working ranges of the half-open mode and the first fully-open mode overlap, both of which work in a small current range (1 mA to 5 mA), the switching between the half-open mode and the first fully-open mode is achieved by changing the ratio of the MOS tubes turned on and off in each group of low-bit MOS tubes.

[0022] (3) The synchronous rectifier corresponds to four working modes, namely, passive mode, half-open mode, first full-open mode and second full-open mode. The rectification efficiency in each mode is higher than or at least equal to that of the prior art. In particular, in the first full-open mode, corresponding to the low current condition, the rectification efficiency can be as high as 92% to 99%, which effectively improves the rectification efficiency.

[0023] (4) In one embodiment, by using the output of the gate voltage control circuit (corresponding to the external output terminal) as the gate voltage control of the high and low MOS transistors at the same time, the circuit is simplified and synchronous control is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Schematic diagram of the structure of a synchronous rectifier according to an embodiment of the present disclosure.

[0025] Figure 2 For Figure 1 The synchronous rectifier shown is a structural schematic diagram of a wireless charging system.

[0026] Figure 3 For Figure 1 FIG. 4 is an equivalent circuit diagram of a synchronous rectifier in a passive mode.

[0027] Figure 4 For Figure 3 The corresponding circuit working timing diagram.

[0028] Figure 5 For Figure 1 FIG. 4 is an equivalent circuit diagram of a synchronous rectifier in half mode.

[0029] Figure 6 For Figure 5 The corresponding circuit working timing diagram.

[0030] Figure 7 For Figure 1 FIG. 4 is a circuit structure equivalent diagram of a synchronous rectifier in a first full-on mode (full mode 1).

[0031] Figure 8 For Figure 7 The corresponding circuit working timing diagram.

[0032] Fig. 9 For Figure 1 FIG. 4 is a circuit structure equivalent diagram of the synchronous rectifier in the second full-on mode (full mode 2).

[0033] Fig.10 For Fig. 9 The corresponding circuit working timing diagram.

[0034]

Explanation of symbols

[0035] BC1: first boost circuit; BC2: second boost circuit;

[0036] AC1: the first AC output terminal; AC2: the second AC output terminal;

[0037] G1: output of the first gate voltage control circuit; G2: output of the second gate voltage control circuit;

[0038] G3: the third grid; G4: the fourth grid;

[0039] M1_L: first MOS tube; M1_M: second MOS tube;

[0040] M2_L: the first second MOS tube; M2_M: the second second MOS tube;

[0041] M3: the third MOS tube; M4: the fourth MOS tube;

[0042] G1_L: first first gate; G1_M: second first gate;

[0043] G2_L: first second gate; G2_M: second second gate;

[0044] 11-a first gate voltage control circuit;

[0045] OA1: first operational amplifier; DRS1: first dual reference voltage switch;

[0046] 12- a second gate voltage control circuit;

[0047] OA2: second operational amplifier; DRS2: second dual reference voltage switch;

[0048] VRECT: square wave / DC output terminal;

[0049] GND: ground;

[0050] C L : load capacitance; I Load : load current;

[0051] TX: transmitter;

[0052] Chinese and English comparison:

[0053] Boost Converter (BC);

[0054] Dual Reference Switcher (DRS);

[0055] Operational Amplifier (OA);

[0056] AC (Alternating Current);

[0057] Direct Current (DC);

[0058] Gate (G). DETAILED DESCRIPTION

[0059] The present disclosure provides a synchronous rectifier and a wireless charging system. Two groups of low-order MOS tubes are respectively connected to the two ends of an AC output, one end of two high-order MOS tubes is respectively connected to the two ends of the AC output, and the other end is connected to the DC output end of the synchronous rectifier. The gate voltage control circuit controls the on-off state of a plurality of low-order MOS tubes in each group of low-order MOS tubes. The plurality of low-order MOS tubes in parallel have the following working states: simultaneously closed, a first number of low-order MOS tubes are opened, a second number of low-order MOS tubes are closed, and simultaneously opened. The synchronous rectifier can work under low current (0-1 mA), small current (1 mA-5 mA), and medium-large current (greater than 5 mA), with an efficiency of up to 95%-99%, and is suitable for a wide range of output currents. It can perform high-efficiency rectification on AC power in various current value ranges, and has broad application prospects.

[0060] In order to make the purpose, technical solution and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings. In the present disclosure, one end and the other end of a MOS tube refer to one of a source or a drain. A "high-position MOS tube" refers to a MOS tube whose source and drain ends are respectively connected between AC1 (or AC2) and VRECT, and a "low-position MOS tube" refers to a MOS tube whose source and drain ends are respectively connected between AC1 (or AC2) and GND.

[0061] First embodiment

[0062] In a first exemplary embodiment of the present disclosure, a synchronous rectifier is provided.

[0063] Figure 1 Schematic diagram of the structure of a synchronous rectifier according to an embodiment of the present disclosure. Figure 2 For Figure 1 The synchronous rectifier shown is a structural schematic diagram of a wireless charging system.

[0064] Reference Figure 1 and Figure 2As shown, the synchronous rectifier disclosed in the present invention comprises: two groups of low-position MOS tubes, each group of low-position MOS tubes has a plurality of low-position MOS tubes connected in parallel, wherein the source and drain electrodes (two ends) of one group of low-position MOS tubes are respectively connected to: a first AC output end and ground, and the source and drain electrodes (two ends) of the other group are respectively connected to: a second AC output end and ground; two high-position MOS tubes, wherein the source and drain electrodes of one high-position MOS tube are respectively connected to: a first AC output end and a DC output end VRECT of the synchronous rectifier, and the source and drain electrodes of the other high-position MOS tube are respectively connected to: a second AC output end and a DC output end VRECT of the synchronous rectifier; wherein in each group of low-position MOS tubes, the gate electrodes of the plurality of parallel low-position MOS tubes are respectively connected in parallel to the external output end of a gate voltage control circuit through switches, and the gate voltage control circuit is used to drive the plurality of parallel low-position MOS tubes in different current states: all are in an off state, all are in an on state, or the first number of low-position MOS tubes are turned on and the second number of low-position MOS tubes are turned off.

[0065] In the embodiment of the present disclosure, the gates of the two high-order MOS transistors are respectively connected to the gate voltage control circuit on the branch corresponding to the other AC input terminal opposite to the AC input terminal connected to the gate via a boost circuit. Of course, in this embodiment, the output of the gate voltage control circuit is directly used as the gate voltage control of the high-order and low-order MOS transistors at the same time, which simplifies the circuit and realizes synchronous control. In other implementations, the high-order MOS transistor can provide gate voltage in other ways.

[0066] In this embodiment, the synchronous rectifier includes: two first MOS transistors connected in parallel, two second MOS transistors connected in parallel, a third MOS transistor and a fourth MOS transistor, wherein one end of the first MOS transistor is connected to the first AC output end, one end of the second MOS transistor is connected to the second AC output end, the other ends of the first MOS transistor and the second MOS transistor are both grounded, the gates of the two first MOS transistors connected in parallel and the two second MOS transistors connected in parallel are respectively connected in parallel to a first gate voltage control circuit and a second gate voltage control circuit through switches, and the first / second gate voltage control circuit is used to drive the two first / second MOS transistors connected in parallel in different current states: both are in a closed state, both are in an open state, or one is opened and the other is closed; one end of the third MOS transistor is connected to the first AC output end, one end of the fourth MOS transistor is connected to the second AC output end, the other ends of the third MOS transistor and the fourth MOS transistor are both connected to the DC output end of the rectifier, the gate of the third MOS transistor is connected to the output of the second gate control circuit via a first boost circuit, and the gate of the fourth MOS transistor is connected to the output of the first gate control circuit via a second boost circuit.

[0067] It should be noted that this embodiment takes the example that each group of low-bit MOS tubes includes two parallel MOS tubes. In the present disclosure, the number (several) of parallel MOS tubes can be a positive integer N, N≥2, the first number N1+the second number N2=N, and the ratio of the first number N1 to the second number N2 can be changed.

[0068] The following is a detailed description of the various parts of the synchronous rectifier of this embodiment in conjunction with the accompanying drawings. The source-drain sequence in the accompanying drawings is only an example, and in other embodiments, the source-drain sequence corresponding to the embodiment may be different as long as the corresponding working mode can be achieved.

[0069] In this embodiment, Figure 1 As shown, for the convenience of introduction, the two first MOS transistors connected in parallel are respectively: a first first MOS transistor M1_L and a second first MOS transistor M1_M, and the two second MOS transistors connected in parallel are respectively: a first second MOS transistor M2_L and a second second MOS transistor M2_M.

[0070] Among them, refer to Figure 1 and Figure 2 As shown, one end of the first MOS transistor is connected to the first AC output terminal AC1, that is, one end (source) of the first first MOS transistor M1_L and the second first MOS transistor M1_M are both connected to the first AC output terminal AC1, and the other end (corresponding to the drain) is grounded. One end of the second MOS transistor is connected to the second AC output terminal AC2, that is: one end (source) of the first second MOS transistor M2_L and the second second MOS transistor M2_M are both connected to the second AC output terminal AC2, and the other end (corresponding to the drain) is grounded.

[0071] like Figure 1 As shown, the gates of the two first MOS transistors connected in parallel are respectively: a first first gate G1_L and a second first gate G1_M, that is, the gate of the first first MOS transistor M1_L is the first first gate G1_L, and the gate of the second first MOS transistor M1_M is the second first gate G1_M.

[0072] The gates of the two second MOS transistors connected in parallel are respectively: a first second gate G2 L and a second second gate G2_M, that is, the gate of the first second MOS transistor M2_L is the first second gate G2_L, and the gate of the second second MOS transistor M2_M is the second second gate G2_M.

[0073] In the present disclosure, the gates of the two first MOS tubes connected in parallel are connected in parallel to the first gate voltage control circuit through switches. The first gate voltage control circuit is used to drive the two first MOS tubes connected in parallel in different current states: both are in the off state, both are in the on state, or one is on and the other is off.

[0074] Reference Figure 1 As shown, the first first gate G1_L and the second first gate G1_M are respectively connected in parallel to the first gate voltage control circuit 11 through switches, and the first gate voltage control circuit 11 is used to drive the first first gate G1_L and the second first gate G1_M correspondingly under different current states to control the first first MOS tube M1_L and the second first MOS tube M1_M: both are in the off state, both are in the on state, or one is on and the other is off.

[0075] In the present disclosure, the gates of the two second MOS tubes connected in parallel are connected in parallel to the second gate voltage control circuit through switches. The second gate voltage control circuit is used to drive the two second MOS tubes connected in parallel in different current states: both are in the off state, both are in the on state, or one is on and the other is off.

[0076] Reference Figure 1 As shown, the first second gate G2_L and the second second gate G2_M are respectively connected in parallel to the second gate voltage control circuit 12 through switches, and the second gate voltage control circuit 12 is used to drive the first second gate G2_L and the second second gate G2_M correspondingly under different current states to control the first second MOS tube M2_L and the second second MOS tube M2_M: both are in the off state, both are in the on state, or one is on and the other is off.

[0077] In this embodiment, refer to Figure 1 As shown, the first gate voltage control circuit 11 and the second gate voltage control circuit 12 have the same structure. The gate voltage control circuit (including the first gate voltage control circuit 11 and the second gate voltage control circuit 12) includes: an operational amplifier and a dual reference voltage switch. One of the two input terminals of the operational amplifier is the first AC input terminal / the second AC input terminal, and the other input terminal is the output of the dual reference voltage switch. The output terminal of the operational amplifier is connected to the input terminal of the dual reference voltage switch, and the output terminal of the operational amplifier serves as the external output terminal of the gate voltage control circuit.

[0078] In each group of low-order MOS tubes, the external input end of the gate voltage control circuit is connected to the first AC input end / the second AC input end, and the external output end of the gate voltage control circuit is also connected to the gate of the high-order MOS tube connected to the second AC input end / the first AC input end via a boost circuit. Of course, as mentioned above, the gates of the two parallel low-order MOS tubes are respectively connected in parallel to the external output end of a gate voltage control circuit through switches. The external output end of the corresponding gate voltage control circuit has two connection paths, one path is used to provide gate voltage for the low-order MOS tube and control the working state of the two parallel low-order MOS tubes, and the other path provides gate voltage for the high-order MOS tube.

[0079] The above “A / B...C / D” in the same paragraph means that A and C are a group of situations, B and D are a group of situations, and the two situations correspond to each other in an or relationship.

[0080] The first gate voltage control circuit 11 includes: a first operational amplifier OA1 and a first dual reference voltage switch DRS1. Among them, one of the two input terminals of the first operational amplifier OA1 is the first AC output terminal AC1, and the other input terminal is the output of the first dual reference voltage switch DRS1. The output G1 of the first operational amplifier OA1 is connected to the input terminal of the first dual reference voltage DRS1. At the same time, one path of the output G1 of the first operational amplifier OA1 is connected to the respective gates of the two first MOS transistors connected in parallel: the first first gate G1_L and the second first gate G1_M through the switch, and the other path is connected to the gate of the fourth MOS transistor M4 - the fourth gate G4 through the second boost circuit BC2.

[0081] Similarly, continue to refer to Figure 2 As shown, the second gate voltage control circuit 12 includes: a second operational amplifier OA2 and a second dual reference voltage switch DRS2. ​​Among them, one of the two input terminals of the second operational amplifier OA2 is the second AC output terminal AC2, and the other input terminal is the output of the second dual reference voltage switch DRS2. ​​The output G2 of the second operational amplifier OA2 is connected to the input terminal of the second dual reference voltage DRS2. ​​At the same time, one path of the output G2 of the second operational amplifier OA2 is connected to the respective gates of the two second MOS transistors connected in parallel: the first second gate G2_L and the second second gate G2_M through the switch, and the other path is connected to the gate of the third MOS transistor M3 - the third gate G3 through the first boost circuit BC1.

[0082] By using a dual reference voltage switch, the first and second gate voltage controls achieve a hysteresis effect, thereby making the control voltage more stable and enhancing the rectifier's anti-interference ability to environmental noise and the like.

[0083] Reference Figure 1 and Figure 2As shown, one end (drain) of the third MOS tube M3 is connected to the first AC output terminal AC1, one end (drain) of the fourth MOS tube M4 is connected to the second AC output terminal AC2, the other ends (corresponding to the source) of the third MOS tube M3 and the fourth MOS tube M4 are connected in parallel to the DC output terminal VRECT of the rectifier, the gate of the third MOS tube M3 is the third gate G3, and the third gate G3 is connected to the output G2 of the second gate voltage control circuit 12 via the first boost circuit BC1, and the gate of the fourth MOS tube M4 is the fourth gate G4, and the fourth gate G4 is connected to the output G1 of the first gate voltage control circuit 11 via the second boost circuit BC2. That is to say, the output G1 of the first gate voltage control circuit 11 is used as the control gate voltage of the fourth MOS tube M4 after being boosted and converted by the second boost circuit BC2, and the output G2 of the second gate voltage control circuit 12 is used as the control gate voltage of the third MOS tube M3 after being boosted and converted by the first boost circuit BC1. The two parallel first MOS tubes: the first first MOS tube M1_L and the second first MOS tube M1_M, and the two parallel second MOS tubes: the first second MOS tube M2_L and the second second MOS tube M2_M are all low-position MOS tubes. The third MOS tube M3 and the fourth MOS tube are all high-position MOS tubes.

[0084] Reference Figure 1 As shown in the figure, the load capacitor C connected after the AC is converted into DC through the structure of the above MOS tube L And the corresponding load circuit I Load Of course, other conventional structures will not be described in detail.

[0085] The synchronous rectifier disclosed in the present invention has four working modes, namely: a passive mode, a half mode and two full modes. The two full modes are respectively described as a first full mode 1 and a second full mode 2.

[0086] Below is the attached figure Figure 3-Figure 10 Provide a detailed introduction.

[0087] Figure 4 , Figure 6 , Figure 8 and Fig.10 In the figure, AC1 is the open-circuit voltage waveform of the first AC output terminal, AC2 is the open-circuit voltage waveform of the second AC output terminal; I_AC represents the current waveform from the first AC output terminal AC1 to the second AC output terminal AC2; in the above figure, the waveform inflection points of AC1 and AC2 in each on (on) and off state (off) are circled with dotted lines.

[0088] 1. Passive mode

[0089] Figure 3 For Figure 1 FIG. 4 is an equivalent circuit diagram of a synchronous rectifier in a passive mode. Figure 4 For Figure 3 The corresponding circuit working timing diagram.

[0090] The passive mode corresponds to low current by default. The current I range of low current is: 0<I≤1mA, refer to Figure 3 As shown, in the passive mode, the first gate voltage control circuit 11 in the synchronous rectifier drives the first MOS tube M1_L and the second MOS tube M1_M to be in a closed state, and the second gate voltage control circuit 12 drives the first second MOS tube M2_L and the second second MOS tube M2_M to be in a closed state, and the high-order MOS tube - the third MOS tube M3 and the fourth MOS tube M4 are also in a closed state. The closed state is as shown in FIG. Figure 3 The dashed box with × in the middle indicates the corresponding Figure 4 In the figure, the gate voltages of G1 (corresponding to G1_L and G1_M are both off), G2 (corresponding to G2_L and G2_M are both off), G3 and G4 are all in a straight line. In order to simplify the description, the following description is only indicated by symbols, and the corresponding component names can be referred to in the previous text. In the above state, only the parasitic diodes in each MOS tube work for rectification. At a certain moment, the current path is as follows Figure 3 As shown by the dashed arrows, the currents of the two branches are from the ground (corresponding to Figure 4 GND in M2_M and M2_L) flows in parallel to AC2 along the parasitic diodes of M2_M and M2_L, and a current flows from AC1 along the parasitic diode in M3 to VRECT. Of course, this process corresponds to Figure 3 In the state where M3 (parasitic diode) changes from M3 on to M3 off, the corresponding M4 is low and in the off state. Correspondingly, when M4 (parasitic diode) changes from M4 on to M4 off, M3 is low and in the off state. The current flow direction is as follows: Figure 3 By making the left and right symmetry in , we can get: the currents of the two branches flow from the ground along the parasitic diodes of M1_M and M1_L in parallel to AC1, and one branch of current flows from AC2 along the parasitic diode in M4 to VRECT.

[0091] In the passive mode, corresponding to the low current situation, both the high-order MOS tube and the low-order MOS tube do not work and are in the off state, and the corresponding parasitic diodes of each MOS tube work; the rectification efficiency is between 70% and 80%, and the power loss is low due to the low current.

[0092] (2) Half mode

[0093] Figure 5 For Figure 1 FIG. 4 is an equivalent circuit diagram of a synchronous rectifier in half mode. Figure 6 For Figure 5 The corresponding circuit working timing diagram.

[0094] The half-open mode works under low current conditions, and the current I range of the low current is: 1mA<I≤5mA. In the half-open mode, if Figure 5 As shown, the high-order MOS tube is in the on state, and the low-order MOS tube is in the off state. Figure 5 The dashed box with × in the middle indicates the corresponding Figure 6 In the figure, the gate voltages of G1 (corresponding to G1_L and G1_M being turned off) and G2 (corresponding to G2_L and G2_M being turned off) are both in a straight line. The rising edge of G3 corresponds to the inflection point after the AC1 waveform rises. Figure 5 In the figure, G3 on is used as an example. The falling edge of G3 corresponds to the turning point before the AC1 waveform falls. Figure 5 In the figure, G3 off is used as an example; similarly, the rising edge of G4 corresponds to the turning point after the AC2 waveform rises. Figure 5 In the figure, G4 on is used as an example. The falling edge of G4 corresponds to the turning point before the AC2 waveform falls. Figure 5 The waveforms of G3 and G4 indicate the states and timings of the third MOS tube M3 and the fourth MOS tube M4 being turned on. Figure 5 and Figure 6 The description of the working current path is similar to the previous one. At a certain moment, the current path is referenced Figure 5 The dotted arrows in the middle indicate that the currents of the two branches flow from the ground along the parasitic diodes of M2_M and M2_L in parallel to AC2, and one current flows from AC1 along the third MOS tube M3 to VRECT. Different from the above passive mode, M3 is in working state and is not rectified by parasitic diodes. The symmetrical rectification path of M4 in the on state can be obtained symmetrically with reference to the above description, which will not be repeated here.

[0095] In the half-open mode, corresponding to the small current situation, the high-order MOS tubes are all turned on, the low-order MOS tubes are all turned off, and the rectification efficiency is 80% to 85%.

[0096] (III) Full mode 1

[0097] Figure 7 For Figure 1 FIG. 4 is a circuit structure equivalent diagram of a synchronous rectifier in a first full-on mode (full mode 1). Figure 8 For Figure 7 The corresponding circuit working timing diagram.

[0098] The first full-open mode works under low current conditions, and the current I range of the low current is: 1mA<I≤5mA. In the first full-open mode, if Figure 7 As shown, the high-order MOS tube is turned on, and only half of the low-order MOS tubes in the two groups are turned on, and the other half are turned off. For example, in this embodiment, M1_L and M2_L are turned on, and M1_M and M2_M are turned off. Figure 8 The waveforms corresponding to G3 and G4 are similar to those in the half-open mode, so we will not go into details here. The following only introduces how to obtain Figure 8 There are two ways to describe the gate voltage corresponding to the low-order MOS tube shown. One is as follows: in the aforementioned structure, G2 is connected to G3 of M3 through BC1, and the waveform of G2 is consistent with that of G3. G1 is connected to G4 of M4 through BC2, and the waveform of G1 is consistent with that of G4. Then, when M1_L and M2_L are turned on and M1_M and M2_M are turned off, the input of the gate G2_L of M2_L is G2, and the waveform of G2_L is consistent with that of G3. Similarly, the input of the gate G1_L of M1_L is G1, and the waveform of G1_L is consistent with that of G4. Another way is that the rising edge of G1_L corresponds to the inflection point after AC1 falls, the falling edge of G1_L corresponds to the inflection point before AC1 rises, the rising edge of G2_L corresponds to the inflection point after AC2 falls, and the falling edge of G2_L corresponds to the inflection point before AC2 rises. Figure 8 The arrows in the figure show this method, which is also based on structural analysis. Figure 7 The dotted arrows in the middle indicate that the currents of the two branches flow from the ground along the parasitic diode of M2_M and M2_L in parallel to AC2, and one current flows from AC1 along the third MOS tube M3 to VRECT. Unlike the aforementioned half-open mode, M2_L is in a working state and is not rectified by a parasitic diode. The rectification path of the symmetrical M2_L in the open state can be obtained symmetrically with reference to the above description, which will not be repeated here; in addition, the same as the half-open mode, the opening of M3 and M4 is the same as it, which will not be repeated here.

[0099] In the first fully-on mode, corresponding to the low current situation, the high-order MOS tubes are all turned on, and the low-order MOS is half turned on and half turned off, with an efficiency of 92% to 99%, resulting in small system losses and low system heat generation. In the first fully-on mode, the rectification efficiency is improved in the case of small current.

[0100] Comparing the two working modes (ii) and (iii), the current ranges corresponding to different working modes can also be adjusted by setting the number of MOS tubes turned on and off in the low-position MOS tubes connected in parallel in each group of low-position MOS tubes, that is, by setting different first numbers N1 and second numbers N2. Since the working ranges of the half-open mode and the first fully-open mode overlap, both work in a small current (1mA to 5mA) range, the switching between the half-open mode and the first fully-open mode is achieved by changing the ratio of the MOS tubes turned on and off in each group of low-position MOS tubes, that is, by changing the ratio of the first number N1 to the second number N2, the current ranges of the half-open mode and the first fully-open mode are adjusted so that the current ranges of the two modes do not overlap and can be switched. For example, each group of low-bit MOS tubes has 55, and the ratio of the first number to the second number can be set to 1:4, that is, in each group of low-bit MOS tubes, 11 low-bit MOS tubes are turned on and 44 low-bit MOS tubes are turned off. When N1:N2=1:4, the corresponding half-open mode works at 1-3mA, and the first fully-open mode works at 3-5mA, so that the working currents of the half-open mode and the first fully-open mode do not overlap, and effective switching can be performed; the ratio of the first number to the second number can also be set to 1:10, that is, in each group of low-bit MOS tubes, 5 low-bit MOS tubes are turned on and 50 low-bit MOS tubes are turned off. When N1:N2=1:10, the half-open mode works at 1-2mA, and the first fully-open mode works at 2-5mA, so that the working currents of the half-open mode and the first fully-open mode do not overlap, and effective switching can be performed. It can be seen from the above-mentioned setting examples of the first quantity and the second quantity that by changing the ratio of the number of turned-on and turned-off low-position MOS tubes in each group, the working currents corresponding to the half-open mode and the first fully-open mode can be controlled to have no overlap and effective switching can be achieved, and the specific current value range is regulated by changing the ratio of turned-on and turned-off MOS tubes.

[0101] (IV) Full Mode 2

[0102] Fig. 9 For Figure 1 FIG. 4 is a circuit structure equivalent diagram of the synchronous rectifier in the second full-on mode (full mode 2). Fig.10 For Fig. 9 The corresponding circuit working timing diagram.

[0103] The second fully open mode works under medium to large current conditions, and the current I range of medium to large current is: I>5mA. Compared with the first fully open mode, the second fully open mode has a different operating current range. The difference in the circuit structure under the working mode is that the low-level MOS tubes in the second fully open mode are all turned on, not half turned on and half turned off in the first fully open mode. Fig. 9 and Fig.10As shown, in the second fully-on mode, the high-order MOS tube and the low-order MOS tube are all turned on, G1 (corresponding to both G1_L and G1_M being turned on), G2 (corresponding to both G2_L and G2_M being turned on), G3 and G4 are all turned on, and the waveform of G1_L and G1_M being turned on in parallel at the same time is similar to the waveform of a single MOS tube being turned on, and you can refer to the introduction of the first fully-on mode.

[0104] In the second fully-on mode, corresponding to the medium to large current situation, both the high-order MOS tubes are turned on, both the low-order MOS tubes are turned on, and the efficiency is between 95% and 99%.

[0105] It should be noted that in the above introduction, the correspondence between the rising edge or falling edge of the gate waveform and the inflection points of AC1 and AC2 is only an example. In other embodiments, the order of the rising edge and the falling edge can be swapped as long as the corresponding situations are consistent in the same structure.

[0106] Second embodiment

[0107] In a second exemplary embodiment of the present disclosure, a wireless charging system is provided. The wireless charging system includes any one of the synchronous rectifiers mentioned in the present disclosure.

[0108] In a specific example, the chip of the wireless charging system may be integrated with a synchronous rectifier or the circuit structure of the wireless charging system may include a synchronous rectifier structure.

[0109] In summary, the present disclosure provides a synchronous rectifier and a wireless charging system, which are respectively connected to the two ends of the AC output by setting two groups of low-order MOS tubes, one end of two high-order MOS tubes is respectively connected to the two ends of the AC output, and the other end is connected to the DC output end of the synchronous rectifier, and the gate voltage control circuit controls the on-off state of a plurality of low-order MOS tubes in parallel in each group of low-order MOS tubes, and the plurality of low-order MOS tubes in parallel have the following working states: simultaneously closed, the first number of low-order MOS tubes are opened, the second number of low-order MOS tubes are closed, and simultaneously opened, and the corresponding synchronous rectifier can work under low current (0-1mA), small current (1mA-5mA) and medium-large current (greater than 5mA), and the efficiency can reach up to 95%-99%, and it is suitable for a wide range of output currents, for various current value ranges. The alternating current can be rectified with high efficiency and has a wide range of application prospects; the synchronous rectifier corresponds to four working modes, namely, a passive mode, a half-open mode, a first fully-open mode and a second fully-open mode, wherein the working ranges of the half-open mode and the first fully-open mode overlap, and the non-overlapping working current range and the switching of the two modes can be achieved by setting the ratio of the number of MOS tubes turned on and off in each group of low-position MOS tubes, and the rectification efficiency in each mode is higher than or at least equal to that of the prior art, wherein especially in the first fully-open mode, corresponding to the low current situation, the rectification efficiency of up to 92% to 99% can be achieved, which effectively improves the rectification efficiency; in one embodiment, by using the output of the gate voltage control circuit (corresponding to the external output terminal) as the gate voltage control of the high and low-position MOS tubes at the same time, the circuit is simplified and synchronous control is achieved.

[0110] It should be emphasized that the ordinal numbers used in the specification and claims, such as "first", "second", "third", etc., to modify the corresponding elements, do not mean that the elements have any ordinal number, quantity or importance, nor do they represent the order of one element and another element, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a component with a certain name clearly distinguishable from another component with the same name. "First first A" and "second first A" represent the specific designations of two "first A", and "first second B" and "second second B" represent the designations of two "second B".

[0111] Furthermore, the words "comprise" or "include" and the like are open-ended and do not exclude other elements, components, parts or items than those explicitly listed. The words "connect" or "connected" and the like are not limited to physical, mechanical or electrical connections, whether direct or indirect. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

[0112] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above description is only a specific embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A synchronous rectifier, characterized in that: include: Two groups of low-bit MOS tubes, each group of low-bit MOS tubes has a plurality of low-bit MOS tubes connected in parallel, the source and drain of one group of low-bit MOS tubes are respectively connected to: the first AC output terminal and the ground, and the source and drain of the other group are respectively connected to: the second AC output terminal and the ground; Two high-order MOS tubes, wherein the source and drain of one high-order MOS tube are respectively connected to: a first AC output terminal and a DC output terminal of the synchronous rectifier, and the source and drain of the other high-order MOS tube are respectively connected to: a second AC output terminal and a DC output terminal of the synchronous rectifier; Among them, in each group of low-bit MOS tubes, the gates of the plurality of parallel low-bit MOS tubes are respectively connected in parallel to the external output end of a gate voltage control circuit through switches, and the gate voltage control circuit is used to drive the plurality of parallel low-bit MOS tubes in different current states: all are in the off state, all are in the on state, or a first number of low-bit MOS tubes are turned on and a second number of low-bit MOS tubes are turned off; Wherein, the gates of the two high-position MOS tubes are respectively connected to the gate voltage control circuit on the branch corresponding to the other AC input terminal opposite to the AC input terminal connected to the gate via a boost circuit; Wherein, the synchronous rectifier operates in a passive mode, or the synchronous rectifier operates in a half-open mode, or the synchronous rectifier operates in a first full-open mode, or the synchronous rectifier operates in a second full-open mode; In the passive mode, both the high-order MOS tube and the low-order MOS tube are in a closed state, and the parasitic diodes of the corresponding MOS tubes work; in the half-open mode, all the high-order MOS tubes are turned on, and all the low-order MOS tubes are turned off; in the first fully-open mode, all the high-order MOS tubes are turned on, and a first number of the low-order MOS tubes in parallel in each group of two groups of low-order MOS tubes are turned on, and a second number of the low-order MOS tubes are turned off; in the second fully-open mode, all the high-order MOS tubes are turned on, and all the low-order MOS tubes are turned on.

2. The synchronous rectifier according to claim 1, characterized in that: In each group of low-bit MOS tubes, the external input end of the gate voltage control circuit is connected to the first AC input end / the second AC input end.

3. The synchronous rectifier according to claim 2, characterized in that: In each group of low-bit MOS tubes, the gate voltage control circuit includes: an operational amplifier and a dual reference voltage switch.

4. The synchronous rectifier according to claim 3, characterized in that: One of the two input terminals of the operational amplifier is a first AC input terminal / a second AC input terminal, and the other input terminal is the output of a dual reference voltage switch. The output terminal of the operational amplifier is connected to the input terminal of the dual reference voltage switch, and the output terminal of the operational amplifier serves as an external output terminal of the gate voltage control circuit.

5. The synchronous rectifier according to claim 1, characterized in that: The passive mode corresponds to low current being enabled by default, and the current I range of the low current is: 0<I≤1mA.

6. The synchronous rectifier according to claim 1, characterized in that: The half-open mode works under a small current, and the current I range of the small current is: 1mA<I≤5mA.

7. The synchronous rectifier according to claim 1, characterized in that: The first full-open mode operates under a small current, and the current I range of the small current is: 1mA<I≤5mA.

8. The synchronous rectifier according to claim 1, characterized in that: The second full-open mode operates at medium to large currents, and the current I range of the medium to large currents is: I>5mA.

9. A wireless charging system, characterized in that: A synchronous rectifier comprising any one of claims 1 to 8.

Images