Three-dimensional integrated circuit structure

Abstract

A three-dimensional integrated circuit structure includes a tube die stacking structure, a metal circuit structure and a protection structure. The tube die stacking structure includes a first tube die and a second tube die bonded together face to face. The metal circuit structure is arranged on the back side of the second tube die. The protection structure is arranged in the back side of the second tube die and separates one of a plurality of substrate through holes of the second tube die from the metal circuit structure.

Description

Technical Field

[0001] An embodiment of the present invention relates to a three-dimensional integrated circuit structure. Background Art

[0002] In recent years, the semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). This improvement in integration density comes from the repeated reduction of the minimum feature size to allow more smaller components to be integrated in a certain area.

[0003] These smaller electronic components also require smaller packages that utilize less area than previous packages. Exemplary types of semiconductor packages include quad flat package (QFP), pin grid array (PGA), ball grid array (BGA), flip chip (FC), three dimensional integrated circuit (3DIC), wafer level package (WLP), and package on package (PoP) devices. Some three dimensional integrated circuits are prepared by placing a chip on top of a chip at the semiconductor wafer level. Because the length of the internal connections between the stacked chips is reduced, the three dimensional integrated circuit provides higher integration density and other advantages, such as faster speed and higher bandwidth. However, there are still many challenges to be addressed for three dimensional integrated circuit technology. Summary of the invention

[0004] An embodiment of the present invention provides a three-dimensional integrated circuit structure, including a die stacking structure, a metal circuit structure and a protection structure. The die stacking structure includes a first die and a second die bonded together face to face. The metal circuit structure is disposed on the rear side of the second die. The protection structure is disposed in the rear side of the second die and separates one of a plurality of substrate through-holes of the second die from the metal circuit structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The various aspects of the present invention will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0006] Figure 1A to Figure 1E is a cross-sectional view of a method of forming a three-dimensional integrated circuit (3DIC) structure according to a first embodiment.

[0007] Figure 2 is a cross-sectional view of a three-dimensional integrated circuit structure according to a second embodiment.

[0008] Figure 3 is a cross-sectional view of a three-dimensional integrated circuit structure according to a third embodiment.

[0009] Figure 4 is a cross-sectional view of a package according to some embodiments. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples of different features for implementing the provided objectives. The specific examples of components and configurations described below are for the purpose of conveying the present disclosure in a simplified manner. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. The repetition of reference numbers is for simplicity and clarity, and does not represent the relationship between the various embodiments and / or configurations to be discussed.

[0011] Additionally, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the component in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative terms used herein interpreted accordingly.

[0012] Other features and processes may also be included. For example, test structures may be included to facilitate verification testing of a three-dimensional (3D) package or a three-dimensional integrated circuit device. The test structures may include, for example, test pads formed in a redistribution layer or on a substrate that enable testing of a 3D package or 3DIC, using probes and / or probe cards, etc. Verification testing may be performed on intermediate structures and final structures. In addition, the structures and methods disclosed herein may be used in conjunction with test methods including intermediate verification of known good dies to improve yield and reduce costs.

[0013] Figure 1A to Figure 1Eis a cross-sectional view of a method for forming a three-dimensional integrated circuit structure according to a first embodiment.

[0014] Reference Figure 1A , forming a die stacking structure 10. Specifically, the die stacking structure 10 includes a first die 100, a second die 200 and a hybrid bonding structure 250. The first die 100 and the second die 200 are hybrid bonded together by the hybrid bonding structure 250. The die stacking structure 10 is formed according to, for example, the following steps.

[0015] like Figure 1A As shown, a first die 100 including a first semiconductor substrate 102 , a first device layer 103 , a first interconnect structure 104 and a first passivation layer 110 is provided.

[0016] In some embodiments, the semiconductor substrate 102 may include silicon or other semiconductor materials. Alternatively or additionally, the first semiconductor substrate 102 may include other elemental semiconductor materials, such as germanium. In some embodiments, the first semiconductor substrate 102 is made of compound semiconductors such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. In some embodiments, the first semiconductor substrate 102 is made of alloy semiconductors such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In some embodiments, the first semiconductor substrate 102 includes an epitaxial layer. For example, the first semiconductor substrate 102 has an epitaxial layer overlying a bulk semiconductor.

[0017] In some embodiments, the first device layer 103 is formed on the first semiconductor substrate 102 in a front-end-of-line (FEOL) process. The first device layer 103 includes a variety of devices. In some embodiments, the device includes active components, passive components, or a combination thereof. In some embodiments, the device may include an integrated circuit device. The device is, for example, a transistor, a capacitor, a resistor, a diode, a photodiode, a fuse device, or other similar devices. In some embodiments, the first device layer 103 includes a gate structure, a source region and a drain region, and an isolation structure, such as a shallow trench isolation (STI) structure (not shown). In the first device layer 103, various N-type metal oxide semiconductor (NMOS) and / or P-type metal oxide semiconductor (PMOS) devices (such as transistors or memories, etc.) can be formed and interconnected to perform one or more functions. Other devices, such as capacitors, resistors, diodes, photodiodes, fuses, etc., can also be formed on the first semiconductor substrate 102. The functions of the device may include memory, processors, sensors, amplifiers, power distribution, input / output circuits, etc.

[0018] Reference Figure 1A, the first interconnect structure 104 is formed on the first device layer 103. In detail, the first interconnect structure 104 includes a first insulating material 106 and a plurality of first metal features 108. The first metal features 108 are formed in the first insulating material 106 and are electrically connected to the first device layer 103. A portion of the first metal features 108 (e.g., top metal features 108a and 108b) is exposed by the first insulating material 106. In some embodiments, the first insulating material 106 includes an inner-layer dielectric (ILD) layer located on the first device layer 103 and at least one inter-metal dielectric (IMD) layer located on the inter-layer dielectric layer. In some embodiments, the first insulating material 106 includes silicon oxide, silicon oxynitride, silicon nitride, a low dielectric constant (low-k) material, or a combination thereof. In some alternative embodiments, the first insulating material 106 may be a single layer or multiple layers. In some embodiments, the first metal features 108 include plugs and metal lines. The plug may include contacts formed in an interlayer dielectric layer and vias formed in an intermetallic dielectric layer. The contact is formed between the first device layer 103 and the bottom metal line and connected to the first device layer 103 and the bottom metal line. The via is formed between the two metal lines and connected to the two metal lines. The first metal feature 108 may be made of tungsten (W), copper (Cu), copper alloy, aluminum (Al), aluminum alloy, or a combination thereof. In some alternative embodiments, a barrier layer (not shown) may be formed between the first metal feature 108 and the first insulating material 106 to prevent the material of the first metal feature 108 from migrating or diffusing to the first device layer 103. The material of the barrier layer includes, for example, tantalum, tantalum nitride, titanium, titanium nitride, cobalt-tungsten (CoW), or a combination thereof.

[0019] Reference Figure 1A , a first passivation layer 110 is formed on the first interconnect structure 104. The first passivation layer 110 covers the first insulating material 106 and some portions of the top metal features 108a and 108b. In some embodiments, the first passivation layer 110 includes silicon oxide, silicon nitride, benzocyclobutene (BCB) polymer, polyimide (PI), polybenzoxazole (PBO), or a combination thereof, and is formed by a suitable process such as spin coating, chemical vapor deposition, etc. After the first passivation layer 110 is formed on the first interconnect structure 104, the first die 100 is completed. Figure 1AAs shown, the first die 100 has a front side 100a and a back side 100b opposite to each other. Herein, the front side 100a of the first die 100 faces upward, while the back side 100b of the first die 100 faces downward. In some embodiments, the front side 100a of the first die 100 is referred to as an active surface.

[0020] Reference Figure 1A , a first bonding structure 114 is formed on the front side 100a of the first die 100. In detail, the first bonding structure 114 includes a first bonding dielectric layer 116 and a plurality of first bonding metal layers 118 and 120. In some embodiments, the first bonding metal layers 118 and 120 are formed in the first bonding dielectric layer 116. The first bonding metal layer 118 includes a via plug 118a and a metal feature 118b disposed on the via plug 118a, and the first bonding metal layer 120 includes a via plug 120a and a metal feature 120b disposed on the via plug 120a. Figure 1A As shown, the via plug 118 a penetrates the first passivation layer 110 and is connected to the first metal feature 108 a , while the via plug 120 a penetrates the first passivation layer 110 and is connected to the first metal feature 108 b .

[0021] In some embodiments, the first bonding metal layers 118 and 120 may include copper, copper alloys, nickel, aluminum, tungsten, or combinations thereof. In some embodiments, the first bonding metal layers 118 and 120 may use the same material and be formed simultaneously. In some other embodiments, the first bonding metal layers 118 and 120 may use different materials and be formed sequentially. The first bonding metal layers 118 and 120 may be formed by depositing a conductive material in the grooves and through-hole openings (not shown) in the first bonding dielectric layer 116, and then removing the conductive material on the top surface of the first bonding dielectric layer 116 by a planarization process (e.g., a chemical mechanical polishing process). After the planarization process, the top surface of the first bonding dielectric layer 116 is substantially coplanar with the top surfaces of the first bonding metal layers 118 and 120.

[0022] Reference Figure 1A , the second die 200 is similar to the second die 100. That is, the second die 200 includes a second semiconductor substrate 202, a second device layer 203, a second interconnect structure 204, a second insulating material 206 and a second passivation layer 210. The configuration, materials and formation method of the second die 200 are similar to those of the first die 100. Therefore, the details are omitted here. In some embodiments, the size of the second die 200 is smaller than the size of the first die 100. As used herein, the term "size" refers to length, width or area. For example, Figure 1A As shown, the length of the second die 200 is shorter than the length of the first die 100 .

[0023] In some embodiments, one of the first die 100 and the second die 200 may be, for example, an application-specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless and radio frequency chip, a voltage regulator chip, or a memory chip. In some alternative embodiments, the first die 100 and the second die 200 may include the same functions or different functions. Figure 1A The die stacking structure 10 shown is a chip-on-wafer (CoW) structure. For example, the second die 200 may be a die, the first die 100 may be a wafer, and the die 200 is disposed on the wafer 100. However, the embodiments of the present invention are not limited thereto. In other embodiments, the die stacking structure 10 includes a chip-on-chip structure, a die-on-die structure, or a combination thereof.

[0024] Reference Figure 1A , a second bonding structure 214 is formed on the front side 200a of the second die 200. In detail, the second bonding structure 214 includes a second bonding dielectric layer 216 and a second bonding metal layer 218. In some embodiments, the second bonding metal layer 218 is formed in the second bonding dielectric layer 216. The second bonding metal layer 218 includes a through-hole plug 218a and a metal feature 218b. Figure 1A As shown, via plug 218a penetrates the second passivation layer 210 and is connected to the second metal feature 208 of the second interconnect structure 204. Metal feature 218b is electrically connected to the second metal feature 208 through via plug 218a.

[0025] In some embodiments, the second bonding metal layer 218 may include copper, copper alloy, nickel, aluminum, tungsten, or a combination thereof. The second bonding metal layer 218 may be formed by depositing a conductive material in the grooves and via openings (not shown) in the second bonding dielectric layer 216, and then removing the conductive material on the top surface of the second bonding dielectric layer 216 by a planarization process (e.g., a chemical mechanical polishing process). After the planarization process, the top surface of the second bonding dielectric layer 216 is substantially coplanar with the top surface of the second bonding metal layer 218.

[0026] Reference Figure 1A, the second die 200 is further turned upside down and mounted on the first die 100. In detail, the first die 100 and the second die 200 are bonded together face-to-face through the first bonding structure 114 and the second bonding structure 214. In some embodiments, before the second die 200 is bonded to the first die 100, the first bonding structure 114 is aligned with the second bonding structure 214 so that the second bonding metal layer 218 can be bonded to the first bonding metal layer 118, and the first bonding dielectric layer 116 can be bonded to the second bonding dielectric layer 216. In some embodiments, the alignment of the first bonding structure 114 and the second bonding structure 214 can be achieved by using an optical sensing method. After the alignment is achieved, the first bonding structure 114 and the second bonding structure 214 are bonded together by hybrid bonding to form a hybrid bonding structure 250.

[0027] The first bonding structure 114 and the second bonding structure 214 are hybrid bonded together by applying pressure and heat. It should be noted that hybrid bonding involves at least two types of bonding methods, including metal-to-metal bonding and non-metal-to-non-metal bonding (such as dielectric-to-dielectric bonding or fusion bonding). Figure 1A As shown, the hybrid bonding structure 250 includes a first bonding metal layer 118 and a second bonding metal layer 218 bonded together by a metal-to-metal bonding method and a first bonding dielectric layer 116 and a second bonding dielectric layer 216 bonded together by a non-metal-to-non-metal bonding method. However, the embodiments of the present invention are not limited thereto. In other embodiments, the first bonding structure 114 and the second bonding structure 214 can be bonded together by other bonding methods (e.g., fusion bonding).

[0028] In addition, if Figure 1AAs shown, the second die 200 also includes a plurality of through-substrate vias (TSVs) 205. In some embodiments, the through-substrate vias 205 are formed in the second semiconductor substrate 202 to be electrically connected to the second interconnect structure 204. In some embodiments, one of the through-substrate vias 205 includes a conductive via and a liner (not shown) surrounding the sidewalls and bottom surface of the conductive via. The conductive via may include copper, copper alloy, aluminum, aluminum alloy, Ta, TaN, Ti, TiN, CoW, or a combination thereof. The liner may include a dielectric material, such as silicon oxide. In some embodiments, the through-substrate vias 205 do not initially penetrate through the second semiconductor substrate 202, and the bottom surface of the through-substrate vias 205 is still covered by the second semiconductor substrate 202. In a subsequent process, a thinning process is performed on the rear surface 202b of the second semiconductor substrate 202 to expose the top surface 205s of the through-substrate vias 205, and the through-substrate vias 205 may be connected to other components. In some embodiments, the thinning process may include a grinding process or a chemical mechanical polishing (CMP) process.

[0029] After the thinning process is performed, the rear surface 202b of the second semiconductor substrate 202 is lower than the top surface 205s of the substrate through-hole 205, so as to ensure that the substrate through-hole 205 can be connected to the metal circuit structure 400 (eg, Figure 1E 205s of the through-substrate via 205 is exposed, a nitride layer 220 (e.g., a silicon nitride layer) is formed over the second die 200. The nitride layer 220 conformally covers the surface of the through-substrate via 205 exposed by the second semiconductor substrate 202, the back surface 202b of the second semiconductor substrate 202, the sidewalls of the second die 200, and the top surface of the first bonding structure 114 that is not bonded to the second bonding structure 214. An oxide layer 222 (e.g., a silicon oxide layer) is conformally formed over the nitride layer 220. A nitride layer 224 (e.g., a silicon nitride layer) is conformally formed over the oxide layer 222. A dielectric layer 226 (e.g., a gap-fill dielectric layer) is formed over the first die 100 and encapsulates the second die 200. That is, the dielectric layer 226 covers the sidewalls of the second die 200 and the bottom surface 202a of the second semiconductor substrate 202. In some embodiments, the dielectric layer 226 may include an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), a molding compound, a molding underfill, a resin (e.g., an epoxy resin), a combination thereof, and the like.

[0030] Then, a planarization process (or referred to as a first planarization process) is performed. In some embodiments, the planarization process is a chemical mechanical polishing process. After the planarization process is performed, the excess dielectric layer 226, the excess nitride layer 224, the excess oxide layer 222, and the excess nitride layer 220 are removed to expose the top surface 205s of the through-substrate hole 205 and the top surface 222t of the remaining oxide layer 222, as shown in FIG. Figure 1A As shown. The remaining oxide layer 222 encapsulates a portion of the substrate through-hole 205 in the lateral direction. The remaining dielectric layer 226 encapsulates the second die 200 in the lateral direction to separate the second die 200 from another die (not shown) bonded on the first die 100. After performing the planarization process, the die stacking structure 10 is completed. In this case, the top surface 222t of the remaining oxide layer 222 can be referred to as the back side 200b of the second die 200. After performing the planarization process, the back side 200b of the second die 200, the top surface 205s of the substrate through-hole 205, and the top surface 226t of the remaining dielectric layer 226 are at substantially the same level. Herein, when elements are described as being "at substantially the same level", these elements are formed at substantially the same height in the same layer, or are embedded in the same position in the same layer. In some embodiments, the elements at substantially the same level are formed using the same process steps and are formed of the same material. In some embodiments, the tops of elements at substantially the same level are substantially coplanar. Figure 1A As shown, the back side 200 b of the second die 200 , the top surface 205 s of the through substrate via 205 , and the top surface 226 t of the remaining dielectric layer 226 are substantially coplanar.

[0031] It should be noted that after performing the planarization process (or referred to as the first planarization process) or the thinning process, a groove R1 is formed in the back side 200b of the second die 200. The groove R1 may be various defects, such as cracks, sharp morphology, bulges, etc. The groove R1 is formed because some undesirable particles may fall on the surface to be polished, and then performing the planarization process or the thinning process may damage the back side 200b of the second die 200. Figure 1AAs shown, the groove R1 extends along the direction D1 from the back side 200b of the second die 200 toward the hybrid bonding structure 250. The groove R1 recesses the substrate through-hole 205b of the second die 200 so that the top surface 205s' of the substrate through-hole 205b is lower than the top surface 205s of the substrate through-hole 205a. In addition, the top surface 205s' of the substrate through-hole 205b has an uneven surface or a sharp shape. In contrast, the top surface 205s of the substrate through-hole 205a that is not damaged by defects has a smooth surface or a flat surface.

[0032] Reference Figure 1B After the planarization process is performed, a conformal layer 305 is formed on the die stack structure 10. The conformal layer 305 conformally covers the back side 200b of the second die 200, the top surface 205s of the substrate through-hole 205, and the top surface 226t of the remaining dielectric layer 226. In addition, the conformal layer 305 also conformally and completely covers the surface of the groove R1 (or the top surface 205s' of the substrate through-hole 205b) to prevent plasma etching arcing during subsequent patterning. In some embodiments, when the groove R1 is detected, the conformal layer 305 can be formed to cover the surface of the groove R1. In some alternative embodiments, when the groove R1 is too slight to be detected, the conformal layer 305 can still be formed to cover the surface of the groove R1. The conformal layer 305 is formed by, for example, an atomic layer deposition (ALD) process. In some embodiments, the conformal layer 305 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In alternative embodiments, conformal layer 305 may be a single layer structure, a double layer structure, or a multi-layer structure. In other embodiments, the thickness of conformal layer 305 is arrive In this context, a conformal layer may be considered to be a layer having a uniform thickness and having a thickness less than (For example ) thickness difference.

[0033] In addition, in some embodiments, before forming the conformal layer 305, a nitride layer 304 (e.g., a silicon nitride layer) is formed on the second die 200. In some embodiments, the nitride layer 304 is formed by a suitable deposition process (e.g., a chemical vapor deposition process or an atomic layer deposition process), and the thickness of the nitride layer 304 is arrive In alternative embodiments, the thickness of conformal layer 305 is greater than the thickness of nitride layer 304. In other embodiments, nitride layer 304 and conformal layer 305 include the same material or different materials.

[0034] Reference Figure 1C , a chemical vapor deposition process is performed to form a filling layer 306 on the conformal layer 305. In some embodiments, the filling layer 306 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In other embodiments, the thickness of the filling layer 306 is arrive Since the conformal layer 305 has better step coverage than the filling layer 306, the conformal layer 305 can completely cover the surface of the groove R1 with a sharp morphology. In some embodiments, the conformal layer 305 and the filling layer 306 have the same material or different materials. In some alternative embodiments, the thickness of the filling layer 306 is greater than or equal to the thickness of the conformal layer 305. However, the embodiments of the present invention are not limited thereto.

[0035] After forming the filling layer 306, a mask pattern 307 is formed over the filling layer 306. In some embodiments, the mask pattern 307 includes a photoresist and is formed by a suitable process (e.g., spin coating and photolithography). After forming the mask pattern 307, an etching process is performed by using the mask pattern 307 as an etching mask to remove portions of the filling layer 306, the conformal layer 305, the nitride layer 304, the dielectric layer 226, the nitride layer 224, the oxide layer 222, and the nitride layer 220, thereby forming the opening 308. Figure 1C As shown, the opening 308 exposes the first bonding metal layer 120. After the opening 308 is formed, the mask pattern 307 is removed.

[0036] Reference Figure 1C and Figure 1D , a conductive material (not shown) is formed to fill the opening 308, and the conductive material is extended to cover the filling layer 306. A planarization process (or second planarization process) is performed to remove the conductive material, the filling layer 306, the conformal layer 305, and some portions of the nitride layer 304 and expose the top surface 205s of the through-substrate via 205. After the planarization process is performed, a through dielectric via (TDV) 310 is formed in the dielectric layer 226, and a protection structure 300 is formed in the back side 200b of the second die 200, as shown in FIG. Figure 1D The dielectric layer through hole 310 is formed in the dielectric layer 226 to electrically connect to the first bonding metal layer 120 and the metal circuit structure 400 to be formed (eg Figure 1E shown).

[0037] Reference Figure 1DIn some embodiments, the protection structure 300 includes a nitride layer 304 filled in the recess R1 , a conformal layer 305 , and a filling layer 306 . The conformal layer 305 is formed between the nitride layer 304 and the filling layer 306 . Figure 1D The protection structure 300 shown is a three-layer structure, however, the embodiments of the present invention are not limited thereto. In other embodiments, the protection structure 300 may include a single-layer structure, a double-layer structure, or a multi-layer (i.e., more than three-layer) structure. For example, the protection structure 300 may be made of only the conformal layer 305, or only the nitride layer 304 and the conformal layer 305, or only the conformal layer 305 and the filling layer 306. After performing the planarization process, the top surface 300t of the protection structure 300, the back side 200b of the second tube core 200, the top surface 205s of the substrate through-hole 205, the top surface 226t of the dielectric layer 226, and the top surface 310t of the dielectric layer through-hole 310 are substantially coplanar. Although Figure 1D Only one dielectric layer through-hole 310 is shown in FIG. 3 , but more than one dielectric layer through-hole 310 may be formed.

[0038] Reference Figure 1E , a metal circuit structure 400 is formed on the back side 200b of the second die 200 by a back-end-of-line (BEOL) process. After the metal circuit structure 400 is formed, the three-dimensional integrated circuit structure 1 is formed. In detail, a dielectric layer 402 is formed on the back side 200b of the second die 200 and the top surface 226t of the dielectric layer 226. A metal feature 404 is formed in the dielectric layer 402 by a patterning process and a suitable deposition process (e.g., a plating process). The metal feature 404 is electrically connected to the dielectric layer through-hole 310 and the substrate through-hole 205a that are not covered by the protective structure 300. In some embodiments, the dielectric layer 402 includes silicon oxide, silicon oxynitride, silicon nitride, a low dielectric constant (low-k) material, or a combination thereof. In some alternative embodiments, the dielectric layer 402 may be a single layer or multiple layers. In some embodiments, the metal feature 404 includes a plug and a metal line. The plug is formed between two metal lines and connected to the two metal lines. The metal feature 404 may be made of tungsten (W), copper (Cu), copper alloys, aluminum (Al), aluminum alloys, or combinations thereof.

[0039] After forming the metal feature 404, a passivation layer 406 is formed to cover the dielectric layer 402 and expose a portion of the metal feature 404. In some embodiments, the passivation layer 406 includes silicon oxide, silicon nitride, benzocyclobutene (BCB) polymer, polyimide (PI), polybenzoxazole (PBO), or a combination thereof and is formed by a suitable process (e.g., spin coating, chemical vapor deposition, etc.). A bonding pad 408 is formed on the passivation layer 406, and the bonding pad 408 extends to cover the metal feature 404. The material of the bonding pad 408 is different from the material of the first metal feature 404. In some embodiments, the material of the bonding pad 408 is softer than the material of the first metal feature 404. In some embodiments, the bonding pad 408 includes a metal material, such as aluminum, copper, nickel, gold, silver, tungsten, or a combination thereof. The bonding pad 408 can be formed by depositing a metal material layer by a suitable process (e.g., an electrochemical plating process, chemical vapor deposition, atomic layer deposition (ALD), physical vapor deposition, etc.), and then patterning the metal material layer.

[0040] It should be noted that the protection structure 300 filled in the groove R1 is disposed between the substrate through-hole 205b of the second die 200 and the metal feature 404 of the metal circuit structure 400 to separate or electrically isolate the substrate through-hole 205b of the second die 200 from the metal feature 404 of the metal circuit structure 400. Figure 1E As shown, the protection structure 300 completely covers the substrate through-hole 205b of the second tube core 200. Therefore, during the patterning process of the metal circuit structure 400, the substrate through-hole 205b with a sharp shape will not cause plasma etching arc discharge. In other words, the reliability and yield of the three-dimensional integrated circuit structure 1 are improved accordingly. On the other hand, although the substrate through-hole 205b is electrically isolated from the metal circuit structure 400, the signal of the second device layer 203 located below the substrate through-hole 205b can still be transmitted to the metal circuit structure 400 through other substrate through-holes (for example, the substrate through-hole 205a). Although Figure 1E Only two through-substrate vias 205a and 205b are shown in FIG. 3 , but more than two through-substrate vias 205a and 205b may be formed. That is, more than one protection structure 300 completely covers more than one through-substrate via 205b.

[0041] Figure 2 is a cross-sectional view of a three-dimensional integrated circuit structure according to a second embodiment.

[0042] Reference Figure 2 , the three-dimensional integrated circuit structure 2 of the second embodiment and Figure 1E The three-dimensional integrated circuit structure 1 of the first embodiment is similar to the three-dimensional integrated circuit structure 1 shown in the figure. The difference between them is that the number of the protection structures 300 of the three-dimensional integrated circuit structure 2 is multiple. The protection structure 300 includes protection structures 301 and 302. Figure 2 As shown, protection structures 301 and 302 are formed on the second semiconductor substrate 202 and both extend along a direction D1 from the back side 200b of the second die 200 toward the hybrid bonding structure 250. The protection structure 301 covers the substrate through-hole 205b of the second die 200, while the protection structure 302 does not cover any substrate through-hole 205 (including substrate through-holes 205a and 205b) of the second die 200. Specifically, the groove R2 obtained by the planarization process or the thinning process can be formed in the area where no substrate through-hole 205 is formed. The conformal layer 305 is deposited in both the grooves R1 and R2 to simultaneously form the protection structures 301 and 302. Although Figure 1E Only two protection structures 301 and 302 are shown, but more than two protection structures 301 and 302 may be formed.

[0043] Figure 3 is a cross-sectional view of a three-dimensional integrated circuit structure according to a third embodiment.

[0044] Reference Figure 3 , the three-dimensional integrated circuit structure 3 of the third embodiment and Figure 1E The three-dimensional integrated circuit structure 3 is similar to the three-dimensional integrated circuit structure 1 of the first embodiment shown. The difference between them is that the three-dimensional integrated circuit structure 3 includes a protection structure 303 extending from the back side 200b of the second tube core 200 into the hybrid bonding structure 250. After performing a planarization process or a thinning process, a groove R3 is formed. The groove R3 is deep and has a sharp morphology, so the conformal layer 305 can completely cover the uneven and sharp surfaces of the groove R3 and the groove R1 to prevent plasma etching arc discharge during the patterning process of the metal circuit structure 400. In some embodiments, the protection structure 303 extends from the back side 200b of the second tube core 200 to the interface 15 between the first bonding structure 114 of the first tube core 100 and the second bonding structure 214 of the second tube core 200.

[0045] Figure 4 is a cross-sectional view of a package according to some embodiments.

[0046] Reference Figure 4 , the three-dimensional integrated circuit structure 4 is mounted on the dielectric layer 11 through the adhesive layer 21. In some embodiments, the three-dimensional integrated circuit structure 4 can be one of the three-dimensional integrated circuit structures 1, 2 and 3 described above. The three-dimensional integrated circuit structure 4 includes a plurality of second dies 201a and 201b arranged in parallel on the first die 100. The second dies 201a and 201b are bonded together face to face with the first die 100. The number of the second dies 201a and 201b is not limited in the present disclosure.

[0047] In this embodiment, the three-dimensional integrated circuit structure 4 further includes a plurality of connectors 18 and a passivation layer 19. The connectors 18 are formed on the bonding pads 408 not covered by the passivation layer 410 and are electrically connected to the bonding pads 408 not covered by the passivation layer 410. For the purpose of clarity, Figure 4 Other components below the bonding pad 408 are not shown, such as Figure 1E The dielectric layer 402 and the metal feature 404 are shown. The connector 18 includes a solder bump, a gold bump, a copper bump, a copper pillar, a copper column, etc. The passivation layer 19 is formed on the passivation layer 410 and beside the connector 18 to cover the sidewalls of the connector 18.

[0048] Reference Figure 4 , an insulating encapsulation body 22 is formed next to the three-dimensional integrated circuit structure 4 to encapsulate the three-dimensional integrated circuit structure 4. A plurality of conductive pillars 14 are formed in the insulating encapsulation body 22, and the plurality of conductive pillars 14 surround the three-dimensional integrated circuit structure 4. A redistribution layer (RDL) structure 23 is formed on the three-dimensional integrated circuit structure 4 and the conductive pillars 14, and the redistribution layer structure 23 is electrically connected to the three-dimensional integrated circuit structure 4 and the conductive pillars 14. In some embodiments, the redistribution layer structure 23 includes a plurality of polymer layers PM1, PM2, PM3, and PM4 stacked alternately and a plurality of redistribution layers RDL1, RDL2, RDL3, and RDL4. The number of polymer layers or redistribution layers is not limited by the present disclosure.

[0049] In other words, the redistribution layer RDL1 penetrates the polymer layer PM1 and is electrically connected to the connector 18 and the conductive pillar 14 of the three-dimensional integrated circuit structure 4. The redistribution layer RDL2 penetrates the polymer layer PM2 and is electrically connected to the redistribution layer RDL1. The redistribution layer RDL3 penetrates the polymer layer PM3 and is electrically connected to the redistribution layer RDL2. The redistribution layer RDL4 penetrates the polymer layer PM4 and is electrically connected to the redistribution layer RDL3. In some embodiments, each of the polymer layers PM1, PM2, PM3 and PM4 includes a photosensitive material, such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (PCB), combinations thereof, etc. In some embodiments, each of the redistribution layers RLD1, RDL2, RDL3 and RDL4 includes a conductive material. The conductive material includes a metal (such as copper, nickel, titanium, combinations thereof, etc.) and is formed by an electroplating process. In some embodiments, the redistribution layers RDL1, RDL2, RDL3 and RDL4 include a seed layer (not shown in the figure) and a metal layer (not shown in the figure) formed on the seed layer, respectively. The seed layer may be a metal seed layer, such as a copper seed layer. In some embodiments, the seed layer includes a first metal layer (e.g., a titanium layer) and a second metal layer (e.g., a copper layer) located on the first metal layer. The metal layer may be copper or other suitable metals. In some embodiments, the redistribution layers RDL1, RDL2, RDL3, and RDL4 include a plurality of through holes and a plurality of traces connected to each other, respectively. The through holes connect the traces, and the traces are located on the polymer layers PM1, PM2, PM3, and PM4, respectively, and extend on the top surfaces of the polymer layers PM1, PM2, PM3, and PM4, respectively.

[0050] In some embodiments, the topmost redistribution layer RDL4 includes RDL4a and RDL4b. The redistribution layer RDL4a is also called an under-ball metallurgy (UBM) layer for ball mounting. The redistribution layer RDL4b can be a micro bump for connecting to an integrated passive device (IPD) 26 formed in a subsequent process.

[0051] Then, a plurality of connectors 24 are formed on the redistribution layer RDL4a of the redistribution layer structure 23, and the plurality of connectors 24 are electrically connected to the redistribution layer RDL4a of the redistribution layer structure 23. In some embodiments, the connectors 24 are made of a conductive material with low resistivity (e.g., Sn, Pb, Ag, Cu, Ni, Bi, or alloys thereof) and are formed by a suitable process (e.g., evaporation, plating, ball drop, or screen printing). An integrated passive device 26 is formed on the redistribution layer RDL4b of the redistribution layer structure 23 and is electrically connected to the redistribution layer RDL4b of the redistribution layer structure 23 through a solder bump 28. The integrated passive device 26 may be a capacitor, a resistor, an inductor, etc., or a combination thereof. The number of the integrated passive devices 26 is not limited to Figure 4 The number is not shown, but can be adjusted according to the design of the product. An underfill layer 27 is formed between the integrated passive device 26 and the polymer layer PM4, and surrounds and covers the exposed RDL 4b, the solder bumps 28 and the bottom surface of the integrated passive device 26.

[0052] like Figure 4 As shown, the dielectric layer 11 is then patterned so that the bottom surface of the conductive pillar 14 is exposed by the dielectric layer 11. After the conductive terminals 30 are respectively formed on the bottom surfaces of the conductive pillars 14, the integrated fan-out package P1 with double-sided terminals is completed. Then another package P2 is provided. In some embodiments, the package P2 is, for example, a memory device. The package P2 is stacked on the integrated fan-out package P1 and is electrically connected to the integrated fan-out package P1 through the conductive terminals 30, thereby forming a stacked package (PoP) structure.

[0053] According to some embodiments, a three-dimensional integrated circuit (3DIC) structure includes a die stacking structure, a metal circuit structure, and a first protection structure. The first die has a front side and a back side, and the second die has a front side and a back side. The front side of the first die is bonded to the front side of the second die. The second die includes a plurality of through substrate vias (TSVs). The metal circuit structure is disposed on the back side of the second die. The protection structure is disposed within the back side of the second die and separates one of the plurality of through substrate vias from the metal circuit structure.

[0054] In some embodiments, a top surface of the first protection structure is substantially coplanar with the back side of the second die.

[0055] In some embodiments, the first protection structure includes a conformal layer or a composite structure, wherein the composite structure includes a conformal layer and a filling layer disposed on the conformal layer.

[0056] In some embodiments, the conformal layer and the filling layer are formed of different materials.

[0057] In some embodiments, the die stacking structure further includes a hybrid bonding structure disposed between the first die and the second die.

[0058] In some embodiments, the three-dimensional integrated circuit structure further includes a second protection structure disposed within the back side of the second die, wherein the first protection structure directly contacts one of the plurality of through-substrate vias and the second protection structure is spaced apart from the plurality of through-substrate vias.

[0059] In some embodiments, the first protection structure extends from the back side of the second die into the hybrid bond structure.

[0060] In some embodiments, another one of the plurality of substrate through-vias is electrically connected to the metal circuit structure, and a top surface of the one of the plurality of substrate through-vias of the second die is lower than a top surface of the other one of the plurality of substrate through-vias of the second die.

[0061] In some embodiments, the three-dimensional integrated circuit structure further includes: a dielectric layer and a through dielectric via (TDV). The dielectric layer laterally encapsulates the second die. The through dielectric via is disposed in the dielectric layer and electrically connected to the first die and the metal circuit structure.

[0062] In some embodiments, a top surface of the dielectric layer, a top surface of the dielectric layer through-hole, the top surface of the first protection structure, and the back side of the second die are substantially coplanar.

[0063] In some embodiments, the die stacking structure includes a chip-on-wafer (CoW) structure, a chip-on-chip structure, a die-on-die structure, or a combination thereof.

[0064] According to some embodiments, a method for manufacturing a three-dimensional integrated circuit structure includes the following steps. A die stacking structure including a first die and a second die bonded together face to face is formed. A first planarization process is performed to expose a plurality of through-substrate vias (TSVs) of the second die at a rear side of the second die. The second die has a groove extending into one of the plurality of through-substrate vias of the second die. A protective structure is filled into the first groove in the form of a conformal layer. A metal circuit structure is formed on the rear side of the second die to be electrically connected to the die stacking structure through another of the plurality of through-substrate vias.

[0065] In some embodiments, filling the protective structure into the first groove includes: performing an atomic layer deposition (ALD) process to form the conformal layer on the back side of the second tube core, wherein the conformal layer completely covers the surface of the first groove; performing a chemical vapor deposition (CVD) process to form a filling layer on top of the conformal layer; and performing a second planarization process to expose the other one of the multiple substrate through-holes of the second tube core.

[0066] In some embodiments, forming the die stacking structure includes: providing the first die and the second die; and forming a hybrid bonding structure between the first die and the second die to bond the first die to the second die.

[0067] In some embodiments, after performing the first planarization process, the back side of the second tube core includes a second groove, the first groove and the second groove extend in a direction from the back side of the second tube core toward the hybrid bonding structure, and the second groove is spaced apart from the multiple substrate through-holes of the second tube core.

[0068] In some embodiments, after performing the first planarization process, the first recess extends from the back side of the second die into the hybrid bonded structure.

[0069] In some embodiments, after performing the first planarization process, a top surface of the one of the plurality of through-substrate vias of the second die is lower than a top surface of the other one of the plurality of through-substrate vias of the second die.

[0070] In some embodiments, after performing the second planarization process, a top surface of the protection structure is substantially coplanar with the back side of the second die.

[0071] According to some embodiments, a package includes a three-dimensional integrated circuit structure, an insulating encapsulation, a redistribution layer (RDL) structure, and a plurality of connectors. The three-dimensional integrated circuit structure includes a die stacking structure, a metal circuit structure, and a protection structure located between the die stacking structure and the metal circuit structure. The metal circuit structure is electrically connected to the die stacking structure through one of a plurality of through-substrate vias (TSVs) of the die stacking structure. The protection structure separates and electrically isolates another one of the through-substrate vias of the die stacking structure from the metal circuit structure. The insulating encapsulation encapsulates the three-dimensional integrated circuit structure in a lateral direction. The redistribution layer structure is disposed on the three-dimensional integrated circuit structure and the insulating encapsulation. The plurality of connectors are disposed on the three-dimensional integrated circuit structure and are electrically connected to the three-dimensional integrated circuit structure through the redistribution layer structure.

[0072] In some embodiments, the die stacking structure includes a first die and a plurality of second dies arranged in parallel on the first die.

[0073] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A three-dimensional integrated circuit structure, characterized in that: include: A die stacking structure, comprising a first die and a second die, the first die having a front side and a back side, the second die having a front side and a back side, the front side of the first die being bonded to the front side of the second die, the second die comprising a plurality of substrate through-holes; a metal circuit structure disposed on the back side of the second die; as well as A first protection structure is disposed within the back side of the second die and separates and electrically isolates one of the plurality of through-substrate vias of the second die from the metal circuit structure.

2. The three-dimensional integrated circuit structure according to claim 1, characterized in that: A top surface of the first protection structure is substantially coplanar with the back side of the second die.

3. The three-dimensional integrated circuit structure according to claim 1, characterized in that: The first protective structure includes a conformal layer.

4. The three-dimensional integrated circuit structure according to claim 1, characterized in that: The first protection structure includes a composite structure, wherein the composite structure includes a conformal layer and a filling layer disposed on the conformal layer, and the conformal layer and the filling layer are formed of different materials.

5. The three-dimensional integrated circuit structure according to claim 1, characterized in that: The die stacking structure further includes a hybrid bonding structure disposed between the first die and the second die.

6. The three-dimensional integrated circuit structure according to claim 5, characterized in that: Also included is a second protection structure disposed within the back side of the second die, wherein the first protection structure directly contacts one of the plurality of through substrate vias and the second protection structure is spaced apart from the plurality of through substrate vias.

7. The three-dimensional integrated circuit structure according to claim 5, characterized in that: The first protection structure extends from the back side of the second die into the hybrid bond structure.

8. The three-dimensional integrated circuit structure according to claim 1, characterized in that: Another one of the plurality of through-substrate vias is electrically connected to the metal circuit structure, and a top surface of the one of the plurality of through-substrate vias of the second die is lower than a top surface of the other one of the plurality of through-substrate vias of the second die.

9. The three-dimensional integrated circuit structure according to claim 1, characterized in that: Also includes: a dielectric layer laterally encapsulating the second die; as well as A through dielectric via (TDV) is disposed in the dielectric layer and electrically connected to the first die and the metal circuit structure.

10. The three-dimensional integrated circuit structure according to claim 9, characterized in that: A top surface of the dielectric layer, a top surface of the dielectric layer through-hole, the top surface of the first protection structure, and the back side of the second die are substantially coplanar.

11. The three-dimensional integrated circuit structure according to claim 1, characterized in that: The die stacking structure includes a chip-on-wafer (CoW) structure, a chip-on-chip structure, a die-on-die structure, or a combination thereof.

12. A method for manufacturing a three-dimensional integrated circuit structure, characterized in that: include: forming a tube die stacking structure, wherein the tube die stacking structure comprises a first tube die and a second tube die bonded together face to face; performing a first planarization process to expose a plurality of through substrate vias (TSVs) of the second die at a back side of the second die, wherein the back side of the second die has a first recess extending into one of the plurality of through substrate vias of the second die; Filling the protective structure into the first groove in a conformal layer; as well as A metal circuit structure is formed over the back side of the second die to be electrically connected to the die stacking structure through another one of the plurality of through-substrate vias, wherein the protection structure electrically isolates the one of the plurality of through-substrate vias of the second die from the metal circuit structure.

13. The method according to claim 12, characterized in that Filling the protection structure into the first groove comprises: performing an atomic layer deposition (ALD) process to form the conformal layer on the back side of the second die, wherein the conformal layer completely covers a surface of the first recess; performing a chemical vapor deposition (CVD) process to form a filling layer over the conformal layer; and A second planarization process is performed to expose the other one of the plurality of through-substrate vias of the second die.

14. The method according to claim 12, characterized in that The forming of the die stacking structure comprises: providing the first die and the second die; and A hybrid bonding structure is formed between the first die and the second die to bond the first die to the second die.

15. The method according to claim 14, characterized in that The back side of the second die after performing the first planarization process includes a second groove, the first groove and the second groove extending in a direction from the back side of the second die toward the hybrid bonding structure, and the second groove is spaced apart from the plurality of substrate through-holes of the second die.

16. The method according to claim 14, characterized in that After performing the first planarization process, the first recess extends from the back side of the second die into the hybrid bonded structure.

17. The method according to claim 12, characterized in that After performing the first planarization process, a top surface of the one of the plurality of through-substrate vias of the second die is lower than a top surface of the other one of the plurality of through-substrate vias of the second die.

18. The method according to claim 13, characterized in that After performing the second planarization process, a top surface of the protection structure is substantially coplanar with the back side of the second die.

19. A package, characterized in that: include: A three-dimensional integrated circuit structure, comprising a die stacking structure, a metal circuit structure, and a protection structure located between the die stacking structure and the metal circuit structure, wherein the metal circuit structure is electrically connected to the die stacking structure through one of a plurality of through substrate vias (TSVs) of the die stacking structure, and the protection structure separates and electrically isolates another one of the plurality of through substrate vias of the die stacking structure from the metal circuit structure; An insulating encapsulation body, encapsulating the three-dimensional integrated circuit structure in a lateral direction; a redistribution layer (RDL) structure disposed on the three-dimensional integrated circuit structure and the insulating package; as well as A plurality of connectors are disposed on the three-dimensional integrated circuit structure and electrically connected to the three-dimensional integrated circuit structure through the redistribution layer structure.

20. The package according to claim 19, characterized in that The die stacking structure includes a first die and a plurality of second dies arranged in parallel on the first die.

21. A three-dimensional integrated circuit structure, characterized in that: include: A die stacking structure, comprising a first die and a second die bonded together, wherein the second die has a plurality of substrate through-holes; a metal circuit structure disposed on a rear side of the second die; as well as A first protective structure is sandwiched between and contacts the bottom surface of the metal circuit structure and the top surface of one of the plurality of substrate through-holes of the second die, wherein the first protective structure is buried within the back side of the second die and separates and electrically isolates the one of the plurality of substrate through-holes of the second die from the metal circuit structure.

22. A method for manufacturing a three-dimensional integrated circuit structure, characterized in that: include: forming a tube die stacking structure, wherein the tube die stacking structure comprises a first tube die and a second tube die bonded together face to face; performing a first planarization process to expose a plurality of through-substrate vias of the second die at a back side of the second die, wherein the back side of the second die has a first recess extending into one of the plurality of through-substrate vias of the second die; Filling the first groove with a protective material; as well as A second planarization process is performed to expose another one of the plurality of through-substrate vias of the second die and to form a protection structure in the first recess, wherein a top surface of the protection structure is substantially coplanar with a top surface of the other one of the plurality of through-substrate vias.

23. A three-dimensional integrated circuit structure, characterized in that: include: A die stacking structure, comprising a first die and a second die bonded together, wherein the second die has a plurality of substrate through-holes; a metal circuit structure disposed on a top surface of the second die; as well as An electrical isolation structure is buried within the top surface of the second die and electrically isolates one of the plurality of through-substrate vias of the second die from the metal circuit structure.

24. A semiconductor packaging structure, characterized in that: include: A first die having a first bonding structure thereon; a second die having a second bonding structure thereon, wherein the second die is bonded to the first die such that a first bonding dielectric layer of the first bonding structure contacts a second bonding dielectric layer of the second bonding structure; a metal circuit structure disposed on a top surface of the second die; as well as The first protection structure is buried in the top surface of the second die and sandwiched between the metal circuit structure and the second die.

25. A method for manufacturing a semiconductor packaging structure, characterized in that: include: forming a first bonding structure on the first die; forming a second bonding structure on the second die; bonding the second die to the first die by contacting the first bonding dielectric layer of the first bonding structure to the second bonding dielectric layer of the second bonding structure; performing a first planarization process on a top surface of the second die to form a first recess in the top surface of the second die; forming a first protective structure in the first groove; as well as A metal circuit structure is formed over the top surface of the second die and a first protection structure, wherein the first protection structure is sandwiched between the metal circuit structure and the second die.

26. A package, characterized in that: include: First chip; A second chip, comprising a plurality of substrate through-holes and bonded to the first chip; a gap-filling dielectric layer disposed on the first chip and laterally encapsulating the second chip; A metal circuit structure disposed on a top surface of the second chip; as well as An electrical isolation structure is buried in the top surface of the second chip and electrically isolates one of the plurality of through-substrate vias of the second chip from the metal circuit structure.

Images