Fan-out semiconductor package with redistribution line structure

Abstract

A fan-out semiconductor package including a redistribution line structure is provided. The fan-out semiconductor package includes: a redistribution line structure including a plurality of redistribution line insulation layers and a plurality of redistribution line patterns, each of the redistribution line patterns being located on one of an upper surface and a lower surface of a redistribution line insulation layer among the plurality of redistribution line insulation layers; at least one semiconductor chip, the at least one semiconductor chip being arranged on the redistribution line structure and having a horizontal width of a coverage area occupied by the at least one semiconductor chip being smaller than a horizontal width of the redistribution line structure; and a molding member, the molding member surrounding the at least one semiconductor chip on the redistribution line structure and having a horizontal width smaller than a horizontal width of the redistribution line structure, wherein the plurality of redistribution line insulation layers have a stepped structure.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0089507, filed on Jul. 31, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor package, and more particularly, to a fan-out type semiconductor package having a redistribution line structure. Background Art

[0004] With the development of the electronics industry and the continuous improvement of user demands, electronic devices are becoming smaller and / or more multifunctional and have higher capacity, thus requiring highly integrated semiconductor chips.

[0005] In particular, in a highly integrated semiconductor chip having a greater number of input and output (I / O) terminals, the distance between the I / O terminals may decrease, and thus, interference may occur between the I / O terminals. A fan-out type semiconductor package has been used to increase the distance between the I / O terminals. Summary of the invention

[0006] The inventive concept provides a fan-out type semiconductor package having a redistribution line structure with improved reliability.

[0007] According to one aspect of the present invention, a fan-out semiconductor package is provided, comprising: a redistribution line structure, the redistribution line structure comprising a plurality of redistribution line insulation layers and a plurality of redistribution line patterns, each of the redistribution line patterns being located on one of an upper surface and a lower surface of a redistribution line insulation layer among the plurality of redistribution line insulation layers; at least one semiconductor chip, the at least one semiconductor chip being located on the redistribution line structure and having a horizontal width of a footprint that is smaller than a horizontal width of the redistribution line structure; and a molding member, the molding member surrounding the at least one semiconductor chip on the redistribution line structure and having a horizontal width that is greater than a horizontal width of the redistribution line structure, wherein the plurality of redistribution line insulation layers have a stepped structure.

[0008] According to another aspect of the present invention, a fan-out semiconductor package is provided, comprising: a redistribution line structure, the redistribution line structure comprising a plurality of redistribution line insulation layers having a stepped structure and a plurality of redistribution line patterns, each of the redistribution line patterns being located on one of an upper surface and a lower surface of a redistribution line insulation layer among the plurality of redistribution line insulation layers; at least one semiconductor chip, the at least one semiconductor chip being located on the redistribution line structure and being electrically connected to the plurality of redistribution line patterns; and a molding member, the molding member surrounding the at least one semiconductor chip on the redistribution line structure, wherein a horizontal width of a redistribution line insulation layer among the plurality of redistribution line insulation layers that is away from the at least one semiconductor chip is greater than a horizontal width of a redistribution line insulation layer among the plurality of redistribution line insulation layers that is close to the at least one semiconductor chip.

[0009] According to another aspect of the inventive concept, a fan-out semiconductor package is provided, the fan-out semiconductor package comprising: a redistribution line structure, the redistribution line structure comprising a plurality of redistribution line insulation layers having a stepped structure, a plurality of redistribution line patterns, and a plurality of redistribution line path patterns, each of the redistribution line patterns being located on an upper surface of one of the plurality of redistribution line insulation layers, each of the redistribution line path patterns being connected to one of the plurality of redistribution line patterns and penetrating one of the plurality of redistribution line insulation layers; and at least one semiconductor chip, the at least one semiconductor chip being located on the redistribution line structure and and is electrically connected to the multiple redistribution line patterns and the multiple redistribution line path patterns; and a molding component, which surrounds the at least one semiconductor chip on the redistribution line structure and protrudes outward further than the redistribution line structure in a horizontal direction, wherein a side surface of each of the multiple redistribution line insulation layers is an inclined surface, each of the inclined surfaces forms an acute angle with a normal to a lower surface of the redistribution line insulation layer, and the acute angle of the side surface of one of the multiple redistribution line insulation layers is smaller than the acute angles of the side surfaces of other redistribution line insulation layers in the multiple redistribution line insulation layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the present invention will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1A and Figure 1B is a cross-sectional view of a fan-out semiconductor package according to at least one embodiment, wherein Figure 1B yes Figure 1A An enlarged cross-sectional view of region Ib;

[0012] Figures 2A to 2Lare cross-sectional views showing a sequence of a method for manufacturing a fan-out semiconductor package according to at least one embodiment;

[0013] Figure 3 is a cross-sectional view of a fan-out semiconductor package according to at least one embodiment;

[0014] Figure 4 is a cross-sectional view of a fan-out semiconductor package according to at least one embodiment;

[0015] Figure 5A and Figure 5B is a cross-sectional view of a fan-out semiconductor package according to at least one embodiment, wherein Figure 5B yes Figure 5A An enlarged cross-sectional view of a region Vb;

[0016] 6A to 6F are cross-sectional views showing a sequence of a method for manufacturing a fan-out semiconductor package according to at least one embodiment;

[0017] Figure 7 is a cross-sectional view of a fan-out semiconductor package according to at least one embodiment; and

[0018] Figure 8 is a cross-sectional view of a fan-out type semiconductor package according to at least one embodiment. DETAILED DESCRIPTION

[0019] Figure 1A and Figure 1B is a cross-sectional view of a fan-out semiconductor package 1 according to at least one embodiment. In detail, Figure 1B yes Figure 1A An enlarged cross-sectional view of region Ib.

[0020] Reference Figure 1A and Figure 1B The fan-out type semiconductor package 1 may include a redistribution line structure 100 and a semiconductor chip 200 located on the redistribution line structure 100 .

[0021] The redistribution line structure 100 may include: a plurality of redistribution line insulation layers 110, 120 and 130 and a plurality of redistribution line patterns 114, 124 and 134 and / or a plurality of redistribution line path patterns 126 and 136, each redistribution line pattern being arranged on one of the upper surface and the lower surface of one of the plurality of redistribution line insulation layers 110, 120 and 130, each redistribution line path pattern penetrating one of the plurality of redistribution line insulation layers 110, 120 and 130 and being connected to the redistribution line pattern by contacting one of the plurality of redistribution line patterns 114, 124 and 134.

[0022] Each of the plurality of redistribution line insulating layers 110, 120, and 130 may include, for example, a material layer including an organic compound. In some embodiments, each of the plurality of redistribution line insulating layers 110, 120, and 130 may include a material layer including an organic polymer material. In some embodiments, each of the plurality of redistribution line insulating layers 110, 120, and 130 may include photosensitive polyimide (PSPI).

[0023] The plurality of seed layers 112, 122, and 132 may be located between each of the plurality of redistribution line patterns 114, 124, and 134 and the plurality of redistribution line via patterns 126 and 136 and any one of the plurality of redistribution line insulating layers 110, 120, and 130. In some embodiments, the plurality of seed layers 112, 122, and 132 may be formed by using physical vapor deposition, and the plurality of redistribution line patterns 114, 124, and 134 and the plurality of redistribution line via patterns 126 and 136 may be formed by using chemical plating.

[0024] The plurality of seed layers 112, 122, and 132 may include, for example, a material selected from the group consisting of Cu, Ti, TiW, TiN, Ta, TaN, Cr, and Al. However, the material of the plurality of seed layers 112, 122, and 132 is not limited thereto. In some embodiments, the plurality of seed layers 112, 122, and 132 may include Cu / Ti (i.e., Cu is stacked on Ti) or Cu / TiW (i.e., Cu is stacked on TiW).

[0025] The plurality of redistribution line patterns 114, 124, and 134 and the plurality of redistribution line via patterns 126 and 136 may include, but are not limited to, metals such as Cu, Al, W, Ti, Ta, In, Mo, Mn, Co, Sn, Ni, Mg, Re, Be, Ga, Ru, etc., or alloys thereof. In some embodiments, when Cu is included in the plurality of redistribution line patterns 114, 124, and 134 and the plurality of redistribution line via patterns 126 and 136, at least one of the plurality of seed layers 112, 122, and 132 may serve as a diffusion barrier layer.

[0026] One or more of the plurality of redistribution line patterns 114, 124, and 134 may be integrally formed with one or more of the plurality of redistribution line path patterns 126 and 136. For example, one or more of the plurality of redistribution line patterns 114, 124, and 134 may be integrally formed with one or more of the plurality of redistribution line path patterns 126 and 136 in the following manner: one or more of the plurality of redistribution line path patterns 126 and 136 are in contact with upper portions of one or more of the plurality of redistribution line patterns 114, 124, and 134, or one or more of the plurality of redistribution line path patterns 126 and 136 are in contact with lower portions of one or more of the plurality of redistribution line patterns 114, 124, and 134.

[0027] The plurality of redistribution line insulation layers 110, 120, and 130 may include a first redistribution line insulation layer 110, a second redistribution line insulation layer 120, and a third redistribution line insulation layer 130 stacked sequentially. The plurality of seed layers 112, 122, and 132 may include a first seed layer 112, a second seed layer 122, and a third seed layer 132 respectively contacting the first to third redistribution line insulation layers 110 to 130. The plurality of redistribution line patterns 114, 124, and 134 may include a first redistribution line pattern 114 located on an upper surface of the first redistribution line insulation layer 110, a second redistribution line pattern 124 located on an upper surface of the second redistribution line insulation layer 120, and a third redistribution line pattern 134 located on an upper surface of the third redistribution line insulation layer 130. The plurality of redistribution line via patterns 126 and 136 may include a first redistribution line via pattern 126 on the first redistribution line pattern 114 and a second redistribution line via pattern 136 on the second redistribution line pattern 124 .

[0028] The detailed structure of the redistribution line structure 100 will be described below.

[0029] The first seed layer 112 is disposed on a portion of the upper surface of the first redistribution line insulation layer 110, and the first redistribution line pattern 114 is disposed on the first seed layer 112. The first seed layer 112 is located between the upper surface of the first redistribution line insulation layer 110 and the lower surface of the first redistribution line pattern 114.

[0030] The second redistribution line insulation layer 120 is stacked on the first redistribution line insulation layer 110, wherein the second redistribution line insulation layer 120 covers a portion of the first redistribution line pattern 114 and has a first via opening VO1 exposing the remaining portion of the first redistribution line pattern 114. The horizontal width W2 of the second redistribution line insulation layer 120 may be smaller than the horizontal width W1 of the first redistribution line insulation layer 110.

[0031] The second seed layer 122 is arranged on a portion of the upper surface of the second redistribution line insulating layer 120, the inner side surface of the first via opening VO1, and a portion of the upper surface of the first redistribution line pattern 114, the portion of the upper surface of the first redistribution line pattern 114 being exposed through the first via opening VO1. The first redistribution line via pattern 126 and the second redistribution line pattern 124 are arranged on the second seed layer 122. The first redistribution line via pattern 126 may cover a portion of the second seed layer 122, the portion of the second seed layer 122 being located in the first via opening VO1 and filling the first via opening VO1. The second redistribution line pattern 124 may be arranged on a portion of the second seed layer 122 on the upper surface of the second redistribution line insulating layer 120 and on the first redistribution line via pattern 126.

[0032] The second seed layer 122 may be located between the second redistribution line pattern 124 and the first redistribution line via pattern 126 and the second redistribution line insulation layer 120, and between the first redistribution line via pattern 126 and the first redistribution line pattern 114. The first redistribution line via pattern 126 and the second redistribution line pattern 124 may be integrally formed.

[0033] The third redistribution line insulation layer 130 is stacked on the second redistribution line insulation layer 120, wherein the third redistribution line insulation layer 130 covers a portion of the second redistribution line pattern 124 and has a second via opening VO2 exposing the remaining portion of the second redistribution line pattern 124. A horizontal width W3 of the third redistribution line insulation layer 130 may be smaller than a horizontal width W2 of the second redistribution line insulation layer 120.

[0034] The third seed layer 132 is arranged on a portion of the upper surface of the third redistribution line insulation layer 130, the inner side surface of the second via opening VO2, and a portion of the upper surface of the second redistribution line pattern 124, and the portion of the upper surface of the second redistribution line pattern 124 is exposed through the second via opening VO2. The second redistribution line via pattern 136 and the third redistribution line pattern 134 are arranged on the third seed layer 132. The second redistribution line via pattern 136 may cover a portion of the third seed layer 132, which is located in the second via opening VO2 and may fill the second via opening VO2. The third redistribution line pattern 134 may be arranged on a portion of the third seed layer 132 on the upper surface of the third redistribution line insulation layer 130 and on the second redistribution line via pattern 136.

[0035] The third seed layer 132 may be located between the third redistribution line pattern 134 and the second redistribution line via pattern 136 and the third redistribution line insulation layer 130, and between the second redistribution line via pattern 136 and the second redistribution line pattern 124. The second redistribution line via pattern 136 and the third redistribution line pattern 134 may be integrally formed.

[0036] Figure 1A The redistribution line structure 100 is illustrated to include three redistribution line insulation layers 110, 120, and 130, three redistribution line patterns 114, 124, and 134, and two redistribution line via patterns 126 and 136. However, the redistribution line structure 100 is not limited thereto but may be variously modified according to the design of circuit wiring in the redistribution line structure 100.

[0037] For example, the redistribution line structure 100 may include more than two, more than three, or more than four redistribution line insulation layers. For example, the redistribution line structure 100 may have a number of redistribution line patterns less than the number of redistribution line insulation layers by one, a number of redistribution line patterns equal to the number of redistribution line insulation layers, or a number of redistribution line patterns greater than the number of redistribution line insulation layers by one. For example, the redistribution line structure 100 may have a number of redistribution line path patterns less than the number of redistribution line insulation layers by two, a number of redistribution line path patterns less than the number of redistribution line insulation layers by one, or a number of redistribution line path patterns equal to the number of redistribution line insulation layers.

[0038] In some embodiments, a portion of the uppermost redistribution line pattern among the redistribution line patterns 114, 124, and 134 (e.g., a portion of the third redistribution line pattern 134) may perform the function of a chip connection pad coupled to the semiconductor chip 200. In some embodiments, a portion of the lowermost redistribution line pattern among the redistribution line patterns 114, 124, and 134 (e.g., a portion of the first redistribution line pattern 114) may perform the function of a terminal connection pad coupled to the external connection terminal 400.

[0039] The semiconductor chip 200 may be coupled on the redistribution line structure 100 . A horizontal width W4 of the semiconductor chip 200 may be smaller than a horizontal width W3 of the third redistribution line insulation layer 130 .

[0040] The redistribution line structure 100 may protrude outward in a horizontal direction more than the semiconductor chip 200. For example, each of the first to third redistribution line insulating layers 110 to 130 included in the redistribution line structure 100 may extend in a horizontal direction to protrude outward more than the semiconductor chip 200.

[0041] The plurality of redistribution line insulation layers 110 , 120 , and 130 included in the redistribution line structure 100 may have a stepped structure in which widths of the plurality of redistribution line insulation layers 110 , 120 , and 130 increase as they are farther from the semiconductor chip 200 .

[0042] In some embodiments, at least one of the plurality of redistribution line patterns 114 , 124 , and 134 included in the redistribution line structure 100 may protrude further outward than the semiconductor chip 200 in a horizontal direction. Figure 1A It is illustrated that a portion of the first redistribution line pattern 114 and a portion of the second redistribution line pattern 124 among the plurality of redistribution line patterns 114, 124, and 134 protrude outward more than the semiconductor chip 200 in the horizontal direction. However, the inventive concept is not limited thereto. For example, a portion of the first redistribution line pattern 114 among the plurality of redistribution line patterns 114, 124, and 134 may protrude outward more than the semiconductor chip 200 in the horizontal direction, or a portion of each of the first redistribution line pattern 114, the second redistribution line pattern 124, and the third redistribution line pattern 134 may protrude outward more than the semiconductor chip 200 in the horizontal direction.

[0043] The semiconductor chip 200 may include, for example, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip. The semiconductor chip 200 may be, for example, a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, a flash memory chip, an electrically erasable programmable read-only memory (EEPROM) chip, a phase change RAM (PRAM) chip, a magnetic RAM (MRAM) chip, or a resistive RAM (RRAM) chip.

[0044] The semiconductor chip 200 may include a semiconductor substrate 210 and a chip pad 220 arranged on a surface of the semiconductor substrate 210 .

[0045] The chip pad 220 of the semiconductor chip 200 may be connected to the third redistribution line pattern 134 of the redistribution line structure 100 via a chip connection member 230. The chip connection member 230 may include, for example, a bump, a solder ball, or a conductive pillar.

[0046] The semiconductor substrate 210 may include, for example, silicon (Si). Alternatively, the semiconductor substrate 210 may include a semiconductor element such as germanium (Ge), or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The semiconductor substrate 210 may have an active surface and an inactive surface opposite to the active surface. In some embodiments, the active surface of the semiconductor substrate 210 may face the redistribution line structure 100.

[0047] In the semiconductor chip 200 , semiconductor devices including a plurality of different types of individual devices may be formed on an active surface of a semiconductor substrate 210 .

[0048] An underfill material layer 250 surrounding the chip connection member 230 may be filled between the semiconductor chip 200 and the redistribution line structure 100. The underfill material layer 250 may include, for example, epoxy resin formed by using a capillary underfill method. In some embodiments, the underfill material layer 250 may be a non-conductive film (NCF).

[0049] The fan-out type semiconductor package 1 may include a molding member 300 surrounding the semiconductor chip 200 on the redistribution line structure 100. The molding member 300 may include, for example, epoxy molding compound (EMC). The molding member 300 may cover the upper surface of the redistribution line structure 100 and the side surface and upper surface of the semiconductor chip 200. The molding member 300 may cover a portion of the upper surface and the side surface of each of the plurality of redistribution line insulating layers 110, 120, and 130 included in the redistribution line structure 100.

[0050] The molding member 300 may protrude further outward than the redistribution line structure 100 in a horizontal direction. The horizontal width W5 of the molding member 300 may be greater than the horizontal width W1 of the first redistribution line insulation layer 110. That is, the horizontal width W5 of the molding member 300 may be greater than the total width of the redistribution line structure 100.

[0051] The lower surface of the molding member 300 and the lower surface of the redistribution line structure 100 (e.g., the lower surface of the first redistribution line insulation layer 110) may be located at the same level. Also, the lower surface of the molding member 300 and the lower surface of the redistribution line structure 100 (e.g., the lower surface of the first redistribution line insulation layer 110) may be coplanar.

[0052] A side surface of each of the plurality of redistribution line insulation layers 110 to 130 may be an inclined surface, each of the inclined surfaces forming an acute angle (between 0° and 90°) with a normal to a lower surface of each of the plurality of redistribution line insulation layers 110 to 130. In some embodiments, a width of each of the plurality of redistribution line insulation layers 110 to 130 may increase as it moves away from the semiconductor chip 200. The first to third redistribution line insulation layers 110 to 130 may have a first side surface SS1, a second side surface SS2, and a third side surface SS3, respectively.

[0053] The first side surface SS1 of the first redistribution line insulation layer 110 may be an inclined surface at a first angle θ1 with respect to a normal line of a lower surface of the first redistribution line insulation layer 110. The second side surface SS2 of the second redistribution line insulation layer 120 may be an inclined surface at a second angle θ2 with respect to a normal line of a lower surface of the second redistribution line insulation layer 120. The third side surface SS3 of the third redistribution line insulation layer 130 may be an inclined surface at a third angle θ3 with respect to a normal line of a lower surface of the third redistribution line insulation layer 130.

[0054] Any one of the first to third angles θ1 to θ3 may have a value different from the other angles. That is, any one of the first to third side surfaces SS1 to SS3 may be an inclined surface having an inclination different from the inclinations of the other side surfaces. For example, the first angle θ1 may be smaller than each of the second angle θ2 and the third angle θ3. That is, the first side surface SS1 may be an inclined surface steeper than the second side surface SS2 and the third side surface SS3. In some embodiments, the second angle θ2 and the third angle θ3 may be the same or substantially the same, but are not limited thereto. That is, the second side surface SS2 and the third side surface SS3 may be inclined surfaces having the same or substantially the same inclination, but are not limited thereto.

[0055] The thickness of any one of the multiple redistribution line insulation layers 110 to 130 may be different from the thickness of the other redistribution line insulation layers. The first redistribution line insulation layer 110 may have a first thickness t1, the second redistribution line insulation layer 120 may have a second thickness t2, and the third redistribution line insulation layer 130 may have a third thickness t3. For example, the first thickness t1 may be less than each of the second thickness t2 and the third thickness t3. That is, the first redistribution line insulation layer 110 may be thinner than each of the second redistribution line insulation layer 120 and the third redistribution line insulation layer 130. In some embodiments, the second thickness t2 and the third thickness t3 may be the same or substantially the same as each other, but are not limited thereto. That is, the second redistribution line insulation layer 120 and the third redistribution line insulation layer 130 may have the same or substantially the same thickness as each other, but are not limited thereto.

[0056] According to the fan-out type semiconductor package 1 conceived in the present invention, side surfaces of the redistribution line structure 100 (i.e., first to third side surfaces SS1 to SS3 of the first to third redistribution line insulation layers 110 to 130, respectively) may be covered by the molding member 300. Therefore, interfaces between the plurality of redistribution line insulation layers 110 to 130 (e.g., interfaces between the first redistribution line insulation layer 110 and the second redistribution line insulation layer 120 and interfaces between the second redistribution line insulation layer 120 and the third redistribution line insulation layer 130) may not be exposed to the outside.

[0057] In particular, when a plurality of fan-out semiconductor packages are formed together and separated into individual fan-out semiconductor packages by performing a sawing process, the cutting process is performed on the molding member 300 instead of the redistribution line structure 100, and thus, damage to the plurality of redistribution line insulation layers 110 to 130 can be reduced or prevented. Therefore, the plurality of redistribution line insulation layers 110 to 130 are not separated from each other, or cracks in the plurality of redistribution line insulation layers 110 to 130 can be reduced or prevented. Therefore, a reliable fan-out semiconductor package 1 can be provided.

[0058] Figures 2A to 2L is a cross-sectional view for sequentially describing a method for manufacturing a fan-out type semiconductor package according to at least one embodiment. In detail, Figures 2A to 2L The process of manufacturing two fan-out semiconductor packages is described sequentially by showing the process of manufacturing two fan-out semiconductor packages together. Figure 1A and Figure 1B A cross-sectional view of a method of illustrating a fan-out type semiconductor package 1 , wherein only a portion of each of two fan-out type semiconductor packages is illustrated, the portions being adjacent to each other.

[0059] Reference Figure 2A , a first redistribution line insulating layer 110 having a first separation space SP1 may be formed on the carrier substrate 10 coupled to the release film 20. As described below, the first separation space SP1 is a region where a package sawing process is performed to separate two fan-out semiconductor packages formed together into separate fan-out semiconductor packages.

[0060] The carrier substrate 10 may support the organic insulating layer and may include a material having stability for a baking process and an etching process. When the carrier substrate 10 is separated and removed later by using laser ablation, the carrier substrate 10 may be a transparent substrate. Alternatively, when the carrier substrate 10 is separated and removed later by heating, the carrier substrate 10 may be a heat-resistant substrate. In some embodiments, the carrier substrate 10 may be a glass substrate. In other embodiments, the carrier substrate 10 may include, but is not limited to, heat-resistant organic polymer materials such as polyimide (PI), polyetheretherketone (PEEK), polyethersulfone (PES), polyphenylene sulfide (PPS), etc.

[0061] The release film 20 may include, for example, a laser reactive layer, which may then be evaporated by reacting to the radiation of the laser beam, thereby separating the carrier substrate 10. The release film 20 may include a carbon-based material layer. For example, the release film 20 may include an amorphous carbon layer (ACL) or a spin-on hard (SOH) mask including a relatively high carbon content hydrocarbon compound or a derivative thereof having a carbon weight percentage of about 85% to about 99%.

[0062] The first redistribution line insulation layer 110 may have a first side surface SS1 at one side of the first separation space SP1. The first side surface SS1 may be an inclined surface forming an acute angle with respect to a normal line of a circumferential surface of the carrier substrate 10 or a normal line of a lower surface of the first redistribution line insulation layer 110.

[0063] Reference Figure 2B The first initial seed layer 112P may be conformally formed to cover an upper surface of the first redistribution line insulation layer 110 , a first side surface SS1 which is an inner side surface of the first separation space SP1 , and a lower surface of the first separation space SP1 .

[0064] Reference Figure 2C A mask pattern MK having an opening OP may be formed on the first preliminary seed layer 112P. The mask pattern MK may completely cover the first separation space SP1, and the opening OP may overlap a portion of the first redistribution line insulating layer 110.

[0065] Reference Figure 2D , the first redistribution line pattern 114 may be formed on the portion of the first initial seed layer 112P exposed in the opening OP by performing chemical plating.

[0066] Reference Figure 2D and Figure 2E The mask pattern MK may be removed, and a portion of the first preliminary seed layer 112P exposed by the removal of the mask pattern MK may be removed to form a first seed layer 112. The first seed layer 112 may be located between the first redistribution line pattern 114 and the first redistribution line insulation layer 110.

[0067] Reference Figure 2F , you can Figure 2E A redistribution line insulating material layer 120p is formed on the resulting structure. The redistribution line insulating material layer 120p may completely cover the first redistribution line pattern 114. The redistribution line insulating material layer 120p may include a material layer including an organic compound. In some embodiments, the redistribution line insulating material layer 120p may include a material layer including an organic polymer material. In some embodiments, the redistribution line insulating material layer 120p may include a polymer material having negative photosensitivity. In some embodiments, the redistribution line insulating material layer 120p may include a photosensitive PI resin having negative photosensitivity.

[0068] In some embodiments, the redistribution line insulating material layer 120p may be formed by spin coating and soft baking. For example, the soft baking may be performed by performing a heating process at a temperature of about 150°C to about 350°C for about 10 seconds to about 5 minutes, but is not limited thereto.

[0069] In some embodiments, a portion of the redistribution line insulating material layer 120p overlapping the first redistribution line insulating layer 110 may have a substantially flat upper surface that is substantially flat relative to the first separation space SP1 (see FIG. Figure 2E )The overlapping portion has a concave upper surface.

[0070] Reference Figure 2G , can be achieved by insulating the redistribution line layer 120p (see Figure 2F ) is exposed and developed to form a second redistribution line insulation layer 120 having a first via opening VO1 and a second separation space SP2. The second separation space SP2 may be connected to the first separation space SP1. At a lower surface of the first via opening VO1, a portion of the first redistribution line pattern 114 may be exposed.

[0071] The second redistribution line insulation layer 120 may have a second side surface SS2 at one side of the second separation space SP2 . The second side surface SS2 may be an inclined surface forming an acute angle with respect to a normal line of a circumferential surface of the carrier substrate 10 or a normal line of a lower surface of the second redistribution line insulation layer 120 .

[0072] Can be done by using Figure 2A The second redistribution line insulation layer 120 is formed by substantially the same method as the first redistribution line insulation layer 110 illustrated.

[0073] Reference Figure 2H , you can repeat the reference Figures 2B to 2G The described process forms a second seed layer 122 , a second redistribution line pattern 124 , a first redistribution line via pattern 126 , a third redistribution line insulation layer 130 having a second via opening VO2 and a third separation space SP3 , a third seed layer 132 , a third redistribution line pattern 134 , and a second redistribution line via pattern 136 .

[0074] The second redistribution line pattern 124 and the first redistribution line via pattern 126 may be integrally formed with each other and may fill the first via opening VO1. The third redistribution line pattern 134 and the second redistribution line via pattern 136 may be integrally formed and may fill the second via opening VO2.

[0075] The third separation space SP3 may be connected to the second separation space SP2 and the first separation space SP1. The third redistribution line insulation layer 130 may have a third side surface SS3 at one side of the third separation space SP3. The third side surface SS3 may be an inclined surface forming an acute angle with a normal line of a circumferential surface of the carrier substrate 10 or a normal line of a lower surface of the third redistribution line insulation layer 130.

[0076] The plurality of redistribution line insulation layers 110, 120, and 130 included in the redistribution line structure 100 may be formed to have a stepped structure in which the widths of the plurality of redistribution line insulation layers 110, 120, and 130 increase as they are farther away from the carrier substrate 10. The width of each of the plurality of redistribution line insulation layers 110, 120, and 130 may increase as the distance from the carrier substrate 10 increases.

[0077] Reference Fig.2I , the semiconductor chip 200 may be coupled to the redistribution line structure 100. The semiconductor chip 200 may be coupled to the redistribution line structure 100 such that the chip pads 220 arranged on the active surface of the semiconductor substrate 210 face the redistribution line structure 100. The chip pads 220 of the semiconductor chip 200 may be connected to the third redistribution line pattern 134 of the redistribution line structure 100 via the chip connection member 230.

[0078] The bottom filling material layer 250 surrounding the chip connection member 230 may be filled between the semiconductor chip 200 and the redistribution line structure 100. After coupling the semiconductor chip 200 to the redistribution line structure 100, the bottom filling material layer 250 may be formed by using a capillary bottom filling method. In some embodiments, after coupling the NCF on the chip pad 220 of the semiconductor chip 200, the bottom filling material layer 250 may be formed by coupling the semiconductor chip 200 on the redistribution line structure 100.

[0079] Reference Figure 2J , a molding member 300 covering the side surface and the upper surface of the semiconductor chip 200 may be formed on the redistribution line structure 100 coupled to the semiconductor chip 200. The molding member 300 may include, for example, EMC. The molding member 300 may fill the first separation space SP1, the second separation space SP2, and the third separation space SP3 (refer to Figure 2H ), and may contact a portion of the release film 20 located below the first to third separation spaces SP1 to SP3, a first side surface SS1 of the first redistribution line insulation layer 110, a second side surface SS2 of the second redistribution line insulation layer 110, and a third side surface SS3 of the third redistribution line insulation layer 130 (refer to Figure 2H ), a portion of the upper surface of the third redistribution line insulating layer 130 and the side surface and upper surface of the semiconductor chip 200.

[0080] Reference Figure 2J and Figure 2K ,based on Figure 2JThe resulting structure can separate the carrier substrate 10 coupled with the release film 20 from the redistribution line structure 100. Afterwards, a portion of the first redistribution line insulating layer 110 can be removed to form a pad opening PO, through which the first seed layer 112 and the first redistribution line pattern 114 are partially exposed, and the external connection terminal 400 can be coupled to the first seed layer 112 and the first redistribution line pattern 114 via the pad opening PO.

[0081] Reference Figure 2L , can be Figure 2K The resulting structure is subjected to a package sawing process to form fan-out type semiconductor packages 1 separated by kerf spaces KE between the fan-out type semiconductor packages 1 .

[0082] The package sawing process may be performed by cutting the molding member 300 and forming a kerf space KE in the molding member 300. Therefore, the kerf space KE may be aligned with the side surfaces of the redistribution line structure 100 (i.e., the first side surface SS1 of the first redistribution line insulation layer 110, the second side surface SS2 of the second redistribution line insulation layer 120, and the third side surface SS3 of the third redistribution line insulation layer 130 (refer to Figure 1B )). Therefore, the first side surface SS1 of the first redistribution line insulation layer 110, the second side surface SS2 of the second redistribution line insulation layer 120, and the third side surface SS3 of the third redistribution line insulation layer 130 may be covered by the molding member 300. Therefore, interfaces between the plurality of redistribution line insulation layers 110 to 130 (for example, an interface between the first redistribution line insulation layer 110 and the second redistribution line insulation layer 120 and an interface between the second redistribution line insulation layer 120 and the third redistribution line insulation layer 130) may not be exposed to the outside.

[0083] Therefore, in the process of manufacturing the fan-out semiconductor package 1, damage to the multiple redistribution line insulation layers 110 to 130 can be reduced or prevented, and thus, detachment of the multiple redistribution line insulation layers 110 to 130 can be reduced or prevented, or cracks in the multiple redistribution line patterns 114, 124 and 134 can be reduced or prevented.

[0084] Figure 3 is a cross-sectional view of a fan-out semiconductor package 1a according to at least one embodiment. Figure 3 The description of various aspects will be omitted. Figure 1A and Figure 1B The same aspects and will mainly describe Figure 3 in Figure 1A and Figure 1B The difference.

[0085] Reference Figure 3, the fan-out type semiconductor package 1 a may include a redistribution line structure 100 and a plurality of semiconductor chips 200 a spaced apart from each other on the redistribution line structure 100 .

[0086] The plurality of semiconductor chips 200a may include a first semiconductor chip 202 and a second semiconductor chip 204. The first semiconductor chip 202 may include, for example, a CPU chip, a GPU chip, or an AP chip. The second semiconductor chip 204 may include, for example, a DRAM chip, an SRAM chip, a flash memory chip, an EEPROM chip, a PRAM chip, an MRAM chip, or an RRAM chip. In some embodiments, the second semiconductor chip 204 may be a high bandwidth memory (HBM) DRAM semiconductor chip.

[0087] The footprint occupied by the plurality of semiconductor chips 200a may be smaller than the horizontal area of ​​the redistribution line structure 100. The total footprint occupied by the plurality of semiconductor chips 200a may overlap with the redistribution line structure 100 in the vertical direction.

[0088] A horizontal width W4a of a footprint occupied by the plurality of semiconductor chips 200a may be smaller than each of the horizontal widths W1, W2, W3, and W5 of the first, second, and third redistribution line insulation layers 110, 120, and 130, and the molding member 300.

[0089] Figure 4 is a cross-sectional view of a fan-out semiconductor package 1b according to at least one embodiment. Figure 4 The description of various aspects will be omitted. Figure 1A and Figure 1B The same aspects and will mainly describe Figure 4 in Figure 1A and Figure 1B The difference.

[0090] Reference Figure 4 The fan-out type semiconductor package 1 b may include a redistribution line structure 100 and a semiconductor chip 200 located on the redistribution line structure 100 .

[0091] The fan-out type semiconductor package 1b may further include a molding member 300a surrounding the semiconductor chip 200 on the redistribution line structure 100. The molding member 300a may cover the upper surface of the redistribution line structure 100 and the side surface of the semiconductor chip 200, but may not cover and may expose the upper surface of the semiconductor chip 200, which is a non-active surface. The molding member 300a may cover a portion of the upper surface and the side surface of each of the plurality of redistribution line insulating layers 110, 120, and 130 included in the redistribution line structure 100.

[0092] In some embodiments, a heat dissipation member may be coupled to the upper surface of the semiconductor chip 200. The heat dissipation member may be, for example, a heat sink or a heat sink. In some embodiments, a thermal interface material (TIM) may be disposed between the heat dissipation member and the upper surface of the semiconductor chip 200. The TIM may include, for example, mineral oil, grease, gap filler putty, phase change gel, phase change material pad, or particle filled epoxy.

[0093] Figure 5A and Figure 5B is a cross-sectional view of a fan-out semiconductor package 2 according to at least one embodiment. In detail, Figure 5B yes Figure 5A An enlarged cross-sectional view of region Vb.

[0094] Reference Figure 5A and Figure 5B The fan-out type semiconductor package 2 may include a redistribution line structure 100 a and a semiconductor chip 200 located on the redistribution line structure 100 a .

[0095] The redistribution line structure 100a may include: a plurality of redistribution line insulation layers 110a, 120a and 130a, a plurality of redistribution line patterns 114a and 124a arranged on the upper surface or the lower surface of each of the plurality of redistribution line insulation layers 110a, 120a and 130a, and a plurality of redistribution line path patterns 116a and 126a penetrating at least one of the plurality of redistribution line insulation layers 110a, 120a and 130a and connected to at least one of the plurality of redistribution line patterns 114a and 124a by contacting at least one of the plurality of redistribution line patterns 114a and 124a.

[0096] The plurality of seed layers 112a and 122a may be located between each of the plurality of redistribution line patterns 114a and 124a and the plurality of redistribution line via patterns 116a and 126a and any one of the plurality of redistribution line insulation layers 110a, 120a, and 130a.

[0097] The plurality of redistribution line insulating layers 110a, 120a, and 130a, the plurality of seed layers 112a and 122a, the plurality of redistribution line patterns 114a and 124a, and the plurality of redistribution line via patterns 116a and 126a may generally be respectively referred to as Figure 1A and Figure 1B The described multiple redistribution line insulation layers 110, 120 and 130, multiple seed layers 112, 122 and 123, multiple redistribution line patterns 114, 124 and 134, and multiple redistribution line via patterns 126 and 136 are the same, so a detailed description will not be given, and different aspects will be mainly described.

[0098] At least one of the plurality of redistribution line patterns 114a and 124a may be integrally formed with at least one of the plurality of redistribution line path patterns 116a and 126a. For example, at least one of the plurality of redistribution line patterns 114a and 124a may be integrally formed with at least one of the plurality of redistribution line path patterns 116a and 126a in the following manner: at least one of the plurality of redistribution line path patterns 116a and 126a contacts an upper portion of at least one of the plurality of redistribution line patterns 114a and 124a, or at least one of the plurality of redistribution line path patterns 116a and 126a contacts a lower portion of at least one of the plurality of redistribution line patterns 114a and 124a.

[0099] The plurality of redistribution line insulation layers 110a, 120a, and 130a may include a first redistribution line insulation layer 110a, a second redistribution line insulation layer 120a, and a third redistribution line insulation layer 130a stacked sequentially. The plurality of seed layers 112a and 122a may include a first seed layer 112a and a second seed layer 122a contacting the first redistribution line insulation layer 110a and the second redistribution line insulation layer 120a, respectively. The plurality of redistribution line patterns 114a and 124a may include a first redistribution line pattern 114a below the first redistribution line insulation layer 110a and a second redistribution line pattern 124a below the second redistribution line insulation layer 120a. The plurality of redistribution line path patterns 116a and 126a may include a first redistribution line path pattern 116a on the first redistribution line pattern 114a and a second redistribution line path pattern 126a on the second redistribution line pattern 124a.

[0100] The structure of the redistribution line structure 100a will be described in detail. The first seed layer 112a may be arranged on a portion of the lower surface of the first redistribution line insulation layer 110a having the first via opening VO1a through which a portion of the lower surface of the chip pad 220 of the semiconductor chip 200 is exposed, the inner side surface of the first via opening VO1a, and a portion of the lower surface of the chip pad 220 (the portion being exposed through the first via opening VO1a). The first redistribution line path pattern 116a and the first redistribution line pattern 114a may be arranged on the first seed layer 112a. The first redistribution line path pattern 116a may cover a portion of the first seed layer 112a located in the first via opening VO1a, and may fill the first via opening VO1a. The first redistribution line pattern 114a may be arranged on a portion of the first seed layer 112a located on the lower surface of the first redistribution line insulation layer 110a, and may be arranged on the first redistribution line path pattern 116a.

[0101] The first seed layer 112a may be located between the first redistribution line pattern 114a and the first redistribution line via pattern 116a and the first redistribution line insulating layer 110a, and between the first redistribution line via pattern 116a and the chip pad 220. The first redistribution line via pattern 116a and the first redistribution line pattern 114a may be integrally formed.

[0102] A second redistribution line insulation layer 120a including a second via opening VO2a may be stacked on a lower surface of the first redistribution line insulation layer 110a, wherein the second redistribution line insulation layer 120a covers a portion of the first redistribution line pattern 114a and the second via opening VO2a exposes the remaining portion of the first redistribution line pattern 114a. A horizontal width W2a of the second redistribution line insulation layer 120a may be smaller than a horizontal width W1a of the first redistribution line insulation layer 110a.

[0103] The second seed layer 122a may be arranged on a portion of the lower surface of the second redistribution line insulation layer 120a having the second via opening VO2a through which a portion of the lower surface of the first redistribution line pattern 114a is exposed, the inner side surface of the second via opening VO2a, and a portion of the lower surface of the first redistribution line pattern 114a exposed through the second via opening VO2a. The second redistribution line via pattern 126a and the second redistribution line pattern 124a may be arranged on the second seed layer 122a. The second redistribution line via pattern 126a may cover a portion of the second seed layer 122a located in the second via opening VO2a and may fill the second via opening VO2a. The second redistribution line pattern 124a may be arranged on a portion of the second seed layer 122a located on the lower surface of the second redistribution line insulation layer 120a and may be arranged on the second redistribution line via pattern 126a.

[0104] The second seed layer 122a may be located between the second redistribution line pattern 124a and the second redistribution line via pattern 126a and the second redistribution line insulating layer 120a, and between the second redistribution line via pattern 126a and a portion of a lower surface of the first redistribution line pattern 114a (the portion being exposed through the second via opening VO2a). The second redistribution line via pattern 126a and the second redistribution line pattern 124a may be integrally formed.

[0105] A third redistribution line insulation layer 130a including a pad opening POa may be stacked on a lower surface of the second redistribution line insulation layer 120a, wherein the third redistribution line insulation layer 130a covers a portion of the second redistribution line pattern 124a and the pad opening POa exposes the remaining portion of the second redistribution line pattern 124a. A horizontal width W3a of the third redistribution line insulation layer 130a may be smaller than a horizontal width W2a of the second redistribution line insulation layer 120a.

[0106] Figure 5A The redistribution line structure 100a is illustrated to include three redistribution line insulation layers 110a, 120a, and 130a / two redistribution line patterns 114a and 124a and two redistribution line via patterns 116a and 126a. However, the redistribution line structure 100a is not limited thereto, but may be variously modified according to the design of circuit wiring in the redistribution line structure 100a.

[0107] For example, the redistribution line structure 100a may include more than two, more than three, or more than four redistribution line insulation layers. For example, the redistribution line structure 100a may have redistribution line patterns whose number is one less than the number of redistribution line insulation layers, the same as the number of redistribution line insulation layers, or one more than the number of redistribution line insulation layers. For example, the redistribution line structure 100a may have redistribution line path patterns whose number is two less than the number of redistribution line insulation layers, one less than the number of redistribution line insulation layers, or the same as the number of redistribution line insulation layers.

[0108] In some embodiments, a portion of a lowermost redistribution line pattern of the redistribution line patterns 114 a and 124 a (eg, a portion of the second redistribution line pattern 124 a ) may perform a function of a terminal connection pad coupled to the external connection terminal 400 a .

[0109] The semiconductor chip 200 may be coupled on the redistribution line structure 100 a . A horizontal width W4 of the semiconductor chip 200 may be smaller than a horizontal width W3 a of the third redistribution line insulating layer 130 .

[0110] The redistribution line structure 100a may protrude outward in a horizontal direction more than the semiconductor chip 200. For example, each of the first to third redistribution line insulating layers 110a to 130a included in the redistribution line structure 100a may protrude outward in a horizontal direction more than the semiconductor chip 200.

[0111] In some embodiments, at least one of the plurality of redistribution line patterns 114a and 124a included in the redistribution line structure 100a may protrude further outward in a horizontal direction than the semiconductor chip 200. For example, Figure 5AIt is illustrated that a portion of the first redistribution line pattern 114a and a portion of the second redistribution line pattern 124a protrude outwardly more than the semiconductor chip 200 in the horizontal direction. However, the inventive concept is not limited thereto. For example, only a portion of the second redistribution line pattern 124a among the plurality of redistribution line patterns 114a and 124a may protrude outwardly more than the semiconductor chip 200 in the horizontal direction.

[0112] The semiconductor chip 200 may include a semiconductor substrate 210 and a chip pad 220 arranged on a surface of the semiconductor substrate 210 .

[0113] The first redistribution line via pattern 116a may be electrically connected to the chip pad 220 of the semiconductor chip 200. A portion of the first seed layer 112a may be located between the chip pad 220 and the first redistribution line via pattern 116a.

[0114] The fan-out type semiconductor package 2 may further include a molding member 300 surrounding the semiconductor chip 200 on the redistribution line structure 100a. The molding member 300 may cover the upper surface of the redistribution line structure 100a and the side surface and the upper surface of the semiconductor chip 200. The molding member 300 may cover a portion of the upper surface of the first redistribution line insulation layer 110a among the plurality of redistribution line insulation layers 110a, 120a, and 130a included in the redistribution line structure 100a. The molding member 300 may not cover the side surface of each of the plurality of redistribution line insulation layers 110a, 120a, and 130a.

[0115] The molding member 300 may protrude further outward than the redistribution line structure 100a in a horizontal direction. The horizontal width W5 of the molding member 300 may be greater than the horizontal width W1a of the first redistribution line insulation layer 110a. That is, the horizontal width W5 of the molding member 300 may be greater than the total horizontal width of the redistribution line structure 100a.

[0116] The lower surface of the molding member 300 and the upper surface of the redistribution line structure 100a (e.g., the upper surface of the first redistribution line insulation layer 110a) may be located at the same level. Also, the lower surface of the molding member 300 and the upper surface of the redistribution line structure 100a (e.g., the upper surface of the first redistribution line insulation layer 110a) may be coplanar.

[0117] A side surface of each of the plurality of redistribution line insulation layers 110a to 130a may be an inclined surface forming an acute angle (between 0° and 90°) with a normal to an upper surface of each of the plurality of redistribution line insulation layers 110a to 130a. The first redistribution line insulation layer 110a may have a first side surface SS1a, the second redistribution line insulation layer 110a may have a second side surface SS2a, and the third redistribution line insulation layer 130a may have a third side surface SS3a.

[0118] The first side surface SS1a of the first redistribution line insulation layer 110a may be an inclined surface at a first angle θ1a with respect to a normal line of an upper surface of the first redistribution line insulation layer 110a. The second side surface SS2a of the second redistribution line insulation layer 120a may be an inclined surface at a second angle θ2a with respect to a normal line of an upper surface of the second redistribution line insulation layer 120a. The third side surface SS3a of the third redistribution line insulation layer 130a may be an inclined surface at a third angle θ3a with respect to a normal line of an upper surface of the third redistribution line insulation layer 130a.

[0119] Any one of the first to third angles θ1a to θ3a may have a value different from the other angles. That is, any one of the first to third side surfaces SS1a to SS3a may be an inclined surface having an inclination different from the inclinations of the other side surfaces. For example, the first angle θ1a may be smaller than each of the second angle θ2a and the third angle θ3a. That is, the first side surface SS1a may be an inclined surface steeper than the second side surface SS2a and the third side surface SS3a. In some embodiments, the second angle θ2a and the third angle θ3a may be the same or substantially the same, but are not limited thereto. That is, the second side surface SS2a and the third side surface SS3a may be inclined surfaces having the same or substantially the same inclination, but are not limited thereto.

[0120] The thickness of any one of the plurality of redistribution line insulation layers 110a to 130a may be different from the thickness of the others. The first redistribution line insulation layer 110a may have a first thickness t1a, the second redistribution line insulation layer 120a may have a second thickness t2a, and the third redistribution line insulation layer 130a may have a third thickness t3a. For example, the first thickness t1a may be less than each of the second thickness t2a and the third thickness t3a. That is, the first redistribution line insulation layer 110a may be thinner than each of the second redistribution line insulation layer 120a and the third redistribution line insulation layer 130a. In some embodiments, the second thickness t2a and the third thickness t3a may be the same or substantially the same as each other, but are not limited thereto. That is, the second redistribution line insulation layer 120a and the third redistribution line insulation layer 130a may have the same or substantially the same thickness as each other, but are not limited thereto.

[0121] The fan-out semiconductor package 2 conceived according to the present invention may be formed so that the molding member 300 may not cover the side surfaces of the redistribution line structure 100a (i.e., the first side surface SS1a of the first redistribution line insulation layer 110a, the first side surface SS2a of the second redistribution line insulation layer 120a, the third side surface SS3a of the third redistribution line insulation layer 130a), and the molding member 300 may protrude further outward than the redistribution line structure 100a in the horizontal direction.

[0122] When a plurality of fan-out semiconductor packages are formed together and separated into individual fan-out semiconductor packages by performing a sawing process, a cutting process is performed on the molding member 300, and the redistribution line structure 100a is separated from the cutting surface of the molding member 300. Therefore, damage to the plurality of redistribution line insulating layers 110a to 130a can be reduced or prevented. Therefore, detachment of the plurality of redistribution line insulating layers 110a to 130a can be reduced or prevented, or cracks can be reduced or prevented from occurring in the plurality of redistribution line patterns 114a and 124a, thereby providing a fan-out semiconductor package 2 with improved reliability.

[0123] 6A to 6F is a cross-sectional view for sequentially describing a method for manufacturing a fan-out type semiconductor package according to at least one embodiment. In detail, 6A to 6F The process of manufacturing two fan-out semiconductor packages is described sequentially by showing the process of manufacturing two fan-out semiconductor packages together. Figure 5A and Figure 5B A cross-sectional view of a method of illustrating a fan-out semiconductor package 2, wherein only a portion of each of two fan-out semiconductor packages is illustrated, the portions being adjacent to each other, and Figure 5A and Figure 5B Unlike the case where the active surface of the semiconductor substrate 210 is the lower surface, the active surface of the semiconductor substrate 210 is the upper surface.

[0124] Reference Fig. 6A , a molding member 300 covering the side surface and the lower surface of the semiconductor chip 200 having the chip pad 220 arranged on the active surface (the active surface being the upper surface) of the semiconductor substrate 210 may be formed.

[0125] Reference Figure 6B, after forming the first redistribution line insulation layer 110a having the first via openings VO1a and the first separation spaces SP1a on the semiconductor chip 200 (whose side surfaces and lower surfaces are covered by the molding member 300), the first initial seed layer 112Pa may be formed. The first initial seed layer 112Pa may be conformally formed to cover the upper surface of the first redistribution line insulation layer 110a, the inner side surface of the first separation space SP1a, and the lower surface of the first separation space SP1a.

[0126] The first redistribution line insulation layer 110a may have a first side surface SS1a at one side of the first separation space SP1a. The first side surface SS1a may be an inclined surface forming an acute angle with a normal to a lower surface of the first redistribution line insulation layer 110a.

[0127] Reference Figure 6C , a mask pattern MKa having an opening OPa may be formed on the first initial seed layer 112Pa. The mask pattern MKa may completely cover the first separation space SP1a, and the opening OPa may be connected to the first via opening VO1a. Thereafter, by performing chemical plating, a first redistribution line pattern 114a and a first redistribution line via pattern 116a may be formed on a portion of the first initial seed layer 112Pa (the portion exposed in the opening OPa).

[0128] The first redistribution line pattern 114 a and the first redistribution line via pattern 116 a may be integrally formed with each other, and the first redistribution line via pattern 116 a may cover the first via opening VO1 a .

[0129] Reference Figure 6C and Fig.6D , the mask pattern MK may be removed, and a portion of the first preliminary seed layer 112Pa exposed by the removal of the mask pattern MKa may be removed to form a first seed layer 112a.

[0130] Reference Fig. 6E , you can Fig.6D A second redistribution line insulating layer 120a having a second via opening VO2a and a second separation space SP2a, a second seed layer 122a, a second redistribution line pattern 124a, a second redistribution line via pattern 126a, and a third redistribution line insulating layer 130a having a third separation space SP3a and a pad opening POa are formed on the resulting structure. The first separation space SP1a may be connected to the second separation space SP2a and the third separation space SP3a.

[0131] The second redistribution line pattern 124 a and the second redistribution line via pattern 126 a may be integrally formed with each other, and the second redistribution line via pattern 126 a may fill the second via opening VO2 a .

[0132] The second redistribution line insulation layer 120a may have a second side surface SS2a at one side of the second separation space SP2a. The second side surface SS2a may be an inclined surface forming an acute angle with a normal to a lower surface of the second redistribution line insulation layer 120a.

[0133] The third redistribution line insulation layer 130a may have a third side surface SS3a at one side of the third separation space SP3a. The third side surface SS3a may be an inclined surface forming an acute angle with a normal to a lower surface of the third redistribution line insulation layer 130a.

[0134] The plurality of redistribution line insulating layers 110a, 120a, and 130a included in the redistribution line structure 100a may be formed to have a stepped structure in which the widths of the plurality of redistribution line insulating layers 110a, 120a, and 130a decrease as they are away from the semiconductor chip 200 and the molding member 300. The width of each of the plurality of redistribution line insulating layers 110a, 120a, and 130a may decrease as they are away from the semiconductor chip 200 and the molding member 300.

[0135] Reference Fig. 6F , can be Fig. 6E A package sawing process is performed on the resultant structure to form fan-out type semiconductor packages 2 separated by kerf spaces KE between the fan-out type semiconductor packages 2 .

[0136] The package sawing process may be performed by cutting the molding member 300 and forming a kerf space KE in the molding member 300. Therefore, the kerf space KE may be spaced apart from side surfaces of the redistribution line structure 100a (i.e., the first side surface SS1a of the first redistribution line insulation layer 110a, the second side surface SS2a of the second redistribution line insulation layer 120a, and the third side surface SS3a of the third redistribution line insulation layer 130a).

[0137] Therefore, in the package sawing process of the fan-out semiconductor package 2, damage to the multiple redistribution line insulation layers 110a to 130a can be reduced or prevented, so that the multiple redistribution line insulation layers 110a to 130a will not detach from each other, or cracks will not appear in the multiple redistribution line patterns 114a, 124a and 134a.

[0138] Figure 7 is a cross-sectional view of a fan-out semiconductor package 2a according to at least one embodiment. Figure 7 The description of various aspects will be omitted. Figure 5A and Figure 5B and will mainly describe Figure 7 in Figure 5A and Figure 5B The difference.

[0139] Reference Figure 7 , the fan-out type semiconductor package 2 a may include a redistribution line structure 100 a and a plurality of semiconductor chips 200 a spaced apart from each other on the redistribution line structure 100 a .

[0140] The plurality of semiconductor chips 200a may include a first semiconductor chip 202 and a second semiconductor chip 204. The first semiconductor chip 202 may be, for example, a CPU chip, a GPU chip, or an AP chip. The second semiconductor chip 204 may be, for example, a DRAM chip, an SRAM chip, a flash memory chip, an EEPROM chip, a PRAM chip, an MRAM chip, or an RRAM chip. In some embodiments, the second semiconductor chip 204 may be an HBM DRAM semiconductor chip.

[0141] The footprint occupied by the plurality of semiconductor chips 200a may be smaller than the horizontal area of ​​the redistribution line structure 100a. The footprint occupied by the plurality of semiconductor chips 200a may completely overlap with the redistribution line structure 100a in the vertical direction.

[0142] A horizontal width W4a of a footprint occupied by the plurality of semiconductor chips 200a may be smaller than each of the horizontal widths W1a, W2a, W3a, and W5 of the first, second, and third redistribution line insulation layers 110a, 120a, and 130a.

[0143] Figure 8 is a cross-sectional view of a fan-out semiconductor package 2b according to at least one embodiment. Figure 8 The description of various aspects will be omitted. Figure 5A and Figure 5B and will mainly describe Figure 8 in Figure 5A and Figure 5B The difference.

[0144] Reference Figure 8 , the fan-out type semiconductor package 2 b may include a redistribution line structure 100 a and a semiconductor chip 200 located on the redistribution line structure 100 a .

[0145] The fan-out type semiconductor package 2b may further include a molding member 300a surrounding the semiconductor chip 200 on the redistribution line structure 100a. The molding member 300a may cover the upper surface of the redistribution line structure 100a and the side surface of the semiconductor chip 200, and may not cover but may expose the upper surface of the semiconductor chip 200, which is a non-active surface. The molding member 300a may cover a portion of the upper surface of the first redistribution line insulation layer 110a among the plurality of redistribution line insulation layers 110a, 120a, and 130a included in the redistribution line structure 100a. The molding member 300a may not cover the side surface of each of the plurality of redistribution line insulation layers 110a, 120a, and 130a.

[0146] In some embodiments, a heat dissipation member may be coupled to the upper surface of the semiconductor chip 200. The heat dissipation member may be, for example, a heat slug or a heat sink. In some embodiments, a TIM may be disposed between the heat dissipation member and the upper surface of the semiconductor chip 200.

[0147] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A fan-out semiconductor package, comprising: a redistribution line structure, the redistribution line structure comprising a plurality of redistribution line insulation layers and a plurality of redistribution line patterns, each of the redistribution line patterns being located on one of an upper surface and a lower surface of a redistribution line insulation layer in the plurality of redistribution line insulation layers; at least one semiconductor chip, the at least one semiconductor chip being located on the redistribution line structure and occupying a coverage area having a horizontal width smaller than a horizontal width of the redistribution line structure; as well as a molding member surrounding the at least one semiconductor chip on the redistribution line structure and having a horizontal width greater than a horizontal width of the redistribution line structure, Wherein, the plurality of redistribution line insulation layers have a stepped structure, The side surface of each of the plurality of redistribution line insulation layers is an inclined surface, and each of the inclined surfaces forms an acute angle with a normal line of a lower surface of the redistribution line insulation layer.

2. The fan-out semiconductor package according to claim 1, wherein: A horizontal width of a redistribution line insulation layer among the plurality of redistribution line insulation layers far from the at least one semiconductor chip is greater than a horizontal width of a redistribution line insulation layer among the plurality of redistribution line insulation layers close to the at least one semiconductor chip.

3. The fan-out semiconductor package according to claim 2, wherein: The molding member covers a side surface of each of the plurality of redistribution line insulation layers.

4. The fan-out semiconductor package according to claim 3, wherein: A lower surface of a redistribution line insulation layer, among the plurality of redistribution line insulation layers, which is farthest from the at least one semiconductor chip, is coplanar with a lower surface of the molding member.

5. The fan-out semiconductor package according to claim 1, wherein: A horizontal width of a redistribution line insulation layer among the plurality of redistribution line insulation layers far from the at least one semiconductor chip is smaller than a horizontal width of a redistribution line insulation layer among the plurality of redistribution line insulation layers close to the at least one semiconductor chip.

6. The fan-out semiconductor package according to claim 5, wherein: An upper surface of a redistribution line insulation layer among the plurality of redistribution line insulation layers closest to the at least one semiconductor chip is coplanar with a lower surface of the molding member.

7. The fan-out semiconductor package according to claim 3, wherein: A thickness of at least one of the plurality of redistribution line insulation layers is smaller than a thickness of other redistribution line insulation layers of the plurality of redistribution line insulation layers.

8. The fan-out semiconductor package according to claim 7, wherein: A thickness of a redistribution line insulation layer among the plurality of redistribution line insulation layers, which is closest to the at least one semiconductor chip, is smaller than thicknesses of other redistribution line insulation layers among the plurality of redistribution line insulation layers.

9. The fan-out semiconductor package according to claim 7, wherein: A thickness of a redistribution line insulation layer among the plurality of redistribution line insulation layers, which is farthest from the at least one semiconductor chip, is smaller than thicknesses of other redistribution line insulation layers among the plurality of redistribution line insulation layers.

10. The fan-out semiconductor package according to claim 1, wherein: At least one redistribution line pattern among the plurality of redistribution line patterns protrudes outward more than a footprint area of ​​the at least one semiconductor chip in a horizontal direction.

11. A fan-out semiconductor package, comprising: A redistribution line structure, the redistribution line structure comprising a plurality of redistribution line insulation layers having a stepped structure and a plurality of redistribution line patterns, each of the redistribution line patterns being located on one of an upper surface and a lower surface of a redistribution line insulation layer in the plurality of redistribution line insulation layers; at least one semiconductor chip located on the redistribution line structure and electrically connected to the plurality of redistribution line patterns; as well as a molding member surrounding the at least one semiconductor chip on the redistribution line structure, The horizontal width of the redistribution line insulation layer far from the at least one semiconductor chip among the plurality of redistribution line insulation layers is greater than the horizontal width of the redistribution line insulation layer close to the at least one semiconductor chip. The side surface of each of the plurality of redistribution line insulation layers is an inclined surface, and each of the inclined surfaces forms an acute angle with a normal line of a lower surface of the redistribution line insulation layer.

12. The fan-out semiconductor package according to claim 11, wherein: The molding member protrudes farther than the redistribution line structure in a horizontal direction.

13. The fan-out semiconductor package according to claim 12, wherein: The molding member has a horizontal width greater than a horizontal width of a footprint occupied by the at least one semiconductor chip and a horizontal width of the redistribution line structure, and The molding member covers a portion of an upper surface and a side surface of each of the plurality of redistribution line insulation layers.

14. The fan-out semiconductor package according to claim 11, wherein: An acute angle of a side surface of a redistribution line insulation layer among the plurality of redistribution line insulation layers farthest from the at least one semiconductor chip is smaller than acute angles of side surfaces of other redistribution line insulation layers among the plurality of redistribution line insulation layers.

15. The fan-out semiconductor package according to claim 11, wherein: The horizontal widths of the plurality of redistribution line insulation layers increase as they are farther away from the at least one semiconductor chip.

16. A fan-out semiconductor package, comprising: a redistribution line structure, the redistribution line structure comprising a plurality of redistribution line insulation layers having a stepped structure, a plurality of redistribution line patterns, and a plurality of redistribution line via patterns, each of the redistribution line patterns being located on an upper surface of one of the plurality of redistribution line insulation layers, each of the redistribution line via patterns being connected to one of the plurality of redistribution line patterns and penetrating one of the plurality of redistribution line insulation layers; at least one semiconductor chip located on the redistribution line structure and electrically connected to the plurality of redistribution line patterns and the plurality of redistribution line via patterns; as well as a molding member that surrounds the at least one semiconductor chip on the redistribution line structure and protrudes outward more than the redistribution line structure in a horizontal direction, The side surface of each of the plurality of redistribution line insulation layers is an inclined surface, each of the inclined surfaces forms an acute angle with a normal line of a lower surface of the redistribution line insulation layer, and An acute angle of a side surface of one of the plurality of redistribution line insulation layers is smaller than acute angles of side surfaces of other redistribution line insulation layers of the plurality of redistribution line insulation layers.

17. The fan-out semiconductor package according to claim 16, wherein: A thickness of a redistribution line insulation layer having a maximum horizontal width among the plurality of redistribution line insulation layers is smaller than thicknesses of other redistribution line insulation layers.

18. The fan-out semiconductor package according to claim 17, wherein: An acute angle of a side surface of the redistribution line insulation layer having the largest horizontal width among the plurality of redistribution line insulation layers is smaller than acute angles of side surfaces of the other redistribution line insulation layers.

19. The fan-out semiconductor package according to claim 17, wherein: The redistribution line insulation layer having the largest horizontal width among the plurality of redistribution line insulation layers is closer to the at least one semiconductor chip than the other redistribution line insulation layers.

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