Semiconductor device and testing device and method thereof

Abstract

A test device includes a test installation circuit, on which a plurality of semiconductor devices are installed as corresponding devices under test. Each device under test includes a corresponding delay control circuit and a target circuit. A test logic device electrically coupled to the test installation circuit is provided. The test logic device is configured to generate a test input, which is provided in parallel to the delay control circuits in the plurality of devices under test. The delay control circuit includes at least a first delay control circuit and a second delay control circuit, which are configured to transmit the test input to the corresponding first target circuit and the second target circuit during corresponding first test time intervals and second test time intervals that are out of phase with each other, so as to achieve a more uniform power consumption requirement of the test installation circuit during the test.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0092053 filed on August 7, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The inventive concept relates to a method of testing a semiconductor device, and more particularly, to a test device and a test method that reduce the occurrence of peak noise and / or peak power consumption during testing, and a semiconductor device on which testing is performed using the test device and the test method. Background Art

[0004] With the rapid development of the electronics industry and user needs, electronic devices have become more compact, more complex, and support larger capacities. Therefore, the testing of semiconductor devices included in electronic devices has become more complex. For example, in a production test environment, a semiconductor device including tens or hundreds of wafer dies or semiconductor packages can be tested simultaneously as a device under test (DUT). In addition, when the device under test (DUT) corresponds to a multi-channel and / or high-capacity memory device, the peak noise and / or peak power consumption may be too large as the operating current increases to tens of amperes (A). Summary of the invention

[0005] The inventive concept provides a test apparatus and a test method capable of reducing test performance degradation due to peak noise and / or peak power consumption in a test environment, and a semiconductor device on which a test is performed using the test apparatus and the test method.

[0006] According to some embodiments of the present invention, a test device is provided, which includes a test installation circuit and a test logic device. A plurality of semiconductor devices are installed on the test installation circuit as corresponding devices under test. Each of these devices under test includes a corresponding delay control circuit and a target circuit to be tested. The test logic device electrically coupled to the test installation circuit is configured to generate a test input, and the test input is usually provided in parallel to the delay control circuits in the plurality of devices under test. These delay control circuits may include at least a first delay control circuit and a second delay control circuit, which are configured to pass the test input to the corresponding first target circuit and the second target circuit during the corresponding first test time interval and the second test time interval that are out of phase with each other. Specifically, the first delay control circuit and the second delay control circuit can receive the same test input from the test logic device at the same time, but provide the test input to the first target circuit and the second target circuit at different times, so that before or after the second test mode is started in the second target circuit using the test input, the first test mode is started in the first target circuit using the test input.

[0007] In some embodiments of the present invention, the first delay control circuit may include a timing control circuit that enables a programmable first delay amount of the test input delay to be delivered to the first target circuit through the first delay control circuit. In addition, the first delay control circuit may be configured to bypass the timing control circuit when delivering the output test data generated by the first target circuit through the first delay control circuit. In some further embodiments of the present invention, the first delay control circuit may include a first timing control circuit that enables a plurality of different delay amounts corresponding to a plurality of partial delays of the test input to be delivered to the first target circuit through the first delay control circuit.

[0008] According to some further embodiments of the present invention, a method for testing a semiconductor device includes: providing a test input to a test installation circuit, on which a plurality of identical semiconductor devices are installed as devices under test, and the devices under test respectively include corresponding delay control circuits and target circuits. Then, the test input is transmitted from the test installation circuit to the plurality of delay control circuits in the plurality of devices under test. Next, the test input is transmitted from the plurality of delay control circuits to the corresponding plurality of target circuits to be tested in a staged asynchronous manner, so that before or after the second test mode is started in the second target circuit in the target circuit using the test input, the first test mode is started in the first target circuit in the target circuit using the test input. According to some of these embodiments of the present invention, the transmission includes: transmitting the test input from all the plurality of delay control circuits to all the corresponding plurality of target circuits to be tested in a staged asynchronous manner, so that each of the plurality of target circuits is tested in an asynchronous manner with respect to all other target circuits using the same test input. In addition, the delay control circuit in the device under test can provide a programmable delay to the test input. In addition, transmitting the test input from the test installation circuit may include: transmitting the test input from the test installation circuit to the plurality of delay control circuits in the plurality of devices under test in parallel.

[0009] According to another embodiment of the present invention, there is provided a test device, comprising: a device under test (DUT) mounting circuit on which a plurality of semiconductor devices are mounted as DUTs; and a test logic device configured to generate a test input provided to a target circuit in the plurality of semiconductor devices, and determine whether the DUT is defective based on the test output from the plurality of semiconductor devices. The test logic device may be configured to provide the test input to the plurality of semiconductor devices in parallel, and the timing of transmitting the test input to the target circuit in some of the plurality of semiconductor devices is different from the timing of transmitting the test input to the target circuit in some other of the plurality of semiconductor devices.

[0010] According to another embodiment of the present invention, there is provided a semiconductor device, including: a delay control circuit configured to receive a test input provided from an external test logic device in a test mode, delay the test input, and output the delayed test input; and a target circuit configured to receive the delayed test input from the delay control circuit. The delay control circuit is configured to delay the test input according to a delay amount set in response to a delay control signal in the test mode. According to another embodiment of the present invention, there is provided a method for testing a semiconductor device, the semiconductor device including a delay control circuit having a programmable delay amount. The method may include: setting a delay amount of the delay control circuit in response to a delay control signal in the test mode; receiving a test input from an external test logic device; performing delay processing on the received test input according to the set delay amount; and sending the delayed test input to the target circuit in the semiconductor device. The moment of transmitting the test input to the target circuit may be adjusted according to the set delay amount. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Embodiments of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a block diagram of a test device according to an example embodiment of the inventive concept;

[0013] Figure 2 and Figure 3 is a block diagram showing an example of a delay control circuit provided in a semiconductor device;

[0014] Figure 4A and Figure 4B is a schematic diagram showing an example of a design for testability (DFT) circuit according to an embodiment of the inventive concept;

[0015] Figure 5 and Figure 6 is a flowchart of a method of testing a semiconductor device according to an example embodiment of the inventive concept;

[0016] Fig. 7A and Figure 7B is a view illustrating an example of a test operation of a semiconductor wafer according to an example embodiment of the inventive concept;

[0017] Figure 8 and Fig. 9 are schematic diagrams respectively showing an example of a group setting of a plurality of devices under test (DUTs) arranged on a test board and an example of delaying a test input;

[0018] Fig.10 and Fig.11is a block diagram showing an example of setting a delay amount of a DUT according to various methods;

[0019] Fig.12 is a block diagram illustrating an example of implementing a semiconductor device according to an example embodiment of the inventive concept as a high bandwidth memory (HBM);

[0020] Fig.13 and Fig.14 is a circuit diagram illustrating an example of a delay control circuit according to an example embodiment of the inventive concept; and

[0021] Fig.15 is a block diagram illustrating an example of implementing a semiconductor device according to an example embodiment of the inventive concept as a memory device. DETAILED DESCRIPTION

[0022] The present invention will now be described more fully with reference to the accompanying drawings, in which preferred embodiments of the present invention are shown. However, the present invention may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and will fully convey the scope of the present disclosure to those skilled in the art. Throughout the drawings, like reference numerals refer to like elements.

[0023] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be referred to as a second element, component, region, layer or part.

[0024] The terms used herein are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. As used herein, the singular forms "one", "an" and "said" are intended to also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when used in this specification, the terms "comprise", "include", "have" and their variants indicate the presence of stated features, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or their combinations. On the contrary, when used in this specification, the term "consisting of..." indicates stated features, steps, operations, elements and / or components, and excludes additional features, steps, operations, elements and / or components.

[0025] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. It should also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted as an ideal or overly formal meaning unless explicitly defined as such herein.

[0026] Figure 1 is a block diagram of a test apparatus 100 according to an exemplary embodiment of the inventive concept. Figure 1 , a test device 100 for testing a semiconductor device may include a tester (or a test logic device) 110 and at least one device under test (DUT) to be tested. In an embodiment, the test device 100 may include a test board, and the test board may include a DUT mounting circuit 120 on which a plurality of DUTs are mounted. Figure 1 An example is shown in which the test logic device 110 is mounted on the test board, but embodiments of the inventive concept are not limited thereto. For example, the test logic device 110 may be defined as being located outside the test board.

[0027] The DUT mounting circuit 120 may include a plurality of sockets (not shown) on which a plurality of semiconductor devices 121_1 to 121_N are mounted as DUTs, respectively. Figure 1 Although not shown in the figure, the test device 100 may further include: a communication device (not shown) for communicating with an external host requesting a test; a memory (not shown) for temporarily storing various types of information related to various tests; and a power supply circuit (not shown) for supplying power to various devices provided in the test device 100. In addition, the test device 100 according to the exemplary embodiment of the present inventive concept may be defined differently. For example, in Figure 1 , components other than the plurality of semiconductor devices 121_1 to 121_N may be defined as constituting the test device 100 .

[0028] According to an embodiment, the test logic device 110 may be implemented as a semiconductor chip such as a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or an application processor (AP), and may transmit and receive various information to and from the semiconductor devices 121_1 to 121_N according to a parallel communication method. For example, the test logic device 110 may provide a test input to the DUT mounting circuit 120 through a plurality of channels, and a plurality of semiconductor devices 121_1 to 121_N in the DUT mounting circuit 120 may receive the test input in parallel from the test logic device 110.

[0029] The test process for determining whether a semiconductor device is defective may be performed at various stages of the semiconductor process, and may include, for example, wafer-level testing and testing after the wafer-level testing. Wafer-level testing may correspond to testing of individual semiconductor dies at the wafer level. Testing after the wafer-level testing may be testing of semiconductor dies before packaging is performed, or may be testing of a semiconductor package in which one semiconductor die (or semiconductor chip) is packaged. Testing of a semiconductor package may be testing of a semiconductor package including a plurality of semiconductor chips. According to an embodiment, when Figure 1 When the test device 100 shown in FIG. 1 is a device for performing a wafer-level test, the plurality of semiconductor devices 121_1 to 121_N may respectively correspond to a plurality of semiconductor dies formed on a semiconductor wafer, and the DUT mounting circuit 120 may be a device on which a semiconductor wafer is placed. Figure 1 When the test apparatus 100 shown in FIG. 1 is an apparatus for testing a semiconductor package, each of the semiconductor devices 121_1 to 121_N mounted on the DUT mounting circuit 120 may be a semiconductor package.

[0030] The semiconductor devices 121_1 to 121_N may be devices that perform various functions. For example, each of the semiconductor devices 121_1 to 121_N may be a memory device including a memory cell array. For example, the memory device may be a dynamic random access memory (DRAM), such as a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate (LPDDR) SDRAM, a graphic double data rate (GDDR) SDRAM, or a Rambus dynamic random access memory (RDRAM). Alternatively, the memory device may correspond to a non-volatile memory, such as a flash memory, a magnetic RAM (MRAM), a ferroelectric RAM (FeRAM), a phase change RAM (PRAM), or a resistive RAM (ReRAM).

[0031] According to an embodiment, the test inputs Input_1 to Input_M from the test logic device 110 may be provided in parallel to the semiconductor devices 121_1 to 121_N in the DUT mounting circuit 120. Each of the semiconductor devices 121_1 to 121_N may include a delay control circuit 122. The delay control circuit 122 may delay the received test input and provide the delayed test input to a target circuit (not shown) in the semiconductor device. For example, referring to the semiconductor device 121_1 as a first semiconductor, the delay control circuit 122 may receive a first test input (i.e., the test input Input_1) and delay the first test input, and send the delayed first test input to a target circuit in the first semiconductor device (i.e., the semiconductor device 121_1).

[0032] According to an embodiment, the plurality of semiconductor devices 121_1 to 121_N can delay the corresponding test input according to different delay amounts. Therefore, the test inputs Input_1 to Input_M are provided to the DUT mounting circuit 120 in parallel (or simultaneously), and the plurality of semiconductor devices 121_1 to 121_N can provide the corresponding test inputs to the corresponding internal target circuits at different time points. Therefore, the plurality of semiconductor devices 121_1 to 121_N can be tested at different times, thereby dispersing the large peak noise that may be caused by simultaneous testing, and thus the characteristics of the DUT can be prevented from being degraded in a parallel test environment.

[0033] According to an embodiment, the number of test inputs Input_1 to Input_M may be equal to the number of semiconductor devices 121_1 to 121_N. The number of test inputs Input_1 to Input_M may be greater than or less than the number of semiconductor devices 121_1 to 121_N. For example, when one test input is provided to each of the semiconductor devices 121_1 to 121_N, the number of test inputs Input_1 to Input_M may be equal to the number of semiconductor devices 121_1 to 121_N. When the semiconductor devices 121_1 to 121_N are classified into a plurality of groups and the same test input is provided for each group, the number of test inputs Input_1 to Input_M may be less than the number of semiconductor devices 121_1 to 121_N. When each of the semiconductor devices 121_1 to 121_N includes a plurality of channels communicating through an independent interface and a separate test input is provided to each channel, the number of test inputs Input_1 to Input_M may be greater than the number of semiconductor devices 121_1 to 121_N.

[0034] According to an embodiment, the delay control circuit 122 within each of the semiconductor devices 121_1 to 121_N may delay the test input according to a programmable delay amount. By way of example, each of the semiconductor devices 121_1 to 121_N may include an element for generating a delay control signal (wherein the delay control signal is used to set the delay amount of the delay control circuit 122), and may delay the test input according to the set delay amount during a test operation mode. In this test operation mode, the test logic device 110 may provide a delay control signal Ctrl_delay to the semiconductor devices 121_1 to 121_N, and each of the semiconductor devices 121_1 to 121_N may set the delay amount in response to the delay control signal Ctrl_delay.

[0035] According to an embodiment, when the delay amounts of the delay control circuits 122 of the semiconductor devices 121_1 to 121_N are set differently, the times of providing the test inputs Input_1 to Input_M to the target circuits of the semiconductor devices 121_1 to 121_N may be different from each other, and thus the times of performing tests on the semiconductor devices 121_1 to 121_N may be different from each other.

[0036] The plurality of semiconductor devices 121_1 to 121_N may be classified into one or more groups, and each group may include one or more semiconductor devices. In addition, when the delay amount of the delay control circuit 122 is set differently on a group basis, the test input may be simultaneously provided to the target circuits of the semiconductor devices belonging to the same group. For example, the delay control circuits 122 of the semiconductor devices belonging to the same group may delay the test input according to the same delay amount. On the other hand, the delay control circuits 122 of the semiconductor devices belonging to different groups may delay the test input according to different delay amounts.

[0037] When any one semiconductor device includes a plurality of channels for receiving test inputs through independent interfaces as described above, tests may be performed on the plurality of channels of each of the semiconductor devices 121_1 to 121_N at different times. In an embodiment, each of the semiconductor devices 121_1 to 121_N may include a plurality of delay control circuits 122 corresponding to the plurality of channels, respectively, and target circuits corresponding to the plurality of delay control circuits 122, respectively, and the delay control circuits 122 of the plurality of channels may delay the test inputs according to different delay amounts.

[0038] According to the above-described embodiment, the semiconductor devices 121_1 to 121_N that may consume a large amount of current when operating in a parallel test environment can be prevented from performing the same operation at the same time. Therefore, the peak current and peak noise of the test device 100 can be reduced, and the characteristics of the DUT can be prevented from being degraded in the test environment. In addition, since it is not necessary to sequentially provide the test inputs Input_1 to Input_M for each semiconductor device from the perspective of the test logic device 110, the test speed can be prevented from being degraded in the parallel test environment.

[0039] When the semiconductor devices 121_1 to 121_N sequentially perform process operations using the test inputs Input_1 to Input_M, the test logic device 110 may sequentially receive test results from the semiconductor devices 121_1 to 121_N of the DUT mounting circuit 120, and may determine whether the semiconductor devices 121_1 to 121_N are defective based on the logic process. For example, the test logic device 110 may determine whether the semiconductor devices 121_1 to 121_N are defective based on determining whether the pattern of the test inputs Input_1 to Input_M provided to the semiconductor devices 121_1 to 121_N is the same as the pattern of the test output provided from the semiconductor devices 121_1 to 121_N.

[0040] Figure 2 and Figure 3 is a block diagram showing an example of a delay control circuit provided in a semiconductor device. Figure 2 The semiconductor device 200A may include a target circuit 220A for receiving a test input and the above-mentioned delay control circuit. The delay control circuit may also be referred to as a design for testability (DFT) circuit 210A, which is a circuit for managing test operations in the semiconductor device 200A. Figure 2 As shown, a test input Input (eg, from an external test logic device) is sent to a target circuit 220A via a DFT circuit 210A.

[0041] The DFT circuit 210A may include a buffer circuit (e.g., a DFT buffer 211A) for receiving a test input Input from an external test logic device and a timing control circuit 212A for receiving the test input Input provided by the DFT buffer 211A and delaying the received test input Input. The target circuit 220A may also include a buffer 221A for receiving a delayed test input, and the buffer 221A may provide the delayed test input to another circuit block (not shown) in the semiconductor device 200A. By way of example, when the semiconductor device 200A corresponds to a memory device including a memory cell array, the delayed test input may have a pattern to be stored in the memory cell array and may be provided to the memory cell array.

[0042] According to an embodiment, the timing control circuit 212A may include a programmable delay circuit, and the delay amount of the timing control circuit 212A may be programmed by various methods such as fuse cutting. For example, a control logic device (not shown) for generating a delay control signal according to a mode may be provided in the semiconductor device 200A, and the delay amount of the timing control circuit 212A may be set based on the control of the control logic device in a test mode. When the above-mentioned external test logic device provides a delay control signal to the semiconductor device 200A, the delay amount of the timing control circuit 212A may be set.

[0043] By way of example, a large number of semiconductor devices 200A can be mass-produced, a DFT circuit 210A can be provided in each of the large number of semiconductor devices 200A, and different delay control signals can be provided to the semiconductor devices 200A in a test mode. Therefore, the delay amount of the test input Input of the plurality of semiconductor devices 200A mounted on one test board can be set differently, and thus the moment of transmitting the test input Input to the target circuit 220A in the plurality of semiconductor devices 200A can be adjusted differently. Therefore, when the test operation is performed in a parallel test environment, the test can be performed on the plurality of semiconductor devices 200A at different times, regardless of when the test input Input is applied from the external test logic device. If the plurality of semiconductor devices 200A are set as a group according to the above example and the test is performed on the semiconductor devices 200A in the same group at the same time, the same delay amount can be set in the timing control circuit 212A of the semiconductor devices 200A in the same group. On the other hand, for the semiconductor devices 200A in different groups, different delay amounts can be set for each group.

[0044] The semiconductor device 200A can perform signal processing using the received test input Input, and provide the processing result as a test output Output to an external test logic device. For example, the DFT buffer 211A may include an input buffer and a transmission buffer, and the test input Input received by the input buffer may be provided to the target circuit 220A via the timing control circuit 212A, and the test output from the target circuit 220A may be provided to the DFT buffer 211A without passing through the timing control circuit 212A.

[0045] Despite Figure 2 2 shows an example in which the target circuit 220A (to which the test input Input is provided) includes the buffer 221A, but the target circuit 220A may be defined differently. By way of example, when the semiconductor device 200A corresponds to a memory device, the test input Input may be provided to various circuit blocks related to the memory operation in the memory device via the buffer 221A, and the target circuit 220A may be defined to include various circuit blocks. By way of example, according to the delay processing of the timing control circuit 212A, the moment at which the test input Input is provided to at least some of the various circuit blocks may be adjusted.

[0046] Figure 3 2 shows an example in which a semiconductor device 200B includes a plurality of channels.

[0047] refer to Figure 3 , the semiconductor device 200B may include a DFT circuit 210B and a target circuit 220B, and a test input from an external test logic device may be provided to the target circuit 220 via the DFT circuit 210B. In addition, the DFT circuit 210B may include a DFT buffer 211B and a timing control circuit 212B. Assuming that the semiconductor device 200B includes A channels, the target circuit 220B may include a first channel buffer 221B_1 to an Ath channel buffer 221B_A.

[0048] although Figure 3An example is shown in which a test input Input is provided to the timing control circuit 212B via the DFT buffer 211B, and the timing control circuit 212B shunts the test input Input and provides the test input Input to the first channel buffer 221B_1 to the Ath channel buffer 221B_A, but the embodiments of the present invention are not limited thereto. For example, the DFT circuit 210B may include a plurality of DFT buffers 211B, an external test logic device may provide a plurality of test inputs Input corresponding to a plurality of channels to the DFT circuit 210B, and the timing control circuit 212B may perform delay processing operations on the plurality of test inputs Input. For example, different delay amounts may be applied to the plurality of test inputs Input, and the plurality of test inputs Input may be provided to the first channel buffer 221B_1 to the Ath channel buffer 221B_A of the target circuit 220B at different times.

[0049] The test input Input provided to the first channel buffer 221B_1 to the Ath channel buffer 221B_A may be independently sent to circuit blocks included in the plurality of channels. For example, when the test input Input corresponds to a pattern to be written into the memory cell array, the test input Input may be provided to the memory cell arrays provided in the plurality of channels at different times.

[0050] Figure 4A and Figure 4B is a schematic diagram illustrating an example of a DFT circuit according to an embodiment of the inventive concept. Figure 4A 1 shows a case where a test input in a test mode and a normal input in a normal mode are received via different pads. Figure 4B A case where a test input and a normal input are received via the same pad is shown.

[0051] refer to Figure 4A , the semiconductor device may include a first input / output buffer IO Buf_N and a second input / output buffer IO Buf_T, the first input / output buffer IO Buf_N is used to receive a normal input via a first pad PAD1 in a normal mode, and the second input / output buffer IO Buf_T is used to receive a test input via a second pad PAD2 in a test mode. Figure 4A, a first pad (i.e., first pad PAD1) for receiving a normal input and a second pad (i.e., second pad PAD2) for receiving a test input are shown, but the semiconductor device may include a plurality of first pads for receiving a normal input and a plurality of second pads for receiving a test input. For example, the semiconductor device may send and receive information through an external memory controller and the first pad PAD1, and may send and receive information through a tester (or a test logic device) and the second pad PAD2.

[0052] According to an embodiment, the delay control circuit Delay Ctrl may be placed on a path for sending a test input via the second input / output buffer IOBuf_T, and the delay amount of the delay control circuit Delay Ctrl may be set in response to a delay control signal in a test mode. As described above, the delay amount of the delay control circuit Delay Ctrl may be set in response to a delay control signal from an external test logic device or a control logic device in a semiconductor device in a test mode.

[0053] The test output may be generated after a certain delay time after the test input is provided to the target circuit. According to an embodiment, the test output may be sent to the outside via the second pad PAD2 without passing through the delay control circuit Delay Ctrl.

[0054] refer to Figure 4B , the input / output buffer IO Buf of the semiconductor device can receive normal input via the pad PAD in the normal mode. In addition, the input / output buffer IO Buf can receive test input via the pad PAD in the test mode. In the test mode of the semiconductor device, the delay amount of the delay control circuit Delay Ctrl can be set according to the above embodiment, and the test input can be provided to the target circuit through the delay control circuit Delay Ctrl.

[0055] The input / output buffer IO Buf can be used to receive a normal input in a normal mode, and can provide the normal input to the target circuit without delay. According to an embodiment, the delay control circuit Delay Ctrl can receive a mode control signal Ctrl_mode, and can enable or disable a delay operation according to the mode control signal Ctrl_mode. In an example, the mode control signal Ctrl_mode can be generated in a semiconductor device, and in normal mode, the mode control signal Ctrl_mode can include information for disabling the delay control circuit Delay Ctrl, so that the delay process can not be applied to the normal input. In addition, in an embodiment, the delay control circuit Delay Ctrl may include a transmission path (first path) to which a delay is applied and a transmission path (second path) to which a delay is not applied, and can send a test input via the first path or send a normal input via the second path in response to the mode control signal Ctrl_mode.

[0056] Figure 5 and Figure 6 is a flowchart of a method for testing a semiconductor device according to an example embodiment of the inventive concept. Figure 5 , wafer-level testing and / or testing after wafer-level testing can be performed during the manufacturing process of the semiconductor device, so that the semiconductor device can enter a test mode based on control from an external tester (operation S11). In addition, the semiconductor device may include a delay control circuit for performing delay processing on a test input, and the delay amount of the delay control circuit can be programmed in response to a delay control signal. By way of example, in the test mode, the semiconductor device can receive a delay control signal from an external tester, and can set the delay amount of the delay control circuit in response to the delay control signal (operation S12). By way of example, when a plurality of semiconductor devices are mass-produced and the plurality of semiconductor devices are tested by the same tester (or mounted on the same test board), the delay amounts applied to the plurality of semiconductor devices may be different from each other.

[0057] After the delay amount is set, the semiconductor device may receive a test input from an external tester and perform delay processing on the received test input (operation S13). The delayed test input may be sent to a target circuit in the semiconductor device (operation S14). By way of example, the target circuit may correspond to one or more different types of circuit blocks, and when the semiconductor device is a memory device and the test input has pattern information to be written into a memory cell array, the delayed test input may be provided to the memory cell array via a data input buffer.

[0058] In addition, according to the above-mentioned embodiment, different delay amounts can be set for multiple semiconductor devices to be tested by the same tester based on a delay control signal, so even if the test input from the tester is provided to multiple semiconductor devices at the same time, the multiple semiconductor devices can perform signal processing for testing at different times.

[0059] Figure 6 An example of the operation of a test device for a test operation according to an embodiment of the inventive concept is shown. The test device may include a test logic device for generating a test input and a DUT mounting circuit on which a plurality of semiconductor devices as DUTs are mounted, respectively. Figure 6 In the operation example of FIG. 1 , a first DUT and a second DUT are shown.

[0060] The test logic device can output multiple test inputs in parallel to test multiple DUTs (operation S21), and can provide multiple test inputs to the DUT mounting circuit at the same time. For example, a first test input can be provided to a first DUT, and a second test input can be provided to a second DUT, and the time when the first test input is provided to the first DUT and the time when the second test input is provided to the second DUT can be substantially the same.

[0061] The first DUT may perform delay processing on the first test input internally and then provide the first test input to the target circuit of the first DUT (operation S22). In addition, the second DUT may perform delay processing on the second test input internally, and may provide the second test input to the target circuit of the second DUT after the first delay after providing the first test input to the target circuit of the first DUT according to the result of performing the delay processing on the second test input internally (operation S23). That is, the difference between the delay amount in the first DUT and the delay amount in the second DUT may correspond to the first delay.

[0062] The first DUT may perform internal signal processing by using the first test input, and may provide a first test result from the first DUT to the test logic device (operation S24). In addition, a second test result from the second DUT may be provided to the test logic device after a second delay after the first test result is provided to the test logic device (operation S25). That is, from the perspective of the test logic device, although the first test input and the second test input are provided to the first DUT and the second DUT at the same time, a difference between the time when the test result is received from the first DUT and the time when the test result is received from the second DUT corresponding to the second delay may be generated.

[0063] The test logic device may determine whether the DUT mounted on the DUT mounting circuit is defective by using a plurality of test results including the first test result and the second test result (operation S26).

[0064] Fig. 7A and Figure 7B 2 is a diagram illustrating an example of a test operation for a semiconductor wafer according to an example embodiment of the inventive concept. Fig. 7A , a plurality of semiconductor dies manufactured by a semiconductor manufacturing process on a semiconductor wafer may be arranged in an array, and in a wafer-level test operation, each of the plurality of semiconductor dies may constitute a DUT. For example, each of the semiconductor dies may have a contact pad (not shown) for electrically connecting an internal circuit to an external device. In addition, although Fig. 7A Although not shown in the drawings, the delay control circuit for performing delay processing on the test input according to the above-described embodiments may be formed in each of the semiconductor dies.

[0065] refer to Figure 7B , the test device 300 according to the example embodiment of the inventive concept may include a probe card 310 for performing a test at a wafer level, and pins 312 that may be electrically contacted with contact pads of a semiconductor die may be arranged on one side of the probe card 310. In addition, the test device 300 according to the example embodiment of the inventive concept may include various components, and for example, a plurality of semiconductor dies formed in a semiconductor wafer 320 as test objects may also be included in the test device 300. The semiconductor wafer 320 may be placed on a wafer prober, and the wafer prober may adjust the position of the semiconductor wafer 320 so that the contact pads of the semiconductor wafer 320 electrically contact the pins 312 of the probe card 310.

[0066] The probe card 310 may have a flat structure including a first surface and a second surface, wherein the pins are arranged on the first surface and a logic circuit is formed on the second surface. For example, the probe card 310 may be implemented with a printed circuit board, and the test logic device 311 may be implemented in or near the second surface.

[0067] According to an example embodiment of the inventive concept, the test logic device 311 of the probe card 310 may control a test operation on a plurality of semiconductor dies formed in a semiconductor wafer 320. By way of example, the test logic device 311 of the probe card 310 may provide a delay control signal to the semiconductor die, the delay control signal being used to adjust the timing of sending a test input provided to the semiconductor die to a target circuit. According to an embodiment, the plurality of semiconductor dies formed in the semiconductor wafer 320 may be classified into a plurality of groups, and different delay amounts may be set for the plurality of groups. Each of the semiconductor dies may include a plurality of channels, and different delay amounts may be set for the plurality of channels.

[0068] Figure 8 and Fig. 9 1 and 2 are schematic diagrams respectively showing an example of a group setting of a plurality of DUTs arranged on a test board and an example of delaying a test input. Figure 8 , a plurality of semiconductor devices are respectively mounted as DUTs on a test board provided in the test device 400A. The plurality of semiconductor devices are classified into a first group Group 1 to a B-th group Group B, and each of the first group Group 1 to the B-th group Group B may include a plurality of semiconductor devices. Figure 8 In the example of , the first group Group 1 to the Bth group Group B include the same number of semiconductor devices. However, the embodiments of the inventive concept are not limited thereto. For example, the first group Group 1 to the Bth group Group B may include different numbers of semiconductor devices. Figure 8 In the present invention, the DUT to be tested can be a semiconductor die or a semiconductor package.

[0069] Fig. 9 Shows the installation Figure 8 The time when the target circuits in the multiple DUTs on the test board send the test input. For example, the tester (or test logic device) can provide a bit stream with one or more bits of information as a test input to multiple semiconductor devices, and the time when the test input is provided to the multiple semiconductor devices can be substantially the same. That is, the tester can provide test input to multiple semiconductor devices at the same time in a parallel test environment.

[0070] According to an embodiment, the delay control circuits of the semiconductor devices in the first group Group 1 may delay the test input according to the first delay amount Delay 1, and the delay control circuits of the semiconductor devices in the second group Group 2 may delay the test input according to the second delay amount Delay 2. Similarly, the delay control circuits of the semiconductor devices in the B-th group Group B may delay the test input according to the B-th delay amount Delay B. The test input to which the delay is applied and provided to the target circuit may be referred to as a valid bit stream, which is effectively provided for testing.

[0071] Fig.10 and Fig.11 is a block diagram showing an example of setting the delay amount for a DUT according to various methods. Fig.10 shows examples of setting different delay amounts for the DUT, and Fig.11 An example of setting different delay amounts for channels in one DUT is shown.

[0072] refer to Fig.10 In the test device 400B, a plurality of semiconductor devices are mounted on the test board as DUTs. Fig.10 An example in which a plurality of semiconductor devices are arranged in a matrix form is shown, but a plurality of semiconductor devices may be arranged on the test board in various forms. Fig.10 As shown, a plurality of semiconductor devices may be arranged in I rows and J columns, so I*J semiconductor devices may be mounted on a test board, and different delay amounts Delay 1 to Delay I*J may be set for the I*J semiconductor devices. Therefore, even if test inputs are provided to the I*J semiconductor devices mounted on the test board at the same time point in a parallel test environment, the test inputs may be transmitted to target circuits in the I*J semiconductor devices at substantially different time points, so that tests for the I*J semiconductor devices may be performed at different time points.

[0073] refer to Fig.11 In the test device 400C, a plurality of semiconductor devices 410C as DUTs may be mounted on a test board, respectively, and each of the semiconductor devices 410C may include a plurality of channels CH 1 to CH A. According to the above-described embodiment, a test input supplied to any one semiconductor device 410C may be supplied to the plurality of channels CH 1 to CH A in the semiconductor device 410C, and delay amounts of the test inputs may be set differently for the plurality of channels CH 1 to CH A. Fig.11An example is shown in which a first delay amount Delay 1 is set for a first channel (i.e., channel CH 1), a second delay amount Delay 2 is set for a second channel (i.e., channel CH 2), and an A-th delay amount Delay A is set for an A-th channel (i.e., channel CH A). Therefore, in any of the semiconductor devices 410C, even if a test input is provided to a plurality of channels CH 1 to CH A at the same time point, the test input can be transmitted to target circuits of the plurality of channels CH 1 to CH A at different time points.

[0074] Fig.12 is a block diagram illustrating an example of implementing a semiconductor device according to an example embodiment of the inventive concept as a high bandwidth memory (HBM) 500. Fig.12 , the HBM 500 may include a plurality of semiconductor dies, for example, a logic die (or buffer die) 510 and one or more core dies 520 including a memory cell array 521. The HBM 500 may have an increased bandwidth by including a plurality of channels CH 1 to CH 8 having independent interfaces, Fig.12 An example is shown in which the HBM 500 includes four core dies 520 and each of the four core dies 520 includes two channels. However, the number of the core dies 520 and the number of the channels CH 1 to CH 8 may be variously changed.

[0075] The logic die 510 may include a through silicon via (TSV) region 511, a physical (PHY) region 512, and a direct access region 513. The logic die 510 may also include a control logic device (not shown) for controlling the overall operation in the HBM 500, and may perform, for example, an internal control operation in response to a command from an external controller. In addition, according to the above-described embodiment, a delay control circuit 514 for delaying a test input may also be included in the logic die 510.

[0076] The TSV region 511 corresponds to a region where a TSV for communication with the core die 520 is formed. The PHY region 512 may include a plurality of input and output circuits for communicating with an external controller, and the direct access region 513 may communicate directly with an external tester via a conductive device located on an outer surface of the HBM 500 in a test mode for the HBM 500. Various signals provided from an external tester may be provided to the core die 520 via the direct access region 513 and the TSV region 511. A test input from an external tester may be provided to the delay control circuit 514 via the direct access region 513, and a delayed test input may be provided to the core die 520 via the TSV region 511.

[0077] According to an example embodiment of the inventive concept, the HBM 500 may be mounted on a test board and receive a test input in a test mode, and for example, a plurality of HBMs 500 may be mounted on the test board. The delay control circuit 514 may receive a test input commonly provided for a plurality of channels CH 1 to CH 8, delay the test input, and then provide the delayed test input to the plurality of channels CH 1 to CH 8. In another embodiment, the delay control circuit 514 may receive a test input provided for a plurality of channels CH 1 to CH 8, respectively, and may output a delayed test input by delaying the test input.

[0078] According to another embodiment, test inputs may be provided to target circuits included in a plurality of channels CH 1 to CH 8 at different times. A plurality of channels CH 1 to CH 8 may be classified into a plurality of channel groups, and test inputs may be provided to target circuits at different times for the channel groups. For example, for the first core die Core Die1 and the second core die Core Die2, test inputs may be provided to target circuits of the first channel and the third channel (i.e., channels CH1 and CH3) of the first core die Core Die1, and then test inputs may be provided to target circuits of the second channel and the fourth channel (i.e., channels CH2 and CH4) of the second core die Core Die2. As various example embodiments, test inputs may be provided to target circuits of channels CH 1 to CH 8 regardless of the stacking order of the plurality of core dies stacked on the logic die 510.

[0079] Fig.13 and Fig.14 is a circuit diagram illustrating an example of a delay control circuit according to an example embodiment of the inventive concept. Fig.13 , the semiconductor device 600A may include a delay control circuit and a target circuit 630A, and the delay control circuit may include a DFT buffer 610A and a timing control circuit 620A. In addition, the timing control circuit 620A may include a plurality of transmission paths for transmitting a test input to the target circuit 630A, and different delay amounts may be applied to the plurality of transmission paths. In addition, a plurality of switches SW1 to SWC may be further included in the timing control circuit 620A to select any one of the plurality of transmission paths.

[0080] According to the above embodiment, the plurality of switches SW1 to SWC can be controlled in response to the delay control signal Ctrl_delay. For example, the semiconductor device 600A can set the delay amount of the test input by selectively turning on any one of the plurality of switches SW1 to SWC in the test mode. For example, in the test mode of the semiconductor device 600A, any one of the plurality of transmission paths can be selected according to the delay control signal Ctrl_delay from the test logic device, so that the delay amount of the test input can be adjusted.

[0081] refer to Fig.14 , the semiconductor device 600B may include a delay control circuit and target circuits 630B_1 to 630B_A, and the delay control circuit may include a DFT buffer 610B and a timing control circuit 620B. Fig.14 FIG. 6 shows an example in which a semiconductor device 600B includes a plurality of channels CH 1 to CH A. Fig.13 As in the embodiment of the present invention, the timing control circuit 620B includes multiple transmission paths, and different delay amounts can be applied to the multiple transmission paths. The timing control circuit 620B may also include multiple switch blocks SW BLK 1 to SW BLK A, which correspond to multiple channels CH 1 to CH A, respectively, and the multiple switch blocks SW BLK 1 to SW BLK A may be controlled by the delay control signal Ctrl_delay.

[0082] According to example embodiments, the switch states of the switch blocks SW BLK 1 to SW BLK A in the test mode of the semiconductor device 600B may be controlled differently. Therefore, the paths for transmitting the test inputs to the target circuits of the plurality of channels CH 1 to CH A may be different from each other. Therefore, the timings for providing the test inputs to the target circuits of the plurality of channels CH 1 to CH A of the semiconductor device 600B may be adjusted differently.

[0083] Fig.15 7 is a block diagram showing an example of implementing a semiconductor device according to an example embodiment of the inventive concept as a memory device 700. Fig.15 , the memory device 700 may include a memory cell array 711, a row decoder 712, and a column decoder 713 to perform memory operations of storing data and reading data. The memory device 700 may also include a control logic device 720 for controlling the overall operation in the memory device 700 and a data buffer 730 for temporarily storing input / output data. In addition, the memory device 700 may also include various other components related to memory operations, such as a voltage generator, a write driver, and a sense amplifier.

[0084] The control logic device 720 may control the memory operation according to various signals from a memory controller (not shown). For example, the control logic device 720 may receive an address ADD from the memory controller, provide a row address for selecting a word line of the memory cell array 711 to the row decoder 712, and provide a column address for selecting a bit line of the memory cell array 711 to the column decoder 713. In addition, the control logic device 720 may include a command decoder 721 that decodes a command CMD from the memory controller to control the operation in the memory device 700.

[0085] According to an example embodiment of the inventive concept, in a test environment for a memory device 700, information corresponding to a command CMD and an address ADD may be provided from a test logic device to the memory device 700 as a test input (e.g., a first test input). In addition, information corresponding to data DATA may be provided to the memory device 700 as a test input (e.g., a second test input). According to the above embodiment, in a test environment, each of the first test input and the second test input may be provided to a target circuit in the memory device 700 via a DFT buffer and a timing control circuit. For example, the first test input may be provided to the control logic device 720 after being delayed by a certain delay amount through a DFT buffer 741 and a timing control circuit 742, and the second test input may be provided to the data buffer 730 after being delayed by a certain delay amount through a DFT buffer 751 and a timing control circuit 752.

[0086] In the test mode, the memory device 700 can perform signal processing and generate a test output using the first test input and the second test input, and provide the test output to an external test logic device. In addition, the memory device 700 can receive commands / addresses CMD / ADD and data DATA for memory operations in the normal mode via a command address (CA) buffer 743 and a data buffer 753, respectively, and can provide the received signals to the circuit blocks in the memory device 700 without delaying the processing. Fig.15 A configuration is shown in which pads and buffers for receiving various types of information in a test mode are provided separately from pads and buffers for receiving various types of information in a normal mode. However, as in the embodiment described above, the memory device 700 may have a configuration in which pads and buffers are shared in a test mode and a normal mode.

[0087] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A testing device comprising: a test mounting circuit on which a plurality of semiconductor devices are mounted as corresponding devices under test, wherein the devices under test include corresponding delay control circuits and target circuits; as well as a test logic device electrically coupled to the test mounting circuit, the test logic device configured to generate test inputs, the test inputs being provided in parallel to delay control circuits within the plurality of devices under test, the delay control circuits comprising at least a first delay control circuit and a second delay control circuit, the first delay control circuit and the second delay control circuit being configured to deliver the test inputs to the corresponding first target circuit and the second target circuit during respective first test time intervals and second test time intervals that are out of phase with each other by delaying the test inputs delivered to the second target circuit relative to the test inputs delivered to the first target circuit such that testing of the second target circuit is delayed relative to the first target circuit; wherein the first target circuit includes a first memory cell array, and the second target circuit includes a second memory cell array; wherein the time at which the test input is written into the first memory cell array is different from the time at which the test input is written into the second memory cell array; and The test logic device is configured to provide a delay control signal to the plurality of semiconductor devices to set different delay amounts for the test input.

2. The test device according to claim 1, wherein: The first delay control circuit and the second delay control circuit receive the same test input from the test logic device simultaneously, but provide the test input to the first target circuit and the second target circuit at different times, so that the first test mode is started in the first target circuit using the test input before the second test mode is started in the second target circuit using the test input.

3. The test device according to claim 2, wherein: The first delay control circuit includes a timing control circuit that causes a first delay amount programmable by the test input delay to be delivered to the first target circuit through the first delay control circuit.

4. The test device according to claim 3, wherein: The first delay control circuit is configured to bypass the timing control circuit when output test data generated by the first target circuit is passed through the first delay control circuit.

5. The test device according to claim 2, wherein: The first delay control circuit includes a first timing control circuit, and the first timing control circuit causes a plurality of different delay amounts corresponding to a plurality of partial delays of the test input to be transmitted to the first target circuit through the first delay control circuit.

6. A testing device comprising: A device under test (DUT) mounting circuit, on which a plurality of semiconductor devices are mounted as DUTs; as well as a test logic device configured to generate test inputs provided to target circuits in the plurality of semiconductor devices and determine whether the DUT is defective based on test outputs from the plurality of semiconductor devices, wherein the test logic device is configured to (i) provide the test inputs to the plurality of semiconductor devices in parallel, and (ii) provide delay control signals to the plurality of semiconductor devices to set different delay amounts for the test inputs, and Wherein, based on the control of the test logic device, since additional programmable delay is added to the test input transmitted to the target circuit in some other semiconductor devices among the multiple semiconductor devices compared to the test input transmitted to the target circuit in some semiconductor devices among the multiple semiconductor devices, the time when the test input is transmitted to the target circuit in some semiconductor devices is different from the time when the test input is transmitted to the target circuit in some other semiconductor devices.

7. The test device according to claim 6, wherein: Each of the plurality of semiconductor devices includes a delay control circuit that receives the test input, delays the test input, and outputs the delayed test input, and The test logic device is configured to provide a delay control signal to the plurality of semiconductor devices to set different delay amounts for the test input.

8. The testing device according to claim 6, wherein: The plurality of semiconductor devices are classified into a first group to an Nth group, wherein N is an integer equal to or greater than 2, each of the first group to the Nth group includes one or more semiconductor devices, The target circuits in the semiconductor devices belonging to the same group receive the test input at the same time, and the target circuits in the semiconductor devices belonging to different groups receive the test input at different times.

9. The testing device according to claim 6, wherein: The plurality of semiconductor devices include M semiconductor devices, where M is an integer equal to or greater than 2, The target circuits in the M semiconductor devices receive the test input at different times.

10. The testing device according to claim 6, wherein: The plurality of semiconductor devices include a first semiconductor device, the first semiconductor device includes a plurality of channels, each channel of the plurality of channels receives the test input via an independent interface, The target circuits in the multiple channels receive the test input at different times.

11. The test device according to claim 10, wherein: The first semiconductor device includes a high bandwidth memory HBM.

12. The test device according to claim 6, wherein: The plurality of semiconductor devices include semiconductor packages, Wherein, the test logic device is on a test board including the DUT mounting circuit.

13. The testing device according to claim 6, wherein: The plurality of semiconductor devices include dies formed in a semiconductor wafer, The test logic device is included in a probe card for testing the die of the semiconductor wafer.

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