Through silicon via structure and forming method thereof, and semiconductor device

Abstract

The present invention provides a silicon through hole structure and a method for forming the same, and a semiconductor device. The method for forming the silicon through hole structure comprises the following steps: firstly forming a first through hole, then sequentially forming a first isolation layer, a sacrificial layer, and a second isolation layer on the side wall and the bottom wall of the first through hole, defining a second through hole, forming a plug in the second through hole, then removing the sacrificial layer, forming an axial gap between the first isolation layer and the second isolation layer, and then forming a third isolation layer to overlap the top of the first isolation layer and the top of the second isolation layer to form a coaxial air cavity sleeve, which surrounds the plug. Therefore, the preparation process is simple, and the axial gap in the formed coaxial air cavity sleeve is uniform, thereby effectively controlling the parasitic capacitance, and the device obtained thereby has improved performance.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to a through silicon via structure and a forming method thereof, and a semiconductor device. Background Art

[0002] Through-Silicon-Via (TSV) is an electrical connection that runs through the chip in an integrated circuit. It can conduct signals from one side of the chip to the other side of the chip, and by combining chip stacking technology, it can achieve three-dimensional integration of multi-layer chips.

[0003] Compared with traditional wire bonding technology, the use of through-vias can effectively shorten the length of interconnection lines between chips, thereby improving the signal transmission performance and operating frequency of electronic systems. It is an important direction for the future development of semiconductor technology. How to form through-vias is the core of realizing three-dimensional integration of multi-layer chips.

[0004] However, the TSV structure will generate parasitic capacitance. For example, patent document EP2408006A3 attempts to improve this defect, but the preparation is complex, the feasibility is not high, and the axial gap formed is uneven, which has limited improvement on the parasitic capacitance. Summary of the invention

[0005] The object of the present invention is to provide a through silicon via structure and a method for forming the same, optimize the preparation process, and better reduce parasitic capacitance.

[0006] In order to solve the above technical problems, the present invention provides a method for forming a through silicon via structure, comprising:

[0007] Providing a chip layer, forming a metal pad at the bottom of the chip layer, and forming a patterned mask layer on the chip layer;

[0008] Using the patterned mask layer as a mask, etching the chip layer to expose the metal pad to form a first through hole;

[0009] forming a first isolation layer, a sacrificial layer, and a second isolation layer on the sidewall and bottom wall of the first through hole in sequence to define a second through hole, and exposing a portion of the metal pad through the second through hole;

[0010] forming a plug in the second through hole, wherein the plug is connected to the metal pad;

[0011] removing the sacrificial layer to form an axial gap between the first isolation layer and the second isolation layer;

[0012] forming a third isolation layer on the chip layer, wherein the third isolation layer overlaps the top of the first isolation layer and the top of the second isolation layer to cover the top of the axial gap, and a coaxial air cavity is defined by the first isolation layer, the second isolation layer and the third isolation layer and is sleeved on the outer periphery of the plug; and

[0013] A metal pattern is formed to be connected to the plug.

[0014] Optionally, for the method for forming the through silicon via structure, the chip layer includes a first chip, and the metal pad and the patterned mask layer are arranged on the relative bottom and top of the first chip; or, the chip layer includes a bonded first chip and a second chip, the metal pad is located on the second chip, and the patterned mask layer is located on the first chip; or, the chip layer includes a carrier and a first chip located on the carrier, the metal pad is located on the carrier, and the patterned mask layer is located on the first chip.

[0015] Optionally, for the method for forming the TSV structure, the step of forming the first isolation layer, the sacrificial layer and the second isolation layer includes:

[0016] forming the first isolation layer on the sidewalls and the bottom wall of the first through hole;

[0017] forming the sacrificial layer to be closely attached to the first isolation layer, the sacrificial layer defining a pore in the first through hole;

[0018] Sequentially etching a bottom wall portion of the sacrificial layer corresponding to the pore and a bottom wall portion of the first isolation layer corresponding to the first through hole to form a third through hole;

[0019] forming the second isolation layer on the sidewalls and bottom wall of the third through hole; and

[0020] The second isolation layer on the bottom wall of the third through hole is etched to expose a portion of the metal pad and define the second through hole.

[0021] Optionally, for the method of forming the TSV structure, a dry etching process is used to etch the bottom wall of the second through hole and a portion of the first isolation layer on the bottom wall of the first through hole, and to etch the second isolation layer on the bottom wall of the third through hole.

[0022] Optionally, for the method for forming the through silicon via structure, the first isolation layer and the second isolation layer include an oxide layer or a nitride layer formed by an atomic layer deposition process.

[0023] Optionally, for the method for forming the TSV structure, the material of the sacrificial layer includes silicon oxide, a carbon-rich dielectric layer, germanium, hydrocarbon polymer or amorphous carbon.

[0024] Optionally, in the method for forming the TSV structure, a wet etching process is used to remove the sacrificial layer.

[0025] Optionally, for the method for forming the TSV structure, the third isolation layer includes an oxide layer or a nitride layer formed by a plasma enhanced chemical vapor deposition process.

[0026] Optionally, in the method for forming a through silicon via structure, a width of the first through hole is 1 μm to 10 μm.

[0027] Optionally, in the method for forming the TSV structure, the width of the axial gap is 0.1 μm to 5 μm.

[0028] Optionally, for the method for forming the TSV structure, the step of forming a metal pattern connected to the plug includes:

[0029] forming a material layer on the chip layer;

[0030] etching the material layer to form an opening, wherein the opening exposes the third isolation layer and the plug of the coaxial air cavity sleeve;

[0031] forming a metal material layer on the material layer and filling the opening; and,

[0032] The metal material layer located above the top surface of the material layer is removed by planarization, and only the portion located in the opening is retained to form the metal pattern.

[0033] The present invention also provides a silicon through-hole structure, comprising:

[0034] Chip layer;

[0035] A metal pad formed at the bottom of the chip layer;

[0036] A plug passing through the chip layer and connected to the metal pad;

[0037] a metal pattern formed on top of the chip layer and connected to the plug;

[0038] A coaxial air cavity sleeve surrounds the portion of the plug penetrating the chip layer, the coaxial air cavity sleeve having an axial gap, the length of which is greater than or equal to the thickness of the chip layer.

[0039] Optionally, for the TSV structure, the width of the axial gap is 0.1 μm to 5 μm.

[0040] Optionally, for the silicon through-hole structure, the coaxial air cavity sleeve is formed on the metal pad, including a first isolation layer, a second isolation layer and a third isolation layer, the first isolation layer is farther away from the plug than the second isolation layer, the first isolation layer and the second isolation layer are connected at the bottom, and the third isolation layer overlaps the top of the first isolation layer and the top of the second isolation layer.

[0041] Optionally, for the TSV structure, a distance between the first isolation layer and two opposite sides of the plug is 1 μm to 10 μm.

[0042] The present invention also provides a semiconductor device, comprising the TSV structure as described above.

[0043] In the present invention, the method for forming a silicon through-hole structure is to first form a first through hole, then sequentially form a first isolation layer, a sacrificial layer, and a second isolation layer on the side wall and the bottom wall of the first through hole, define a second through hole, form a plug in the second through hole, then remove the sacrificial layer, form an axial gap between the first isolation layer and the second isolation layer, then form a third isolation layer and overlap the top of the first isolation layer and the top of the second isolation layer to form a coaxial air cavity sleeve, and the coaxial air cavity sleeve surrounds the plug. Therefore, the preparation process is simple, and the axial gap in the formed coaxial air cavity sleeve is uniform, thereby effectively controlling the parasitic capacitance, and the device obtained thereby has improved performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 Schematic diagram of the process of forming a through silicon via structure in Embodiment 1 of the present invention;

[0045] Figure 2 A schematic diagram of a front-end structure is provided for the method for forming a through silicon via structure in Embodiment 1 of the present invention;

[0046] Figure 3 It is a schematic diagram of the method for forming a through silicon via structure in the first embodiment of the present invention when forming a first through hole;

[0047] Figure 4 It is a schematic diagram of the method for forming a through silicon via structure in the first embodiment of the present invention when forming a first isolation layer;

[0048] Figure 5 It is a schematic diagram of the method for forming a through silicon via structure in the first embodiment of the present invention when forming a sacrificial layer;

[0049] Figure 6-Figure 7 is a schematic diagram of the method for forming a through silicon via structure in Embodiment 1 of the present invention when forming a third through hole;

[0050] Figure 8It is a schematic diagram of the method for forming a through silicon via structure in Embodiment 1 of the present invention when forming a second isolation layer;

[0051] Fig. 9 It is a schematic diagram of the method for forming a through silicon via structure in Embodiment 1 of the present invention when etching the third isolation layer;

[0052] Fig.10 It is a schematic diagram of the method for forming a through silicon via structure in the first embodiment of the present invention when forming a plug;

[0053] Fig.11 It is a schematic diagram of the method for forming a through silicon via structure in Embodiment 1 of the present invention when removing the sacrificial layer;

[0054] Fig.12 It is a schematic diagram of the method for forming a through silicon via structure in Embodiment 1 of the present invention when forming a third isolation layer;

[0055] Fig.13 It is a schematic diagram of the method for forming a through silicon via structure in Embodiment 1 of the present invention when forming a coaxial air cavity sleeve;

[0056] Fig.14 It is a schematic diagram of the method for forming a through silicon via structure in the first embodiment of the present invention when forming a material layer;

[0057] Fig.15 It is a schematic diagram of the method for forming a through silicon via structure in Embodiment 1 of the present invention when forming a second metal material layer;

[0058] Fig.16 Schematic diagram of the TSV structure formed in the first embodiment of the present invention.

[0059] The reference numerals are as follows:

[0060] 10- second chip;

[0061] 11- a first dielectric layer;

[0062] 12-Metal pad;

[0063] 20-first chip;

[0064] 21- a second dielectric layer;

[0065] 22- a third dielectric layer;

[0066] 23-mask layer;

[0067] 25- material layer;

[0068] 30-first through hole;

[0069] 31- a first isolation layer;

[0070] 32-sacrificial layer;

[0071] 33- second isolation layer;

[0072] 34- third isolation layer;

[0073] 35-pores;

[0074] 36- third through hole;

[0075] 37- second through hole;

[0076] 40-plug;

[0077] 50- axial gap;

[0078] 60 coaxial air cavity sleeve;

[0079] 70-metal material layer;

[0080] 71-metal pattern 71;

[0081] 80-Opening. DETAILED DESCRIPTION

[0082] The through silicon via structure and the method for forming the same of the present invention will be described in more detail below in conjunction with the schematic diagram, wherein preferred embodiments of the present invention are shown, and it should be understood that those skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Therefore, the following description should be understood as being widely known to those skilled in the art, and not as a limitation of the present invention.

[0083] In the following description, it should be understood that when a layer (or film), region, pattern or structure is referred to as being "on" a substrate, layer (or film), region, pad and / or pattern, it may be directly on another layer or substrate, and / or there may be an intervening layer. In addition, it should be understood that when a layer is referred to as being "under" another layer, it may be directly under another layer, and / or there may be one or more intervening layers. In addition, references to being "on" and "under" each layer may be made based on the accompanying drawings.

[0084] The main idea of ​​the present invention is to provide a method for forming a through silicon via structure, such as Figure 1 As shown, it mainly includes:

[0085] Step S11, providing a chip layer, forming a metal pad at the bottom of the chip layer, and forming a patterned mask layer on the chip layer;

[0086] Step S12, etching the chip layer using the patterned mask layer as a mask to expose the metal pad to form a first through hole;

[0087] Step S13, sequentially forming a first isolation layer, a sacrificial layer, and a second isolation layer on the sidewalls and the bottom wall of the first through hole to define a second through hole, and exposing a portion of the metal pad through the second through hole;

[0088] Step S14, forming a plug in the second through hole, wherein the plug is connected to the metal pad;

[0089] Step S15, removing the sacrificial layer to form an axial gap between the first isolation layer and the second isolation layer;

[0090] Step S16, forming a third isolation layer on the chip layer, wherein the third isolation layer overlaps the top of the first isolation layer and the top of the second isolation layer to cover the top of the axial gap, and a coaxial air cavity is defined by the first isolation layer, the second isolation layer and the third isolation layer to cover the outer periphery of the plug; and

[0091] Step S17, forming a metal pattern connected to the plug.

[0092] The silicon through-hole structure thus obtained is easy to prepare and can make the axial gap well controllable and highly uniform, thereby effectively improving the parasitic capacitance.

[0093] Please refer to Figure 2 For step S11, a chip layer is provided, a metal pad 12 is formed at the bottom of the chip layer, and a patterned mask layer 23 is formed on the chip layer.

[0094] In one embodiment, the chip layer includes a first chip 20, and the metal pad 12 and the patterned mask layer 23 are arranged on the relative bottom and top of the first chip 20; or, the chip layer includes a bonded first chip 20 and a second chip 10, the metal pad 12 is located on the second chip 10, and the patterned mask layer 23 is located on the first chip 20; or, the chip layer includes a carrier and a first chip 20 located on the carrier, the metal pad 12 is located on the carrier, and the patterned mask layer 23 is located on the first chip.

[0095] For example, Figure 2 In the illustrated embodiment, the chip layer is a structure including a first chip 20 and a second chip 10 bonded together.

[0096] For example, the second chip 10 may be a silicon substrate, such as a single crystal silicon substrate, etc. A buried layer, such as a device layer, may also be formed in the second chip 10 .

[0097] A first dielectric layer 11 is formed on the second chip 10 , and may be, for example, silicon oxide, silicon nitride, etc.

[0098] The metal pad 12 is as follows Figure 2 As shown in , the metal pad 12 may be patterned on the first dielectric layer 11. According to actual conditions, the upper surface of the metal pad 12 may be higher than or flush with the first dielectric layer 11. For example, the metal pad 12 may be made of copper, gold, silver or the like.

[0099] In this embodiment, a second dielectric layer 21 is formed at the bottom of the first chip 20, a third dielectric layer 22 is formed on the top of the first chip 20, the patterned mask layer 23 is formed on the third dielectric layer 22, and the second chip 10 and the first chip 20 are bonded together through the first dielectric layer 11 and the second dielectric layer 21.

[0100] The first chip 20 can be made of the same material as the second chip 10 , such as a single crystal silicon substrate.

[0101] The second dielectric layer 21 and the third dielectric layer 22 may be made of the same material as the first dielectric layer 11 , such as silicon oxide or silicon nitride.

[0102] In one embodiment, the mask layer 23 may be a silicon oxide layer or a silicon nitride layer.

[0103] For example, the first dielectric layer 11 , the second dielectric layer 21 , and the third dielectric layer 22 may be silicon oxide layers, and the mask layer 23 may be a silicon nitride layer.

[0104] Please refer to Figure 3 For step S12 , the chip layer is etched using the patterned mask layer 23 as a mask to expose the metal pad 12 to form a first through hole 30 .

[0105] Specifically, the third dielectric layer 22 , the first chip 20 , and the second dielectric layer 21 may be etched in sequence to form the first through hole 30 .

[0106] The etching process may be dry etching to obtain a better edge morphology.

[0107] For example, the width of the first through hole 30 is 1 μm to 10 μm, such as 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, etc.

[0108] In one embodiment, the first through hole 30 may have various shapes such as circle, square, hexagon, etc. when viewed from the top surface. For a circle, its width refers to the diameter, and for a polygon, it refers to the maximum width.

[0109] Please refer to Figures 4 to 9For step S13, a first isolation layer 31, a sacrificial layer 32 and a second isolation layer 33 are sequentially formed on the sidewalls and the bottom wall of the first through hole to define a second through hole, and the second through hole exposes a portion of the metal pad 12.

[0110] Specifically, this step includes:

[0111] like Figure 4 As shown, a first isolation layer 31 is formed on the sidewalls and the bottom wall of the first through hole 30. The first isolation layer 31 can be selected as an oxide layer or a nitride layer, for example, a silicon nitride layer is selected here.

[0112] The first isolation layer 31 can be obtained by a deposition process, such as an atomic layer deposition process (ALD). It is understood that the formation process of the first isolation layer 31 is not limited thereto, and other feasible processes are also in line with the concept of the present invention.

[0113] In one embodiment, the thickness of the first isolation layer 31 may be 50 nm to 500 nm, for example, 100 nm, 200 nm, 300 nm, 400 nm, etc.

[0114] It is understandable that the first isolation layer 31 will also be formed on the mask layer 23 (not shown), and since the materials are the same, it will not have adverse effects on subsequent operations.

[0115] Please refer to Figure 5 A sacrificial layer 32 is formed closely against the first isolation layer 31 , and the sacrificial layer 32 defines a pore 35 in the first through hole.

[0116] In one embodiment, the material of the sacrificial layer 32 includes silicon oxide, a carbon-rich dielectric layer, germanium, a hydrocarbon polymer, or amorphous carbon. For example, a silicon oxide layer is selected here. It is understandable that the sacrificial layer 32 can also have other options, which are not listed here one by one.

[0117] The sacrificial layer 32 does not completely fill the first through hole, that is, it can be understood that after the sacrificial layer 32 is formed, the size of the first through hole is reduced, including the height and width.

[0118] In one embodiment, the sacrificial layer 32 may have a thickness of 0.1 μm to 5 μm, for example, 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, etc.

[0119] Please refer to Figure 6 , etching the portion of the sacrificial layer corresponding to the bottom wall of the pore 35 , removing the sacrificial layer on the bottom wall of the pore 35 , and exposing the first isolation layer 31 .

[0120] Here, a dry etching process can be used to better ensure the directionality of etching, which in turn helps to achieve uniformity of the subsequent axial gap. Figure 6 As can be seen in FIG. 1 , the sacrificial layer formed on the mask layer 23 is also removed.

[0121] Then please refer to Figure 7 , continue to etch the portion of the first isolation layer 31 corresponding to the bottom wall of the first through hole (ie, Figure 6 The exposed portion in the middle) exposes a portion of the metal pad 12 to form a third through hole 36.

[0122] Here, the dry etching process can still be used. It is understandable that due to different materials, the wet etching process can also be used.

[0123] Then, please refer to Figure 8 , forming a second isolation layer 33 on the sidewalls and bottom wall of the third through hole 36 .

[0124] The second isolation layer 33 may be an oxide layer or a nitride layer, for example, a silicon nitride layer is selected here.

[0125] The second isolation layer 33 can be obtained by a deposition process, such as an atomic layer deposition process (ALD). It is understood that the formation process of the second isolation layer 33 is not limited thereto, and other feasible processes are also in line with the concept of the present invention.

[0126] In one embodiment, the thickness of the second isolation layer 33 may be 50 nm to 500 nm, for example, 100 nm, 200 nm, 300 nm, 400 nm, etc.

[0127] It can be understood that the second isolation layer 33 will also be formed on the mask layer 23 .

[0128] Afterwards, if Fig. 9 As shown, the second isolation layer on the bottom wall of the third through hole 36 is etched to expose a portion of the metal pad 12 and define the second through hole 37 .

[0129] Here, dry etching can be selected for processing. Moreover, after etching, the second isolation layer on the top (i.e., on the top surface of the mask layer 23 and the sacrificial layer 32) is also removed to expose the sacrificial layer 32. If the second isolation layer on the top is not completely removed, a removal process such as a CMP process can be performed again when removing the sacrificial layer.

[0130] Please refer to Fig.10 For step S14 , a plug 40 is formed in the second through hole, and the plug is connected to the metal pad 12 .

[0131] The plug 40 may be made of copper, aluminum, tungsten, titanium, etc.

[0132] In one embodiment, the plug 40 may be obtained by first sputtering a seed layer, then growing to fill the entire through hole, and then performing a planarization process, such as a CMP process, to remove the metal above the top surface of the mask layer 23 .

[0133] Please refer to Fig.11 For step S15 , the sacrificial layer is removed to form an axial gap 50 between the first isolation layer 31 and the second isolation layer 33 .

[0134] The sacrificial layer may be removed by a wet etching process.

[0135] For example, a diluted hydrofluoric acid solution (DHF) may be selected.

[0136] Since the sacrificial layer is designed in the present invention, the axial gap 50 obtained after removal is uniform in size.

[0137] Please refer to Figure 12-13 For step S16, a third isolation layer 34 is formed on the chip layer, and the third isolation layer 34 overlaps the top of the first isolation layer 31 and the top of the second isolation layer 33 to cover the top of the axial gap, and a coaxial air cavity sleeve 60 is defined by the first isolation layer, the second isolation layer and the third isolation layer on the outer periphery of the plug 40.

[0138] In one embodiment, the third isolation layer 34 may be an oxide layer or a nitride layer, for example, a silicon nitride layer.

[0139] The third isolation layer 34 can be obtained by a deposition process, such as plasma enhanced chemical vapor deposition (PECVD). It is understood that the formation process of the third isolation layer 34 is not limited thereto, and other feasible processes also conform to the concept of the present invention.

[0140] After the third isolation layer 34 is formed, the axial gap 50 is sealed.

[0141] Depend on Fig.12 It can be seen that the bottom surface position of the third isolation layer 34 at the top of the axial gap is lower than the mask layer 23, so that after the mask layer 23 is removed, the axial gap 50 can still be covered.

[0142] Please refer to Fig.13 , flattened so that the third isolation layer 34 remains at the top of the axial gap 50 , exposing the plug 40 , and the first isolation layer, the second isolation layer and the third isolation layer form a coaxial air cavity sleeve 60 .

[0143] In one embodiment, the planarization is performed by using a CMP process. In this step, all the film layers on the top surface of the third dielectric layer 22 are removed.

[0144] At this point, the coaxial air cavity sleeve 60 of the present invention is obtained, which is in the shape of a ring column, that is, it is arranged around the plug 40. In addition, the coaxial air cavity sleeve 60 has uniformly distributed axial gaps 50.

[0145] The length of the axial gap 50 is greater than or equal to the thickness of the chip layer. Specifically, the chip layer here refers to the semiconductor layer, that is, for example Fig.13 The first chip 20 shown does not include the dielectric layer and the second chip 10 (or carrier) thereunder.

[0146] Please refer to Figure 14-16 In step S17 , a metal pattern 71 is formed to connect with the plug 40 .

[0147] Specifically, Fig.14 A material layer 25 is formed on the chip layer; in one embodiment, the material layer 25 may be, for example, a nitride layer or an oxide layer, and a silicon oxide layer is selected here.

[0148] Next, the material layer 25 is etched to form an opening 80 , exposing the top surface of the coaxial air cavity sleeve 60 and the top surface of the plug 40 .

[0149] Then, if Fig.15 As shown, a metal material layer 70 is formed on the material layer 25 to fill the opening; then, the metal material layer located above the top surface of the material layer 25 is planarized and removed, leaving only the portion located in the opening to form the metal pattern 71, as shown in FIG. Fig.16 shown.

[0150] Thus, the present invention obtains a through silicon via structure, comprising:

[0151] Chip layer;

[0152] A metal pad 12 formed at the bottom of the chip layer;

[0153] A plug 40 passing through the chip layer and connected to the metal pad;

[0154] A metal pattern 71 formed on top of the chip layer and connected to the plug 40;

[0155] A coaxial air cavity sleeve 60 is disposed around the plug 40 and penetrates the chip layer. The coaxial air cavity sleeve 60 has an axial gap 50. The length of the axial gap 50 is greater than or equal to the thickness of the chip layer. Specifically, the chip layer here refers to a semiconductor layer, that is, for example Fig.16 The first chip 20 shown does not include the dielectric layer and the second chip 10 (or carrier) thereunder.

[0156] In one embodiment, the axial gaps 50 are evenly distributed.

[0157] In one embodiment, the width of the axial gap 50 is 0.1 μm to 5 μm, for example, 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, etc.

[0158] The coaxial air cavity sleeve 60 is formed on the metal pad 12, and includes a first isolation layer 31, a second isolation layer 33 and a third isolation layer 34. The first isolation layer 31 is farther away from the plug 40 than the second isolation layer 33. The first isolation layer 31 and the second isolation layer 33 are connected at the bottom, and the third isolation layer 34 overlaps the top of the first isolation layer 31 and the top of the second isolation layer 33.

[0159] The coaxial air cavity sleeve 60 includes a bottom, a top, an inner side and an outer side, wherein the bottom and the outer side may be an “L”-shaped first isolation layer 31 , the inner side may be a second isolation layer 33 , and the top may be a third isolation layer 34 .

[0160] The first isolation layer 31 may be an oxide layer or a nitride layer, for example, a silicon nitride layer is selected here.

[0161] In one embodiment, the thickness of the first isolation layer 31 may be 50 nm to 500 nm, for example, 100 nm, 200 nm, 300 nm, 400 nm, etc.

[0162] In one embodiment, the distance between the first isolation layer 31 and the two opposite sides of the plug is 1 μm to 10 μm, for example, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, etc.

[0163] The second isolation layer 33 may be an oxide layer or a nitride layer, for example, a silicon nitride layer is selected here.

[0164] In one embodiment, the thickness of the second isolation layer 33 may be 50 nm to 500 nm, for example, 100 nm, 200 nm, 300 nm, 400 nm, etc.

[0165] In one embodiment, the third isolation layer 34 may be an oxide layer or a nitride layer, for example, a silicon nitride layer.

[0166] Based on the above disclosure of the present invention, it can be applied in semiconductor devices, such as DRAM structures, etc. It can be understood that the design concept of the present invention can be adopted for structures involving through-hole processes.

[0167] In the present invention, the method for forming a silicon through-hole structure is to first form a first through hole, then sequentially form a first isolation layer, a sacrificial layer, and a second isolation layer on the side wall and the bottom wall of the first through hole, define a second through hole, form a plug in the second through hole, then remove the sacrificial layer, form an axial gap between the first isolation layer and the second isolation layer, then form a third isolation layer and overlap the top of the first isolation layer and the top of the second isolation layer to form a coaxial air cavity sleeve, and the coaxial air cavity sleeve surrounds the plug. Therefore, the preparation process is simple, and the axial gap in the formed coaxial air cavity sleeve is uniform, thereby effectively controlling the parasitic capacitance, and the device obtained thereby has improved performance.

[0168] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for forming a through silicon via structure, characterized in that: include: Providing a chip layer, forming a metal pad at the bottom of the chip layer, and forming a patterned mask layer on the chip layer; Using the patterned mask layer as a mask, etching the chip layer to expose the metal pad to form a first through hole; forming a first isolation layer, a sacrificial layer, and a second isolation layer on the sidewall and bottom wall of the first through hole in sequence to define a second through hole, and exposing a portion of the metal pad through the second through hole; forming a plug in the second through hole, wherein the plug is connected to the metal pad; removing the sacrificial layer to form an axial gap between the first isolation layer and the second isolation layer; forming a third isolation layer on the chip layer, wherein the third isolation layer overlaps the top of the first isolation layer and the top of the second isolation layer to cover the top of the axial gap, and a coaxial air cavity is defined by the first isolation layer, the second isolation layer and the third isolation layer and is sleeved around the outer periphery of the plug; and A metal pattern is formed to be connected to the plug.

2. The method for forming a through silicon via structure according to claim 1, wherein: The chip layer includes a first chip, and the metal pad and the patterned mask layer are arranged on the relative bottom and top of the first chip; or, the chip layer includes a bonded first chip and a second chip, the metal pad is located on the second chip, and the patterned mask layer is located on the first chip; or, the chip layer includes a carrier and a first chip located on the carrier, the metal pad is located on the carrier, and the patterned mask layer is located on the first chip.

3. The method for forming a through silicon via structure according to claim 1, wherein: The step of forming the first isolation layer, the sacrificial layer and the second isolation layer comprises: forming the first isolation layer on the sidewalls and the bottom wall of the first through hole; forming the sacrificial layer to be closely attached to the first isolation layer, the sacrificial layer defining a pore in the first through hole; Sequentially etching a bottom wall portion of the sacrificial layer corresponding to the pore and a bottom wall portion of the first isolation layer corresponding to the first through hole to form a third through hole; forming the second isolation layer on the sidewalls and bottom wall of the third through hole; and The second isolation layer on the bottom wall of the third through hole is etched to expose a portion of the metal pad and define the second through hole.

4. The method for forming a through silicon via structure according to claim 3, wherein: A dry etching process is used to etch the bottom wall of the second through hole and a portion of the first isolation layer on the bottom wall of the first through hole, and to etch the second isolation layer on the bottom wall of the third through hole.

5. The method for forming a through silicon via structure according to claim 1, wherein: The first isolation layer and the second isolation layer include an oxide layer or a nitride layer formed by an atomic layer deposition process.

6. The method for forming a through silicon via structure according to claim 1, wherein: The material of the sacrificial layer includes silicon oxide, a carbon-rich dielectric layer, germanium, a hydrocarbon polymer or amorphous carbon.

7. The method for forming a through silicon via structure according to claim 1, wherein: The sacrificial layer is removed by a wet etching process.

8. The method for forming a through silicon via structure according to claim 1, wherein: The third isolation layer includes an oxide layer or a nitride layer formed by a plasma enhanced chemical vapor deposition process.

9. The method for forming a through silicon via structure according to claim 1, wherein: The width of the first through hole is 1 μm-10 μm.

10. The method for forming a through silicon via structure according to claim 1, wherein: The width of the axial gap is 0.1 μm to 5 μm.

11. The method for forming a through silicon via structure according to claim 1, wherein: The step of forming a metal pattern connected to the plug includes: forming a material layer on the chip layer; etching the material layer to form an opening, wherein the opening exposes the third isolation layer and the plug of the coaxial air cavity sleeve; forming a metal material layer on the material layer and filling the opening; and, The metal material layer located above the top surface of the material layer is removed by planarization, and only the portion located in the opening is retained to form the metal pattern.

12. A through silicon via structure, characterized in that: include: Chip layer; A metal pad formed at the bottom of the chip layer; A plug passing through the chip layer and connected to the metal pad; a metal pattern formed on top of the chip layer and connected to the plug; A coaxial air cavity sleeve surrounds the portion of the plug that passes through the chip layer, the coaxial air cavity sleeve having an axial gap, the length of the axial gap being greater than or equal to the thickness of the chip layer, the coaxial air cavity sleeve being formed on the metal pad, comprising a first isolation layer, a second isolation layer and a third isolation layer, the first isolation layer being farther away from the plug than the second isolation layer, the first isolation layer and the second isolation layer being connected at the bottom, the third isolation layer overlapping the top of the first isolation layer and the top of the second isolation layer, the axial gap being located between the first isolation layer and the second isolation layer, and the thickness of the first isolation layer being between 50nm and 500nm.

13. The through silicon via structure according to claim 12, characterized in that: The width of the axial gap is 0.1 μm to 5 μm.

14. The through silicon via structure according to claim 12, wherein: The distance between the first isolation layer and the two opposite sides of the plug is 1 μm to 10 μm.

15. A semiconductor device, characterized in that: It comprises the through silicon via structure as described in any one of claims 12 to 14.

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