Word line driver and method for manufacturing the same

Abstract

The present invention provides a word line driver and a preparation method thereof, the method comprising: providing a substrate, forming an active area in the substrate, and the substrate includes a first area for forming NMOS and a second area for forming PMOS, forming a groove in the substrate in the first area, the groove is in a closed ring shape, filling a metal material layer in the groove, etching the metal material layer until the remaining part of the metal material layer is in the groove to form an NMOS gate, forming a first dielectric layer, the first dielectric layer covers the substrate and fills the groove, removing the first dielectric layer in the second area, and forming a PMOS gate on the substrate in the second area. The NMOS gate in the word line driver provided by the present invention is a buried gate, which can reduce the area of ​​the word line driver, reduce the area of ​​a single chip, increase the number of chips on a single substrate, and reduce costs; at the same time, the NMOS gate is in a ring shape, which can omit the NMOS gate interconnection line, increase the area of ​​the gate contact, and increase the process window.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design and manufacturing, and in particular to a word line driver and a preparation method thereof. Background Art

[0002] The word line driver of DRAM (dynamic random access memory) is made of planar MOS. Each word line driver consists of 2 NMOS and 1 PMOS. There is a word line driver between every two array areas (storage array areas). Each word line driver controls half of the word lines of the two array areas on both sides, which means that each array area needs to be equipped with a word line driver. Therefore, the word line driver occupies a large area ratio in a single chip.

[0003] With the increasing integration of semiconductor manufacturing processes, it has become a trend to reduce the word line driving area to reduce the area of ​​a single chip and increase the number of chips on a single silicon wafer. Summary of the invention

[0004] The main purpose of the present invention is to provide a word line driver and a preparation method thereof, so as to reduce the area of ​​the word line driver, reduce the area of ​​a single chip, increase the number of chips on a single substrate, and reduce the cost.

[0005] To achieve the above object, the present invention provides a method for preparing a word line driver, comprising:

[0006] Providing a substrate, forming an active region in the substrate, and the substrate includes a first region for forming an NMOS and a second region for forming a PMOS;

[0007] forming a groove in the substrate of the first region, wherein the groove is in a closed ring shape;

[0008] Filling a metal material layer in the groove;

[0009] Etching the metal material layer until the remaining portion of the metal material layer is within the groove to form an NMOS gate;

[0010] forming a first dielectric layer, wherein the first dielectric layer covers the substrate and fills the groove;

[0011] The first dielectric layer in the second region is removed, and a PMOS gate is formed on the substrate in the second region.

[0012] Optionally, the step of forming a groove in the substrate in the first region includes:

[0013] forming a second dielectric layer, a pattern transfer layer and a patterned photoresist layer on the substrate in sequence;

[0014] forming a first mask layer, wherein the first mask layer covers the patterned photoresist layer and the pattern transfer layer;

[0015] Etching the first mask layer and the patterned photoresist layer until the first mask layer on the sidewall of the patterned photoresist layer remains;

[0016] Using the remaining first mask layer as a mask, etching the pattern transfer layer, and removing the remaining first mask layer;

[0017] forming a second mask layer, wherein the second mask layer covers the second dielectric layer and surrounds the remaining sidewalls of the pattern transfer layer;

[0018] The second mask layer is used as a mask to etch the remaining pattern transfer layer and the second dielectric layer and a portion of the substrate thereunder to form a groove.

[0019] Optionally, the step of forming a second mask layer, wherein the second mask layer covers the second dielectric layer and surrounds the remaining sidewalls of the pattern transfer layer comprises:

[0020] forming a second mask layer, wherein the second mask layer covers the second dielectric layer and the remaining pattern transfer layer;

[0021] The second mask layer is planarized until the remaining pattern transfer layer is exposed.

[0022] Optionally, after forming the groove and before filling the metal material layer, the method further includes:

[0023] A gate dielectric layer and a barrier layer are sequentially formed on the sidewall and bottom of the groove.

[0024] Optionally, the depth of the groove is between 100nm and 200nm; the width of the groove is between 15nm and 30nm;

[0025] The metal material layer is etched to a depth of one quarter to one third of the groove.

[0026] Optionally, the substrate further includes a third region for forming a memory array, and an embedded device is formed in the third region while an NMOS gate is formed in the first region.

[0027] Optionally, after forming the PMOS gate, the method further includes:

[0028] forming an insulating layer, wherein the insulating layer covers the first dielectric layer and the PMOS gate;

[0029] forming a plurality of metal plugs, wherein the metal plugs are located in the insulating layer and the first dielectric layer and are in contact with the NMOS drain or the PMOS drain;

[0030] A plurality of metal interconnection layers are formed, wherein the metal interconnection layers connect the NMOS drain and the PMOS drain to the word lines in the third region through the metal plugs.

[0031] Optionally, two NMOSs and one PMOS are formed, and the two NMOSs are respectively located on two opposite sides of the PMOS.

[0032] Accordingly, the present invention further provides a word line driver, comprising:

[0033] A substrate, wherein an active region is formed in the substrate, and the substrate includes a first region for forming an NMOS and a second region for forming a PMOS;

[0034] A metal material layer is filled in the bottom of a portion of the annular groove of the substrate in the first region to form an NMOS gate;

[0035] A first dielectric layer, covering the substrate in the first region and filling the groove;

[0036] A PMOS gate is located on the substrate in the second region.

[0037] Optionally, also include:

[0038] an insulating layer, covering the first dielectric layer and the PMOS gate;

[0039] a metal plug, located in the insulating layer and the first dielectric layer, and in contact with the NMOS drain or the PMOS drain; and

[0040] A metal interconnection layer is provided, wherein the metal interconnection layer connects the NMOS drain and the PMOS drain to a word line of a storage array through the metal plug.

[0041] Optionally, the word line driver includes two NMOSs and one PMOS, and the two NMOSs are located at two opposite sides of the PMOS.

[0042] Compared with the prior art, the present invention has the following beneficial effects:

[0043] The NMOS gate in the word line driver provided by the present invention is a buried gate, which can reduce the area of ​​the word line driver, reduce the area of ​​a single chip, increase the number of chips on a single substrate, and reduce costs; at the same time, the NMOS gate is ring-shaped, which can save the NMOS gate interconnection line, increase the area of ​​the gate contact, and increase the process window.

[0044] Furthermore, the NMOS gate and the embedded device of the memory array are manufactured simultaneously without adding additional processes.

[0045] Furthermore, the two NMOS are located on opposite sides of the PMOS, so that the wire lengths from the output end of the word line driver PMOS to the word lines in the left and right array areas are the same, effectively reducing the time difference of turning on the word lines on both sides and improving device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 A flow chart of a method for preparing a word line driver provided in one embodiment of the present invention;

[0047] Figure 2a FIG. 1 is a top view of a substrate provided in a method for preparing a word line driver according to an embodiment of the present invention. Figure 2b for Figure 2a A schematic cross-sectional view in the AA' direction on the first region;

[0048] Figure 3a is Figure 2a A top view of a patterned photoresist layer formed on the structure shown, Figure 3b is Figure 2b A schematic cross-sectional view of a patterned photoresist layer formed on the structure shown;

[0049] Figure 4a is Figure 3a A top view of a first mask layer formed on the structure shown, Figure 4b is Figure 3b A schematic cross-sectional view of forming a first mask layer on the structure shown;

[0050] Figure 5a is Figure 4a A top view of etching the first mask layer on the structure shown, Figure 5b is Figure 4b A cross-sectional schematic diagram of etching the first mask layer on the structure shown;

[0051] Figure 6a is Figure 5a A top view of the etched pattern transfer layer on the structure shown, Figure 6b is Figure 5b A schematic cross-sectional view of etching a pattern transfer layer on the structure shown;

[0052] Figure 7a is Figure 6a A top view of the structure shown in FIG. 1 after the remaining first mask layer is removed. Figure 7b is Figure 6b A cross-sectional schematic diagram of removing the remaining first mask layer from the structure shown;

[0053] Figure 8a is Figure 7a A top view of a second mask layer formed on the structure shown, Figure 8b is Figure 7b A cross-sectional schematic diagram of forming a second mask layer on the structure shown;

[0054] Figure 9a is Figure 8a A top view of the planarized second mask layer on the structure shown, Figure 9b is Figure 8b A schematic cross-sectional view of a planarized second mask layer on the structure shown;

[0055] Fig.10a is Figure 9a A top view of a groove formed on the structure shown, Fig.10b is Figure 9b A schematic cross-sectional view of a groove formed on the structure shown;

[0056] Fig.11a is Fig.10a A top view of a metal material layer filled on the structure shown, Fig.11b is Fig.10b A schematic cross-sectional view of a metal material layer filled on the structure shown;

[0057] Fig.12a is Fig.11a A top view of an NMOS gate is formed on the structure shown. Figure 12b is Fig.11b A cross-sectional schematic diagram of forming an NMOS gate on the structure shown;

[0058] Fig.13a is Fig.12a A top view of a first dielectric layer formed on the structure shown, Fig.13b is Figure 12b A cross-sectional schematic diagram of forming a first dielectric layer on the structure shown;

[0059] Fig.14 is Fig.13a A top view of a PMOS gate formed on the structure shown;

[0060] Fig.15a is Fig.14 A top view of a metal plug formed on the structure shown, Fig.15b is Fig.13b A schematic cross-sectional view of a metal plug formed on the structure shown;

[0061] Fig.16 is a top view of a word line driver provided by an embodiment of the present invention;

[0062] Fig.17FIG. 4 is a top view of a word line driver provided by another embodiment of the present invention.

[0063] The reference numerals are as follows:

[0064] 10-substrate; 10A-first region; 10B-second region;

[0065] 11-active area;

[0066] 12-Isolation structure;

[0067] 13- second dielectric layer;

[0068] 14- pattern transfer layer;

[0069] 15-patterned photoresist layer;

[0070] 16-a first mask layer;

[0071] 17- a second mask layer;

[0072] 18-groove;

[0073] 19-gate dielectric layer;

[0074] 20- barrier layer;

[0075] 21-metal material layer;

[0076] 22-NOMS gate;

[0077] 23-a first dielectric layer;

[0078] 31-gate dielectric layer;

[0079] 32-PMOS gate;

[0080] 33-insulating layer;

[0081] 34-Metal plug;

[0082] 35-Metal interconnect layer. DETAILED DESCRIPTION

[0083] As described in the background technology, the word line driver occupies a large area ratio in a single chip, and the area of ​​the word line driver needs to be reduced to reduce the area of ​​a single chip. In addition, since the word line driver is composed of two NMOS and one PMOS, the length of the wire from the output end of the word line driver PMOS to the left and right word lines will be different, resulting in different output impedance and current, resulting in a time difference between the word line switches in the left and right array regions, affecting the device performance.

[0084] Based on the above problems, the present invention provides a method for preparing a word line driver, comprising: providing a substrate, forming an active area in the substrate, and the substrate includes a first area for forming an NMOS and a second area for forming a PMOS; forming a groove in the substrate in the first area, the groove being in a closed ring shape; filling a metal material layer in the groove; etching the metal material layer to a remaining depth of the metal material layer in the groove to form an NMOS gate; forming a first dielectric layer, the first dielectric layer covering the substrate and filling the groove; removing the first dielectric layer in the second area, and forming a PMOS gate on the substrate in the second area.

[0085] Correspondingly, the present invention also provides a word line driver, comprising: a substrate, an active area is formed in the substrate, and the substrate includes a first area for forming NMOS and a second area for forming PMOS; a metal material layer, filling the bottom of a partial annular groove of the substrate in the first area to form an NMOS gate; a first dielectric layer, covering the substrate in the first area and filling the groove; a PMOS gate, located on the substrate in the second area.

[0086] In the word line driver and preparation method thereof provided by the present invention, the NMOS gate in the word line driver is a buried gate, which can reduce the area of ​​the word line driver, reduce the area of ​​a single chip, increase the number of chips on a single substrate, and reduce costs; at the same time, the NMOS gate is ring-shaped, which can save the NMOS gate interconnection line, increase the area of ​​the gate contact, and increase the process window. Furthermore, the NMOS gate and the buried device of the storage array are manufactured at the same time without adding additional processes. Furthermore, the two NMOS are respectively located on opposite sides of the PMOS, so that the length of the wire from the output end of the word line driver PMOS to the left and right array area word lines is the same, effectively reducing the time difference of opening the word lines on both sides and improving device performance.

[0087] To make the content of the present invention more clear and understandable, the content of the present invention is further described below in conjunction with the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general replacements known to those skilled in the art are also covered within the protection scope of the present invention.

[0088] Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Secondly, the present invention is described in detail using schematic diagrams. When describing the examples of the present invention in detail, for the sake of convenience, the schematic diagrams are not partially enlarged according to general proportions, and this should not be used as a limitation of the present invention.

[0089] Please refer to Figure 1 , which is a flow chart of a method for preparing a word line driver provided by an embodiment of the present invention. Figure 1 As shown, the method for preparing the word line driver comprises the following steps:

[0090] Step S01: providing a substrate, forming an active region in the substrate, and the substrate includes a first region for forming an NMOS and a second region for forming a PMOS;

[0091] Step S02: forming a groove in the substrate of the first region, wherein the groove is in a closed ring shape;

[0092] Step S03: filling a metal material layer in the groove;

[0093] Step S04: etching the metal material layer until the remaining depth of the metal material layer is within the groove to form an NMOS gate;

[0094] Step S05: forming a first dielectric layer, wherein the first dielectric layer covers the substrate and fills the groove;

[0095] Step S06: removing the first dielectric layer in the second region, and forming a PMOS gate on the substrate in the second region.

[0096] Figure 2a FIG. 1 is a top view of a substrate provided in a method for preparing a word line driver according to an embodiment of the present invention. Figure 2b for Figure 2a Schematic diagram of the cross section in the AA' direction on the first area. Please refer to Figure 2a and Figure 2b As shown, a substrate 10 is provided, an active region 11 is formed in the substrate 10 , and the substrate 10 includes a first region 10A for forming an NMOS and a second region 10B for forming a PMOS.

[0097] The material of the substrate 10 may be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi) or silicon carbide (SiC), or may be silicon on insulator (SOI) or germanium on insulator (GOI); or may be other materials, such as III-V compounds such as gallium arsenide. In this embodiment, the material of the substrate 10 is preferably single crystal silicon (Si).

[0098] The substrate 10 includes a first region 10A and a second region 10B. The first region 10A is used to form an NMOS of a word line driver, and the second region 10B is used to form a PMOS of the word line driver. Each word line driver includes two NMOS and one PMOS, which can be Figure 2aTwo NMOS are formed on the first region 10A, and one PMOS is formed on the second region 10B. Figure 2a In the first region 10A shown in the figure, an NMOS is formed, and another first region is arranged on the other side of the second region 10B opposite to the first region 10A, and another NMOS is formed on the first region, so that the two NMOS are symmetrically arranged on both sides of the PMOS. Since only the preparation method of the NMOS and the PMOS, that is, the preparation method of the word line driver, is introduced in the following, Figure 2a FIG. 4 shows only one first region 10A in the second region 10B.

[0099] Of course, the substrate 10 also includes a third region (not shown), the third region is used to form a memory array, each of the word line drivers is located between adjacent memory arrays, and is used to control the word lines of the memory array. An embedded device, such as an embedded transistor, is also formed in the memory array, and the NMOS gate in the first region 10A and the embedded device in the third region can be formed in the same process step, that is, the formation of the NMOS gate in the first region 10A does not add additional processes.

[0100] A plurality of regularly arranged active regions 11 are formed in the substrate 10, and the active regions 11 may be located in the first region 10A, the second region 10B, or / and the third region. A plurality of isolation structures 12 are also formed in the substrate 10, and the isolation structures 12 are located at the periphery of the active regions 11, and are used to isolate adjacent active regions 11. It can also be understood that the active regions 11 are defined by forming the isolation structures 12. The isolation structures 12 may be trench isolation structures.

[0101] Furthermore, since it is necessary to form NMOS and PMOS of the word line driver on the substrate 10, in the subsequent process flow, an ion doping process can be performed on the active areas on both sides of the gate formation area to form ion doping areas respectively. For example, the ion doping area corresponding to the left side of the gate formation area can constitute the source area of ​​the transistor, and the ion doping area corresponding to the right side of the gate formation area can constitute the drain area of ​​the transistor, that is, an NMOS source and an NMOS drain are formed in the active area 11 of the first area 10A, and a PMOS source and a PMOS drain are formed in the active area 11 of the second area 10B.

[0102] Figure 3a is Figure 2a A top view of a patterned photoresist layer formed on the structure shown, Figure 3b is Figure 2b A schematic cross-sectional view of a patterned photoresist layer formed on the structure shown. Figure 4a is Figure 3a A top view of a first mask layer formed on the structure shown, Figure 4b is Figure 3b A schematic cross-sectional view of forming a first mask layer on the structure shown; Figure 5a is Figure 4a A top view of etching the first mask layer on the structure shown, Figure 5b is Figure 4b A cross-sectional schematic diagram of etching the first mask layer on the structure shown; Figure 6a is Figure 5a A top view of the etched pattern transfer layer on the structure shown, Figure 6b is Figure 5b A schematic cross-sectional view of etching a pattern transfer layer on the structure shown; Figure 7a is Figure 6a A top view of the structure shown in FIG. 1 after the remaining first mask layer is removed. Figure 7b is Figure 6b A cross-sectional schematic diagram of removing the remaining first mask layer from the structure shown; Figure 8a is Figure 7a A top view of a second mask layer formed on the structure shown, Figure 8b is Figure 7b A cross-sectional schematic diagram of forming a second mask layer on the structure shown; Figure 9a is Figure 8a A top view of a planarized second mask layer formed on the structure shown, Figure 9b is Figure 8b A schematic cross-sectional view of forming a planarized second mask layer on the structure shown; Fig.10a is Figure 9a A top view of a groove formed on the structure shown, Fig.10b is Figure 9b A schematic cross-sectional view of a groove formed on the structure shown.

[0103] Please refer to Figure 3a to Figure 10a as well as Figure 3b to Figure 10b As shown, a groove 18 is formed in the substrate 10 in the first region 10A, and the groove 18 is in a closed ring shape.

[0104] For details, please refer to Figure 3a and Figure 3bAs shown, a second dielectric layer 13, a pattern transfer layer 14, and a patterned photoresist layer 15 are sequentially formed on the substrate 10. The material of the second dielectric layer 13 includes but is not limited to silicon nitride, and the material of the pattern transfer layer 14 includes but is not limited to silicon oxide, silicon oxynitride, or BPSG. In this embodiment, the second dielectric layer 13 can be formed on the substrate 10 by a deposition process, and then the pattern transfer layer 14 can be formed on the second dielectric layer 13 by a deposition process, and then a photoresist layer is formed on the pattern transfer layer 14 by a spin coating process, and then the photoresist layer is exposed and developed to form a patterned photoresist layer 15.

[0105] In this embodiment, the photoresist layer is also subjected to plasma treatment, preferably oxygen plasma treatment, so that the photoresist layer on the pattern transfer layer 14 except the patterned photoresist layer 15 is completely removed, and the adhesion between the patterned photoresist layer 15 and the first mask layer 16 formed subsequently can be increased.

[0106] Next, please refer to Figure 4a and Figure 4b As shown, a first mask layer 16 is formed on the pattern transfer layer 14, and the first mask layer 16 covers the patterned photoresist layer 15 and the pattern transfer layer 14. In this embodiment, the first mask layer 16 includes but is not limited to silicon oxide, and the first mask layer 16 can be formed by a deposition process. Please refer to Figure 5a and Figure 5b As shown, the first mask layer 16 and the patterned photoresist layer 15 are etched until the first mask layer 16 on the sidewall of the patterned photoresist layer 15 remains. For example, the first mask layer 16 on the upper surface of the pattern transfer layer 14 and the upper surface of the patterned photoresist layer 15 is etched, while the first mask layer 16 on the sidewall of the patterned photoresist layer 15 is retained, and the patterned photoresist layer 15 is removed by etching, so that the first mask layer 16 on the sidewall of the patterned photoresist layer 15 remains.

[0107] Next, please refer to Figure 6a and Figure 6b , Figure 7a and Figure 7b As shown, the remaining first mask layer 16 is used as a mask to etch the pattern transfer layer 14 until the second dielectric layer 13 is exposed, and then the remaining first mask layer 16 is removed. Figure 8a and Figure 8b , Figure 9a and Figure 9bAs shown, a second mask layer 17 is formed on the second dielectric layer 13, and the second mask layer 17 covers the second dielectric layer 13 and the remaining pattern transfer layer 14. Then, the second mask layer 17 is planarized until the remaining pattern transfer layer 14 is exposed, that is, the second mask layer 17 covers the second dielectric layer 13 and surrounds the side wall of the remaining pattern transfer layer 14.

[0108] Finally, please refer to Fig.10a and Fig.10b As shown, the second mask layer 17 is used as a mask to etch the remaining pattern transfer layer 14 and the second dielectric layer 13 and part of the substrate 10 thereunder to form a groove 18. First, the second mask layer 17 is used as a mask to etch the remaining pattern transfer layer 14 until the second dielectric layer 13 is exposed. Then, the second mask layer 17 is used as a mask to etch the exposed second dielectric layer 13 until the substrate 10 is exposed. Then, the second mask layer 17 is used as a mask to etch the exposed part of the substrate 10 until the substrate 10 is etched to a depth of 100nm to 200nm to form a groove 18. Finally, the second mask layer 17 is removed.

[0109] The depth of the groove 18 is between 100nm and 200nm, and the width of the groove 18 is between 15nm and 30nm. Fig.10b As shown, the groove 18 is in the shape of a closed ring.

[0110] from Figures 3a to 10a as well as Figure 3b to Figure 10b This is the step of forming the groove 18 on the substrate 10 described in this embodiment. In other embodiments, other methods can also be used to form the groove 18 on the substrate 10, and are not limited to the above method.

[0111] Fig.11a is Fig.10a A top view of a metal material layer filled on the structure shown, Fig.11b is Fig.10b A schematic cross-sectional view of a metal material layer filled on the structure shown. Fig.11a and Fig.11b As shown, a metal material layer 21 is filled in the groove 10 . For example, a metal material layer 21 may be formed on the substrate 10 by a deposition process, and the metal material layer 21 covers the substrate 10 and fills the groove 18 .

[0112] In this embodiment, before forming the metal material layer 21, it also includes: forming a gate dielectric layer 19 on the sidewall and bottom of the groove 18. In this embodiment, it is preferred to form the gate dielectric layer 19 by thermal oxidation, so the gate dielectric layer 19 is only located at the inner wall and bottom of the groove 18 where the substrate 10 exists. In other embodiments, the gate dielectric layer can also be formed by other methods such as deposition process, and the gate dielectric layer can be located on the sidewall, bottom and surface of the second dielectric layer 13 of the groove. Then, after forming the gate dielectric layer 19, it also includes: forming a barrier layer 20 on the sidewall and bottom of the groove. For example, the barrier layer 20 can be formed by deposition process, and the barrier layer 20 covers the sidewall, bottom and surface of the second dielectric layer 13 of the groove 18. Finally, the metal material layer 21 is filled in the groove. The material of the gate dielectric layer 19 includes but is not limited to silicon oxide, the material of the barrier layer 20 includes but is not limited to titanium nitride, and the material of the metal material layer 21 includes but is not limited to tungsten.

[0113] Fig.12a is Fig.11a A top view of an NMOS gate is formed on the structure shown. Figure 12b is Fig.11b A cross-sectional diagram of an NMOS gate formed on the structure shown. Fig.12a and Figure 12b As shown, the metal material layer 21 is etched until the remaining part of the metal material layer 21 is in the groove 18 to form the NMOS gate 22. For example, the metal material layer 21 can be etched by wet etching, and the metal material layer 21 on the second dielectric layer 13 is completely etched until the metal material layer 21 in the groove 18 is etched to one-quarter to one-third of the depth of the groove 18, that is, the metal material layer 21 at one-quarter to one-third of the depth of the top of the groove 18 is etched. Of course, the barrier layer 20 is also etched to one-quarter to one-third of the depth of the groove, and the barrier layer 20 and the metal material layer 21 remaining in the groove 18 constitute the NMOS gate 22.

[0114] The NMOS gate is a buried gate, which can reduce the area of ​​the word line driver, reduce the area of ​​a single chip, increase the number of chips on a single substrate, and reduce costs; at the same time, the NMOS gate is ring-shaped, which can eliminate the NMOS gate interconnection line and increase the gate contact area, thereby increasing the process window; and the NMOS gate can be manufactured simultaneously with the buried device of the memory array without adding additional processes.

[0115] Fig.13a is Fig.12a A top view of a first dielectric layer formed on the structure shown, Fig.13b is Figure 12b A cross-sectional schematic diagram of forming a first dielectric layer on the structure shown in FIG. Fig.13a and Fig.13b As shown, a first dielectric layer 23 is formed, and the first dielectric layer 23 covers the substrate 10 and fills the groove 18. In this embodiment, the material of the first dielectric layer 23 is the same as that of the second dielectric layer 13, including but not limited to silicon nitride. The first dielectric layer 23 can be formed by a deposition process, and the first dielectric layer 23 covers the first dielectric layer 13 and fills the groove 18. Since the material of the first dielectric layer 23 is the same as that of the second dielectric layer 13, Fig.13a and 13b In the embodiment, the first dielectric layer 23 and the second dielectric layer 13 are filled with the same material.

[0116] Fig.14 is Fig.13a A top view of a PMOS gate is formed on the structure shown. Since the cross-sectional diagram in this embodiment is a schematic diagram of the first region 10A, and this step is performed on the second region 10B, the corresponding cross-sectional diagram is not drawn. Please refer to Fig.14 As shown, the first dielectric layer 23 and the second dielectric layer 13 on the second region 10B are removed to expose the substrate 10 , and then a PMOS gate is formed on the substrate 10 in the second region 10B.

[0117] After removing the first dielectric layer 23 and the second dielectric layer 13 on the second region 10B, the method further includes: forming a gate dielectric layer 31 on the substrate 10 in the second region 10B, wherein the gate dielectric layer 31 includes but is not limited to silicon oxide and can be formed by thermal oxidation. Then, a polysilicon layer is deposited on the gate dielectric layer 31, and a PMOS gate 32 is formed by an exposure process. Preferably, the PMOS gate 32 is also in a closed ring shape.

[0118] Fig.15a is Fig.14 A top view of a metal plug formed on the structure shown, Fig.15b is Fig.13b A schematic cross-sectional view of a metal plug formed on the structure shown in FIG. Fig.15a and Fig.15bAs shown, after forming the NMOS gate 22 and the PMOS gate 32, an insulating layer 33 is formed, the insulating layer 33 covers the first dielectric layer 23 of the first region 10A, and covers the PMOS gate 32 and the gate dielectric layer 31 of the second region 10B. Preferably, the insulating layer 33 can be formed by a deposition method, and the material of the insulating layer 33 includes but is not limited to silicon oxide. Then, the insulating layer 33 is etched to form a plurality of through holes, and the through holes respectively expose the NMOS gate 22, the PMOS gate 33, the NMOS drain or the PMOS drain. Then, a metal material is filled in the through hole to form a plurality of metal plugs 34 that are in contact with the NMOS gate, the PMOS gate, the NMOS drain or the PMOS drain.

[0119] Of course, it also includes forming a plurality of metal interconnection layers, wherein the metal interconnection layers connect the NMOS drain and the PMOS drain to the word lines of the storage array through the metal plugs.

[0120] As described above, each of the word line drivers includes two NMOS and one PMOS. The two NMOS can be located on the same side of the PMOS or on opposite sides of the PMOS. Fig.16 and Fig.17 shown.

[0121] like Fig.16 As shown, the word line driver includes two NMOS and one PMOS, and the two NMOS are located on the same side of the PMOS, that is, Fig.16The two NMOS are located in the first region 10A, and the two NMOS gates 22 are annular and located in the substrate 10, forming a buried ring gate. An active region 11 is formed in the substrate 10 of the first region 10A, and an NMOS source (not shown) and an NMOS drain (not shown) are also formed in the active region 11. Metal plugs 34 are formed on both the NMOS gate 22 and the NMOS drain. The PMOS is located in the second region 10B, and the PMOS gate 32 is also annular, and multiple PMOS gates 32 are connected in series, and an active region 11 is formed in the substrate 10 of the second region 10B, and a PMOS source (not shown) and a PMOS drain (not shown) are also formed in the active region 11, and metal plugs 34 are formed on both the PMOS gate 32 and the PMOS drain. A plurality of metal interconnection layers 35 are also formed on the substrate 10, and the metal interconnection layers 35 connect the NMOS drain and the PMOS drain to the word lines of the storage array area located on both sides of the word line driver through the metal plugs 34, and the extension direction of the metal interconnection layers 35 is parallel to the direction of the word lines.

[0122] like Fig.17 As shown, the word line driver includes two NMOS and one PMOS, and the two NMOS are located on opposite sides of the PMOS. The two first regions 10A are located on both sides of the second region 10B, and the two NMOS are located in the first regions 10A on both sides, respectively. The two NMOS gates 22 are annular and located in the substrate 10, forming a buried ring gate. An active region 11 is formed in the substrate 10 of each first region 10A, and an NMOS source (not shown) and an NMOS drain (not shown) are also formed in each active region 11. Metal plugs 34 are formed on the NMOS gates 22 and the NMOS drains. The PMOS is located in the second region 10B, the PMOS gate 32 is also annular, and a plurality of the PMOS gates 32 are connected in series, and an active region 11 is formed in the substrate 10 of the second region 10B, a PMOS source (not shown) and a PMOS drain (not shown) are also formed in the active region 11, and metal plugs 34 are formed on the PMOS gate 32 and the PMOS drain. A plurality of metal interconnect layers 35 are also formed on the substrate 10, and the metal interconnect layers 35 connect the NMOS drain and the PMOS drain to the word lines of the storage array area located on both sides of the word line driver through the metal plugs 34, and the extension direction of the metal interconnect layer 35 is parallel to the direction of the word lines.

[0123] exist Fig.17In the word line driver shown, the two NMOS are located on opposite sides of the PMOS, so that the wire lengths from the output end of the word line driver PMOS to the left and right array area word lines are the same, effectively reducing the time difference of opening the word lines on both sides and improving device performance.

[0124] Correspondingly, the present invention also provides a word line driver, which is prepared by the method for preparing the word line driver as described above. Fig.15a and Fig.15b As shown, the word line driver comprises:

[0125] A substrate 10 is provided, wherein an active region 11 is formed in the substrate 10, and the substrate 10 includes a first region 10A for forming an NMOS and a second region 10B for forming a PMOS; a metal material layer 21 is filled at the bottom of a partial annular groove of the substrate 10 in the first region 10A to form an NMOS gate 22; a first dielectric layer 23 covers the substrate 10 in the first region 10A and fills the groove; and a PMOS gate 32 is located on the substrate 10 in the second region 10B.

[0126] Furthermore, an NMOS source (not shown) and an NMOS drain (not shown) are formed in the active area 11 of the first region 10A, and a PMOS source (not shown) and a PMOS drain (not shown) are formed in the active area 11 of the second region 10B.

[0127] Preferably, the word line driver further comprises: an insulating layer 33 covering the first dielectric layer 23 and the PMOS gate 32; a plurality of metal plugs 34 located in the insulating layer 33 and the first dielectric layer 23, the metal plugs 34 respectively contacting the NMOS gate 22, the PMOS gate 32, the NMOS drain or the PMOS drain; and a metal interconnect layer 35 (such as Fig.16 and Fig.17 As shown), the metal interconnect layer 35 connects the NMOS drain and the PMOS drain to the word line of the storage array through the metal plug 34.

[0128] Preferably, the word line driver further includes: a gate dielectric layer 19 and a gate dielectric layer 31, wherein the gate dielectric layer 19 is located on the sidewall and bottom of the groove in the first region 10A, and the gate dielectric layer 31 is located on the substrate 10 in the second region 10B. The word line driver further includes a barrier layer 20, wherein the barrier layer 20 is located in the groove and between the gate dielectric layer 19 and the metal material layer 21. The word line driver further includes a second dielectric layer 13, wherein the second dielectric layer 13 is located on the substrate 10, and the first dielectric layer 23 covers the second dielectric layer 13.

[0129] The word line driver includes two NMOS and one PMOS, and the two NMOS can be located on the same side of the PMOS or on opposite sides of the PMOS. Fig.16 As shown, the two NMOS are located on the same side of the PMOS. Fig.17 The two NMOSs are located on opposite sides of the PMOS.

[0130] In summary, in the word line driver and the preparation method thereof provided by the present invention, the NMOS gate is a buried gate, which can reduce the area of ​​the word line driver, reduce the area of ​​a single chip, increase the number of chips on a single substrate, and reduce costs; at the same time, the NMOS gate is ring-shaped, which can eliminate the NMOS gate interconnection line, increase the gate contact area, and increase the process window.

[0131] Furthermore, the NMOS gate and the embedded device of the memory array are manufactured simultaneously without adding additional processes.

[0132] Furthermore, the two NMOS are located on opposite sides of the PMOS, so that the wire lengths from the output end of the word line driver PMOS to the word lines in the left and right array areas are the same, effectively reducing the time difference of turning on the word lines on both sides and improving device performance.

[0133] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for preparing a word line driver, characterized in that: include: Providing a substrate, forming an active region in the substrate, and the substrate includes a first region for forming an NMOS and a second region for forming a PMOS; forming a groove in the substrate of the first region, wherein the groove is in a closed ring shape; Filling a metal material layer in the groove; Etching the metal material layer until the remaining portion of the metal material layer is within the groove to form an NMOS gate; forming a first dielectric layer, wherein the first dielectric layer covers the substrate and fills the groove; removing the first dielectric layer in the second region, and forming a PMOS gate on the substrate in the second region; The substrate further includes a third region for forming a storage array, and an NMOS gate is formed in the first region while an embedded device is formed in the third region.

2. The method for preparing a word line driver according to claim 1, wherein: The step of forming a groove in the substrate in the first region comprises: forming a second dielectric layer, a pattern transfer layer and a patterned photoresist layer on the substrate in sequence; forming a first mask layer, wherein the first mask layer covers the patterned photoresist layer and the pattern transfer layer; Etching the first mask layer and the patterned photoresist layer until the first mask layer on the sidewall of the patterned photoresist layer remains; Using the remaining first mask layer as a mask, etching the pattern transfer layer, and removing the remaining first mask layer; forming a second mask layer, wherein the second mask layer covers the second dielectric layer and surrounds the remaining sidewalls of the pattern transfer layer; The second mask layer is used as a mask to etch the remaining pattern transfer layer and the second dielectric layer and a portion of the substrate thereunder to form a groove.

3. The method for preparing a word line driver according to claim 2, wherein: The step of forming a second mask layer, wherein the second mask layer covers the second dielectric layer and surrounds the remaining sidewalls of the pattern transfer layer comprises: forming a second mask layer, wherein the second mask layer covers the second dielectric layer and the remaining pattern transfer layer; The second mask layer is planarized until the remaining pattern transfer layer is exposed.

4. The method for preparing a word line driver according to claim 1, wherein: After forming the groove and before filling the metal material layer, the method further includes: A gate dielectric layer and a barrier layer are sequentially formed on the sidewall and bottom of the groove.

5. The method for preparing a word line driver according to claim 1, wherein: The depth of the groove is between 100nm and 200nm; the width of the groove is between 15nm and 30nm; The metal material layer is etched to a depth of one quarter to one third of the groove.

6. The method for preparing a word line driver according to claim 5, characterized in that: After forming the PMOS gate, the method further includes: forming an insulating layer, wherein the insulating layer covers the first dielectric layer and the PMOS gate; forming a plurality of metal plugs, wherein the metal plugs are located in the insulating layer and the first dielectric layer and are in contact with the NMOS drain or the PMOS drain; A plurality of metal interconnection layers are formed, wherein the metal interconnection layers connect the NMOS drain and the PMOS drain to the word lines in the third region through the metal plugs.

7. The method for preparing a word line driver according to any one of claims 1 to 6, characterized in that: Two NMOSs and one PMOS are formed, and the two NMOSs are respectively located at two opposite sides of the PMOS.

8. A word line driver, characterized in that: The method for preparing a word line driver according to any one of claims 1 to 7 comprises: A substrate, wherein an active region is formed in the substrate, and the substrate includes a first region for forming an NMOS and a second region for forming a PMOS; A metal material layer is filled in the bottom of a portion of the annular groove of the substrate in the first region to form an NMOS gate; A first dielectric layer, covering the substrate in the first region and filling the groove; A PMOS gate is located on the substrate in the second region; The embedded device is located in the third region for forming the memory array.

9. The word line driver according to claim 8, wherein: Also includes: an insulating layer, covering the first dielectric layer and the PMOS gate; A metal plug, located in the insulating layer and the first dielectric layer, and in contact with the NMOS drain or the PMOS drain; as well as A metal interconnection layer is provided, wherein the metal interconnection layer connects the NMOS drain and the PMOS drain to a word line of a storage array through the metal plug.

10. The word line driver according to claim 8, wherein: The word line driver includes two NMOS and one PMOS, and the two NMOS are respectively located at two opposite sides of the PMOS.

11. A method for preparing a word line driver, characterized in that: include: Providing a substrate, forming an active region in the substrate, and the substrate includes a first region for forming an NMOS and a second region for forming a PMOS; forming a groove in the substrate of the first region, wherein the groove is in a closed ring shape; Filling a metal material layer in the groove; Etching the metal material layer until the remaining portion of the metal material layer is within the groove to form an NMOS gate; forming a first dielectric layer, wherein the first dielectric layer covers the substrate and fills the groove; removing the first dielectric layer in the second region, and forming a PMOS gate on the substrate in the second region; The step of forming a groove in the substrate in the first region comprises: forming a second dielectric layer, a pattern transfer layer and a patterned photoresist layer on the substrate in sequence; forming a first mask layer, wherein the first mask layer covers the patterned photoresist layer and the pattern transfer layer; Etching the first mask layer and the patterned photoresist layer until the first mask layer on the sidewall of the patterned photoresist layer remains; Using the remaining first mask layer as a mask, etching the pattern transfer layer, and removing the remaining first mask layer; forming a second mask layer, wherein the second mask layer covers the second dielectric layer and surrounds the remaining sidewalls of the pattern transfer layer; The second mask layer is used as a mask to etch the remaining pattern transfer layer and the second dielectric layer and a portion of the substrate thereunder to form a groove.

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