NPN type Schottky collector region AlGaN / GaN HBT device and preparation method thereof

Abstract

The present invention discloses an NPN type Schottky collector region AlGaN / GaN HBT device and a preparation method thereof, which comprises, from bottom to top, a substrate, a buried oxide layer, a collector region, a base region and an emitter region, wherein the collector region comprises a lower N-type single crystal silicon layer and an upper TiSi2 layer, the base region comprises a P-type GaN layer, and the emitter region comprises an N-type AlGaN layer and an N-type GaN cap layer thereon; a collector electrode is disposed on the N-type single crystal silicon layer, a base electrode is disposed on the base region, and an emitter electrode is disposed on the GaN cap layer. The present invention has good contact interface characteristics, can improve the switching speed and cut-off frequency of the device, has a simple process and is compatible with existing silicon-based processes.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors, and in particular relates to an NPN-type Schottky collector region AlGaN / GaN HBT device and a preparation method thereof. Background Art

[0002] Traditional semiconductor materials represented by silicon (Si) and gallium arsenide (GaAs) are no longer able to meet the requirements of radiation resistance, high temperature, high voltage and high power for the development of modern electronic technology. Wide bandgap semiconductor GaN electronic devices can be used in high temperature, high pressure, high frequency and harsh environments, such as radar and wireless communication base stations and satellite communications.

[0003] Due to GaN's large bandgap, high breakdown voltage, high electron saturation drift velocity, excellent electrical and optical properties and good chemical stability, it is favored in high-frequency, high-power, and high-temperature electronic devices. GaN heterojunction bipolar transistors (HBTs) have high current gain. At present, it is reported that the AlGaN / GaN NPN HBT device used for power amplifiers of high-power communications and radars can work at a high temperature of up to 300°C, which has attracted widespread attention in the fields of national defense and communications.

[0004] As GaN device technology matures, GaN HBT will be used more and more in communication system equipment to maximize the system's operating capacity and reliability: in the military, Raytheon is developing GaN HBT-based transceiver components for future military radar upgrades; in civilian use, GaN HBT's high-frequency and high-power processing capabilities are important for the development of amplifiers and modulators and other key devices in advanced communication networks.

[0005] However, the existing GaN HBT devices, on the one hand, are limited by the high dislocation density of GaN single crystals grown by heteroepitaxial technology using sapphire and silicon carbide (SiC) as substrates, and their performance is not satisfactory. The DC current gain of GaN HBT is still relatively small, and the process is not very stable. On the other hand, in order to further improve the switching performance of the existing HBT devices, it is necessary to introduce additional process flows on the original basis, which not only makes the process flow more complicated, but also increases the production cost and reduces the production efficiency. Summary of the invention

[0006] In view of the deficiencies in the prior art, the present invention discloses an NPN-type Schottky collector AlGaN / GaN HBT device having good contact interface characteristics, capable of improving device switching speed and cutoff frequency, simple process, and compatibility with existing silicon-based processes, and a preparation method thereof.

[0007] In one aspect of the present invention, an NPN-type Schottky collector region AlGaN / GaN HBT device comprises, from bottom to top, a substrate, a buried oxide layer, a collector region, a base region and an emitter region, wherein the collector region comprises a lower N-type single crystal silicon layer and an upper metal silicide layer, the base region comprises a P-type GaN layer, and the emitter region comprises an N-type AlGaN layer and an N-type GaN cap layer thereon; a collector electrode is disposed on the N-type single crystal silicon layer, a base electrode is disposed on the base region, and an emitter electrode is disposed on the GaN cap layer; and the metal silicide in the metal silicide layer is TiSi 2 、CoSi 2 、MoSi 2 One of the .

[0008] Furthermore, a first intrinsic GaN barrier layer is provided between the P-type GaN layer and the metal silicide layer, a second intrinsic GaN barrier layer is provided between the P-type GaN layer and the N-type AlGaN layer, and the base is provided on the second intrinsic GaN barrier layer.

[0009] Particularly, the thickness of the first intrinsic GaN barrier layer and the second intrinsic GaN barrier layer is 5-10 nm.

[0010] Furthermore, the N-type AlGaN layer includes N-type doped Al x Ga 1-x N layer and N-type doped Al thereon r Ga 1-r N composition graded layer, in which the N-type doped Al r Ga 1-r The molar composition r of Al in the N composition gradient layer changes from x to 0 from bottom to top.

[0011] In particular, the N-type doped Al x Ga 1-x The thickness of the N layer is 100 nm; the N-type doped Al r Ga 1-r The thickness of the N component graded layer is 150 nm.

[0012] In another aspect of the present invention, a method for preparing an NPN-type Schottky collector region AlGaN / GaN HBT device comprises the following steps:

[0013] S1: preparing an SOI substrate, the top layer of which is an N-type single crystal silicon layer; cleaning and chemical mechanical polishing the surface of the N-type single crystal silicon layer;

[0014] S2: Deposit and grow a layer of metal Ti, Co or Mo, and then perform rapid thermal annealing to oxidize the surface of the metal Ti, Co or Mo and the N-type single crystal silicon layer below to TiSi 2or CoSi 2 or MoSi 2 , forming a metal silicide layer as a collector region;

[0015] S3: growing a first intrinsic GaN barrier layer on the metal silicide layer; growing a P-type GaN layer on the first intrinsic GaN barrier layer; and growing a second intrinsic GaN barrier layer on the P-type GaN layer;

[0016] S4: growing an N-type AlGaN layer on the second intrinsic GaN barrier layer;

[0017] S5: Continue to grow an N-type GaN cap layer;

[0018] S6: Prepare the emitter, base and collector.

[0019] Furthermore, the method for growing the N-type AlGaN layer in step S4 includes: firstly growing a layer of N-type doped Al by MOCVD; x Ga 1-x N layer, and then doping Al x Ga 1-x A layer of N-type doped Al is grown on the N layer r Ga 1-r N component gradient layer; the N-type doped Al r Ga 1-r The molar composition r of Al in the N composition gradient layer changes from x to 0 from bottom to top.

[0020] In particular, the molar component r of Al changes gradually from x to 0 in a linear or exponential manner.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] 1. By growing an extremely thin layer of metal silicide with good interface morphology and interface state on the single crystal silicon material, a Schottky contact of silicon / metal silicide is formed with the single crystal silicon, which not only ensures excellent contact interface characteristics, but also improves the switching speed and cut-off frequency of the device. At the same time, the preparation process is relatively simple, compatible with conventional silicon-based processes, and has high production efficiency;

[0023] 2. By introducing SOI substrate technology in the preparation of AlGaN / GaN HBT devices, it can further reduce parasitic capacitance effects, reduce device power consumption, avoid latch-up effects, etc., which can improve the overall performance of the device and facilitate process integration with current small-size, low-power SOI CMOS devices;

[0024] 3. By preparing the first and second intrinsic GaN barrier layers on both sides of the P-type GaN layer, the negative effects caused by the diffusion of doped atoms in the P-type heavily doped GaN base region to the emitter region and the collector region can be effectively suppressed, thereby suppressing the parasitic barrier effect;

[0025] 4. By adopting a multi-layer emitter structure including a gradient composition, under the forward bias condition of the AlGaN / GaN emitter junction, the gradient Al x Ga 1-x Introducing an electric field in the N layer to accelerate the transport of reverse-injected minority carriers further increases the time constant of the emission region, which can effectively improve the frequency characteristics of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic diagram of the structure of the NPN-type Schottky collector region AlGaN / GaN HBT device in the present invention;

[0027] Figure 2 N-type doped Al r Ga 1-r Schematic diagram of the gradient of N-component gradient layer;

[0028] Figure 3 It is a schematic diagram of the device structure after step S1 of the method for preparing an NPN-type Schottky collector region AlGaN / GaN HBT device in the present invention;

[0029] Figure 4 Schematic diagram of the device structure after step S2 of the method for preparing an NPN-type Schottky collector region AlGaN / GaN HBT device in the present invention;

[0030] Figure 5 It is a schematic diagram of the device structure after step S3 of the method for preparing an NPN-type Schottky collector region AlGaN / GaN HBT device in the present invention;

[0031] Figure 6 It is a schematic diagram of the device structure after step S5 of the method for preparing an NPN-type Schottky collector region AlGaN / GaN HBT device in the present invention.

[0032] Among them, 1 substrate, 2 buried oxide layer, 3 collector region, 31 N-type single crystal silicon layer, 32 metal silicide layer, 33 collector, 4 base region, 41 P-type GaN layer, 42 base, 43 first intrinsic GaN barrier layer, 44 second intrinsic GaN barrier layer, 5 emitter region, 51 N-type GaN cap layer, 52 emitter, 53 N-type doped Al x Ga 1-x N layer, 54N type doped Al r Ga 1-r N component gradient layer. DETAILED DESCRIPTION

[0033] In order to make the technical means, creative features, objectives and effects of the invention easy to understand, the invention is further described below in conjunction with specific diagrams. It can be understood that the directional terms such as "upper" and "lower" used in this article do not refer to a specific direction, do not constitute a limitation of the scheme itself, but are merely a description method that is easy to understand based on the specific instructions and drawings.

[0034] In one aspect of the present invention, an NPN-type Schottky collector region AlGaN / GaN HBT device, such as Figure 1 As shown, from bottom to top, it includes: substrate 1, buried oxide layer 2, collector region 3, base region 4 and emitter region 5, the collector region 3 includes a lower N-type single crystal silicon layer 31 and an upper metal silicide layer 32, the base region 4 includes a P-type GaN layer 41, and the emitter region 5 includes an N-type AlGaN layer and an N-type GaN cap layer 51 located thereon; a collector electrode 33 is provided on the N-type single crystal silicon layer 31, a base electrode 42 is provided on the base region 4, and an emitter electrode 52 is provided on the GaN cap layer 51. In particular, the metal silicide in the metal silicide layer 32 can be TiSi 2 、CoSi 2 、MoSi 2 One of the .

[0035] The substrate can be a P-type lightly doped single crystal silicon substrate, and the two sides of the N-type single crystal silicon layer are collector contact areas. The metal silicide layer is very thin, and its thickness is usually less than 10nm. In practice, it is found that the interface morphology and interface state at the interface between the metal silicide layer and the single crystal silicon below it have a greater impact on the device characteristics. The metal silicide layer and the N-type single crystal silicon layer below it form a "combined collector" structure. The N-type GaN cap layer can be doped with arsenic (As), and the doping concentration can be 5×10 18 cm -3 The P-type GaN layer may be doped with boron (B), and the boron doping concentration may be 2×10 19 cm -3 , the thickness can be 50nm.

[0036] First, this solution uses SOI substrate, which further reduces parasitic capacitance effects, reduces device power consumption, avoids latch-up effects, and improves the overall performance of the device. It is easy to integrate with the current small-size, low-power SOI CMOS devices and is in line with the technical route of proportional device reduction.

[0037] Secondly, this scheme replaces the collector junction of the conventional HBT with a Schottky junction. In addition to avoiding the large dislocations and interface states generated by the single-crystal GaN collector based on sapphire or silicon carbide substrates, it can also further improve the operating speed of the device. This is because the Schottky contact has the following two obvious main advantages: (1) The collector resistance is 0; (2) Because there is no collector junction space charge region, the collector junction transit time can be 0, and the charge storage time is also zero, which can further increase the cutoff frequency. At the same time, it also takes into account the compatibility with conventional silicon-based CMOS processes, which is convenient for large-scale commercial manufacturing. Considering that titanium silicide (TiSi 2 ) has very ideal material physical properties: high conductivity, high selectivity, excellent thermal stability, better silicon adsorption, good process adaptability and very low signal interference. In this scheme, a very thin layer of metal silicide TiSi with good interface morphology and interface state is grown on the single crystal silicon material. 2 , forming Si / TiSi with single crystal silicon 2 The Schottky contact not only ensures excellent contact interface characteristics, but also improves the switching speed and cutoff frequency of the device. At the same time, the preparation process is relatively simple and compatible with conventional silicon-based processes. 2 It can also be replaced by CoSi with similar properties. 2 and MoSi 2 As far as the current technology is concerned, TiSi 2 It is the preferred option.

[0038] As a further optimization, a first intrinsic GaN barrier layer 43 is provided between the P-type GaN layer 41 and the metal silicide layer 32, a second intrinsic GaN barrier layer 44 is provided between the P-type GaN layer 41 and the N-type AlGaN layer, and the base 42 is provided on the second intrinsic GaN barrier layer 44. In particular, the thickness of the first intrinsic GaN barrier layer 43 and the second intrinsic GaN barrier layer 44 may be 5 to 10 nm. If the barrier layer is too thin, it will not play a blocking role and increase the series resistance; if it is too thick, it will increase the transport time of carriers and affect the frequency performance.

[0039] On the one hand, this solution arranges an undoped first intrinsic GaN barrier layer on the metal silicide layer in the collector region, and on the other hand, arranges an undoped second intrinsic GaN barrier layer under the heavily doped N-type AlGaN layer in the emitter region. This can effectively suppress the negative effects caused by the diffusion of doped atoms in the P-type heavily doped GaN base region to the emitter region and the collector region, and suppress the parasitic barrier effect.

[0040] As a further optimization, the N-type AlGaN layer includes N-type doped Al x Ga 1-x The N-type doped Al layer 53 and the N-type doped Al layer 53r Ga 1-r N-composition graded layer 54, in which the molar composition r of Al from bottom to top in the N-type doped Al r Ga 1-r N-composition graded layer 54 gradually changes from x to 0.

[0041] In the N-type doped Al x Ga 1-x N layer, 0 < x < 1, and the value of x can be adjusted according to actual needs. To avoid base region collapse, the N-type doped Al x Ga 1-x N layer is preferably doped with arsenic, and the doping concentration can be 1×10 18 cm -3 , and the thickness of this layer can be 100 nm. In the N-type doped Al r Ga 1-r N-composition graded layer, 0 < r < x, is preferably doped with arsenic, and the doping concentration can be 1×10 18 cm -3 , and the thickness of this layer can be 150 nm. As Figure 2 shown, the gradient mode can be linear gradient or exponential gradient.

[0042] In this solution, a multi-layer emitter structure is adopted. Under the condition of forward bias of the AlGaN / GaN emitter junction, the conduction band of the Al r Ga 1-r N-composition graded layer hardly tilts, and the change in the bandgap width is mainly reflected in the valence band. In the graded Al x Ga 1-x N layer in the emitter region, an electric field that accelerates the transport of minority carriers (holes) for reverse injection is introduced, further improving the time constant of the emitter region and effectively improving the frequency characteristics of the device.

[0043] On the other hand, a method for fabricating an NPN-type Schottky collector region AlGaN / GaN HBT device of the present invention includes the following steps:

[0044] S1: Prepare an SOI substrate, the top N-type single-crystalline silicon layer of which is heavily doped, and the doping element can be P or As, and the doping concentration can be 2×10 19 cm -3 ; clean and perform chemical mechanical polishing (CMP) treatment on the surface of the N-type single-crystalline silicon layer; as Figure 3 shown;

[0045] S2: Fabricate a metal silicide layer: deposit and grow a layer of metal titanium (Ti) or cobalt (Co) or molybdenum (Mo), and then perform rapid thermal annealing (RTA) treatment to oxidize Ti and the surface of the underlying N-type single-crystalline silicon layer to TiSi 2or CoSi 2 or MoSi 2 , forming a metal silicide layer as a collector region; Figure 4 As shown;

[0046] S3: growing a first intrinsic GaN barrier layer on the metal silicide layer, the thickness of which may be 5 nm; growing a P-type GaN layer on the first intrinsic GaN barrier layer, the thickness of which may be 50 nm; growing a second intrinsic GaN barrier layer on the P-type GaN layer, the thickness of which may be 5 nm; Figure 5 As shown;

[0047] S4: growing an N-type AlGaN layer on the second intrinsic GaN barrier layer;

[0048] S5: Continue to grow an N-type GaN cap layer; Figure 6 As shown;

[0049] S6: Prepare the emitter, base and collector: Etch the emitter region, base region and collector region in sequence according to the preset emitter, base and collector widths to form a mesa structure; dry oxygen oxidation is performed on the entire etched mesa structure to form a SiO2 layer covering the entire mesa. 2 Oxide layer; then the oxide layer of the emitter region, base region and collector region window is etched away to form the emitter region, base region and collector region window, and metal is deposited on the emitter region, base region and collector region window to form the emitter, base and collector. Figure 1 shown.

[0050] The growth of metallic titanium in step S2 may be carried out by physical vapor deposition (PVD). The growth of the intrinsic GaN barrier layer in step S3 may be carried out by metal organic chemical vapor deposition (MOCVD). The growth of the N-type AlGaN layer in step S4 may be carried out by metal organic chemical vapor deposition (MOCVD). The buried oxide layer thickness of the SOI substrate should not be too thick, and its typical value may be 0.5 μm. The thickness of the metallic titanium may be 5 nm, and the thickness of the metal silicide layer formed by oxidation is usually less than 10 nm. The P-type GaN layer may be boron doped, and the doping concentration may be 2×10 19 cm -3 The N-type GaN cap layer can be doped with arsenic, with a doping concentration of 5×10 18c m -3 The thickness can be 50 μm. The method for preparing the emitter, base and collector in step S6 belongs to the prior art.

[0051] The thickness of the N-type single-crystalline silicon layer should be much greater than the depletion thickness t of this layer caused by the substrate bias. Under the action of the substrate voltage, a back-to-back MOS capacitor structure is formed in the SOI substrate at this time. According to semiconductor device physics, the depletion thickness t can be solved by the following quadratic equation:

[0052]

[0053] In the formula, q is the electron charge, N Si is the doping concentration of the N-type single-crystalline silicon layer above the oxide layer, ε Si and ε OX are the dielectric constants of single-crystalline silicon and the oxide layer respectively, tOX is the thickness of the oxide layer, V S , V C and V MS are the substrate voltage, the collector voltage and the work function difference of the single-crystalline silicon regions on both sides of the oxide layer respectively.

[0054] As a further optimization, the method for growing the N-type AlGaN layer in step S4 includes:

[0055] First, grow a layer of N-doped Al x Ga 1-x N layer by MOCVD, and then grow a layer of N-doped Al x Ga 1-x N layer on the N-doped Al r Ga 1-r N layer; in the N-doped Al x Ga 1-x N layer, 0 < x < 1, and the value of x can be adjusted according to actual needs. In the N-doped Al r Ga 1-r N composition gradient layer, the molar fraction r of Al gradually changes from x to 0 from bottom to top.

[0056] The N-doped Al x Ga 1-x N layer is preferably doped with arsenic, and the doping concentration is 1×10 18 cm -3 , and the thickness of this layer can be 100 nm. The N-doped Al r Ga 1-r N composition gradient layer is preferably doped with arsenic, and the doping concentration is 1×10 18 cm -3 , and the thickness of this layer can be 150 nm. The gradient method can be a linear gradient or an exponential gradient, as shown in Figure 2 .

[0057] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiment. All technical solutions belonging to the principle of the present invention belong to the protection scope of the present invention. For those skilled in the art, several improvements made without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. NPN type Schottky collector AlGaN / GaN HBT device, characterized in that: From bottom to top, it successively includes: a substrate, a buried oxide layer, a collector region, a base region, and an emitter region. The collector region includes a lower N-type single-crystalline silicon layer and an upper metal silicide layer. The N-type single-crystalline silicon layer forms a Schottky contact with the metal silicide layer. The base region includes a P-type GaN layer. The emitter region includes an N-type AlGaN layer and an N-type GaN cap layer thereon. A collector is provided on the N-type single-crystalline silicon layer, a base is provided on the base region, and an emitter is provided on the GaN cap layer. The metal silicide in the metal silicide layer is one of TiSi2, CoSi2, and MoSi2. The N-type AlGaN layer includes an N-type doped Al x Ga 1-x N layer and an N-type doped Al r Ga 1-r N composition graded layer thereon. In the N-type doped Al r Ga 1-r N composition graded layer, the molar fraction r of Al gradually changes from x to 0 from bottom to top, where 0 < x < 1. The thickness of the N-type doped Al x Ga 1-x N layer is 100 nm. The thickness of the N-type doped Al r Ga 1-r N composition graded layer is 150 nm. The way of gradually changing from the molar fraction r of Al changing from x to 0 is linear gradation or exponential gradation.

2. The NPN Schottky collector region AlGaN / GaN HBT device according to claim 1, characterized in that: A first intrinsic GaN barrier layer is provided between the P-type GaN layer and the metal silicide layer, a second intrinsic GaN barrier layer is provided between the P-type GaN layer and the N-type AlGaN layer, and the base is provided on the second intrinsic GaN barrier layer.

3. The NPN Schottky collector region AlGaN / GaN HBT device according to claim 2, characterized in that: The thickness of the first intrinsic GaN barrier layer and the second intrinsic GaN barrier layer is 5-10 nm.

4. A method for preparing an NPN-type Schottky collector region AlGaN / GaN HBT device, characterized in that: The steps include: S1: preparing an SOI substrate, the top layer of which is an N-type single crystal silicon layer; cleaning and chemical mechanical polishing the surface of the N-type single crystal silicon layer; S2: depositing and growing a layer of metal Ti, Co or Mo, and then performing a rapid thermal annealing process to silicidize the metal Ti, Co or Mo and the surface of the N-type single crystal silicon layer thereunder into TiSi2, CoSi2 or MoSi2, forming a metal silicide layer as a collector region, wherein the N-type single crystal silicon layer forms a Schottky contact with the metal silicide layer; S3: growing a first intrinsic GaN barrier layer on the metal silicide layer; growing a P-type GaN layer on the first intrinsic GaN barrier layer; and growing a second intrinsic GaN barrier layer on the P-type GaN layer; S4: growing an N-type AlGaN layer on the second intrinsic GaN barrier layer; S5: Continue to grow an N-type GaN cap layer; S6: Prepare the emitter, base and collector.

5. The method for preparing an NPN Schottky collector region AlGaN / GaN HBT device according to claim 4, characterized in that: The method for growing an N-type AlGaN layer in step S4 includes first growing an N-type doped AlGaN layer by MOCVD. x Ga 1-x N layer, and then doping Al x Ga 1-x A layer of N-type doped Al is grown on the N layer r Ga 1-r N component gradient layer; the N-type doped Al r Ga 1-r The molar composition r of Al in the N composition gradient layer changes from x to 0, 0 <x<1。

Images