AD converter device and millimeter wave radar system

Abstract

Various embodiments of the present disclosure relate to an AD converter device and a millimeter wave radar system. A MASH type Σ-Δ AD converter includes a modulator; an analog filter that filters an extracted signal obtained by extracting a detection signal and a quantization error generated in a quantizer within the Σ-Δ modulator; a low-speed AD converter that performs AD conversion on an output signal of the analog filter; a first adaptive filter that searches for a transfer function of the Σ-Δ modulator; a second adaptive filter that searches for a transfer function from the output of the modulator via the analog filter to the low-speed AD converter; and a noise elimination circuit that uses the search results of the first and second adaptive filters to eliminate the detection signal and the quantization error included in the output signal of the quantizer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2018-219382 filed on November 22, 2018 including the specification, drawings and abstract is incorporated herein by reference in its entirety. Technical Field

[0003] The present application relates to an AD (Analog to Digital) converter device and a millimeter wave radar system having the AD converter device, for example, an AD converter device and a millimeter wave radar system suitable for performing high-accuracy AD conversion. Background Art

[0004] U.S. Patent No. 6970120 (Patent Document 1) discloses an AD conversion circuit including a calibration circuit for searching for filter coefficients of a calibration filter. During the startup time of the AD conversion circuit, the calibration circuit searches for the filter coefficients by observing the final output of the AD converter while providing a pseudo-random signal to the AD conversion circuit.

[0005] Non-patent document 1 (Yun-Shiang Shu and 4 others, "LMS-Based noise leakage calibration of cascaded continuous-time delta-sigma modulators", IEEE JSSC, Vol. 45, February 2010, pp. 368-379) discloses a delta-sigma modulator including a calibration circuit for performing calibration so that the time constant of an analog loop filter matches the time constant of a digital noise elimination filter. In particular, the calibration circuit uses an LMS (least mean square) algorithm to search for the time constant of the analog loop filter while injecting binary pulses into a quantizer. The analog loop filter is used to zero the residual power in the final output of the delta-sigma modulator. Summary of the invention

[0006] For example, a millimeter wave radar system for vehicle use requires a robust AD converter with high resolution and a wide signal band. As an AD converter for this requirement, one known is a MASH (multi-stage noise shaping) type Σ-Δ (ΣΔ) AD converter device (also referred to as a Δ-Σ (ΔΣ) AD converter). Note, however, that in a MASH type ΣΔAD converter device, if a characteristic change occurs in an analog circuit, the resolution cannot be improved. It is considered that calibration is performed using the methods of Patent Document 1 and Non-Patent Document 1. However, the methods of Patent Document 1 and Non-Patent Document 1 cannot perform high-accuracy AD conversion due to insufficient calibration.

[0007] According to one embodiment, a MASH type Σ-Δ AD converter device is provided, which includes a detection signal generating circuit, a first modulator, an analog filter, a first AD converter, a first adaptive filter, a second adaptive filter and a noise elimination circuit. The detection signal generating circuit generates a detection signal. The first modulator includes a first analog integrator configured with an analog circuit and a first quantizer, and the first quantizer is used to quantize the added signal obtained by adding the detection signal to the output signal of the first analog integrator. The analog filter filters the extracted signal obtained by extracting the detection signal and the quantization error generated in the first quantizer. The first AD converter converts the output signal of the analog filter from an analog signal to a digital signal, and the first AD converter operates at an operating frequency lower than the operating frequency of the first modulator. The first adaptive filter searches for a first transfer function by observing the output signal of the first quantizer according to the detection signal, and the first transfer function is a transfer function of the first modulator. The second adaptive filter searches for a second transfer function by observing the output signal of the first AD converter according to the detection signal, and the second transfer function is a transfer function from the output of the first modulator to the first AD converter via the analog filter. The noise removal circuit removes a quantization error and a detection signal included in an output signal of the first quantizer using a search result of the first adaptive filter and a search result of the second adaptive filter.

[0008] According to one embodiment, a millimeter wave radar system is provided, which includes a transmitting antenna, a plurality of receiving antennas, a high frequency unit, a low pass filter and a baseband unit. The transmitting antenna radiates a transmission wave into the air. A plurality of receiving antennas receive reflected waves of the transmission wave from an object. The high frequency unit generates a plurality of difference frequency signals by down-converting the reflected waves received by the plurality of receiving antennas using the transmission wave. The low pass filter filters the plurality of difference frequency signals. The baseband unit processes the plurality of difference frequency signals filtered by the low pass filter. The baseband unit includes a plurality of MASH type Σ-ΔAD converters, which are used to convert the plurality of difference frequency signals filtered by the low pass filter from analog signals to digital signals respectively. Each of the MASH type Σ-ΔAD converters includes a detection signal generation circuit, a first modulator, an analog filter, a first AD converter, a first adaptive filter, a second adaptive filter and a noise elimination circuit. The detection signal generation circuit generates a detection signal. The first modulator includes a first analog integrator configured with an analog circuit and a first quantizer, the first quantizer being used to quantize an added signal obtained by adding a detection signal to an output signal of the first analog integrator. The analog filter filters an extracted signal obtained by extracting the detection signal and a quantization error generated in the first quantizer. The first AD converter converts the output signal of the analog filter from an analog signal to a digital signal, and the first AD converter operates at an operating frequency lower than the operating frequency of the first modulator. The first adaptive filter searches for a first transfer function by observing the output signal of the first quantizer according to the detection signal, and the first transfer function is a transfer function of the first modulator. The second adaptive filter searches for a second transfer function by observing the output signal of the first AD converter according to the detection signal, and the second transfer function is a transfer function from the output of the first modulator to the first AD converter via the analog filter. The noise elimination circuit uses the search results of the first adaptive filter and the search results of the second adaptive filter to eliminate the quantization error and the detection signal included in the output signal of the first quantizer.

[0009] According to the above-described embodiments, an AD converter device and a millimeter wave radar system capable of performing highly accurate AD conversion can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a schematic diagram illustrating a configuration example of a main part of the millimeter wave radar system according to the first embodiment.

[0011] Figure 2 : is a block diagram illustrating a configuration example of a main part of a MASH type Σ-Δ AD converter device according to the first embodiment.

[0012] Figure 3 It is shown in Figure 2A diagram of a configuration example of an analog integrator unit provided in a MASH type Σ-Δ AD converter device shown in FIG.

[0013] Figure 4 It is shown in Figure 3 0 is a diagram of a first configuration example of an analog integrator provided in an analog integrator unit shown in .

[0014] Figure 5 It is shown in Figure 3 0 is a diagram of a second configuration example of the analog integrator provided in the analog integrator unit shown in .

[0015] Figure 6 It is shown in Figure 3 0 is a diagram of a third configuration example of the analog integrator provided in the analog integrator unit shown in .

[0016] Figure 7 It is shown in Figure 2 A diagram of a configuration example of an analog adder-subtractor provided in a MASH type Σ-Δ AD converter device shown in FIG.

[0017] Figure 8 It is shown in Figure 2 0 is a diagram of a first configuration example of an analog filter provided in a MASH type Σ-Δ AD converter device shown in FIG.

[0018] Fig. 9 It is shown in Figure 2 0 is a diagram of a second configuration example of an analog filter provided in a MASH type Σ-Δ AD converter device shown in FIG.

[0019] Fig.10 It is shown in Figure 2 0 is a diagram of a third configuration example of an analog filter provided in a MASH type Σ-Δ AD converter device shown in FIG.

[0020] Fig.11 It is a graphic Fig.10 The timing diagram of the operation of the analog filter is shown in .

[0021] Fig.12 It is shown in Figure 2 0 is a diagram of a fourth configuration example of an analog filter provided in a MASH type Σ-Δ AD converter device shown in FIG.

[0022] Fig.13 It is a graphic Fig.12 The timing diagram of the operation of the analog filter is shown in .

[0023] Fig.14 It is used to illustrate Figure 2The operation of an adaptive filter is provided in a MASH type Σ-Δ AD converter as shown in the diagram.

[0024] Fig.15 It is used to illustrate Figure 2 FIG. 5 is a diagram of the operation of another adaptive filter provided in a MASH type Σ-Δ AD converter device.

[0025] Fig.16 It is a graphic Figure 2 FIG. 5 is a diagram of a modified example of the MASH type Σ-Δ AD converter device shown in FIG.

[0026] Fig.17 It is shown in Fig.16 FIG. 4 is a diagram of a configuration example of respective capacitive elements including an analog filter provided in a MASH type Σ-Δ AD converter device shown in FIG.

[0027] Fig.18 : is a block diagram illustrating a configuration example of a main part of a MASH type Σ-Δ AD converter device according to the second embodiment.

[0028] Fig.19 It is shown in Fig.18 A diagram of a configuration example of a low-speed AD converter provided in a MASH type Σ-Δ AD converter device shown in FIG.

[0029] Fig. 20 It is a graphic Fig.19 0 is a timing diagram of the operation of the low-speed AD converter shown in .

[0030] Fig.21 It is used to illustrate that Fig.19 The operation of the four successive approximation AD converters of the low-speed AD converter is shown in the diagram.

[0031] Fig. 22 : is a block diagram illustrating a configuration example of a main part of a MASH type Σ-Δ AD converter device according to the third embodiment.

[0032] Fig.23 It is shown in Fig. 22 0 is a diagram of a specific configuration example of a quantizer provided in a sigma-delta modulator of a MASH type sigma-delta AD converter device shown in FIG.

[0033] Fig.24 It is shown as Fig.23 0 is a timing diagram of the operation of the successive approximation AD converter of the quantizer shown in .

[0034] Fig.25 : is a block diagram illustrating a configuration example of a main part of a MASH type Σ-Δ AD converter device according to the fourth embodiment.

[0035] Fig.26 is a block diagram illustrating a configuration example of a MASH type Σ-Δ AD converter device according to a fifth embodiment.

[0036] Fig. 27 is a block diagram illustrating a basic configuration example of a MASH type Σ-Δ AD converter device.

[0037] Fig.28 It is a graphic Fig. 27 An example of a problem in a MASH type Σ-Δ AD converter device is shown in the figure.

[0038] Fig.29 is a block diagram illustrating a configuration example of a main part of a MASH type Σ-Δ AD converter device according to a comparative example. DETAILED DESCRIPTION

[0039] In order to make the description clear, the following description and drawings may be appropriately omitted or simplified. In addition, each element of the functional blocks shown in the drawings as performing various processes may be formed by a CPU (central processing unit), a memory, and other circuits in hardware form, and may be implemented by a program loaded into the memory in software form. Therefore, it will be understood by those skilled in the art that these functional blocks may be implemented in various ways by hardware only, software only, or a combination thereof, without any limitation. Throughout the drawings, the same components are represented by the same reference numerals, and repeated descriptions will be omitted where appropriate.

[0040] Any type of non-transitory computer-readable medium can be used to store the program and provide it to the computer. Non-transitory computer-readable media include any type of tangible storage media. Examples of non-transitory computer-readable media include magnetic storage media (such as floppy disks, magnetic tapes, hard disk drives, etc.), optical magnetic storage media (for example, magneto-optical disks), CD-ROMs (compact disk read-only memory), CD-Rs, CD-R / Ws, and semiconductor memories (such as mask ROMs, PROMs (programmable ROMs), EPROMs (erasable PROMs), flash ROMs, RAMs (random access memories), etc.). Any type of transient computer-readable medium can be used to provide the program to the computer. Examples of transient computer-readable media include electrical signals, optical signals, and electromagnetic waves. Transient computer-readable media can provide the program to the computer via a wired communication line (such as electrical wires and optical fibers) or a wireless communication line.

[0041] First embodiment

[0042] Millimeter wave radar system solution

[0043] Figure 11 is a schematic diagram illustrating a configuration example of a main part of a millimeter wave radar system SYS1 according to the first embodiment. Figure 1 As shown in , the millimeter wave radar system SYS1 includes a baseband unit BBU, a high frequency unit RFU, a low pass filter LPF, a transmitting antenna ANTt, and “n” (n is an integer equal to or greater than 1) receiving antennas ANTr_1 to ANTr_n.

[0044] The high frequency unit RFU is a unit that processes various signals in the high frequency band. The high frequency unit RFU includes a modulator MOD, an oscillator OSC, and a power amplifier PA as a transmitting circuit. The high frequency unit RFU includes "n" mixers MIX_1 to MIX_n and "n" amplifiers IA_1 to IA_n as a receiving circuit.

[0045] The baseband unit BBU includes one semiconductor chip such as a microcontroller and performs various signal processing in the baseband. The baseband unit BBU includes "n" AD converters ADC_1 to ADC_n, a CPU 11, a RAM 12, a DA converter 13, and an NVM (Non-Volatile Memory) 14 such as a flash memory.

[0046] The modulator MOD and the oscillator OSC generate a frequency modulated transmission wave (transmission wave using the FM-CW method) or two transmission waves with different frequencies (transmission wave using the dual frequency CW method) from the baseband signal output from the baseband unit BBU. The transmission wave includes a frequency in the 60 GHz band or the 76 GHz band, and is radiated into the air from the transmission antenna ANTt via the power amplifier PA.

[0047] The transmission wave radiated from the transmission antenna ANTt into the air is reflected by an object and then received by the "n" receiving antennas ANTr_1 to ANTr_n. The "n" mixers MIX_1 to MIX_n respectively down-convert the reception waves (reflected waves) received by the receiving antennas ANTr_1 to ANTr_n using the transmission waves from the oscillator OSC, thereby outputting "n" difference frequency signals. The "n" difference frequency signals are respectively input to the "n" AD converters ADC_1 to ADC_n via the low-pass filter (anti-aliasing filter) LPF.

[0048] In the baseband unit BBU, "n" AD converters ADC_1 to ADC_n each include a MASH type and a Σ-Δ (ΣΔ) type configuration, and convert "n" difference frequency signals from the low-pass filter LPF into digital signals, respectively. The baseband unit BBU processes the digital signals output from the AD converters ADC_1 to ADC_n using a CPU 11 or the like, thereby detecting the distance or relative speed of an object.

[0049] The above-mentioned millimeter wave radar system SYS1 is used not only in fields such as automation and medical equipment, but also in various other fields. Here, the "n" digital-to-analog converters ADC_1 to ADC_n are required to have high resolution (i.e., wide dynamic range) and wide signal frequency band in order to improve the radar performance of the millimeter wave radar system SYS1. A Σ-ΔAD converter (Σ-ΔAD converter device) is known as an AD converter that meets this requirement.

[0050] The Σ-Δ ADC has a higher sampling rate (sampling frequency) on the operating principle of performing oversampling. Therefore, when a Σ-Δ AD converter is adopted for the AD converters ADC_1 to ADC_n provided in the millimeter wave radar system SYS1, the specifications of the low-pass filter (anti-aliasing filter) LPF can be relaxed, and it is more effective than the case of a Nyquist AD converter (e.g., a pipeline type, a continuous comparison type, or a flash memory type). The Σ-Δ AD converter includes a discrete time type (e.g., a switched capacitor type) integrator or a continuous time type (e.g., an RC type) integrator. For example, when the Σ-Δ AD converter includes a continuous time type integrator, the specifications of the low-pass filter LPF can be further relaxed. This can help widen the signal band of the Σ-Δ converter.

[0051] Solutions and Problems of MASH Type Σ-Δ AD Converter Devices

[0052] First, a basic configuration of a MASH type Σ-Δ AD converter device will be described. Fig. 27 is a block diagram illustrating a basic configuration example of a MASH type Σ-Δ AD converter device 50. Fig. 27 As shown in , the MASH type Σ-Δ AD converter 50 converts an external input signal SI (an analog signal input from the outside) into a digital signal, and outputs the digital signal as an external output signal SO.

[0053] The MASH type Σ-Δ AD converter 50 includes multi-stage (two-stage in this case) modulators (Σ-Δ modulators) SDM51 and SDM52 and a noise canceling circuit NCU51 .

[0054] The modulator SDM51 in the first stage includes an analog adder-subtractor AS11 , an analog integrator unit INTU1 , a quantizer QT1 , and DA converter circuits DAC11 and DAC12 .

[0055] The quantizer QT1 quantizes the output signal of the analog integrator unit INTU1 configured with an analog circuit. Both the DA converter circuits DAC11 and DAC12 convert the output signal of the quantizer QT1 into an analog signal. The analog adder-subtractor AS11 outputs a differential signal between the external input signal SI and the output signal of the DA converter circuit DAC11 to the analog integrator unit INTU1. Here, in the quantizer QT1, a quantization error Q1 is generated in the form of being added by the quantizer QT1. The quantization error Q1 can be extracted from the differential signal between the output signal of the DA converter circuit DAC12 and the output signal of the analog integrator unit INTU1.

[0056] The modulator SDM52 in the second stage includes an analog adder-subtractor AS21, an analog integrator unit INTU2, a quantizer QT2, and a DA converter circuit DAC21. The quantizer QT2 quantizes the output signal of the analog integrator unit INTU2 configured with an analog circuit. As in the case of the quantizer QT1, a quantization error Q2 is also generated in the quantizer QT2. The DA converter circuit DAC21 converts the output signal of the quantizer QT2 into an analog signal. The analog adder-subtractor AS21 outputs a differential signal between the extracted signal of the quantization error Q1 generated in the above-mentioned modulator SDM51 and the output signal of the DA converter circuit DAC21 to the analog integrator unit INTU2.

[0057] The noise cancellation circuit NCU 51 includes noise cancellation filters NCF51 and NCF52, and a digital adder-subtractor DAS31. The noise cancellation filter NCF51 is a digital filter to which the output signal S11 of the quantizer QT1 is input. The noise cancellation filter NCF52 is a digital filter to which the output signal S21 of the quantizer QT2 is input. The digital filter may be, for example, a FIR (finite impulse response) filter or an IIR (infinite impulse response) filter for realizing a desired filter characteristic using a plurality of tap coefficients. The digital adder-subtractor DAS31 calculates the difference (in this case, "S12-S22") between the output signal S12 of the noise cancellation filter NCF51 and the output signal S22 of the noise cancellation filter NCF52, and outputs an external output signal SO.

[0058] In the following, the transfer function H 1A (f) is defined as "the transfer function from the point of application of the quantization error Q1 to the output signal S11 of the modulator SDM51 (quantizer QT1). Fig. 27 In the case of 1A (f) is consistent with the noise transfer function (NTF) of modulator SDM51. 2A(f) is defined as "the transfer function from the point of application of the quantization error Q1 to the output signal S21 of the modulator SDM52 (quantizer QT2). Fig. 27 In the case of 2A (f) is consistent with the signal transfer function (STF) of modulator SDM52.

[0059] The output signal S11 of the modulator SDM51 is represented as “H 2A (f)·Q1+STF1·SI". Here, "STF1" is the signal transfer function of the modulator SDM51. The output signal S21 of the modulator SDM52 is represented as "H 2A (f)·Q1+NTF2·Q2". Here, "NTF2" is the noise transfer function of the modulator SDM52.

[0060] Here, the transfer function H of the noise cancellation filter NCF51 is 2D (f) is set in advance as the transfer function H 2A (f) Transfer function H of noise cancellation filter NCF52 1D (f) is set in advance as the transfer function H 1A (f). As a result, the output signal S12 of the noise cancellation filter NCF51 can be expressed as “H 1A (f) H 2A (f) ·Q1+STF1·H 2A (f) · SI". The output signal S22 of the noise cancellation filter NCF52 can be expressed as "H 2A (f) H 1A (f)·Q1+NTF2·H 1A (f)·Q2”.

[0061] As a result, the signal component of the external input signal SI is delayed by "STF1·H 2A (f)" (i.e., the total integrated degree of the delayed analog integrator units INTU1 and INTU2), and then output as the external output signal SO. The quantization error Q1 is eliminated. In addition, the quantization error Q2 is reduced by "NTF2·H" using noise shaping. 1A (f)” (the degree to which the total integral is reduced).

[0062] For example, in Figure 1In the millimeter wave radar system SYS1 shown in FIG, input noise having a high frequency component may be generated. However, when a MASH type Σ-Δ AD converter 50 is adopted for the AD converters ADC_1 to ADC_n provided in the millimeter wave radar system SYS1, even if the external input signal SI includes a high frequency component, the MASH type Σ-Δ AD converter 50 can be stably operated compared to a non-MASH type (single loop type) Σ-Δ AD converter.

[0063] That is, generally, the degree of integrator must be increased to achieve high resolution of the Σ-Δ AD converter. Here, when the fourth degree is implemented in the MASH type Σ-Δ AD converter 50, the analog integrator units INTU1 and INTU2 may include two-stage integrators, respectively. In a non-MASH type AD converter, a four-stage integrator is necessary in a single loop. As a result, if the external input signal SI includes a high frequency component, the processing of the loop operation is prone to instability.

[0064] For example, when a four-stage MASH type Σ-Δ AD converter is used, the quantization error Q2 is sufficiently reduced to a negligible level by noise shaping corresponding to the fourth degree. Therefore, in the MASH type Σ-Δ AD converter 50, as long as the quantization error Q1 can be eliminated, its high resolution can be obtained. However, when the quantization error Q1 is not sufficiently eliminated, the resolution is reduced due to the residual quantization error Q1.

[0065] Fig.28 It is a graphic Fig. 27 An example of a problem in a MASH type Σ-Δ AD converter device is shown in FIG. Fig.28 As shown in , in actual analog integrator units INTU1 and INTU2, various characteristic variations can be generated with reference to a certain ideal state. In the case of a continuous-time type integrator, some factors of characteristic variation include manufacturing variations of RC (resistor, capacitor) elements, insufficient gain of an operational amplifier, and insufficient frequency band.

[0066] Results, such as Fig.28 As shown in FIG. 1 , the “H” in the output signal S11 of the modulator SDM51 1A (f)·Q1” is actually “H 1A_R (f)·Q1". Transfer function H 1A_R (f) is the ideal transfer function H 1A_R (f) is the actual transfer function. Similarly, Fig.28 As shown in FIG. 1 , the “H” in the output signal S21 of the modulator SDM52 2A (f)·Q1” is actually “H 2A_R (f)·Q1". Transfer function H 2A_R (f) is the ideal transfer function H2A On the other hand, the transfer functions H of the noise elimination filters NCF51 and NCF52 are 2D (f) and H 1D (f) are the ideal transfer functions H set in advance. 2A (f) and H 1A (f) As a result, the quantization error Q1 is not sufficiently eliminated. Therefore, the quantization error Q1 remains in the external output signal SO.

[0067] As a solution to this problem, the inventors first studied Fig.29 A MASH type Σ-Δ AD converter 60 shown in FIG. Schemes and problems of MASH type Σ-Δ AD converter device (comparative example)

[0068] Fig.29 is a block diagram illustrating a configuration example of a main portion of a MASH type Σ-Δ AD converter device 60 according to a comparative example.

[0069] Fig.29 The MASH type Σ-Δ AD converter 60 shown in FIG. 5 includes an analog integrator unit INTU1a having variable circuit parameters instead of the analog integrator unit INTU1 provided in the Σ-Δ modulator SDM51, and is connected to the analog integrator unit INTU1a. Fig. 27 Compared with the MASH type Σ-Δ AD converter 50 shown in , the MASH type Σ-Δ AD converter 60 further includes a calibration circuit CAL51. Since the remaining configuration of the MASH type Σ-Δ AD converter 60 is the same as that of the MASH type Σ-Δ AD converter 50, the description thereof is omitted.

[0070] First, as a first solution, adjust the actual transfer function H 1A_R (f) and H 2A_R (f), and make it approximate to the ideal transfer function H 1A (f) and H 2A (f)( Fig.29 Specifically, when the calibration circuit CAL51 observes the residual quantization error Q1 remaining on the external output signal SO in a predetermined calibration period, the calibration circuit CAL51 adjusts and minimizes the circuit parameters (specifically, the time constant of RC) in the analog integrator unit INTU1a. Therefore, the actual transfer function H 1A_R (f) Transfer function H close to the ideal state 1A (f).

[0071] However, in the first solution (method A), since the characteristic change of the operational amplifier in the analog integrator unit INTU1a is not adjusted, the residual quantization error Q1 in the external output signal SO is still not fully eliminated. It is also possible to consider adjusting the circuit parameters of the analog integrator unit INTU2 and the circuit parameters of the analog integrator unit INTU1. However, in this way, when multiple analog integrator units INTU1 and INTU2 are adjusted based on one observation result (residual quantization error Q1 in the external output signal SO), the adjustment process may be undesirably complicated, and the adjustment accuracy may be undesirably reduced. In some cases, it may be difficult to obtain a solution.

[0072] Next, as a second solution, one of the noise removal filters NCF51 and NCF52 (in this case, NCF51) is fixed, and ( Fig.29 Method B) shown in another (NCF52). Specifically, when the calibration circuit CAL51 observes the residual quantization error Q1 in the external output signal SO, for example, in a predetermined calibration period, it adjusts and minimizes the tap coefficients of the noise cancellation filter NCF52.

[0073] However, in the second solution (method B), since only one of the noise elimination filters NCF51 and NCF52 is adjusted, the residual quantization error Q1 remaining in the external output signal SO cannot be fully suppressed. It is also possible to consider adjusting the tap coefficients of both the noise elimination filters NCF51 and NCF52. However, when the noise elimination filters NCF51 and NCF52 are adjusted based on one observation result (the residual quantization error Q1 in the external output signal SO), the adjustment process may be undesirably complicated, and the adjustment accuracy may be undesirably reduced. In some cases, it may be difficult to obtain a solution.

[0074] Therefore, the inventors of the present invention have found the MASH type Σ-Δ AD converter 1 according to the first embodiment, which can perform highly accurate AD conversion by effectively suppressing the residual quantization error Q1 in the external output signal SO.

[0075] Solutions and Problems of MASH Type Σ-Δ AD Converter Device (First Embodiment)

[0076] Figure 2 : is a block diagram illustrating a configuration example of a main part of a MASH type Σ-Δ AD converter device 1 according to the first embodiment.

[0077] like Figure 2As shown in , the MASH type Σ-Δ AD converter 1 includes a modulator (Σ-Δ modulator) SDM1, an analog adder-subtractor AS21, an analog filter FLT1, a low-speed AD converter (first AD converter) LC1, a noise canceling circuit NCU1, and a calibration circuit CAL1.

[0078] The calibration circuit CAL1 includes a detection signal generating circuit XG, a plurality of (in this case, two) adaptive filters AF1 and AF2, and a plurality of (in this case, two) digital adder-subtractors DAS41 and DAS42.

[0079] Similar to the modulator SDM51 , the modulator SDM1 includes an analog adder-subtractor AS11 , an analog integrator unit INTU1 , a quantizer QT1 , and DA converter circuits DAC11 and DAC12 . The modulator SDM1 also includes an analog adder-subtractor AS12 and a DA converter circuit DAC13 .

[0080] The DA converter circuit DAC13 converts the detection signal X generated by the detection signal generating circuit XG (to be described later) into an analog signal and then outputs the analog signal. The analog adder-subtractor AS12 adds the output signal (component of the detection signal X) of the DA converter circuit DAC13 to the output signal of the analog integrator unit INTU1 and outputs the added signal to the quantizer QT1. Since the remaining configuration of the modulator SDM1 is the same as that of the modulator SDM51, its description is omitted.

[0081] The analog adder-subtractor AS21 extracts the components of the detection signal X and the quantization error Q1 generated in the modulator SDM51 by subtracting the output signal of the analog integrator unit INTU1 from the output signal of the modulator SDM1 (the output signal of the DA converter circuit DAC12), and outputs the components of the detection signal X and the quantization error Q1.

[0082] The analog filter FLT1 is a low-pass filter (anti-aliasing filter), and suppresses high-frequency components among frequency components included in the output signal of the analog adder-subtractor AS21, and passes low-frequency components. As a result, the low-speed AD converter LC1 provided at the rear stage of the analog filter FLT1 can suppress aliasing noise even at a lower sampling frequency, compared with a case where the analog filter FLT1 is not used.

[0083] The low-speed AD converter LC1 is a Nyquist-type AD converter, which converts the output signal of the analog filter FLT1 into a digital signal at a sampling frequency fs / M, and outputs the digital signal as an output signal S21. The sampling frequency fs / M is 1 / M (M is an integer greater than 2) of the sampling frequency (clock frequency, operating frequency) fs of the modulator SDM1 in the initial stage.

[0084] Here, the MASH type Σ-Δ AD converter device 1 includes an analog adder-subtractor AS21, an analog filter FLT1, and a low-speed AD converter LC1 instead of the Σ-Δ modulator SDM52, compared with the MASH type Σ-Δ AD converter device 60. As a result, the MASH type Σ-Δ AD converter device 1 does not need to include a high-speed analog integrator unit INTU2, a quantizer QT2, and a DA converter circuit DAC21. Therefore, power consumption can be reduced.

[0085] The detection signal generation circuit XG generates a detection signal X. The detection signal X is, for example, a pseudo-random signal, preferably a 1-bit (binary) pseudo-random signal. The detection signal X is converted into an analog signal by the DA converter circuit DAC13 of the modulator SDM1, and the analog signal is input to the quantizer QT1 via the analog adder-subtractor AS12. The detection signal X is also input to the adaptive filters AF1 and AF2 as a digital signal.

[0086] The adaptive filter AF1 searches for the actual transfer function of the modulator SDM1 by observing the output signal S11 of the modulator SDM1 (quantizer QT1) according to the detection signal X. Specifically, the digital adder-subtractor DAS41 calculates the error between the output signal S13 of the adaptive filter AF1 and the output signal S11 of the modulator SDM1 (quantizer QT1) according to the detection signal X, and outputs the calculation result as the error signal E1. Based on the detection signal X and the error signal E1, the adaptive filter AF1 searches for its own filter coefficient (tap coefficient) using the LMS algorithm.

[0087] Here, the injection point of the detection signal X and the application point of the quantization error Q1 are substantially the same. Therefore, the output signal S11 includes the actual transfer function H by using the quantization error Q1. 1A_R (f) represents the component “H 1A_R (f)·X". On the other hand, the output signal S13 is expressed as "H 1D (f)·X”.

[0088] Strictly speaking, the output signal S11 includes the component of the quantization error Q1 and the component of the external input signal SI, such as Fig. 27However, from the perspective of the input signal to the adaptive filter AF1 via the digital adder-subtractor DAS41, the component of the quantization error Q1 and the component of the external input signal SI can be ignored. The adaptive filter AF1 searches for the tap coefficients to minimize the error between the output signal S11 and the output signal S13. As a result, the transfer function H of the adaptive filter AF1 is 1D (f) Converges to the transfer function H 1A_R (f).

[0089] The adaptive filter AF2 searches for the actual transfer function from the analog adder-subtractor AS21 to the low-speed AD converter LC1 via the analog filter FLT1 by observing the output signal S21 of the low-speed AD converter LC1 according to the detection signal X. Specifically, the digital adder-subtractor DAS42 calculates the error between the output signal S21 of the low-speed AD converter LC1 and the output signal S23 of the adaptive filter AF2 according to the detection signal X, and outputs the calculation result as the error signal E2. Based on the detection signal X and the error signal E2, the adaptive filter AF2 searches for its own filter coefficient (tap coefficient) using the LMS algorithm.

[0090] Here, the injection point of the detection signal X and the application point of the quantization error Q1 are substantially the same. Therefore, the output signal S21 includes the actual transfer function H by using the quantization error Q1. 2A_R (f) represents the component “H 2A_R (f)·X". On the other hand, the output signal S23 is expressed as "H 2D (f)·X”.

[0091] Strictly speaking, the output signal S21 includes a component of the quantization error Q1. However, from the point of view of the input signal to the adaptive filter AF2 via the digital adder-subtractor DAS42, the component of the quantization error Q1 may be negligible. The adaptive filter AF2 searches for tap coefficients to minimize the error between the output signal S21 and the output signal S23. As a result, the transfer function H of the adaptive filter AF2 is 2D (f) Converges to the transfer function H 2A_R (f).

[0092] The noise canceling circuit NCU1 includes noise canceling filters NCF1 and NCF2, and a digital adder-subtractor DAS31. Fig. 27 The digital adder-subtractor DAS31 shown in FIG. 1 has the same configuration, so its description is omitted.

[0093] Similar to Fig. 27The transfer functions of the noise cancellation filters NCF51 and NCF52 shown in FIG. 1 and NCF2 are respectively expressed as H 2D (f) and H 1D (f) Here, the noise cancellation filter NCF1 is configured to be able to adjust the tap coefficients according to the search result of the adaptive filter AF2. Thus, the transfer function H of the noise cancellation filter NCF1 is 2D (f) is adjusted to the transfer function H 2A_R (f) The noise cancellation filter NCF2 is configured to be able to adjust the tap coefficients according to the search result of the adaptive filter AF1. Thus, the transfer function H of the noise cancellation filter NCF2 is 1D (f) is adjusted to the transfer function H 1A_R (f).

[0094] As a result, the quantization error Q1 is eliminated in the external output signal SO. Since the detection signal X is also transmitted through the same path as the quantization error Q1, it is cancelled in the external output signal SO. Fig. 27 As described in , the external output signal SO includes a component of the external input signal SI and a component of the noise shaping quantization error Q2.

[0095] The detection signal X is, for example, a 1-bit digital signal indicating two values ​​such as "+0.1" and "-0.1". If the reference voltage is "Vref", the DA converter circuit DAC13 converts the detection signal X into voltage signals such as "+0.1·Vref" and "-0.1·Vref". The detection signal X can also be injected in parallel (i.e., in the background) with the A / D conversion process of the external input signal SI.

[0096] In this embodiment, the case where adaptive filters AF1 and AF2 and noise elimination filters NCF1 and NCF2 are provided respectively is described as an example, but the present invention is not limited thereto. The adaptive filter AF1 and the noise elimination filter NCF2 may be formed integrally, or the adaptive filter AF2 and the noise elimination filter NCF1 may be formed integrally. That is, the adaptive filter AF1 may be used not only as the original function of the adaptive filter AF1, but also as the noise elimination filter NCF2. The adaptive filter AF2 may be used not only as the original function of the adaptive filter AF2, but also as the noise elimination filter NCF1.

[0097] Details of the analog integrator unit

[0098] Figure 3 is a diagram illustrating a configuration example of an analog integrator unit INTU1 provided in the MASH type Σ-Δ AD converter 1 .

[0099] like Figure 3 As shown in , the analog integrator unit INTU1 includes, for example, two (ie, two-stage) analog integrators AINT1 and AINT2, analog adder-subtractors ASi1 and ASi2, a DA converter circuit DACi, and amplifier circuits AMP11, AMP12, and AMP21.

[0100] The analog integrator AINT1 integrates the calculation result of the analog adder-subtractor AS11 and outputs the result signal. The DA converter circuit DACi converts the output signal S11 of the quantizer QT1 into an analog signal and outputs the result signal. The analog adder-subtractor ASi1 adds a signal obtained by multiplying the output signal of the analog integrator AINT1 by a predetermined coefficient α1 using the amplifier circuit AMP11 and a signal obtained by multiplying the output signal of the DA converter circuit DACi by a predetermined coefficient β1 using the amplifier circuit AMP21, and outputs the result signal.

[0101] The analog integrator AINT2 integrates the calculation result of the analog adder-subtractor ASi1 and outputs the result signal. The analog adder-subtractor ASi2 adds the output signal of the analog integrator AINT2 to the signal obtained by multiplying the output signal of the analog integrator AINT1 by a predetermined coefficient α2 using the amplifier AMP12, and outputs the result signal. The analog integrator unit INTU1 outputs the output signal of the analog adder-subtractor ASi2 as the output signal of the analog integrator unit INTU1.

[0102] The analog integrator unit INTU1 may further include an amplifier circuit AMP13. In this case, the analog adder-subtractor ASi2 adds a signal obtained by multiplying the output signal of the analog integrator AINT1 by a predetermined coefficient α2 using the amplifier circuit AMP12, the output signal of the analog integrator AINT2, and a signal obtained by multiplying the external input signal SI by a predetermined coefficient α3 using, for example, the amplifier circuit AMP13, and outputs the resulting signal.

[0103] Various configurations of the analog integrator unit INTU1 are known, and the configuration of INTU1 is not limited to the above configuration, and the configuration of INTU1 can be appropriately changed to various configurations having equivalent functions. The degree of the analog integrator unit INTU1 can also be appropriately changed.

[0104] First configuration example of analog integrator cell

[0105] Figure 4 It is shown in Figure 3A diagram of a first configuration example of analog integrator AINT1 as analog integrator AINT1a is provided in analog integrator unit INTU1 shown in FIG. Since the configuration of analog integrator AINT2 is the same as that of analog integrator AINT1, a description thereof is omitted.

[0106] like Figure 4 As shown in , the analog integrator AINT1a is an RC type integrator (which is a type of continuous time integrator) and includes a resistor element R1a, a capacitor element C1a, and an operational amplifier OPA1a. In this embodiment, the analog integrator AINT1a is a single-ended type, but the present invention is not limited thereto and may be a differential amplification type.

[0107] In the analog integrator AINT1a, the input signal (for convenience, referred to as Vi) is converted into a current by the resistor element R1a, and the charge of the current is accumulated in the capacitor element C1a. As a result, the integration result of the input signal Vi is obtained as the output signal of the analog integrator AINT1a (for convenience, referred to as Vo).

[0108] If the gain and bandwidth of the operational amplifier OPA1a are both infinite, the analog integrator AINT1a is an ideal integrator. However, the gain and bandwidth of the operational amplifier OPA1a are actually finite. In reality, the values ​​of the resistor element R1a and the capacitor element C1a are also different from the ideal values ​​due to manufacturing variations, etc. Therefore, the actual transfer function H 1A_R (f) and H 2A_R (f) and the transfer function H under ideal conditions 1A (f) and H 2A (f) Different.

[0109] Therefore, the MASH type Σ-Δ AD converter device 1 searches for an actual transfer function H including the influence of the finite gain and finite bandwidth of the operational amplifier OPA1a. 1A_R (f) and H 2A_R (f), and the transfer functions H of the noise elimination filters NCF2 and NCF1 are 2D (f) and H 1D (f) converge to the transfer function H 1A_R (f) and H 2A_R (f). As a result, the MASH type Σ-Δ AD converter device 1 can effectively suppress the residual quantization error Q1 in the external output signal SO. Therefore, the MASH type Σ-Δ AD converter device 1 is capable of performing high-accuracy AD conversion. In addition, since the requirements on the performance of the operational amplifier OPA1a are relaxed, the operating current can be reduced.

[0110] Second Configuration Example of Analog Integrator Cell

[0111] Figure 5 It is shown in Figure 3 A diagram of a second configuration example of analog integrator AINT1 as analog integrator AINT1b is provided in analog integrator unit INTU1 shown in FIG. Since the configuration of analog integrator AINT2 is the same as that of analog integrator AINT1, a description thereof is omitted.

[0112] like Figure 5 As shown in , the analog integrator AINT1b is a current amplifier type integrator (which is a type of continuous time type integrator), and includes a current amplifier (gm amplifier) ​​OTA1b and a capacitive element C1b. In this embodiment, the analog integrator AINT1b is a single-ended type, but the present invention is not limited thereto, and may be a differential amplification type.

[0113] In the analog integrator AINT1b, the input signal (for convenience, referred to as Vi) is converted into a current based on the transconductance gm of the current amplifier OTA1b, and the charge of the current is accumulated in the capacitive element C1b. As a result, the integration result of the input signal Vi is obtained as the output signal of the analog integrator AINT1b (for convenience, referred to as Vo). Generally, compared with the RC type integrator, the current amplifier type integrator is inferior in linearity, but can reduce current consumption.

[0114] If the output resistance of the current amplifier OTA1b is infinite, the output resistance of the analog integrator AINT1b is that of an ideal integrator. However, the output resistance of the current amplifier OTA1b is actually finite. Moreover, due to manufacturing variations, etc., the values ​​of the capacitive element C1b and the transconductance gm actually vary from the ideal values. Therefore, the actual transfer function H 1A_R (f) and H 2A_R (f) and the transfer function H under ideal conditions 1A (f) and H 2A (f) Different.

[0115] Therefore, the MASH type Σ-Δ AD converter device 1 searches for the actual transfer function H including the influence of the finite output resistance of the current amplifier OTA1b. 1A_R (f) and H 2A_R (f), and the transfer functions H of the noise elimination filters NCF2 and NCF1 are 2D (f) and H 1D (f) converge to the transfer function H 1A_R (f) and H 2A_R(f). As a result, the MASH type Σ-Δ AD converter device 1 can effectively suppress the residual quantization error Q1 in the external output signal SO. Therefore, the MASH type Σ-Δ AD converter device 1 can perform high-accuracy AD conversion. In addition, since the requirements on the performance of the current amplifier OTA1b are relaxed, the operating current can be reduced.

[0116] Third Configuration Example of Analog Integrator Cell

[0117] Figure 6 It is shown in Figure 3 A diagram of a third configuration example of analog integrator AINT1 as analog integrator AINT1c is provided in analog integrator unit INTU1 shown in FIG. Since the configuration of analog integrator AINT2 is the same as that of analog integrator AINT1, a description thereof is omitted.

[0118] like Figure 6 As shown in , analog integrator AINT1c is a discrete time type integrator and includes switches SW1c to SW4c, capacitance elements C1c and C2c, and operational amplifier OPA1c. In this embodiment, analog integrator AINT1c is a single-ended type, but the present invention is not limited thereto and may be a differential amplification type.

[0119] Switches SW1c and SW2c are clocked by the sampling clock. Switches SW3c and SW4c are switched on and off by The sampling clock is obtained by inverting to switch on and off.

[0120] In the analog integrator AINT1c, when the switches SW1c and SW2c are turned on and the switches SW3c and SW4c are turned off, the input signal (for convenience, referred to as Vi) is sampled by the capacitive element C1c. When the switches SW1c and SW2c are turned on and the switches SW3c and SW4c are turned off, the signal sampled by the capacitive element C1 is transferred to the capacitive element C2c. As a result, the integration result of the input signal Vi is obtained as the output signal (for convenience, referred to as Vo) of the analog integrator AINT1c.

[0121] If the gain of the operational amplifier OPA1c is infinite and if the over-response to the output signal Vo converges in each sampling period, the analog integrator AINT1c is an ideal integrator. Regarding the convergence of the over-response to the output signal Vo in each sampling period, this can be ensured by controlling sufficient current to flow through, for example, the operational amplifier OPA1c. However, the gain of the operational amplifier OPA1c is actually limited. Therefore, the actual transfer function H 1A_R (f) and H 2A_R(f) and the transfer function H under ideal conditions 1A (f) and H 2A (f) Different.

[0122] Therefore, the MASH type Σ-Δ AD converter device 1 searches for the actual transfer function H including the influence of the finite gain of the operational amplifier OPA1c. 1A_R (f) and H 2A_R (f), and the transfer functions H of the noise elimination filters NCF2 and NCF1 are 2D (f) and H 1D (f) converge to the transfer function H 1A_R (f) and H 2A_R (f). As a result, the MASH type Σ-Δ AD converter device 1 can effectively suppress the residual quantization error Q1 in the external output signal SO. Therefore, the MASH type Σ-Δ AD converter device 1 is capable of performing highly accurate AD conversion. In addition, since the requirements on the performance of the operational amplifier OPA1c are relaxed, the operating current can be reduced.

[0123] The adaptive filters AF1 and AF2 provided in the MASH type Σ-Δ AD converter device 1 search for the transfer function H based on the “z” function, respectively. 1A_R (f) and H 2A_R (f). Here, when the analog integrator unit INTU1 is composed of Figure 6 When the discrete-time integrator configuration is shown in 1A_R (f) and H 2A_R (f) Based on the “z” function definition. Then, the adaptive filters AF1 and AF2 can accurately search the transfer function H by themselves. 1A_R (f) and H 2A_R (f).

[0124] On the other hand, when the analog integrator unit INTU1 includes Figure 4 and Figure 5 For the continuous-time integrator shown in 1A_R (f) and H 2A_R (f) is strictly defined based on the Laplace function ("s" function). In this case, the adaptive filters AF1 and AF2 will be represented by the transfer function H of the Laplace function. 1A_R (f) and H 2A_R (f) Convert to a "z" function and search.

[0125] Analog adder-subtractor details

[0126] Figure 7 It is shown in Figure 2The configurations of the analog adder-subtractors AS12 and AS21 are the same as that of the analog adder-subtractor AS11, so description thereof is omitted.

[0127] like Figure 7 As shown in FIG. 1 , the analog adder-subtractor AS11 includes input resistors R1d and R2d, a feedback resistor R3d, and an operational amplifier OPA1d. Two input signals (referred to as Vi1 and Vi2 for convenience) are converted into currents by the input resistors R1d and R2d, respectively, and their total current is converted into a voltage by the feedback resistor R1c. As a result, the addition result of the input signals Vi1 and Vi2 is obtained as the output signal (referred to as Vo for convenience) of the analog adder-subtractor AS11.

[0128] In this embodiment, the analog adder-subtractor AS11 is a single-ended type, but the present invention is not limited thereto, and the analog adder-subtractor AS11 may be a differential amplifier type. An input signal of inverted polarity (e.g., "-Vi2") is also input to the analog adder-subtractor AS11. Thus, the analog adder-subtractor AS11 can perform subtraction using an input signal of inverted polarity.

[0129] If the gain and bandwidth of the operational amplifier OPA1d are both infinite, the analog adder-subtractor AS11 is an ideal adder-subtractor. At this time, the output signal Vo is expressed by equation (1).

[0130] Vo=-(R3d / R1d)·Vi1-(R3d / R2d)·Vi2 (1)

[0131] As can be seen from equation (1), the respective added weights of the input signals Vi1 and Vi2 are set by the respective resistances of the input resistor signals R1d and R2d.

[0132] However, the gain and bandwidth of the actual operational amplifier OPA1d are limited. Therefore, even with the influence of the analog adder-subtractor AS11, the actual transfer function H 1A_R (f) and H 2A_R (f) may also be related to the ideal transfer function H 1A (f) and H 2A (f) Different.

[0133] Therefore, the MASH type Σ-Δ AD converter device 1 searches for the actual transfer function H including the influence of the finite gain and finite bandwidth of the analog adder-subtractor AS11. 1A_R (f) and H 2A_R(f), and the transfer functions H of the noise elimination filters NCF2 and NCF1 are 2D (f) and H 1D (f) converge to the transfer function H 1A_R (f) and H 2A_R (f) As a result, the MASH type Σ-Δ AD converter device 1 can effectively suppress the residual quantization error Q1 in the external output signal SO. Therefore, the MASH type Σ-Δ AD converter device 1 can perform highly accurate AD conversion.

[0134] In the analog adder-subtractor AS11, the feedback resistor R3d can be replaced with a feedback capacitor. Then, all the analog adders-subtractors AS11, AS12 and AS21 provided in the MASH type Σ-Δ AD converter device 1, and the analog integrator unit INTU1 can be configured using the same type of operational amplifier with feedback capacitance.

[0135] Alternatively, the analog adder-subtractor AS11 may be configured as a passive adder-subtractor using a resistance element and a capacitance element instead of the operational amplifier OPAId. However, in this case, since the gain is less than 1, a circuit for compensating the gain is separately required. In addition, the analog adder-subtractor AS11 may be configured as a discrete time type adder-subtractor using a switched capacitor.

[0136] Analog filter details

[0137] Next, the analog filter FLT1 will be described in detail.

[0138] First specific configuration example of analog filter

[0139] Figure 8 is a diagram illustrating a first specific configuration example of the analog filter FLT1 as the analog filter FLT1a.

[0140] like Figure 8 As shown in , the analog filter FLT1a is an operational amplifier feedback type active filter (which is a type of continuous time type filter), and includes resistor elements R1f to R3f, capacitor elements C1f and C2f, and an operational amplifier OPA1f. In this embodiment, the analog filter FLT1a is described as a single-ended type, but the present invention is not limited thereto, and may be a differential amplification type.

[0141] The resistor element R1f is formed between the input terminal to which the input signal (for convenience, referred to as Vi) is provided and the node N1f. The resistor element R2f is formed between the node N1f and the inverting input terminal of the operational amplifier OPA1f. The capacitor element C1f is formed between the node N1f and the ground voltage terminal GND. The resistor element R3f is formed between the output terminal of the operational amplifier OPA1f and the node N1f. The capacitor element C2f is formed between the output terminal and the inverting input terminal of the operational amplifier OPA1f. The non-inverting input terminal of the operational amplifier OPA1f is connected to the ground voltage terminal GND. As a result, the filtering result of the input signal Vi is obtained as the output signal (for convenience, referred to as Vo) of the analog filter FLT1.

[0142] The gain and bandwidth of the operational amplifier OPA1f are actually limited. Due to manufacturing variations, etc., the values ​​of the resistor elements R1f to R3f and the values ​​of the capacitor elements C1f and C2f are actually different from the ideal values. Therefore, the actual transfer function H 2A_R (f) and the transfer function H under ideal conditions 2A (f) Different.

[0143] Therefore, the MASH type Σ-Δ AD converter 1 searches for the actual transfer function H including the influence of the finite gain and finite bandwidth of the operational amplifier OPA1f. 1A_R (f) and H 2A_R (f), and the transfer functions H of the noise elimination filters NCF2 and NCF1 are 2D (f) and H 1D (f) converge to the transfer function H 1A_R (f) and H 2A_R (f). As a result, the MASH type Σ-Δ AD converter device 1 can effectively suppress the residual quantization error Q1 in the external output signal SO. Therefore, the MASH type Σ-Δ AD converter device 1 is capable of performing high-accuracy AD conversion. In addition, since the requirements on the performance of the operational amplifier OPA1f are relaxed, the operating current can be reduced.

[0144] The analog filter FLT1a is not limited to the above-described configuration, and may be appropriately changed to another configuration capable of achieving the same function.

[0145] Second specific configuration example of analog filter

[0146] Fig. 9 is a diagram illustrating a second specific configuration example of the analog filter FLT1 as the analog filter FLT1b.

[0147] like Fig. 9As shown in , the analog filter FLT1b is a Gm-C filter which is one of continuous time type filters, and includes differential amplifier type current amplifiers (gm amplifiers) OTA1g to OTA4g, and capacitive elements C1g to C4g.

[0148] The current amplifier OTA4g converts two input signals (for convenience, referred to as Vip and Vin) into currents based on the transconductance gm4 of the current amplifier OTA4g. The current amplifier OTA1g converts the differential output signal of the current amplifier OTA2g into currents based on the transconductance gm1 of the current amplifier OTA1g. The charges of the inverted output signals of the current amplifiers OTA4g and OTA1g are accumulated in the capacitive element C1g. The charges of the corresponding non-inverted output signals of the current amplifiers OTA4g and OTA1g are accumulated in the capacitive element C2g.

[0149] The current amplifier OTA2g converts the voltage corresponding to the charge accumulated in the capacitor C1g and the voltage corresponding to the charge accumulated in the capacitor C2g into a current based on the transconductance gm2 of the current amplifier OTA2g. The current amplifier OTA3g converts the voltage corresponding to the charge accumulated in the capacitor C3g and the voltage corresponding to the charge accumulated in the capacitor C4g into a current based on the transconductance gm3 of the current amplifier OTA3g. The charge of the corresponding inverted outputs of the current amplifiers OTA2g and OTA3g is accumulated in the capacitor C3g. The charge of each non-inverted output signal of the current amplifiers OTA2g and OTA3g is accumulated in the capacitor C4g. As a result, the filtering results of the input signals Vip and Vin are obtained as the output signals (for convenience, referred to as Vop and Von) of the analog filter FLT1b.

[0150] The output resistance of the current amplifiers OTA1g to OTA4g is actually finite. Moreover, due to manufacturing variations, etc., the values ​​of the capacitive elements C1g to C4g and the values ​​of the transconductances gm1 to gm4 actually vary from the ideal values. Therefore, the actual transfer function H 2A_R (f) and the transfer function H under ideal conditions 2A (f) Different.

[0151] Therefore, the MASH type Σ-Δ AD converter device 1 searches for an actual transfer function H including the influence of the finite output resistance of the current amplifiers OTA1g to OTA4g. 1A_R (f) and H 2A_R (f), and the transfer functions H of the noise elimination filters NCF2 and NCF1 are 2D (f) and H 1D (f) converge to the transfer function H 1A_R (f) and H 2A_R(f). As a result, the MASH type Σ-Δ AD converter device 1 can effectively suppress the residual quantization error Q1 in the external output signal SO. Therefore, the MASH type Σ-Δ AD converter device 1 can perform high-accuracy AD conversion. In addition, since the requirements for the performance of the current amplifiers OTA1g to OTA4g are relaxed, the operating current can be reduced.

[0152] The analog filter FLT1b is not limited to the above-described configuration, and may be appropriately changed to another configuration capable of achieving the same function.

[0153] Third specific configuration example of analog filter

[0154] Fig.10 is a diagram illustrating a third specific configuration example of the analog filter FLT1 as the analog filter FLT1c. Fig.11 is a timing diagram illustrating the operation of the analog filter FLT1c.

[0155] like Fig.10 As shown in , the analog filter FLT1c is a discrete time type filter and includes switches SW1h_1 to SW1h_7, switches SW2h_1 to SW2h_7, switches SW1i_1 to SW1i_7, switches SW2i_1 to SW2i_7, switches SW3h and SW3i, capacitance elements C1h to C7h, capacitance elements C1i to C7i, and capacitance element C8h. Fig.10 , the ratio of the capacitance values ​​of the capacitance elements C1h to C7h is 1:2:3:4:3:2:1. The ratio of the capacitance values ​​of the capacitance elements C1i to C7i is 1:2:3:4:3:2:1.

[0156] Here, in Fig.10 In the embodiment of the present invention, two filters are arranged in parallel to achieve effective filtering. The first filter includes switches SW1h_1 to SW1h_7, switches SW2h_1 to SW2h_7, switches SW3h, capacitive elements C1h to C7h, and capacitive element C8h. The second filter includes switches SW1i_1 to SW1i_7, switches SW2i_1 to SW2i_7, switches SW3i, capacitive elements C1i to C7i, and capacitive element C8h. Capacitive element C8h is shared by the first filter and the second filter.

[0157] First, filtering according to the first filter is performed. Specifically, in the first filter, the control signal to are sequentially and temporarily set to the H level, and the switches SW1h_1 to SW1h_7 are sequentially and temporarily turned on, whereby the charge of the input signal (referred to as Vi for convenience) is sequentially accumulated in the capacitive elements C1h to C7h (time t11 to t13). Thereafter, the control signal is temporarily set to H level, and then the switches SW2h_1 to SW2h_7 are turned on simultaneously, whereby voltage signals corresponding to the charges accumulated in the capacitive elements C1h to C7h are output simultaneously (time t14). is temporarily set to H level, and thus switch SW3h is turned on. Therefore, the charge of these voltage signals is accumulated in capacitor C8h (time t14). Thereafter, the voltage output (time t15 to t17) corresponding to the charge accumulated in capacitor C8h is used as the output signal (for convenience, referred to as Vo) of analog filter FLT1c.

[0158] Next, in the second filter, filtering starts after M (here, 4) clock cycles have passed since the start of filtering by the first filter (time t12).

[0159] Specifically, in the second filter, the control signal from the first filter After M (= 4) clock cycles from the start of the rise, the control signal to are sequentially and temporarily set to the H level, and then the switches SW1i_1 to SW1i_7 are sequentially and temporarily turned on, whereby the charge of the input signal Vi is sequentially accumulated in the capacitive elements C1i to C7i (time t12 to t16). Thereafter, the control signal is temporarily set to H level, and the switches SW2i_1 to SW2i_7 are turned on simultaneously, whereby voltage signals corresponding to the charges accumulated in the capacitive elements C1i to C7i are simultaneously output (time t17). The switch SW3i is temporarily set to the H level and turned on, so the charges of these voltage signals are accumulated in the capacitor C8h (time t17). Thereafter, the voltage corresponding to the charge accumulated in the capacitor C8h is output (time t18 to t19) as the output signal Vo of the analog filter FLT1c.

[0160] In the first filter, after M (=4) clock cycles from the start of filtering by the second filter (i.e., from the control signal of the second filter After M (=4) clock cycles from the start of the rise of fs), since the sampling operation has been completed, the subsequent filtering will begin. In the first filter and the second filter, this operation is repeated. Therefore, the filtering result of the analog filter FLT1c is output at a frequency (fs / M) of 1 / M of the clock frequency fs.

[0161] exist Fig.10 In , the number of taps of each filter is 7, but the number of taps is not limited to this. The number of taps of each filter can be set arbitrarily. Fig.10 In the embodiment, two filters are arranged in parallel, but the present invention is not limited thereto. It can be appropriately changed to a configuration in which any number of filters are arranged in parallel. Fig.10 In the above description, the case of M (=4) has been described, but the present invention is not limited thereto. The value of M can be arbitrarily set according to the number of taps of each filter, the number of filters, and the like.

[0162] Since the analog filter FLT1c does not include an amplifier, the operating current can be reduced.

[0163] Fourth specific configuration example of analog filter

[0164] Fig.12 is a diagram illustrating a fourth specific configuration example of the analog filter FLT1 as the analog filter FLT1d. Fig.13 is a timing diagram illustrating the operation of the analog filter FLT1d.

[0165] exist Fig.10 In the analog filter FLT1c shown in FIG. 1 , two filters share the capacitive element C8h. On the other hand, in Fig.12 In the analog filter FLT1d shown in FIG. 1 , each of the two filters has separate capacitive elements C8h and C8i. Since the remaining configuration of the analog filter FLT1d is the same as that of the analog filter FLT1c, the description thereof is omitted.

[0166] basically, Fig.12 The first filter shown in performs a process similar to that of the analog filter FLT1c. Here, when the switch SW3h is turned on, the charge of the voltage signal corresponding to the charge accumulated in the capacitor elements C1h to C7h is accumulated in the capacitor element C8h (time t14). Thereafter, the voltage corresponding to the charge accumulated in the capacitor element C8h is output (time t15 to t19) as the output signal (for convenience, referred to as Vo1) of the analog filter FLT1d.

[0167] Next, in Fig.12In the second filter shown in , filtering starts (time t12) after M (here, 4) clock cycles have passed since filtering started by the first filter.

[0168] basically, Fig.12 The second filter shown in performs a process similar to that of the analog filter FLT1c. Here, when the switch SW3i is turned on, the charge of the voltage signal corresponding to the charge accumulated in the capacitor elements C1i to C7i is accumulated in the capacitor element C8i (time t17). Thereafter, the voltage corresponding to the charge accumulated in the capacitor element C8i is output (time t18 to t20) as the output signal of the analog filter FLT1d (for convenience, referred to as Vo2).

[0169] In the first filter, after M (=4) clock cycles from the start of filtering by the second filter (i.e., from the control signal of the second filter After M (=4) clock cycles from the start of the rise of fs), since the sampling operation has been completed, the subsequent filtering will start. In the first and second filters, this operation is repeated. Therefore, the filtering result of the analog filter FLT1c is output at a frequency (fs / M) of 1 / M of the clock frequency fs.

[0170] Since the analog filter FLT1d does not include an amplifier, the operating current can be reduced. In addition, in the analog filter FLT1d, since the first filter and the second filter have separate capacitive elements C8h and C8i, respectively, the holding time of each sampling result becomes longer compared with the holding time when the capacitive element C8h is shared. As a result, the low-speed AD converter LC1 of the rear stage can spend a sufficiently long AD conversion period. Here, the low-speed AD converter LC1 is configured to be able to perform AD conversion on the corresponding voltages of the capacitive elements C8h and C8i in parallel.

[0171] Adaptive filter details

[0172] Fig.14 and Fig.15 1 and 2 are diagrams for explaining the operations of adaptive filters AF1 and AF2 respectively provided in the MASH type Σ-Δ AD converter device 1 .

[0173] like Fig.14 As shown in , the adaptive filter AF1 uses the LMS algorithm to search its filter coefficients (tap coefficients) so that the error signal E1 is close to zero. The error signal E1 represents the error between the output signal S11 of the modulator SDM1 (quantizer QT1) according to the detection signal X and its own output signal S13.

[0174] More specifically, the output signal S11 of the modulator SDM1 according to the detection signal X is represented as “H 1A_R (f)·X". Here, the transfer function H 1A_R (f) can be expressed as "a0z -0 +a1z -1 +a2z -2 +a3z -3 On the other hand, the output signal S13 of the adaptive filter AF1 is represented as “H 1D (f)·X". Here, the transfer function H 1D (f) is defined as “a0 (D) z -0 +a1 (D) z -1 +a2 (D) z -2 +a3 (D) z -3 Therefore, the adaptive filter AF1 searches for the condition that satisfies "a0=a0 (D) ”, “a1=a1 (D) ”, “a2=a2 (D) ”, “a3=a3 (D) "a0 (D) ”, “a1 (D) ”, “a2 (D) " and "a3 (D) ”.

[0175] like Fig.15 As shown in , the adaptive filter AF2 uses the LMS algorithm to search for its own tap coefficients so that the error signal E2 approaches zero, and the error signal E2 represents the error between the output signal S21 of the low-speed AD converter LC1 according to the detection signal X and its own output signal S23.

[0176] More specifically, the output signal S21 of the low-speed AD converter LC1 according to the detection signal X is represented as “H 2A_R (f)·X". Here, the transfer function H 2A_R (f) can be expressed as “b0z -0 +b1z -1 +b2z -2 +b3z -3 On the other hand, the output signal S23 of the adaptive filter AF2 is represented as “H 2D (f)·X". Here, the transfer function H 2D (f) is defined as “b0 (D) z -0 +b1 (D) z -1 +b2 (D) z-2 +b3 (D) z -3 Therefore, the adaptive filter AF2 searches for the value that satisfies "b0=b0 (D) ”, “b1=b1 (D) ”, “b2=b2 (D) ”, “b3=b3 (D) "b0 (D) ”, “b1 (D) ”, “b2 (D) ” and “b3 (D) ”.

[0177] Main Effects of MASH Type Σ-Δ AD Converter Device (First Embodiment)

[0178] As described above, the MASH type Σ-Δ AD converter device 1 according to the first embodiment can eliminate the quantization error Q1 generated in the quantizer QT1 by using the calibration circuit CAL1. Therefore, AD conversion with high accuracy can be performed. Fig.29 Unlike the comparative example shown in , the MASH type Σ-Δ AD converter device 1 adjusts the transfer function of the noise elimination filter NCF2 based on the observation result of the output signal of the modulator SDM1, and adjusts the transfer function of the noise elimination filter NCF1 based on the observation result of the output signal of the low-speed AD converter LC1. That is, the MASH type Σ-Δ AD converter device 1 adjusts 1 noise elimination filter based on 1 observation result. Thus, since the adjustment process is simplified, a solution can be easily obtained, and the accuracy of the solution (in other words, the search accuracy of the adaptive filters AF1 and AF2) can be improved.

[0179] The MASH type Σ-Δ AD converter device 1 according to the first embodiment includes an analog adder-subtractor AS21, an analog filter FLT1, and a low-speed AD converter LC1, instead of the Σ-Δ modulator SDM2 in the subsequent stage of the Σ-Δ modulator SDM1 in the initial stage. As a result, the MASH type Σ-Δ AD converter device 1 does not need to include a quantizer QT2, a DA converter circuit DAC21, and an analog integrator unit INTU2 that require high-speed operation. Therefore, power consumption can be reduced.

[0180] In addition, the MASH type Σ-ΔAD converter device 1 according to the first embodiment is not limited to the characteristic changes of the analog integrator, and even in the presence of characteristic changes of various other circuits (for example, characteristic changes of the analog adder-subtractor, characteristic changes due to the reference voltage mismatch between the quantizer and DA converter circuits, etc.), the quantization error Q1 can be eliminated by using the noise elimination filters NCF1 and NCF2.

[0181] In addition, Fig.29 Unlike the comparative example shown in , the MASH type Σ-Δ AD converter device 1 according to the first embodiment can perform the search operation of the adaptive filters AF1 and AF2 in parallel with performing the A / D conversion of the external input signal SI (i.e., in the background). Thus, even when the characteristics of various circuits change due to, for example, changes in the use environment, the quantization error Q1 can be quickly eliminated by using the noise elimination filters NCF1 and NCF2.

[0182] Modification example of MASH type Σ-Δ AD converter device

[0183] Fig.16 is a diagram illustrating a modified example of the MASH type Σ-Δ AD converter device 1 as the MASH type Σ-Δ AD converter 1 e .

[0184] like Fig.16 As shown in FIG. 1 , the MASH type Σ-Δ AD converter device 1e includes an analog filter FLT1e as a modified example of the analog filter FLT1. The analog filter FLT1e is configured to be able to adjust the analog filter according to the actual transfer function H performed by the adaptive filter AF2. 2A_R Since the remaining configuration of the MASH type Σ-Δ AD converter 1e is the same as that of the MASH type Σ-Δ AD converter device 1, its description is omitted.

[0185] Fig.17 1 is a diagram illustrating a configuration example of respective capacitive elements including the analog filter FLT1e. Fig.17 As shown in , each capacitive element provided in the analog filter FLT1e has a plurality of capacitors C5e to C1e having binary weighted capacitance values, and a plurality of switches SW5e to SW1e provided in series with each of the plurality of capacitors C5e to C1e, and is configured to be able to adjust the capacitance value. Here, the capacitance value of the corresponding capacitive element is initially set so as to indicate an intermediate value, and is adjusted according to the search result of the adaptive filter AF2.

[0186] The MASH type Σ-Δ AD converter device 1 e can achieve the same effects as the MASH type Σ-Δ AD converter device 1 , and can suppress an increase in noise and a decrease in a signal band by adjusting the frequency characteristics of the analog filter FLT1 e .

[0187] Second embodiment

[0188] Fig.18: is a block diagram illustrating a configuration example of a main part of a MASH type Σ-Δ AD converter device 2 according to the second embodiment.

[0189] like Fig.18 As shown in , the MASH type Σ-Δ AD converter device 2 includes an analog filter FLT2 and a low-speed AD converter LC2 instead of the analog filter FLT1 and the low-speed AD converter LC1 , compared with the MASH type Σ-Δ AD converter device 1 .

[0190] The low-speed AD converter LC2 is a successive approximation AD converter, and the analog filter FLT2 includes a capacitive element provided in the low-speed AD converter LC2. In other words, the analog filter FLT2 and the low-speed AD converter LC2 share a capacitive element. Fig.18 In FIG. 1 , the low-speed AD converter LC2 includes four successive approximation AD converters arranged in parallel.

[0191] Details of low speed AD converter

[0192] Fig.19 is a diagram illustrating a configuration example of the low-speed AD converter LC2. Fig.19 , one of four successive approximation AD converters and an analog filter corresponding thereto are shown. In this embodiment, although the successive approximation AD converter is a single-ended type, the present invention is not limited thereto and may be a differential amplification type.

[0193] like Fig.19 As shown in, the low-speed AD converter LC2 includes a DA converter 201, a comparator 202, and a comparison control unit 203. The DA converter 201 converts the digital signal continuously output from the comparison control unit 203 into an analog voltage V1a, which ranges from a lower limit value "-Vr" to an upper limit value "+Vr" as a full scale. The DA converter 201 also includes a function as a sample-and-hold circuit for sampling and holding an input voltage (referred to as Vi for convenience). The comparator 202 compares the input voltage Vi held by the sample-and-hold function of the DA converter 201 with the analog voltage V1a generated from the AD conversion performed by the DA converter 201, and outputs a comparison result. The comparison control unit 203 switches the value of the digital signal based on the comparison result of the comparator 202. By repeating this operation, the value of the digital signal corresponding to the analog voltage V1a indicating the value closest to the input voltage Vi is determined. The low-speed AD converter LC2 outputs a digital signal as an output signal S21.

[0194] More specifically, the DA converter 201 includes: a plurality of capacitance elements C1_8 to C1_0 having capacitance values ​​weighted in binary from high to low bits; a dummy capacitance element C1_d having the same capacitance value as the capacitance element C1_0 of the least significant bit; a plurality of switches SW1_8 to SW1_0 and SW1_d provided in series with each of the capacitance elements C1_8 to C1_0 and C1_d; and a switch SW1_b. The switch SW1_b is provided between the ground voltage terminal GND and a node between the comparator 202 and electrodes on one side of the capacitance elements C1_8 to C1_0 and C1_d (electrodes on one side of the comparator 202).

[0195] exist Fig.19 , the capacitance values ​​of the capacitance elements C1_8 to C1_0 and C1_d respectively indicate 256C, 128C, 64C, 32C, 16C, 8C, 4C, 2C, C, and C. That is, the ratio of the capacitance values ​​of the capacitance elements C1_8 to C1_0 and C1_d is 2^8:2^7:2^6:2^5:2^4:2^3:2^2:2^1:2^0:2^0.

[0196] Switches SW1_8 to SW1_0, SW1_d and SW1_b are controlled by the comparison control unit 203 based on the operation mode and the value of the digital signal to be DA converted. For example, switch SW1_8 supplies a voltage "+Vr" or a voltage "-Vr" to the electrode on the other side of the capacitor C1_8 according to the control signal D18, or stops supplying. Switch SW1_7 supplies a voltage "+Vr" or a voltage "-Vr" to the electrode on the other side of the capacitor C1_7 according to the control signal D17, or stops supplying. Switch SW1_6 supplies a voltage "+Vr" or a voltage "-Vr" to the electrode on the other side of the capacitor C1_6 according to the control signal D16, or stops supplying. Switch SW1_5 supplies a voltage "+Vr" or a voltage "-Vr" to the electrode on the other side of the capacitor C1_5 according to the control signal D15, or stops supplying. The switch SW1_4 supplies the voltage “+Vr” or the voltage “-Vr” to the electrode on the other side of the capacitor element C1_4, or stops supplying, according to the control signal D14. The switch SW1_3 supplies the voltage “+Vr” or the voltage “-Vr” to the electrode on the other side of the capacitor element C1_3, or stops supplying, according to the control signal D13. The switch SW1_2 supplies the voltage “+Vr” or the voltage “-Vr” to the electrode on the other side of the capacitor element C1_2, or stops supplying, according to the control signal D12. The switch SW1_1 supplies the voltage “+Vr” or the voltage “-Vr” to the electrode on the other side of the capacitor element C1_1, or stops supplying, according to the control signal D11. The switch SW1_d supplies the voltage “+Vr” or the voltage “-Vr” to the electrode on the other side of the capacitor element C1_d, or stops supplying, according to the control signal D1d. The switch SW1_b is controlled by the control signal Switch on and off.

[0197] exist Fig.19 In FIG. 1 , the capacitance element C1_8 includes three capacitance elements C1_8a to C1_8c arranged in parallel. The capacitance values ​​of the capacitance elements C1_8a to C1_8c are 96C, 96C, and 64C, respectively. The switch SW1_8 includes switches SW1_8a to SW1_8c provided in series with the capacitance elements C1_8a to C1_8c, respectively.

[0198] Here, in Fig.19 In the embodiment of the present invention, the configuration of the analog filter FLT2 is realized by using the capacitive elements C1_8 to C1_0 and C1_d provided in the successive approximation AD converter. Specifically, Fig.10 The capacitive element C1h in is configured by the capacitive element C1_5 having a capacitance value of 32C. Fig.10 The capacitor element C2h in is configured by the capacitor element C1_6 with a capacitance value of 64C. Fig.10The capacitor element C3h in is configured by the capacitor element C1_8c with a capacitance value of 96C. Fig.10 The capacitor element C4h in is configured by the capacitor element C1_7 with a capacitance value of 128C. Fig.10 The capacitor element C5h in is configured by the capacitor element C1_8b with a capacitance value of 96C. Fig.10 The capacitor element C6h in is configured by the capacitor element C1_8a with a capacitance value of 64C. Fig.10 The capacitance element C7h in is configured by the capacitance element C1_x, and the capacitance element C1_x is composed of the capacitance elements C1_4 to C1_0 and C1_d with a total capacitance value of 32C.

[0199] That is, when the supply of the voltages “+Vr” and “−Vr” to the capacitor element C1_5 stops, the switch SW1_5 is switched on according to the control signal To switch whether to provide the input voltage Vi to the capacitor element C1_5. When the voltages "+Vr" and "-Vr" are stopped from being provided to the capacitor element C1_6, the switch SW1_6 is switched according to the control signal To switch whether to provide the input voltage Vi to the capacitor element C1_6. When the voltage "+Vr" and "-Vr" are stopped from being provided to the capacitor element C1_8c, the switch SW1_8c is switched according to the control signal To switch whether to provide the input voltage Vi to the capacitor element C1_8c. When the voltages "+Vr" and "-Vr" are stopped from being provided to the capacitor element C1_7, the switch SW1_7 is switched according to the control signal To switch whether to provide the input voltage Vi to the capacitor element C1_7. When the voltages "+Vr" and "-Vr" are stopped from being provided to the capacitor element C1_8b, the switch SW1_8b is switched according to the control signal To switch whether to provide the input voltage Vi to the capacitor element C1_8b. When the voltage "+Vr" and "-Vr" are stopped from being provided to the capacitor element C1_8a, the switch SW1_8a is switched according to the control signal To switch whether to supply the input voltage Vi to the capacitor C1_8a. When the supply of the voltages "+Vr" and "-Vr" to the capacitor C1_x is stopped, the switches SW1_4 to SW1_0 and SW1_d are switched according to the control signal Whether or not to supply the input voltage Vi to the capacitive element C1_x is switched. Thus, filtering by the analog filter FLT2 can be realized.

[0200] Fig. 20 is a timing chart illustrating the operation of the low-speed AD converter LC2.

[0201] First, in sampling mode, when the control signal When the control signals D18 to D10 and Dd indicate to stop supplying the voltages “+Vr” and “-Vr” to the capacitor elements, the ground level voltage (0V) is supplied to the electrodes on one side of the capacitor elements C1_5, C1_6, C1_8c, C1_7, C1_8b, C1_8a and C1_x (time t21 to t22). Fig. 20 "Shutdown" in the control signal to The input voltage Vi is temporarily set to the H level sequentially, whereby the charge of the input voltage Vi is sequentially accumulated in the electrodes on the other side of the capacitor element electrodes C1_5, C1_6, C1_8c, C1_7, C1_8b, C1_8a and C1_x (time t21 to t22). That is, in the sampling mode, not only the sampling of the input voltage Vi is performed, but also the filtering performed by the analog filter FLT2 is performed at the same time.

[0202] After that, in the hold mode, the control signal The control signal is changed from the H level to the L level, and the switch SW1_b is turned off. Therefore, the electrode on one side of each capacitive element is switched to a floating state. to All are switched from the H level to the L level, thereby stopping the supply of the input voltage Vi to the electrode on the other side of each capacitor element (time t22).

[0203] Thereafter, in the charge redistribution mode, first, the voltage "+Vr" is supplied to the electrode on the other side of the capacitive element C1_8 of the most significant bit, and the voltage "-Vr" is supplied to the electrode on the other side of the remaining capacitive elements C1_7 to C1_0 and C1_d (time t22 to t23). As a result, the voltage -Vi is supplied to the two input terminals of the comparator 202 as a differential voltage. Based on the comparison result of the comparator 202 at this time, the comparison control unit 203 fixes the voltage of the electrode on the other side of the capacitive element C1_8 supplied to the most significant bit to the voltage "+V" or "-Vr" (time t23 to t25). For example, if Vi>0, the value of the most significant bit of the digital signal (output signal S21) output from the comparison control unit 203 is determined to be 1. In this case, the voltage of the electrode on the other side of the capacitive element C1_8 supplied to the most significant bit is fixed to the voltage "+Vr". If Vi<0, the value of the most significant bit of the digital signal output from the comparison control unit 203 is determined to be 0. Here, the voltage supplied to the electrode on the other side of the capacitive element C1_8 of the most significant bit is fixed to the voltage “−Vr”.

[0204] Thereafter, the voltage "+Vr" is supplied to the electrode on the other side of the capacitor C1_7, which is the high bit immediately after the most significant bit, and the voltage "-Vr" is supplied to the electrodes on the other side of the remaining capacitors C1_6 to C1_0 and C1_d (time t23 to t24). As a result, "-Vi+Vr·(value of the most significant bit)-Vr / 2" is supplied to the two input terminals of the comparator 202 as a differential voltage. Based on the comparison result of the comparator 202 at this time, the comparison control unit 203 determines the value of the second most significant bit of the digital signal, and fixes the voltage supplied to the electrode on the other side of the capacitor C1_7 to the voltage "+V" or "-Vr" (time t24 to t25).

[0205] This operation is sequentially repeated up to the least significant capacitance element C1_0, whereby the digital signal (output signal S21) output from the comparison control unit 203 is fixed (time t25).

[0206] In this embodiment, AD converter LC2 includes four successive approximation AD converters arranged in parallel. By using four successive approximation AD converters to perform AD conversion at different timings, AD converter LC2 can perform AD conversion efficiently and with high accuracy. Fig.19 and Fig. 20 In addition, reference will be made to Fig.21 Give a brief description.

[0207] Fig.21 1 is a diagram for explaining the operation of four successive approximation AD converters including AD converter LC2. In this embodiment, AD converter LC2 performs sampling at a sampling frequency fs / M, which is 1 / M of the sampling frequency fs of modulator SDM1 in the initial stage. That is, each of the four successive approximation AD converters including AD converter LC2 performs sampling by moving the time once every M clock cycles. In this case, the AD conversion period assigned to one successive approximation AD converter is "M×the number of successive approximation AD converters (the number of slices)-the number of analog filter taps" clock cycles. In this embodiment, since M=4, the number of slices=4 and the number of taps=7, the AD conversion period assigned to one successive approximation AD converter is 9 (=4×4-7) clock cycles.

[0208] First, in the first successive approximation AD converter, sampling and filtering are performed for a period of 7 clock cycles (CLK), and then AD conversion is performed for a period of 9 clock cycles. In the second successive approximation AD converter, after 4 clock cycles from the first successive approximation AD converter sampling, sampling and filtering are performed for a period of 7 clock cycles, and then AD conversion is performed for a period of 9 clock cycles. In the third successive approximation AD converter, after 4 clock cycles from the second successive approximation AD converter sampling, sampling and filtering are performed for a period of 7 clock cycles, and then AD conversion is performed for a period of 9 clock cycles. In the fourth successive approximation AD converter, after 4 clock cycles from the third successive approximation AD converter sampling, sampling and filtering are performed for a period of 7 clock cycles, and then AD conversion is performed for a period of 9 clock cycles. Here, after 4 clock cycles from the fourth successive approximation AD converter sampling, the AD conversion performed by the first successive approximation AD converter is completed. Therefore, the subsequent sampling and filtering are started by the first successive approximation AD converter. Repeat this operation.

[0209] As described above, the MASH type Σ-Δ AD converter device 2 according to the second embodiment is effective as the MASH type Σ-Δ AD converter device 1. In addition, in the MASH type Σ-Δ AD converter device 2 according to the second embodiment, since the analog filter FLT2 and the low-speed AD converter LC2 share the capacitance element, the increase in the circuit scale can be suppressed, and it is not necessary to provide a buffer between the analog filter FLT2 and the low-speed AD converter LC2. Therefore, the increase in power consumption can be suppressed.

[0210] In this embodiment, the case where M=4, the number of slices=4, and the number of taps=7 is described as an example, but the present invention is not limited to this. The value of M, the number of slices, and the number of taps can be set to any value as long as AD conversion can be performed efficiently and accurately. Each successive approximation AD converter is not limited to the case of generating a digital signal with a 9-bit width, and each successive approximation AD converter can be appropriately changed to generate a digital signal with an arbitrary bit width determined according to the value of M, the number of slices, the number of taps, etc.

[0211] Third embodiment

[0212] Fig. 22 : is a block diagram illustrating a configuration example of a main part of a MASH type Σ-Δ AD converter device 3 according to the third embodiment.

[0213] like Fig. 22As shown in FIG. 1 , compared with the MASH type Σ-Δ AD converter device 1, the MASH type Σ-Δ AD converter device 3 includes a successive approximation AD converter QT1a as a quantizer QT1 provided in the Σ-Δ modulator SDM1, and outputs a voltage signal M11 of a charge holding node N2 of the successive approximation AD converter QT1a to an analog filter FLT1 as an output signal of the Σ-Δ modulator SDM1. The MASH type Σ-Δ AD converter device 3 does not include the DA converter circuits DAC12 and DAC13, and the analog adder-subtractor AS21.

[0214] Details of Successive Approximation AD Converters

[0215] Fig.23 is a diagram illustrating a configuration example of a successive approximation AD converter QT1a. Fig.23 , the function of the analog adder-subtractor AS12 is included in the successive approximation AD converter QT1a. In this embodiment, the successive approximation AD converter QT1a is a single-ended type, but the present invention is not limited thereto, and may be a differential amplification type.

[0216] like Fig.23 As shown in , the successive approximation AD converter QT1a includes a DA converter 301, a comparator 302, and a comparison control unit 303. The DA converter 301 converts the digital signals sequentially output from the comparison control unit 303 into an analog voltage V2a, which ranges from a lower limit value "-Vr" to an upper limit value "+Vr" as a full scale. The DA converter 301 also includes a function of serving as a sample-and-hold circuit for sampling and holding an input voltage (referred to as Vi for convenience). The comparator 302 compares the input voltage Vi held by the sample-and-hold function of the DA converter 301 with the analog voltage V2a generated from the AD conversion performed by the DA converter 301, and outputs a comparison result. The comparison control unit 303 switches the value of the digital signal based on the comparison result of the comparator 302. By repeating this operation, the value of the digital signal corresponding to the analog voltage V2a indicating the value closest to the input voltage Vi is determined. The successive approximation AD converter QT1a outputs the digital signal as an output signal S11.

[0217] Specifically, the DA converter 301 includes: three capacitance elements C2_2 to C2_0, which have capacitance values ​​weighted in binary from high to low; a capacitance element C2_d, which has the same capacitance value as the capacitance element C2_0 of the least significant bit; a capacitance element C2_3, which has a capacitance value 8αC obtained by multiplying the coefficient α by the capacitance value 8C, and the capacitance value 8C is 2 times the capacitance value of the capacitance element C2_2 of the most significant bit; and a plurality of switches SW2_3 to SW2_0 and SW2_d, which are provided in series with each of the capacitance elements C2_3 to C2_0 and C2_d, respectively. The switch SW2_b is provided between the ground terminal GND and a node between the electrodes on one side of the capacitance elements C2_3 to C2_0 and C2_d (the electrodes on one side of the charge holding node N2) and the comparator 302.

[0218] The switches SW2_2 to SW2_0 and SW2_d are controlled by the comparison control unit 303 based on the operation mode and the value of the digital signal to be DA-converted. For example, the switch SW2_2 is controlled based on the control signal D22 and the control signal D2_0. Selects one of the voltages "+Vr", "-Vr" and Vi, and supplies the selected voltage to the electrode on the other side of the capacitive element C2_2. The switch SW2_1 is connected to the capacitor C2_2 according to the control signal D21 and the control signal One of the voltages "+Vr", "-Vr" and Vi is selected and the selected voltage is supplied to the electrode on the other side of the capacitive element C2_1. The switch SW2_0 is switched according to the control signal D20 and the control signal One of the voltages "+Vr", "-Vr" and Vi is selected and the selected voltage is supplied to the electrode on the other side of the capacitive element C2_0. The switch SW2_d is switched according to the control signal D2d and the control signal One of the voltages "+Vr", "-Vr" and Vi is selected and the selected voltage is supplied to the electrode on the other side of the capacitive element C2_d. The switch SW2_b is controlled by the control signal Switch on and off.

[0219] The switch SW2_3 is controlled by a control signal indicating a value corresponding to the detection signal X. For example, when the detection signal X indicates "+1", the switch SW2_3 supplies the voltage "+Vr" to the electrode on the other side of the capacitive element C2_3. When the detection signal X indicates "-1", the switch SW2_3 supplies the voltage "-Vr" to the electrode on the other side of the capacitive element C2_3.

[0220] Fig.24 is a timing chart illustrating the operation of successive approximation AD converter QT1a.

[0221] First, in sampling mode, when the control signal When the control signals D22 to D20 and D2d indicate to stop supplying the voltages “+Vr” and “-Vr” to the electrodes on the other side of the capacitive elements C2_2 to C2_0 and C2_d (time t31 to t32), the ground level voltage (0V) is supplied to one of the electrodes on the other side of the capacitive elements C2_3 to C2_0 and C2_d (time t31 to t32). Fig.24 "Shutdown" in the control signal Set to H level, whereby the input voltage Vi is supplied to the electrode on the other side of the capacitive elements C2_2 to C2_0 and C2_d (time t31 to t32). At this time, the voltage "+Vr" or "-Vr" according to the detection signal X is supplied to the electrode on the other side of the capacitive element C2_3 (time t31 to t32). That is, the component of the detection signal X is added to the input voltage Vi.

[0222] After that, in the hold mode, the control signal The control signal SW2_b is changed from the H level to the L level, and the switch SW2_b is turned off. Therefore, the electrodes on one side of the capacitive elements C2_3 to C2_0 and C2_d are switched to a floating state. The voltage V1 is switched from the H level to the L level, thereby stopping the supply of the input voltage Vi to the other electrode of each of the capacitive elements C2_2 to C2_0 and C2_d (time t32).

[0223] Thereafter, in the charge redistribution mode, first, the voltage "+Vr" is supplied to the electrode on the other side of the capacitive element C2_2 of the most significant bit, and the voltage "-Vr" is supplied to the electrode on the other side of the remaining capacitive elements C2_3, C2_1, C2_0 and C2_d (time t32 to t33). As a result, "-Vi-(the voltage of the component of the detection signal X)" is supplied to the two input terminals of the comparator 302 as a differential voltage. Based on the comparison result of the comparator 302 at this time, the voltage of the electrode on the other side of the capacitive element C2_2 supplied to the most significant bit is fixed to the voltage "+Vr" or "-Vr" (time t33 to t36) by the comparison control unit 303. For example, if "Vi+(the voltage of the component of the detection signal X)" > 0, the value of the most significant bit of the digital signal (output signal S11) output from the comparison control unit 303 is determined to be 1. Here, the voltage of the electrode on the other side of the capacitive element C2_2 supplied to the most significant bit is fixed to the voltage "+Vr". On the other hand, if "Vi+(voltage of component of detection signal X)" < 0, the value of the most significant bit of the digital signal output from the comparison control unit 303 is determined to be 0. Here, the voltage of the electrode on the other side of the capacitive element C2_2 supplied to the most significant bit is fixed to the voltage "-Vr".

[0224] Thereafter, the voltage "+Vr" is supplied to the electrode on the other side of the capacitor element C2_1, which is the high bit immediately after the most significant bit, and the voltage "-Vr" is supplied to the electrodes on the other side of the remaining capacitor elements C2_3, C2_0 and C2_d (time t33 to t34). As a result, "-Vi+Vr (the value of the most significant bit)-Vr / 2" is supplied to the two input terminals of the comparator 302 as a differential voltage. Based on the comparison result of the comparator 302 at this time, the comparison control unit 303 determines the value of the second most significant bit of the digital signal, and the voltage supplied to the electrode on the other side of the capacitor element C2_1 is fixed to the voltage "+V" and "-Vr" (time t34 to t36).

[0225] This operation is sequentially repeated until the least significant capacitance element C2_0, whereby the digital signal (output signal S11) output from the comparison control unit 203 is fixed (time t25). The output signal S11 includes a component of the detection signal X.

[0226] Then, the voltage "+Vr" or "-Vr" according to the detection signal X is supplied again to the electrode on the other side of the capacitive element C2_3 (time t35 to t36). As a result, the charge holding node N2 has a voltage value obtained by adding the component of the detection signal X and the quantization error Q1. The voltage of the charge holding node N2 is output to the analog filter FLT2 as the intermediate signal M11 of the successive approximation AD converter QT1a.

[0227] Since the remaining configuration of the MASH type Σ-Δ AD converter device 3 is the same as that of the MASH type Σ-Δ AD converter device 1 , the description thereof is omitted.

[0228] As described above, the MASH type Σ-ΔAD converter device 3 according to the third embodiment is effective as the MASH type Σ-ΔAD converter device 1. In addition, since the MASH type Σ-ΔAD converter device 3 according to the third embodiment does not need to be provided with the analog adder-subtractor AS21, it is possible to suppress an increase in circuit size and suppress an increase in power consumption.

[0229] In this embodiment, the case where the successive approximation AD converter QT1a generates the output signal S11 with a 3-bit width is described as an example, but the present invention is not limited to this and the present invention can be appropriately changed to a configuration for generating an output signal S11 with any bit width.

[0230] Fourth embodiment

[0231] Fig.25 : is a block diagram illustrating a configuration example of a main part of a MASH type Σ-Δ AD converter device 4 according to the fourth embodiment.

[0232] like Fig.25 As shown in , compared with the MASH type Σ-Δ AD converter device 1, the MASH type Σ-Δ AD converter device 4 further includes a filter FLT4, a tap coefficient conversion and thinning circuit (hereinafter referred to as a thinning circuit) DM1, and a thinning circuit DM2.

[0233] The filter FLT4 is provided between the sigma-delta modulator SDM1 and the noise cancellation filter NCF1. The filter FLT4 filters the output signal S11 of the sigma-delta modulator SDM1 and outputs the filtered output signal S11 to the noise cancellation filter NCF1.

[0234] Here, preferably, the transfer function H as searched by the adaptive filter AF1 1A_R The transfer function H of the noise canceling filter NCF2 is expressed as the product of (f) and the transfer function of the filter FLT4.1D (f) is adjusted. Therefore, the sparse circuit DM1 first calculates the transfer function H searched by the adaptive filter AF1 1A_R (f) The product of the transfer function of filter FLT4.

[0235] The noise cancellation filter NCF2 usually operates at the same operating frequency fs / M as the low-speed AD converter LC1. However, the transfer function calculated by the thinning circuit DM1 is calculated based on the assumption that it operates at the operating frequency fs. Then, the thinning circuit DM1 further thins out the plurality of tap coefficients used to represent the calculated transfer function by 1 / M. As a result, it is considered that the tap coefficients output from the thinning circuit DM1 operate at the operating frequency fs / M. The transfer function H of the noise cancellation filter NCF2 1D (f) Adjusted by the tap coefficient output from the thinning circuit DM1.

[0236] On the other hand, according to the noise canceling filter NCF2, the noise canceling filter NCF1 is usually operated at the operating frequency fs / M. Therefore, the sparse circuit DM2 will be used to represent the transfer function H searched by the adaptive filter AF2. 2A_R The plurality of tap coefficients of (f) are thinned out by 1 / M. As a result, it is considered that the tap coefficients output from the thinning circuit DM2 operate at the operating frequency fs / M. The transfer function H of the noise canceling filter NCF1 is 2D (f) Adjusted by the tap coefficient output from the thinning circuit DM2.

[0237] Since the remaining configuration of the MASH type Σ-Δ AD converter device 4 is the same as that of the MASH type Σ-Δ AD converter device 1 , the description thereof is omitted.

[0238] The MASH type Σ-Δ AD converter device 4 according to the fourth embodiment is as effective as the MASH type Σ-Δ AD converter device 1. In addition, the MASH type Σ-Δ AD converter device 4 sparses 1 / M a plurality of tap coefficients for representing the transfer function searched by each of the adaptive filters AF1 and AF2. Therefore, the MASH type Σ-Δ AD converter device 4 can adopt the sparse result as a transfer function suitable for the noise cancellation filters NCF 2 and NCF1 operating at the same operating frequency fs / M as the low-speed AD converter LC1.

[0239] It should be noted that the configuration of the MASH type Σ-Δ AD converter 4 can be adopted not only to the MASH type Σ-Δ AD converter device 1 but also to other MASH type Σ-Δ AD converter devices.

[0240] Fifth embodiment

[0241] Fig.26: is a block diagram illustrating a configuration example of a main part of a MASH type Σ-Δ AD converter device 5 according to the fifth embodiment.

[0242] like Fig.26 As shown in, compared with the MASH type Σ-ΔAD converter device 1, the MASH type Σ-ΔAD converter device 5 generates an addition signal obtained by adding a component of the detection signal X and the quantization error Q1 by combining the voltages of multiple internal nodes of the analog integrator unit INTU1; instead of generating another addition signal, which is obtained by adding a component of the detection signal X and the quantization error Q1 by subtracting the signals before and after the quantizer QT1 by the analog adder-subtractor AS21.

[0243] The remaining configuration of the MASH type Σ-Δ AD converter device 5 is the same as that of the MASH type Σ-Δ AD converter device 1 , and thus a description thereof is omitted.

[0244] The MASH type Σ-Δ AD converter device 5 according to the fifth embodiment is as effective as the MASH type Σ-Δ AD converter device 1. In addition, since the MASH type Σ-Δ AD converter device 5 does not need to be provided with the analog adder-subtractor AS21 and the DA converter circuit DAC12, an increase in circuit size can be suppressed, and an increase in power consumption can be suppressed.

[0245] The configuration of the MASH type Σ-Δ AD converter device 5 can be adopted not only to the MASH type Σ-Δ AD converter device 1 but also to other MASH type Σ-Δ AD converter devices.

[0246] As described above, the MASH type Σ-Δ AD converter device according to the first, second, third, fourth and fifth embodiments can eliminate the quantization error Q1 generated in the quantizer QT1 by using the calibration circuit CAL1, thereby performing high-accuracy AD conversion. In addition, the MASH type Σ-Δ AD converter device according to the first, second, third, fourth and fifth embodiments includes an analog filter and a low-speed AD converter instead of further including a Σ-Δ modulator in the subsequent stage of the Σ-Δ modulator in the initial stage. As a result, the MASH type Σ-Δ AD converter device according to the first, second, third, fourth and fifth embodiments can reduce the analog integrator unit, quantizer and DA converter circuit required for high-speed operation, thereby reducing the consumed power.

[0247] In addition, the MASH type Σ-ΔAD converter device according to the first, second, third, fourth and fifth embodiments is not limited to the characteristic changes of the analog integrator, and even in the presence of characteristic changes of various other circuits (for example, characteristic changes of the analog adder-subtractor, characteristic changes due to the reference voltage mismatch between the quantizer and DA converter circuits, etc.), the quantization error Q1 can be eliminated by using noise elimination filters NCF1 and NCF2.

[0248] In addition, the MASH type Σ-Δ AD converter device according to the first, second, third, fourth and fifth embodiments can perform the search operation of the adaptive filters AF1 and AF2 in the background while performing the A / D conversion on the external input signal SI. Therefore, even when the characteristics of various circuits change due to, for example, changes in the use environment, the quantization error Q1 can be quickly eliminated by using the noise elimination filters NCF1 and NCF2.

[0249] Although the invention made by the inventors has been specifically described based on the embodiments, the present invention is not limited to the embodiments that have been described, and it goes without saying that various modifications can be made without departing from the gist thereof.

[0250] For example, in the semiconductor device according to the above-described embodiment, the conductivity type (p-type or n-type) of the semiconductor substrate, the semiconductor layer, the diffusion layer (diffusion region), etc. may be reversed. Therefore, in the case where one of the conductivity types of the n-type and the p-type is the first conductivity type and the other conductivity type is the second conductivity type, the first conductivity type may be the p-type and the second conductivity type may be the n-type, or conversely, the first conductivity type may be the n-type and the second conductivity type may be the p-type.

Claims

1. A multi-stage noise shaping MASH type Σ-Δ AD converter device, comprising: A detection signal generating circuit, used for generating a detection signal; a first modulator including a first analog integrator configured with an analog circuit and a first quantizer, wherein the first quantizer is used to quantize an added signal obtained by adding the detection signal to an output signal of the first analog integrator; an analog filter for filtering an extracted signal obtained by extracting the detection signal and a quantization error generated in the first quantizer; a first AD converter, for converting the output signal of the analog filter from an analog signal to a digital signal, the first AD converter operating at an operating frequency lower than an operating frequency of the first modulator; a first adaptive filter for searching a first transfer function by observing an output signal of the first quantizer according to the detection signal, the first transfer function being a transfer function of the first modulator; a second adaptive filter for searching for a second transfer function by observing an output signal of the first AD converter according to the detection signal, the second transfer function being a transfer function from the output of the first modulator to the first AD converter via the analog filter; as well as a noise elimination circuit for eliminating the quantization error and the detection signal included in the output signal of the first quantizer using the search result of the first adaptive filter and the search result of the second adaptive filter, The analog filter is configured to be able to adjust frequency characteristics according to the search result of the second adaptive filter.

2. The MASH type Σ-Δ AD converter device according to claim 1, The analog filter is a low pass filter.

3. The MASH type Σ-Δ AD converter device according to claim 1, The analog filter is an operational amplifier feedback type active filter.

4. The MASH type Σ-Δ AD converter device according to claim 1, The analog filter is a Gm-C filter.

5. The MASH type Σ-Δ AD converter device according to claim 1, The analog filter is a discrete time filter.

6. The MASH type Σ-Δ AD converter device according to claim 1, wherein the analog filter comprises a plurality of discrete time filters arranged in parallel, and The plurality of discrete-time filters are configured to perform filtering at different timings.

7. The MASH type Σ-Δ AD converter device according to claim 1, The analog filter includes a capacitive element configured to adjust a capacitance value used to determine the frequency characteristic according to the search result of the second adaptive filter.

8. The MASH type Σ-Δ AD converter device according to claim 1, The first AD converter is a Nyquist AD converter.

9. The MASH type Σ-Δ AD converter device according to claim 1, wherein the first AD converter is a successive approximation AD converter, and The analog filter is configured using a capacitive element formed in the first AD converter.

10. The MASH type Σ-Δ AD converter device according to claim 1, wherein the first AD converter comprises a plurality of successive approximation AD converters arranged in parallel, The analog filter comprises a plurality of discrete time filters arranged in parallel, wherein the plurality of discrete time filters are respectively configured to perform filtering at different timings and are configured using capacitive elements formed in the plurality of successive approximation AD converters, and The plurality of successive approximation AD converters are configured to convert output signals of the plurality of discrete-time filters from analog signals to digital signals, respectively.

11. The MASH type Σ-Δ AD converter device according to claim 1, The first quantizer is a successive approximation AD converter and is configured to output a voltage of a node as the extraction signal, at which a voltage corresponding to the detection signal is held in the first quantizer.

12. The MASH type Σ-Δ AD converter device according to claim 1, wherein the first quantizer is a successive approximation AD converter, and The first quantizer comprises: A sample-and-hold circuit, used for sampling and holding the output signal of the first analog integrator; a DA converter configured using the sample-and-hold circuit and for converting a digital signal continuously output from a comparison control unit into an analog signal; a comparator for comparing a voltage of an output signal of the first analog integrator held by the sample-and-hold circuit with a voltage of the analog signal converted by the DA converter; and The comparison control unit is used to switch the value of the digital signal based on the comparison result of the comparator, wherein the sample-and-hold circuit comprises a plurality of first capacitive elements arranged in parallel and a second capacitive element arranged in parallel with the plurality of first capacitive elements, wherein the second capacitive element samples and holds a voltage corresponding to the detection signal, and The voltage corresponding to the detection signal held in the sample-and-hold circuit is output as the extraction signal.

13. The MASH type Σ-Δ AD converter device according to claim 1, further comprising: a first thinning circuit for thinning a plurality of tap coefficients representing the first transfer function searched by the first adaptive filter according to the operating frequency of the first AD converter; as well as a second thinning circuit for thinning out a plurality of tap coefficients representing the second transfer function searched by the second adaptive filter according to the operating frequency of the first AD converter, The noise elimination circuit eliminates the quantization error and the detection signal included in the output signal of the first quantizer using the output of the first sparse circuit and the output of the second sparse circuit.

14. The MASH type Σ-Δ AD converter device according to claim 13, further comprising: a digital filter for filtering the output signal of the first quantizer, wherein the first sparsifying circuit is further configured to multiply the first transfer function by a transfer function of the digital filter, and The first thinning circuit is configured to thin out a plurality of tap coefficients representing a transfer function calculated by multiplying the first transfer function by the transfer function of the digital filter according to the operating frequency of the first AD converter.

15. The MASH type Σ-Δ AD converter device according to claim 1, The detection signal is a 1-bit pseudo-random signal.

16. The MASH type Σ-Δ AD converter device according to claim 1, The noise elimination circuit comprises: a first noise cancellation filter in which the first transfer function searched by the first adaptive filter is set as a transfer function; a second noise cancelling filter in which the second transfer function searched by the second adaptive filter is set as a transfer function; and a digital adder-subtractor for outputting a differential signal between an output signal of the first noise cancelling filter and an output signal of the second noise cancelling filter as an output signal of the noise cancelling circuit.

17. The MASH type Σ-Δ AD converter device according to claim 1, wherein the first adaptive filter is configured to search for tap coefficients representing the first transfer function based on a first error signal representing an error between an output signal of the first adaptive filter and an output signal of the first quantizer according to the detection signal by using a least mean square LMS algorithm, and The second adaptive filter is configured to search for tap coefficients representing the second transfer function based on a second error signal representing an error between an output signal of the second adaptive filter and an output signal of the first AD converter according to the detection signal by using the LMS algorithm.

18. A millimeter wave radar system, comprising a plurality of MASH type Σ-Δ AD converter devices according to claim 1, the millimeter wave radar system comprising: A transmitting antenna for radiating transmission waves into the air; A plurality of receiving antennas, used for receiving reflected waves from objects in response to the transmitted waves; A high frequency unit for generating a plurality of difference frequency signals by down-converting the reflected waves received by the plurality of receiving antennas using the transmission waves; A low-pass filter, used for filtering the multiple difference frequency signals; as well as a baseband unit, configured to process the plurality of difference frequency signals filtered by the low-pass filter; The baseband unit includes a plurality of MASH Σ-ΔAD converters, and the MASH Σ-ΔAD converters are used to convert the plurality of difference frequency signals filtered by the low-pass filter from analog signals to digital signals respectively.

19. A multi-stage noise shaping MASH type Σ-Δ AD converter device comprising: A detection signal generating circuit, used for generating a detection signal; a first modulator including a first analog integrator configured with an analog circuit and a first quantizer, wherein the first quantizer is used to quantize an added signal obtained by adding the detection signal to an output signal of the first analog integrator; an analog filter for filtering an extracted signal obtained by extracting the detection signal and a quantization error generated in the first quantizer; a first AD converter, for converting the output signal of the analog filter from an analog signal to a digital signal, the first AD converter operating at an operating frequency lower than an operating frequency of the first modulator; a first adaptive filter for searching a first transfer function by observing an output signal of the first quantizer according to the detection signal, the first transfer function being a transfer function of the first modulator; a second adaptive filter for searching for a second transfer function by observing an output signal of the first AD converter according to the detection signal, the second transfer function being a transfer function from the output of the first modulator to the first AD converter via the analog filter; as well as a noise elimination circuit for eliminating the quantization error and the detection signal included in the output signal of the first quantizer using the search result of the first adaptive filter and the search result of the second adaptive filter, wherein the first AD converter is a successive approximation AD converter, and The analog filter is configured using a capacitive element formed in the first AD converter.

20. A multi-stage noise shaping MASH type Σ-Δ AD converter device comprising: A detection signal generating circuit, used for generating a detection signal; a first modulator including a first analog integrator configured with an analog circuit and a first quantizer, wherein the first quantizer is used to quantize an added signal obtained by adding the detection signal to an output signal of the first analog integrator; an analog filter for filtering an extracted signal obtained by extracting the detection signal and a quantization error generated in the first quantizer; a first AD converter, for converting the output signal of the analog filter from an analog signal to a digital signal, the first AD converter operating at an operating frequency lower than an operating frequency of the first modulator; a first adaptive filter for searching a first transfer function by observing an output signal of the first quantizer according to the detection signal, the first transfer function being a transfer function of the first modulator; a second adaptive filter for searching for a second transfer function by observing an output signal of the first AD converter according to the detection signal, the second transfer function being a transfer function from the output of the first modulator to the first AD converter via the analog filter; as well as a noise elimination circuit for eliminating the quantization error and the detection signal included in the output signal of the first quantizer using the search result of the first adaptive filter and the search result of the second adaptive filter, wherein the first AD converter comprises a plurality of successive approximation AD converters arranged in parallel, The analog filter comprises a plurality of discrete time filters arranged in parallel, wherein the plurality of discrete time filters are respectively configured to perform filtering at different timings and are configured using capacitive elements formed in the plurality of successive approximation AD converters, and The plurality of successive approximation AD converters are configured to convert output signals of the plurality of discrete-time filters from analog signals to digital signals, respectively.

21. A multi-stage noise shaping MASH type Σ-Δ AD converter device comprising: A detection signal generating circuit, used for generating a detection signal; a first modulator including a first analog integrator configured with an analog circuit and a first quantizer, wherein the first quantizer is used to quantize an added signal obtained by adding the detection signal to an output signal of the first analog integrator; an analog filter for filtering an extracted signal obtained by extracting the detection signal and a quantization error generated in the first quantizer; a first AD converter, for converting the output signal of the analog filter from an analog signal to a digital signal, the first AD converter operating at an operating frequency lower than an operating frequency of the first modulator; a first adaptive filter for searching a first transfer function by observing an output signal of the first quantizer according to the detection signal, the first transfer function being a transfer function of the first modulator; a second adaptive filter for searching for a second transfer function by observing an output signal of the first AD converter according to the detection signal, the second transfer function being a transfer function from the output of the first modulator to the first AD converter via the analog filter; as well as a noise elimination circuit for eliminating the quantization error and the detection signal included in the output signal of the first quantizer using the search result of the first adaptive filter and the search result of the second adaptive filter, wherein the first quantizer is a successive approximation AD converter, and The first quantizer comprises: A sample-and-hold circuit, used for sampling and holding the output signal of the first analog integrator; a DA converter configured using the sample-and-hold circuit and for converting a digital signal continuously output from a comparison control unit into an analog signal; a comparator for comparing a voltage of an output signal of the first analog integrator held by the sample-and-hold circuit with a voltage of the analog signal converted by the DA converter; and The comparison control unit is used to switch the value of the digital signal based on the comparison result of the comparator, wherein the sample-and-hold circuit comprises a plurality of first capacitive elements arranged in parallel and a second capacitive element arranged in parallel with the plurality of first capacitive elements, wherein the second capacitive element samples and holds a voltage corresponding to the detection signal, and The voltage corresponding to the detection signal held in the sample-and-hold circuit is output as the extraction signal.

22. A multi-stage noise shaping MASH type Σ-Δ AD converter device comprising: A detection signal generating circuit, used for generating a detection signal; a first modulator including a first analog integrator configured with an analog circuit and a first quantizer, wherein the first quantizer is used to quantize an added signal obtained by adding the detection signal to an output signal of the first analog integrator; an analog filter for filtering an extracted signal obtained by extracting the detection signal and a quantization error generated in the first quantizer; a first AD converter, for converting the output signal of the analog filter from an analog signal to a digital signal, the first AD converter operating at an operating frequency lower than an operating frequency of the first modulator; a first adaptive filter for searching a first transfer function by observing an output signal of the first quantizer according to the detection signal, the first transfer function being a transfer function of the first modulator; a second adaptive filter for searching for a second transfer function by observing an output signal of the first AD converter according to the detection signal, the second transfer function being a transfer function from the output of the first modulator to the first AD converter via the analog filter; as well as a noise elimination circuit for eliminating the quantization error and the detection signal included in the output signal of the first quantizer using the search result of the first adaptive filter and the search result of the second adaptive filter, The MASH type Σ-Δ AD converter device further comprises: a first thinning circuit for thinning a plurality of tap coefficients representing the first transfer function searched by the first adaptive filter according to the operating frequency of the first AD converter; as well as a second thinning circuit for thinning out a plurality of tap coefficients representing the second transfer function searched by the second adaptive filter according to the operating frequency of the first AD converter, The noise elimination circuit eliminates the quantization error and the detection signal included in the output signal of the first quantizer using the output of the first sparse circuit and the output of the second sparse circuit.

23. The MASH type Σ-Δ AD converter device according to claim 22, further comprising: a digital filter for filtering the output signal of the first quantizer, wherein the first sparsifying circuit is further configured to multiply the first transfer function by a transfer function of the digital filter, and The first thinning circuit is configured to thin out a plurality of tap coefficients representing a transfer function calculated by multiplying the first transfer function by the transfer function of the digital filter according to the operating frequency of the first AD converter.

24. A multi-stage noise shaping MASH type Σ-Δ AD converter device comprising: A detection signal generating circuit, used for generating a detection signal; a first modulator including a first analog integrator configured with an analog circuit and a first quantizer, wherein the first quantizer is used to quantize an added signal obtained by adding the detection signal to an output signal of the first analog integrator; an analog filter for filtering an extracted signal obtained by extracting the detection signal and a quantization error generated in the first quantizer; a first AD converter, for converting the output signal of the analog filter from an analog signal to a digital signal, the first AD converter operating at an operating frequency lower than an operating frequency of the first modulator; a first adaptive filter for searching a first transfer function by observing an output signal of the first quantizer according to the detection signal, the first transfer function being a transfer function of the first modulator; a second adaptive filter for searching for a second transfer function by observing an output signal of the first AD converter according to the detection signal, the second transfer function being a transfer function from the output of the first modulator to the first AD converter via the analog filter; as well as a noise elimination circuit for eliminating the quantization error and the detection signal included in the output signal of the first quantizer using the search result of the first adaptive filter and the search result of the second adaptive filter, wherein the noise elimination circuit comprises: a first noise elimination filter in which the first transfer function searched by the first adaptive filter is set as a transfer function; a second noise cancelling filter in which the second transfer function searched by the second adaptive filter is set as a transfer function; and a digital adder-subtractor for outputting a differential signal between an output signal of the first noise cancelling filter and an output signal of the second noise cancelling filter as an output signal of the noise cancelling circuit.

25. A multi-stage noise shaping MASH type Σ-Δ AD converter device comprising: A detection signal generating circuit, used for generating a detection signal; a first modulator including a first analog integrator configured with an analog circuit and a first quantizer, wherein the first quantizer is used to quantize an added signal obtained by adding the detection signal to an output signal of the first analog integrator; an analog filter for filtering an extracted signal obtained by extracting the detection signal and a quantization error generated in the first quantizer; a first AD converter, for converting the output signal of the analog filter from an analog signal to a digital signal, the first AD converter operating at an operating frequency lower than an operating frequency of the first modulator; a first adaptive filter for searching a first transfer function by observing an output signal of the first quantizer according to the detection signal, the first transfer function being a transfer function of the first modulator; a second adaptive filter for searching for a second transfer function by observing an output signal of the first AD converter according to the detection signal, the second transfer function being a transfer function from the output of the first modulator to the first AD converter via the analog filter; as well as a noise elimination circuit for eliminating the quantization error and the detection signal included in the output signal of the first quantizer using the search result of the first adaptive filter and the search result of the second adaptive filter, wherein the first adaptive filter is configured to search for tap coefficients representing the first transfer function based on a first error signal representing an error between an output signal of the first adaptive filter and an output signal of the first quantizer according to the detection signal by using a least mean square LMS algorithm, and The second adaptive filter is configured to search for tap coefficients representing the second transfer function based on a second error signal representing an error between an output signal of the second adaptive filter and an output signal of the first AD converter according to the detection signal by using the LMS algorithm.

26. A millimeter wave radar system comprising a plurality of MASH type Σ-Δ AD converter devices according to any one of claims 2-17 and 19-25, the millimeter wave radar system comprising: A transmitting antenna for radiating transmission waves into the air; A plurality of receiving antennas, used for receiving reflected waves from objects in response to the transmitted waves; A high frequency unit for generating a plurality of difference frequency signals by down-converting the reflected waves received by the plurality of receiving antennas using the transmission waves; A low-pass filter, used for filtering the multiple difference frequency signals; as well as a baseband unit, configured to process the plurality of difference frequency signals filtered by the low-pass filter, The baseband unit includes a plurality of the MASH Σ-ΔAD converters, and the MASH Σ-ΔAD converters are used to convert the plurality of difference frequency signals filtered by the low-pass filter from analog signals to digital signals respectively.

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