A power receiving device and power receiving system supporting dual-port Ethernet power receiving

Abstract

The present invention discloses a power receiving device and a power receiving system supporting dual-port Ethernet power receiving, wherein the power receiving device comprises a first power receiving detection chip, a first power receiving circuit, a second power receiving circuit and a delayed conduction circuit. Through this technical solution, the problem of competition between detection signals in dual-port power supply is solved, and both network ports in the power receiving device can simultaneously support Ethernet power supply, thereby avoiding the situation where the use of two sets of power receiving circuits causes the device cost to be too high, and improving the use range and user experience of this type of power receiving device.

Description

Technical Field

[0001] The present invention relates to the field of Ethernet power supply, and in particular to a power receiving device and a power receiving system supporting dual-network-port Ethernet power receiving. Background Art

[0002] Power over Ethernet is a technology that can transmit power and data to devices via twisted pair cables in Ethernet. This technology allows devices including Internet phones, wireless base stations, cameras, hubs, computers, etc. to be powered by Power over Ethernet. Since electronic devices that can be powered by Ethernet do not require additional power sockets, they can save time and money in configuring power cords, making the cost of the entire device system relatively low. RJ-45 network sockets are currently widely used around the world, so various Ethernet devices are compatible. This technology does not require changes to the Ethernet cable architecture to operate, so the use of an Ethernet power supply system not only saves costs and facilitates wiring and installation, but also has the ability to remotely power on and off.

[0003] A typical Ethernet power supply system includes power supply equipment (PSE equipment), powered devices (PD equipment) and network cables. Power supply equipment includes POE switches, POE injectors and other product forms, while powered devices include AP (wireless access point), IP Camera, IP phone and other product forms.

[0004] Some powered devices have two or more Ethernet ports, and users hope that both ports support Ethernet power receiving function. In this way, when one port fails, the other port can also obtain power through Ethernet power supply, that is, the powered device supports dual-port Ethernet power receiving.

[0005] As the instruction manual Figure 1 As shown, the current typical design uses two sets of power detection circuits, and each network port uses a separate power detection chip. In this way, there will be no detection competition problem when the two network ports are tested for Ethernet power supply at the same time. However, its disadvantage is that it increases the configuration cost of the equipment and the PCB usage space, and at the same time hinders the appearance design of the product, thereby restricting its scope of use.

[0006] If two network ports can share a set of power detection circuits, the product cost will be greatly reduced and the application scope will be expanded. However, the current industry design of two network ports sharing a set of power detection circuits is defective. When two network ports perform power detection at the same time, the competition between the two detection signals will cause the power detection result to be invalid, which will lead to the failure of powering on the powered device. This result is unacceptable in commercial applications of products. Figure 2As shown, another typical design is to temporarily shut down the Ethernet power supply function of one of the network ports on the power supply device side, and only retain the power supply of a single network port at the same time. The defect of this technical solution is that the user is required to perform additional settings on the power supply device, which leads to a poor user experience. Summary of the invention

[0007] In view of the above problems existing in the prior art, a powered device supporting dual-port Ethernet power receiving is now provided, and the specific technical solution is as follows:

[0008] A powered device supporting dual-port Ethernet power receiving, characterized by comprising:

[0009] A power receiving detection chip;

[0010] A first power receiving circuit connected between a first power receiving end network port and a power receiving detection chip;

[0011] A second power receiving circuit connected between a second power receiving end network port and a power receiving detection chip;

[0012] The first power receiving circuit includes a first forward path and a first return path;

[0013] The second power receiving circuit includes a second forward path and a second return path;

[0014] The invention also includes a delayed conduction circuit, which is arranged in the first return path and the second return path to make the first power receiving circuit be turned on later than the second power receiving circuit, and to prevent the first power receiving circuit from being turned on when the second power receiving circuit is turned on.

[0015] Preferably, in the power receiving device, the first power receiving circuit includes a first rectifier circuit for converting direct current with different polarities received by the first power receiving end network port into direct current with fixed polarity;

[0016] The second power receiving circuit includes a second rectifier circuit for converting direct current with different polarities received by the second power receiving end network port into direct current with fixed polarity.

[0017] Further preferably, in the power receiving device, the first rectifier circuit is a bridge rectifier circuit, and the first rectifier circuit includes two rectifier bridges connected in parallel;

[0018] The second rectifier circuit has the same structure as the first rectifier circuit.

[0019] Preferably, in the powered device, the delayed conduction circuit comprises a diode, a three-terminal delay switch element and a voltage management circuit;

[0020] A first node is provided on the first forward path;

[0021] A second node is provided on the first return flow path;

[0022] The voltage management circuit is connected in series between the first node and the second node, and the voltage management circuit also includes a voltage output branch;

[0023] The three-terminal delay switch element is arranged on the first return current path and directly connected between the second node and the negative terminal of the power receiving detection chip, and the control end of the three-terminal delay switch element is connected to the voltage output branch;

[0024] A third node is provided between the control terminal of the three-terminal delay switch element and the voltage output branch;

[0025] A fourth node is arranged on the second return path, and the fourth node is also connected to the third node;

[0026] The diode is arranged on the second return current path and is directly connected between the fourth node and the negative terminal of the power receiving detection chip;

[0027] Preferably, in the powered device, the diode is a Schottky diode.

[0028] Preferably, in the powered device, the three-terminal delay switch element is an N-channel MOS tube;

[0029] The source of the N-channel MOS tube is close to the negative terminal of the power detection chip, the drain of the N-channel MOS tube is close to the second node, and the gate of the N-channel MOS tube is connected to the voltage output branch.

[0030] Further preferably, in the powered device, the voltage management circuit comprises a first voltage-dividing resistor and a voltage-stabilizing diode, and the first voltage-dividing resistor and the voltage-stabilizing diode are connected in series;

[0031] A fifth node is arranged between the first voltage-dividing resistor and the voltage-stabilizing tube, and a voltage output branch is led out from the fifth node.

[0032] Preferably, in the power receiving device, the three-terminal delay switch element is a thyristor;

[0033] The anode of the thyristor is close to the negative terminal of the power detection chip, the cathode of the thyristor is close to the second node, and the control electrode of the thyristor is connected to the voltage output branch.

[0034] Further preferably, in the powered device, the voltage management circuit includes a second voltage-dividing resistor and a third voltage-dividing resistor, and the second voltage-dividing resistor and the third voltage-dividing resistor are connected in series;

[0035] A sixth node is arranged between the second voltage-dividing resistor and the third voltage-dividing resistor, and a voltage output branch is led out from the sixth node.

[0036] A power receiving system supporting dual-port Ethernet power receiving, characterized by comprising a power receiving device as any one of the above items;

[0037] The power receiving system also includes a power supply device, which includes a first power supply end network port and a second power supply end network port, and is used to send a power receiving detection signal to the power receiving device and provide 36-57V DC power;

[0038] The first power supply end network port is correspondingly connected to the first power receiving end network port via a network cable;

[0039] The second power supply end network port is correspondingly connected to the second power receiving end network port through a network cable.

[0040] The above technical solution has the following advantages or beneficial effects:

[0041] This technical solution is applicable to both Endpoint-type Ethernet power supply equipment and Midspan-type Ethernet power supply equipment. Through this technical solution, the problem of competition between detection signals in dual-port power supply is solved, and both network ports in the powered device can support Ethernet power supply at the same time, thereby avoiding the use of two sets of powered circuits resulting in excessively high equipment costs, and improving the scope of use and user experience of this type of powered device. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a structural schematic diagram of an Ethernet power supply system supporting dual network ports in the prior art;

[0043] Figure 2 It is a structural schematic diagram of an Ethernet power supply system supporting single network port power supply in the prior art;

[0044] Figure 3 It is a schematic structural diagram of an Ethernet power supply system in a first embodiment of a powered device and a powered system supporting dual-port Ethernet power supply according to the present invention;

[0045] Figure 4 The present invention is a schematic structural diagram of an Ethernet power supply system in a second embodiment of a powered device and a powered system supporting dual-port Ethernet power supply.

[0046] in:

[0047] 00 is the power supply device, 001 is the first power supply end network port, and 002 is the second power supply end network port;

[0048] 01 is the powered device, 011 is the first powered end network port, and 012 is the second powered end network port;

[0049] 11 is a first rectifier circuit, 12 is a second rectifier circuit;

[0050] 2 is a power detection chip;

[0051] 3 is a voltage regulator;

[0052] 4 is a diode;

[0053] 51 is an N-channel MOS tube, S is the source, D is the drain, and G1 is the gate;

[0054] 52 is a thyristor, A is an anode, K is a cathode, and G2 is a control electrode;

[0055] 6 is a voltage management circuit, 61 is a first voltage-dividing resistor, 62 is a voltage-stabilizing diode, 63 is a second voltage-dividing resistor, and 64 is a third voltage-dividing resistor;

[0056] a is the first node, b is the second node, c is the third node, d is the fourth node, e is the fifth node, and f is the sixth node. DETAILED DESCRIPTION

[0057] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0058] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0059] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0060] In view of the above problems existing in the prior art, a powered device supporting dual-port Ethernet power receiving is now provided, and the specific technical solution is as follows:

[0061] A powered device 01 supporting dual-port Ethernet power supply is applied to an Ethernet power supply system, such as Figure 3-4 As shown, the Ethernet power supply system also includes a power supply device 00, and the power supply device 00 includes a first power supply end network port 001 and a second power supply end network port 002;

[0062] The powered device 01 specifically includes:

[0063] A first power receiving end network port 011, the first power receiving end network port 011 is electrically connected to the first power supply end network port 001 through a network cable;

[0064] The second power receiving end network port 012 is electrically connected to the second power supply end network port 002 via a network cable;

[0065] A power receiving detection chip 2;

[0066] The first power receiving end network port 011 is connected to the power receiving detection chip 2 through a first rectifier circuit 11, and the first power receiving end network port 011, the first rectifier circuit 11 and the power receiving detection chip 2 constitute a first power receiving loop;

[0067] The second power receiving end network port 012 is connected to the power receiving detection chip 2 through a second rectifier circuit 12. The second power receiving end network port 012, the second rectifier circuit 12 and the power receiving detection chip 2 form a second power receiving circuit.

[0068] A third node c and a diode 4 are provided between the negative terminal of the power receiving detection chip 2 and the second rectifier circuit 12. The diode 4 is connected in series between the third node c and the negative terminal of the power receiving detection chip 2. The negative terminal of the diode 4 is close to the third node c.

[0069] A first node a and a second node b are provided between the power receiving detection chip 2 and the first rectifier circuit, and a voltage management circuit 6 is provided between the first node a and the second node b. The voltage management circuit 6 includes a voltage output branch;

[0070] A time delay switch element is connected in series between the negative electrode port of the power receiving detection chip 2 and the second node b, wherein the time delay switch element includes a control electrode connected to the voltage output branch;

[0071] A fourth node d is arranged between the voltage output branch and the control electrode, and the fourth node d is connected to the third node c.

[0072] In a preferred embodiment of the present invention, a solution is proposed to solve the problem of dual network ports sharing an Ethernet power supply detection system and thus generating competition for detection signals. By building a delay switch circuit on one Ethernet power receiving path of the powered device, the detection signal on the other Ethernet power receiving path can reach the power receiving detection chip earlier to complete the detection process and power on first, thereby avoiding competition and conflict between the two detection signals.

[0073] In the above preferred embodiment, the powered device is applied to an Ethernet power supply system, and the Ethernet power supply system also includes a power supply device 00, and the power supply device 00 includes a first power supply end network port 001 and a second power supply end network port 002, which are used for power supply and power receiving detection: when the power supply device 00 is powered on again, the power supply device 00 will decide whether to perform a single network port power supply operation or a dual network port power supply operation according to the preset rules inside the device or the instructions given by external personnel; when the power supply device 00 performs a single network port power supply operation, the network port to be powered will first be switched off at a predetermined interval. A detection waveform is sent once to detect whether the powered device 01 has been normally docked with it, and the sending of the detection waveform is stopped and the power-on state is maintained after it is learned that the powered device 01 has been normally docked. When the power supply device 00 needs to perform a dual-port power supply operation, the first power supply end network port 001 and the second power supply end network port 002 send a detection waveform at the same time at every predetermined interval to detect whether the powered receiving end network port connected with them is normally docked, and after it is learned that any powered receiving end network port is normally docked, the sending of the detection waveform is stopped and the powered receiving end network port is maintained in the power-on state.

[0074] In the above preferred embodiment, the power supply network port of the power supply device 00 and the power receiving network port of the powered device 01 are connected by a Category 5 twisted pair cable.

[0075] like Figure 3-Figure 4 As shown, in the above preferred embodiment, the delay switch circuit includes a diode 4, a voltage management circuit 6 and a delay switch element. When the power supply device 00 needs to perform a dual-port power supply operation, the second return path with the diode 4 will be turned on first, and the first return path with the delay switch element will be delayed in the conduction state, so that the return detection waveform will not produce competition conflicts. At the same time, the function of dual-port power supply can be fully automatically realized without human intervention, so that the problems existing in the prior art are effectively solved.

[0076] As a preferred embodiment, in the power receiving device 01 , the first rectifier circuit 11 and the second rectifier circuit 12 have the same structure.

[0077] Furthermore, in the powered device 01 , the first rectifier circuit 11 is a bridge rectifier circuit, and the first rectifier circuit 11 includes two rectifier bridges connected in parallel.

[0078] In another preferred embodiment of the present invention, Figure 3-Figure 4 As shown, the structures of the first rectifier circuit 11 and the second rectifier circuit 12 are exactly the same, both of which are bridge rectifier circuits. Eight diodes form two parallel-connected rectifier bridges, which can efficiently convert direct current with different polarities supplied by the power supply equipment into direct current with fixed polarity, and have the characteristics of small size and easy use.

[0079] As a preferred implementation, in the powered device 01 , the diode 4 is a Schottky diode.

[0080] In another preferred embodiment of the present invention, a Schottky diode is used, which has the advantages of high switching frequency and low forward voltage drop, and is suitable for use as a high-frequency rectifier in low-voltage, high-current output situations. As a preferred choice, it perfectly fits the application scenario of the present technical solution.

[0081] As a preferred embodiment, the powered device 01 further includes a voltage regulator 3; the voltage regulator 3 is connected to the power detection chip 2. After the power detection is completed, the power supply device 00 can provide Ethernet power to the powered device 01, and the fixed-polarity DC power obtained by the rectifier circuit will be regulated by the voltage regulator and then provided to specific devices for power use.

[0082] Two specific embodiments are now provided to further illustrate and describe the technical solution:

[0083] In the first embodiment of the present invention, Figure 3 As shown, the delay switch element adopts an N-channel MOS tube 51, such as Figure 3 As shown, the source S of the N-channel MOS transistor is close to the negative terminal of the power detection chip 2, the drain D of the N-channel MOS transistor is close to the second node b, and the gate G1 of the N-channel MOS transistor is connected to the voltage output branch; at the same time, the voltage management circuit 6 is composed of a first voltage-dividing resistor 61 and a voltage-stabilizing tube 62, and the first voltage-dividing resistor 61 and the voltage-stabilizing tube 62 are connected in series; a fifth node e is set between the first voltage-dividing resistor 61 and the voltage-stabilizing tube 62, and the voltage output branch is derived from the fifth node e.

[0084] In the first embodiment, after the power supply device 00 is powered on again, if only the first power receiving end network port 011 needs to be powered according to the setting, a detection waveform is firstly sent out through the first power supply end network port 001, and the detection waveform is rectified by the first rectifier circuit and reaches the power receiving detection chip to complete the detection and then flow back. At this time, the voltage management circuit 6 composed of the first voltage dividing resistor 61 and the voltage regulator 62 provides a conduction voltage to the gate G1 of the N-channel MOS transistor 51, so that the N-channel MOS transistor 51 can be smoothly turned on, the first power receiving circuit is turned on to complete the power receiving detection, and at this time, the first power receiving end network port 011 completes the power-on process and remains in the power-on state.

[0085] In the first embodiment, when the power supply device 00 is powered on again, if only the second power receiving end network port 012 needs to be powered according to the setting, since the diode 4 can be directly turned on, the second power receiving circuit can be directly turned on to complete the power receiving detection. At this time, the second power receiving end network port 012 completes the power-on process and remains in the powered-on state.

[0086] In the first embodiment, after the power supply device 00 is powered on again, if the first power receiving end network port 011 and the second power receiving end network port 012 are powered at the same time according to the setting requirements, the power supply device 00 transmits the detection waveform synchronously once at a predetermined interval through the first power supply end network port 001 and the second power supply end network port 002: due to the existence of the N-channel MOS transistor 51, the first return path will be connected later than the second return path. As the second return path is connected, the third node c and the fourth node d have the same potential, which directly lowers the gate voltage so that the gate G1 cannot be turned on. At this time, the second power receiving end network port 012 successfully completes the power-on process and maintains the power supply state until the second power receiving circuit fails and needs to switch to dual-channel power reception. The first power receiving circuit can be reconnected due to the recovery of the gate voltage.

[0087] In a second embodiment of the present invention, Figure 4 As shown, the difference from the first embodiment is that: the delay switch element uses a thyristor 52 instead of an N-channel MOS tube, the anode A of the thyristor 52 is close to the negative terminal of the power detection chip 2, the cathode K of the thyristor 52 is close to the second node b, and the control electrode G2 of the thyristor 52 is connected to the voltage output branch; at the same time, the voltage management circuit 6 is changed to include a second voltage-dividing resistor 63 and a third voltage-dividing resistor 64, the second voltage-dividing resistor 63 and the third voltage-dividing resistor 64 are connected in series, and a sixth node f is set between the second voltage-dividing resistor 63 and the third voltage-dividing resistor 64, and the voltage output branch is derived from the sixth node f.

[0088] In the above-mentioned second embodiment, a thyristor 52 is used as a delay switch element, which has the advantages of small size, high efficiency and long life; whether it is powered by a single network port or a dual network port, the power detection process after the power supply device 00 is powered on again is the same as the above-mentioned first embodiment, and will not be repeated here.

[0089] To sum up, this technical solution is applicable to both Endpoint-type Ethernet power supply equipment and Midspan-type Ethernet power supply equipment. Through this technical solution, the problem of competition between detection signals in dual-port power supply is solved, and both network ports in the powered device can support Ethernet power supply at the same time, thereby avoiding the use of two sets of power receiving circuits that result in excessively high equipment costs, and improving the scope of use and user experience of this type of powered device.

[0090] The above description is only a preferred embodiment of the present invention, and does not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A powered device supporting dual-port Ethernet power receiving, characterized in that: include: A power receiving detection chip; A first power receiving circuit connected between a first power receiving end network port and the power receiving detection chip; A second power receiving circuit connected between a second power receiving end network port and the power receiving detection chip; The first power receiving circuit includes a first forward path and a first return path; The second power receiving circuit includes a second forward path and a second return path; The invention also includes a delayed conduction circuit, wherein the delayed conduction circuit is arranged on the first return path and the second return path, so that the first power receiving circuit is turned on later than the second power receiving circuit, and when the second power receiving circuit is turned on, the first power receiving circuit is prevented from being turned on; The delayed conduction circuit includes a diode, a three-terminal delay switch element and a voltage management circuit; A first node is provided on the first forward path; A second node is provided on the first return path; The voltage management circuit is connected in series between the first node and the second node, and the voltage management circuit further includes a voltage output branch; The three-terminal time-delay switch element is arranged on the first return path and directly connected between the second node and the negative terminal of the power receiving detection chip, and the control end of the three-terminal time-delay switch element is connected to the voltage output branch; A third node is provided between the control terminal of the three-terminal delay switch element and the voltage output branch; A fourth node is provided on the second return path, and the fourth node is also connected to the third node; The diode is arranged on the second return path and is directly connected between the fourth node and the negative terminal of the power receiving detection chip; The three-terminal delay switch element is a thyristor; The anode of the thyristor is close to the negative terminal of the power detection chip, the cathode of the thyristor is close to the second node, and the control electrode of the thyristor is connected to the voltage output branch; The voltage management circuit includes a second voltage-dividing resistor and a third voltage-dividing resistor, wherein the second voltage-dividing resistor and the third voltage-dividing resistor are connected in series; A sixth node is provided between the second voltage-dividing resistor and the third voltage-dividing resistor, and the voltage output branch is led out from the sixth node; The first power receiving circuit includes a first rectifier circuit, which is used to convert the DC power with different polarities received by the first power receiving end network port into DC power with fixed polarity; The second power receiving circuit includes a second rectifier circuit, which is used to convert the direct current with different polarities received by the second power receiving end network port into the direct current with fixed polarity.

2. The power receiving device according to claim 1, characterized in that: The first rectifier circuit is a bridge rectifier circuit, and the first rectifier circuit includes two rectifier bridges connected in parallel; The second rectifier circuit has the same structure as the first rectifier circuit.

3. The power receiving device according to claim 1, characterized in that: The diode is a Schottky diode.

4. A power receiving system supporting dual-port Ethernet power receiving, characterized in that: A powered device comprising a powered device as claimed in any one of claims 1 to 3; The power receiving system further includes a power supply device, the power supply device including a first power supply end network port and a second power supply end network port, which is used to send a power receiving detection signal to the power receiving device and provide 36-57V DC power; The first power supply end network port is correspondingly connected to the first power receiving end network port via a network cable; The second power supply end network port is correspondingly connected to the second power receiving end network port via a network cable.

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