Method and corresponding system for managing storage space of a memory device

Abstract

Embodiments of the present disclosure relate to methods and corresponding systems for managing storage space of a memory device. A system includes a memory device that includes: a first memory area to store first data at a first address, and a second storage area to store second data at a second address or store error correction code parity bits associated with the first data at a third address according to a command.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of French Patent Application No. 1872239 filed on December 3, 2018, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention generally relates to semiconductor memories and, in particular embodiments, to methods and corresponding systems for managing the storage space of a memory device. Background Art

[0004] Error correction codes are known to those skilled in the art and it is possible to correct the logical value of an error in a bit. More precisely, with an error correction code, if s parity bits are added to b data bits, it is possible to correct r errors in the b + s bits.

[0005] When it is desired to implement an error correction code, the size of the memory containing the data and the parity bits is greater than the size of a memory intended to store data without using an error correction code.

[0006] By way of indication, a static memory intended to store data on a 32-bit width (32-bit word) has an additional 7-bit width for storing parity bits, thus resulting in a total width of 39 bits and enabling the storage of 39-bit words.

[0007] As a result, this represents a 22% increase in area compared to a 32-bit memory not intended to store parity bits.

[0008] If in a particular application the user does not wish to use an error correction code, this additional 22% of memory area will not be used as it is inaccessible for data storage. Now, this lost memory area has a direct impact on the leakage current, which is not negligible for low-power consumption products.

[0009] The increase in memory area also has an impact on the cost of the device.

[0010] Therefore, there is a need to rectify this drawback and to provide greater flexibility in the management of the storage space of a memory in order to take into account the optional nature of using an error correction code. Summary of the Invention

[0011] According to one embodiment, the system advantageously determines a third address based on a first location.

[0012] This makes it possible to simplify the calculation of the third address and to link the address of the verification word associated with the data to the address of the data word, so that the verification word in the second memory area can be retrieved very simply.

[0013] According to one embodiment, the system includes an interface.

[0014] The interface is configured to receive the first data and the first initial address associated with the first data.

[0015] The interface is further configured to possibly receive the second data and the second initial address associated with the second data.

[0016] The interface is further configured to deliver the first address based on the first initial address and the second address based on the second initial address.

[0017] In particular, the first initial address and the second initial address are generally transmitted on the bus according to the structure of the system and the size of the memory device, and the first address and the second address in the memory device may be the same as or different from the first initial address and the second initial address.

[0018] Thus, for example, the first initial address and the second initial address may be encoded on 17 bits, while the first address and the second address may be encoded on 15 bits, for example, by truncating two bits of the initial address.

[0019] The system further includes an error correction code circuit configured to determine a check bit associated with the first data.

[0020] The system further includes a processing circuit configured to determine a third address of the check bit; and a control circuit configured to deliver the second data and the second address, or the check bit and the third address, to the second memory area.

[0021] According to one embodiment, the first memory area includes at least one first memory bank having a first memory size (e.g., n kilobits, where n can be equal to 32 or 64, and these values are not limited), and the second memory area containing the second memory bank also has the above-mentioned first size.

[0022] The above-mentioned at least one first memory bank and the second memory bank contain rows.

[0023] And, according to one embodiment, the processing circuit is configured to determine the third address such that the check bits associated with the first data stored in the first consecutive number of first rows of the at least one first memory bank are stored in the second number of rows of the second memory bank, and the second number is less than the first number.

[0024] More particularly, when each row of the at least one first memory region and each row of the second memory region are configured to store a word of p bytes, the processing circuitry is configured to determine the third address such that a parity bit associated with first data stored in p consecutive rows of the at least one first memory region is stored in p bytes of a row of the second memory region.

[0025] Thus, for example, if each row has a capacity to store a 32-bit (4-byte) word, the parity bits associated with 32-bit data words stored in four consecutive rows of the first memory region will be stored in four bytes of a row of the second memory region.

[0026] For example, if each row has a capacity to store a 64-bit (8-byte) word, the parity bits associated with 64-bit data stored in eight consecutive rows of the first memory region will be stored in 8 bytes of a row of the second memory region.

[0027] In practice, the first memory region may comprise a plurality of first memory regions, such as but not limited to four first memory regions, each first memory region having the first memory size (e.g., 64 kilobits).

[0028] More particularly, as noted above, if p represents the number of bytes that can be stored in a row, the first memory region may comprise k times p first memory regions, and the second memory region may comprise k second memory regions (k is an integer greater than or equal to 1).

[0029] The memory device may be a volatile memory device, such as a static random access memory (SRAM), but may also be a non-volatile memory, such as an EEPROM memory, and these examples are not limiting.

[0030] According to another aspect, there is provided a method for managing the storage space of a memory device comprising a first memory region and a second memory region, the method comprising storing first data at a first address in the first region and, in accordance with a command, storing second data at a second address in the second memory region or storing error correction code parity bits associated with the first data at a third address in the second memory region.

[0031] According to one mode of implementation, the method comprises determining a third address based on the first address.

[0032] Determining the third address advantageously comprises truncating the first address.

[0033] According to one mode of implementation, the method includes: receiving first data and a first initial address associated with the first data; and possibly receiving second data and a second initial address associated with the second data; formulating a first address based on the first initial address and formulating a second address based on the second initial address; determining a check bit associated with the first data; determining a third address of the check bit; and delivering, according to a command, the second data and the second address or the check bit and the third address to a second memory region.

[0034] According to one mode of implementation, the first memory region includes at least one first memory bank having a first memory size, and the second memory region includes a second memory bank also having the first memory size.

[0035] According to one mode of implementation, the at least one first memory bank and the second memory bank include rows, and a check bit associated with first data stored in a first number of consecutive rows of the at least one first memory bank is stored in a second number of rows of the second memory bank, the second number being less than the first number.

[0036] According to one mode of implementation, each row of the at least one first memory bank and each row of the second memory bank are configured to store a word of p bytes, and a check bit associated with first data stored in p consecutive rows of the at least one first memory bank is stored in p bytes of a row of the second memory bank.

[0037] According to one mode of implementation, the first memory region includes a plurality of memory banks, each memory bank having the first memory size.

[0038] According to one mode of implementation, the first memory region includes k times p first memory banks, and the second memory region includes k second memory banks, where k is an integer greater than or equal to 1.

[0039] The memory device may be a volatile memory device. Description of the Drawings

[0040] Based on the detailed description of the fully non-limiting embodiments, modes of implementation of the present invention, and the drawings, other advantages and features of the present invention will become apparent, where:

[0041] Figure 1 An embodiment of a memory device in a first configuration according to the present invention is shown.

[0042] Figure 2 An embodiment of a memory device in a second configuration according to the present invention is shown.

[0043] Figure 3 An embodiment of a system according to the present invention is shown,

[0044] Figure 4 Partially shows a mode of implementation of a method according to the present invention,

[0045] Figure 5 Partially illustrates a mode of implementation of the method according to the present invention,

[0046] Figure 6 Partially shows a mode of implementation of the method according to the present invention, and

[0047] Figure 7 Partially shows an exemplary implementation of the present invention. Detailed Description

[0048] Modes of implementation and embodiments of the present invention relate to the management of storage space in a memory device, particularly to volatile memory devices, and in particular, for example, to static random access memory (SRAM) when the use of error correction codes is optional.

[0049] According to one mode of implementation and an embodiment, what is proposed is a memory that can store data and error correction check bits, and in some applications, if there is no requirement to use error correction codes, the memory can reuse the memory space provided for these check bits for the purpose of storing data.

[0050] According to one aspect, what is proposed is a system of a memory device including a first memory area and a second memory area. The first memory area is intended to store first data at a first address, and the second memory area is intended to store second data at a second address or store error correction code check bits associated with the first data at a third address according to a command.

[0051] In Figure 1 the figure, the reference numeral DMM identifies the memory device, and in this case, the memory device is a volatile memory device including a first memory area DM1 and a second memory area DM2.

[0052] The first memory area DM1 includes four memory areas sram1, sram2, sram3, and sram4 of the same memory size.

[0053] In the example illustrated herein, these memory areas are formed by separate static random access memories. That is to say, these memory areas can also be considered as memory areas of the same memory.

[0054] The second memory region DM 2 includes a memory area sram 5, which has the same memory size as the memory areas sram 1 to sram 4.

[0055] And in this situation, the memory area sram 5 is a static random access memory.

[0056] In the example described herein, the width of the memory device is equal to 32 bits, which means that the memory can store 32-bit data words each containing four bytes.

[0057] The memory size is equal to n kilobits (for example, 64 kilobits).

[0058] The memory areas sram 1 to sram 4 are intended to store data Data-mem-cut 1 to Data-mem-cut4 respectively.

[0059] In Figure 1 In the configuration illustrated in, the memory area sram 5 is intended to contain error correction code parity bits associated with the data stored in the memory areas sram 1 to sram 4.

[0060] This is performed based on the command of the signal SCECC (for example, the command has a logical value 1 in this situation).

[0061] Figure 2 Illustrated is another configuration of the memory device DMM, where this time, the memory area sram 5 is intended to store the second data Data-mem-cut 5.

[0062] This corresponds to a situation where the user may not wish to use the error correction code, but may instead wish to use the available space in the memory area sram 5 to store data therein.

[0063] In this situation, the control signal SCECC is equal to 0.

[0064] Now will refer more particularly to Figure 3 , in order to describe an embodiment of the system according to the present invention.

[0065] The system SYS includes an interface SRINT connected to the bus BSS, which can have any conventional structure and is, for example, an AHB bus using a protocol such as that described in the document ARM (2001, 2006) AMBA3 AHB-Lite Protocol V1.0 specification.

[0066] Specifically, the bus transfers the first data Data-mem-cut 1 to Data-mem-cut 4, the first initial address HADRR associated with the first data, the possible second data Add-memory-cut 5 and the second initial address HADRR, as well as other conventional bus signals, which are not shown here for simplicity.

[0067] The interface SRINT with a conventional structure known per se is configured to deliver the first address associated with the first data Data-mem-cut 1 to Data-mem-cut 4 and possibly to deliver the second address associated with the second data Data-mem-cut 2.

[0068] These first and second addresses are respectively extracted from the first and second initial addresses HADRR transmitted on the bus BSS.

[0069] The first and second addresses may be the same as the first initial address. That is, depending on the structure of the system and particularly on the width of the memory area, the first and second addresses may be obtained by truncating one or more bits based on the first and second initial addresses.

[0070] In the example described herein, a 32-bit word formed by 4 bytes of 8 bits each may be written to each row (where i is equal to 1, 2, 3, or 4) of the memory area sram i.

[0071] Thus, in this example, the reference numerals Add-mem-cut 1 to Add-mem-cut 4 represent the addresses of the rows of the memory areas sram1 to sram 4, and the reference numerals Mask-mem-cut 1 to Mask-mem-cut 4 represent the number of bytes in the indicated rows of the memory area under consideration.

[0072] Thus, the addresses Add-mem-cut 1 to Add-mem-cut 4 and the masks Mask-mem-cut 1 to Mask-mem-cut 4 form the first address.

[0073] Similarly, the address Add-mem-cut 5 and the mask Mask-mem-cut 5 form the second address associated with the second item of the data Data-mem-cut5.

[0074] The signals WEN-cut-1 to WEN-cut-4 and WEN-cut 5 are conventional control signals for writing to various memory areas, and the signals CSEN-cut 1 to CSEN-cut 4 and CSEN-cut 5 are conventional signals for selecting the memory areas under consideration.

[0075] The system SYS further includes an error correction code circuit MECC, which has a conventional and well-known structure per se, and the error correction code circuit MECC is configured to determine parity bits associated with the above-mentioned first data Data-mem-cut 1-4.

[0076] More precisely, for 4-byte words stored in the rows of memory areas sram 1 to sram 4, the reference sign S denotes the parity bit associated with the 4-byte word.

[0077] In the case of a 32-bit word, S is a 7-bit word. As a result, S can be stored in one byte of memory area sram 5.

[0078] If the width of the memory is 64 bits instead of 32 bits, S will have a length of 8 bits, which can still be stored in one byte of memory area sram 5.

[0079] As is conventional, in order to write a new 32-bit word to a row of one of the memory areas sram 1 to sram 4, the word already stored in that row will be read first among all.

[0080] Then, the error correction code circuit MECC determines a syndrome based on the set S of parity bits and the data bits.

[0081] Recall here that the syndrome is an intermediate calculation performed during error correction, enabling it to detect and locate errors.

[0082] If a bit is defective, the MECC block effectively detects the defective bit and corrects it.

[0083] Before writing the new word to the address of the previous word in the corresponding memory area, the MECC block will calculate a new set S of new parity bits corresponding to the new byte of data. When implementable in this regard, the new set S of parity bits is calculated using the corrected value of the defective bit.

[0084] Then the new word is written to the corresponding memory area at the corresponding first address.

[0085] As illustrated in Figure 3 the new set S of parity bits is delivered to the input of the multiplexer MX.

[0086] The system SYS further includes a processing circuit MT, configured to determine a third storage address for these parity bits S.

[0087] These parity bits S will be stored in memory area sram 5 in particular.

[0088] In this situation, the third address includes the address A-ecc of a row of the memory area sram 5, and a mask M-ecc for selecting one of four bytes in said row.

[0089] As will be seen in more detail below, these third addresses are determined based on the first address, and more precisely, these third addresses are determined based on the row addresses Add-mem-cut1 to Add-mem-cut 4.

[0090] The system SYS also includes a control circuit MCMD, which is configured to deliver the second data Data-mem-cut 5 and the associated second address Add-mem-cut 5, Mask-mem-cut 5 or parity bit S, and the third addresses A-ecc and M-ecc to the second memory area, that is to say in this situation to the memory area sram 5.

[0091] In this situation the control circuit MCMD includes a module BMCM, for example a logic check unit delivering a control signal SCECC, and a multiplexer MX receiving said control signal SCECC at its control input.

[0092] Of course, depending on the value of the signal SCECC, the signals WEN-cut 5 and CSEN-cut5 will also be delivered to the memory interface DM2INT coupled to the memory area sram 5.

[0093] In contrast, the signals WEN-cut 1 to WEN-cut 4 and CSEN-cut 1 to CSEN-cut 4 are only delivered in part to the interface SM1INT coupled to the first memory area DM 1.

[0094] Reference will now be made more particularly to Figures 4 to 7 , in order to illustrate a mode of implementation of the method according to the invention.

[0095] Figure 4 More specifically, it is illustrated how a first address associated with first data intended to be stored in the memory areas sram1 - sram4 is obtained based on a first initial address HADRR received by the memory interface SRINT.

[0096] In the example described here, the initial address HADDR is an address encoded on 18 bits b0 to b17.

[0097] Figure 4 The left part of illustrates these addresses in hexadecimal format.

[0098] The first address Add-mem-cut is obtained by truncating the two least significant bits b0 and b1 of the initial address.

[0099] Thus, in Figure 4 the right part of

[0100] illustrates these Add-mem-cut addresses in hexadecimal format.

[0101] More precisely, the value 0000 is the starting address of memory area sram 1, and the address 3FFF is the ending address of this memory area sram 1.

[0102] The address 4000 is the starting address of memory area sram 2, and the address 7FFF is the ending address of this memory area sram 2.

[0103] The address 8000 is the starting address of memory area sram 3, and the address BFFF is the ending address of this memory area sram 3.

[0104] Of course, the memory address Add-mem-cut 5 associated with the data that may be intended to be stored in memory area sram 5 is obtained in the same way as just described.

[0105] Figure 5 Illustrates an example of obtaining the third address A-ecc based on the first address Add-mem-cut.

[0106] More precisely, also in this case, the address Add-mem-cut is truncated by two bits in order to obtain the address A-ecc of the corresponding row in memory area sram 5.

[0107] More precisely, this truncation is the truncation of the two least significant bits b0 and b1 of the address Add-mem-cut.

[0108] The parity bit S is associated with the data stored in memory area sram 1, and thus will be written between the addresses 0000 and 0FFF of memory area sram 5.

[0109] The parity bit associated with the data written to memory area sram 2 will be stored between the addresses 1000 and 1FFF of memory area sram 5.

[0110] The parity bit associated with the data written to memory area sram 3 will be stored between the addresses 2000 and 2FFF of memory area sram 5.

[0111] Finally, the parity bits associated with the data written to memory area SRAM 4 will be stored between addresses 3000 and 3FFF of memory area SRAM5.

[0112] Finally, as illustrated in Figure 6 the mask M-ecc depends on the two least significant bits b0 and b1 of the address Add-mem-cut.

[0113] More precisely, if the two bits b0 and b1 are equal to 0, the first byte of M-ecc is equal to 1 while the other bits are equal to 0, which means that the first byte of the corresponding row is selected to store the parity bit S.

[0114] If the two bits b1 and b0 have the respective values 0 and 1, then this time the second byte of the mask M-ecc has the value 1, which means that the second byte of the row is selected to store the parity bit S.

[0115] If the bits b1 and b0 have the respective values 1 and 0, then this time the third byte of M-ecc has the value 1, which corresponds to the selection of the third byte of the corresponding row to store the parity bit.

[0116] Finally, if both of the two bits b1 and b0 have the value 1, the fourth byte of M-ecc has the value 1, which corresponds to the selection of the fourth byte of the corresponding row to store the parity bit.

[0117] Of course, this technique for determining M-ecc can also be applied to determining Mask-mem-cut 1 to Mask-mem-cut 4 as well as Mask-mem-cut 5, so as to select the corresponding byte in the address row for each byte of each data word to be stored.

[0118] Thus, for example, if the data byte expected to be stored at the initial address HADDR is equal to 0x2001ABC8, then after truncating the initial address, the first address will be equal to 6AF2, which corresponds to the first address Add-mem-cut 2 of the second memory area SRAM 2.

[0119] Regarding the 7-bit word of the word S that forms the parity bit associated with the new 32-bit word stored in the row, the address A-ecc of the corresponding row in memory area SRAM 5 has the value 1ABC after truncating the first address Add-mem-cut 2.

[0120] Since the two least significant bits b1 and b0 of the first address have the respective values 1 and 0, the mask M-ecc associated with the row address indicates the selection of the third byte of that row to store the verification word S.

[0121] Now will refer more specifically toFigure 7 to illustrate an exemplary implementation of the method according to the present invention.

[0122] In this example, it is assumed that all memory regions sram 1 to sram 2 and sram 5 have a memory size of 64 kilobits and a word width of 32 bits.

[0123] As a result, each memory region contains 2048 rows, and each row can contain a 32-bit (4-byte) word.

[0124] An error correction code is applied. Each check word is associated with a 32-bit data word containing 7 check bits.

[0125] By applying the address and mask determination rules described above, it can be seen that the set S11 of check bits associated with the four bytes OCT 01, OCT 11, OCT 21, and OCT 31 of the first row of memory region sram 1 will be stored in byte OCT 35 of the first row of memory region sram 5.

[0126] Similarly, the check bit word S21 is associated with the four bytes OCT 02, OCT 12, OCT 22, and OCT 32 of the second row of memory region sram 2 and will be stored in byte OCT 25 of the first row of memory region sram 5.

[0127] The check bit word S31 is associated with the four bytes OCT 03, OCT 13, OCT 23, and OCT 33 of the third row of memory region sram 3 and will be stored in byte OCT 15 of the first row of memory region sram 5.

[0128] Finally, the check bit word S41 is associated with the four bytes OCT 04, OCT 14, OCT24, and OCT 34 of the fourth row of memory region sram 4 and will be stored in byte OCT 05 of the first row of memory region sram 5.

[0129] And the process of storing the various check bit words associated with the various rows will continue.

[0130] Generally speaking, the four check bits associated with four consecutive words of four consecutive rows of memory region sram i (where i varies between 1 and 4) will be stored in only one and the same row of memory region sram 5.

[0131] Therefore, the check words associated with the 2048 rows of memory region sram 1 will be stored in 512 rows of memory region sram 5.

[0132] Also, after the 512 rows of the memory region sram 5 will be dedicated to storing the parity bits S i2 associated with the data stored in the memory region sram 2.

Claims

1. An electronic system, comprising: A memory device, comprising A first memory area for storing first data at a first address, and A second memory area for storing second data at a second address when a signal command is set to a first value, and configured to store an error correction code check bit associated with the first data at a third address when the signal command is set to a second value; the third address is a truncated first address; A processing circuit configured to determine the third address based on the first address.

2. The system according to claim 1, further comprising: An interface configured to receive the first data and a first initial address associated with the first data, and the second data and a second initial address associated with the second data, and deliver the first address and the second address based on the first initial address and the second initial address, An error correction code circuit configured to determine the error correction code check bit associated with the first data, and A control circuit configured to deliver any one of the following to the second memory area: The second data and the second address; or The error correction code check bit and the third address.

3. The system according to claim 1, wherein the first memory area comprises at least one first memory bank having a first memory size, and the second memory area comprises a second memory bank also having the first memory size.

4. The system according to claim 3, wherein the at least one first memory bank and the second memory bank comprise rows, wherein the first data is stored in a first number of consecutive rows of the at least one first memory bank, and wherein the error correction code check bit associated with the first data is stored in a second number of rows of the second memory bank, the second number being less than the first number.

5. The system according to claim 4, wherein each row of the at least one first memory bank and each row of the second memory bank are configured to store a word of p bytes, and the error correction code check bit associated with the first data stored in p consecutive rows of the at least one first memory bank is stored in the p bytes of the rows of the second memory bank.

6. The system according to claim 5, wherein the first memory area contains k times p first memory banks, and the second memory area comprises k second memory banks, k being an integer greater than or equal to 1.

7. The system according to claim 3, wherein the first memory area comprises a plurality of first memory banks, each of the plurality of first memory banks having the first memory size.

8. The system according to claim 1, wherein the memory device is a volatile memory device.

9. A memory device, comprising: A plurality of memory areas, including a first memory area and a second memory area, the first memory area being configured to store first data at a first address; An error correction code circuit configured to determine a parity bit associated with first data to be stored in the first memory region; and a control circuit configured to determine whether a signal command is set to a first value or a second value different from the first value; in response to determining that the signal command is set to the first value, delivering second data to be stored at a second address in the second memory region, and in response to determining that the signal command is set to the second value, delivering the parity bit to be stored at a third address in the second memory region determined based on the first address.

10. The memory device according to claim 9, wherein the first memory region includes at least one first memory bank having a first memory size, and the second memory region includes a second memory bank also having the first memory size.

11. The memory device according to claim 10, further comprising a processing circuit configured to determine the third address for the parity bit, wherein the at least one first memory bank and the second memory bank include rows, wherein the first data is stored in a first number of consecutive rows of the at least one first memory bank, and wherein the parity bit associated with the first data is stored in a second number of rows of the second memory bank, the second number being less than the first number.

12. The memory device according to claim 11, wherein each row of the at least one first memory bank and each row of the second memory bank is configured to store a word of p bytes, and wherein the parity bit associated with the first data stored in p consecutive rows of the at least one first memory bank is stored in the p bytes of the row of the second memory bank.

13. The memory device according to claim 12, wherein the first memory region contains k times p first memory banks, and the second memory region includes k second memory banks, k being an integer greater than or equal to 1.

14. A method for managing a memory space of a memory device, the method comprising: storing first data at a first address in a first memory region of the memory device; in response to determining that a signal command is set to a first value, storing second data at a second address in a second memory region of the memory device; in response to determining that the signal command is set to a second value different from the first value, storing an error correction code parity bit associated with the first data at a third address in the second memory region, and determining the third address based on the first address, wherein determining the third address includes: truncating the first address.

15. The method according to claim 14, further comprising: receiving the first data and a first initial address associated with the first data, and receiving the second data and a second initial address associated with the second data; formulating the first address based on the first initial address, and formulating a second address based on the second initial address; Determine the error correction code check bits associated with the first data; Determine the third address of the error correction code check bits; and In response to determining that the signal command is set to the first value or the second value, deliver the second data and the second address or the error correction code check bits and the third address to the second memory region.

16. The method according to claim 14, wherein the first memory region includes at least one first memory bank having a first memory size, and the second memory region includes a second memory bank also having the first memory size.

17. The method according to claim 16, wherein the at least one first memory bank and the second memory bank include rows, wherein the first data is stored in a first number of consecutive rows of the at least one first memory bank, and the error correction code check bits associated with the first data are stored in a second number of rows of the second memory bank, the second number being less than the first number.

18. The method according to claim 17, wherein each row of the at least one first memory bank and each row of the second memory bank are configured to store words of p bytes, and the error correction code check bits associated with the first data stored in p consecutive rows of the at least one first memory bank are stored in the p bytes of the rows of the second memory bank.

19. The method according to claim 18, wherein the first memory region includes k times p first memory banks, and the second memory region includes k second memory banks, k being an integer greater than or equal to 1.

20. The method according to claim 16, wherein the first memory region includes a plurality of memory banks, each of the plurality of memory banks having the first memory size.

21. The method according to claim 14, wherein the memory device is a volatile memory device.

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