Interconnection method of semiconductor structure and semiconductor structure

Abstract

The present disclosure provides an interconnection method and a semiconductor structure for a semiconductor structure. The interconnection method includes: providing a stacking structure, the stacking structure includes multiple layers of bonded wafers or chips, each layer of the wafers or chips includes a substrate and a wiring layer, the wiring layer includes multiple metal wires; forming a through silicon via in the stacking structure, the through silicon via is connected to a first number of metal wires; insulating a second number of metal wires connected to the through silicon via, the second number is less than the first number; filling the through silicon via with a conductive material. The interconnection method disclosed in the present disclosure can produce a semiconductor structure that electrically connects each layer of wafers or chips in the stacking structure through a single mask etching process.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit manufacturing, and in particular to a semiconductor structure interconnection method and a semiconductor structure. Background Art

[0002] In the process of integrated circuit manufacturing, stacking multiple chips and establishing mechanical and electrical connections is an important method to reduce the size of integrated circuits. The current practice usually involves first making TSVs (Through Silicon Vias) for each chip to be stacked, then forming a bump (Micro-Bump) for each TSV, and finally using a chip-to-chip or chip-to-wafer method for positioning and bonding, and using each bump and TSV to achieve electrical connection between the upper chip and the lower chip.

[0003] First, the low efficiency in the chip-to-chip or chip-to-wafer bonding process leads to high costs. In addition, each chip needs to be pre-made with TSV and bumps. There is a high risk of positioning errors and connection errors during the bonding process, which can easily lead to disconnection of the electrical connection path between the upper and lower chips, resulting in a decrease in the yield rate.

[0004] Therefore, a solution for inter-chip electrical connection that can overcome the above problems is needed.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] The purpose of the present disclosure is to provide an interconnection method and a semiconductor structure for a semiconductor structure, which are used to at least to a certain extent overcome the problems of complex semiconductor structure manufacturing procedures and low yield rate caused by the limitations and defects of related technologies.

[0007] According to a first aspect of the present disclosure, a method for interconnecting a semiconductor structure is provided, comprising:

[0008] Providing a stacked structure, the stacked structure comprising multiple layers of bonded wafers or chips, each layer of the wafer or chip comprising a substrate and a wiring layer, the wiring layer comprising a plurality of metal wires;

[0009] Forming a through silicon via in the stacked structure, wherein the through silicon via is connected to a first number of the metal wires;

[0010] Insulating a second number of the metal wires connected to the through silicon vias, the second number being smaller than the first number;

[0011] Filling the through silicon via with a conductive material.

[0012] In an exemplary embodiment of the present disclosure, forming a through silicon via in the stacked structure includes:

[0013] m first blind holes H1n having a first diameter and a length L1n are vertically formed on the stacked structure, wherein the penetration position of each first blind hole in each layer of the wafer or chip is located between the metal wires, and the first diameter is smaller than the spacing between the metal wires, and L1n is smaller than the height L0 of the stacked structure, wherein n is a sequence number;

[0014] Etching a second blind hole H2n having a second diameter and a length L2n on the upper portion of the first blind hole H1n, wherein the sidewall of the second blind hole exposes end surfaces of a first number of the metal wires;

[0015] The second blind hole is filled with a mask material.

[0016] In an exemplary embodiment of the present disclosure, the insulating process of the second number of metal wires connected to the through silicon vias comprises:

[0017] Etching a third blind hole H3n having the second diameter and a length L3n on the upper portion of the second blind hole H2n, wherein the sidewall of the third blind hole exposes the end surface of the metal wire;

[0018] The end surface of the metal wire in the third blind hole is insulated.

[0019] In an exemplary embodiment of the present disclosure, the step of forming a second blind hole H2n having a second diameter and a length L2n on the upper portion of the first blind hole H1n includes:

[0020] Applying a mask material to the insides of the m first blind holes and the upper surface of the stacked structure;

[0021] Performing dry etching on the masks on the upper portions of the m first blind holes to remove the masks having a length of L2n from top to bottom in the first blind holes H1n;

[0022] A second blind hole H2n having the second diameter and a length L2n is formed at a portion of the first blind hole H1n where the mask is removed, so that the sidewall of the second blind hole exposes the end surface of the metal wire.

[0023] In an exemplary embodiment of the present disclosure, the dry etching of the mask on the upper portion of the m first blind holes to remove the mask having a length L2n from top to bottom in the first blind hole H1n includes repeating the following steps:

[0024] Removing a mask having a width L3 on the upper surface of the stacked structure directly facing the first blind hole H1n through a photolithography process;

[0025] The mask having a length L2n is removed from top to bottom in the first blind hole H1n by a dry stripping process.

[0026] In an exemplary embodiment of the present disclosure, the step of removing the mask from the first blind hole H1n to form the second blind hole H2n having the second diameter and the length L2n includes:

[0027] Widening the portion of the first blind hole H1n in the x-layer wafer or chip substrate to the second diameter by a first wet etching process, wherein the x-layer wafer or chip substrate is within the length range of the first blind hole removal mask;

[0028] The first blind hole H1n is partially widened to the second diameter in the wiring layer of the x-layer wafer or chip through a second wet etching process to expose the end surface of the metal wire, thereby forming the second blind hole H2n.

[0029] In an exemplary embodiment of the present disclosure, the filling of the conductive material in the through silicon via comprises:

[0030] Making a dielectric isolation layer on the inner surfaces of the first blind hole and the second blind hole;

[0031] The dielectric isolation layer at the location of the effective metal wire is etched by a plasma dry etching process to expose the end surface, a part of the upper surface and the bottom of the first blind hole of the effective metal wire.

[0032] Sputtering a seed metal onto the inner wall and the bottom of the first blind hole and the second blind hole, wherein the seed metal comprises copper;

[0033] A metal is grown in the first blind hole and the second blind hole, wherein the metal includes copper.

[0034] In an exemplary embodiment of the present disclosure, it further includes:

[0035] Grinding the bottom layer of the stacked structure to expose the conductive material filled at the bottom of the through silicon via;

[0036] Producing bumps on the surface of the conductive material.

[0037] In an exemplary embodiment of the present disclosure, the cross-sectional shape of the through silicon via includes a circle, a polygon and an irregular shape.

[0038] In an exemplary embodiment of the present disclosure, the insulation treatment includes oxidation, quality change, phase change, dry / wet etching, laser / high temperature destruction, and isolation layer coating on the end surface of the metal wire.

[0039] According to a second aspect of the present disclosure, there is provided a semiconductor structure, comprising:

[0040] A stacked structure, the stacked structure comprising multiple layers of bonded wafers or chips, each layer of the wafers or chips comprising a substrate and a wiring layer, the wiring layer comprising a plurality of metal wires;

[0041] m through silicon vias, which are manufactured in an exemplary embodiment of the present disclosure and penetrate the stacked structure, wherein the center of the penetration position on each layer of the wafer or chip is located between the metal wires, and the through silicon vias include:

[0042] A first portion having a first diameter smaller than a pitch of the metal wires;

[0043] A second portion having a second diameter greater than the pitch of the metal wires, coupled to the upper surface of the first portion and aligned with the center of the first portion, and having a sidewall intersecting with a first number of the metal wires;

[0044] The third portion is formed after the second portion and located above the second portion, and is formed by performing an invalidation treatment on a second number of the metal wires on the sidewall of the second portion, wherein the second number is smaller than the first number.

[0045] In an exemplary embodiment of the present disclosure, the cross-sectional shape of the through silicon via includes a circle, a polygon and an irregular shape.

[0046] The interconnection method for semiconductor structures provided by the embodiments of the present disclosure manufactures blind holes that penetrate the stacked structure on the bonded wafers or chips, and expands the blind holes by wet etching to expose the wire end faces of the preset wafers or chips in the stacked structure, then insulates part of the wire end faces, and finally fills the blind holes with conductive materials to form TSVs connecting the preset wires. A relatively complex interconnection structure between different wafers or chips can be manufactured through a single etching process, avoiding the problems of complex processes and low connection yield caused by the use of bumps to achieve electrical connection between chips in the related art.

[0047] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0049] Figure 1A to Figure 1DThey are respectively a main flow chart of the interconnection method in the exemplary embodiment of the present disclosure and sub-flow charts of step S2, step S3, and step S4.

[0050] Figure 2 is a schematic diagram of step S1.

[0051] Figure 3 is a schematic diagram of step S21.

[0052] Figure 4 This is a flowchart of step S22.

[0053] Figure 5 It is a schematic diagram of step S221.

[0054] Figure 6A to Figure 6E It is a schematic diagram of step S222.

[0055] FIG. 7A to FIG. 7D It is a schematic diagram of step S223.

[0056] Figure 8 It is a schematic diagram of step S23.

[0057] Fig. 9 is a schematic diagram of step S31.

[0058] Fig.10 It is a schematic diagram of step S32.

[0059] Fig.11 is a schematic diagram of step S41.

[0060] Figures 12A to 12G It is a schematic diagram of steps S42 to S45.

[0061] Fig.13 It is a schematic diagram of the conductive path in the completed interconnect structure.

[0062] Figure 14A to Figure 14B is a schematic diagram of step S5.

[0063] Fig.15 It is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0064] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0065] In addition, the accompanying drawings are only schematic diagrams of the present disclosure, and the same reference numerals in the drawings represent the same or similar parts, so their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities, which do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0066] The exemplary embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0067] Figure 1A The flowchart of the semiconductor interconnection method in the exemplary embodiment of the present disclosure is schematically shown. Figure 1A , the interconnection method 100 may include:

[0068] Step S1, providing a stacking structure, wherein the stacking structure includes multiple layers of bonded wafers or chips, each layer of the wafer or chip includes a substrate and a wiring layer, and the wiring layer includes multiple metal wires;

[0069] Step S2, forming a through silicon via in the stacked structure, wherein the through silicon via is connected to a first number of metal wires;

[0070] Step S3, performing insulation treatment on a second number of the metal wires connected to the through silicon vias, wherein the second number is smaller than the first number;

[0071] Step S4, filling the through silicon via with a conductive material.

[0072] The interconnection method for semiconductor structures provided by the embodiments of the present disclosure manufactures blind holes that penetrate the stacked structure on the bonded wafers or chips, and expands the blind holes by wet etching to expose the wire end faces of the preset wafers or chips in the stacked structure, then insulates part of the wire end faces, and finally fills the blind holes with conductive materials to form TSVs connecting the preset wires. A relatively complex interconnection structure between different wafers or chips can be manufactured through a single etching process, avoiding the problems of complex processes and low connection yield caused by the use of bumps to achieve electrical connection between chips in the related art.

[0073] Next, each step of the interconnection method 100 is described in detail.

[0074] Figure 2 is a schematic diagram of the stacking structure 200 provided in step S1. It can be understood that Figure 2 The process of manufacturing the stacked structure 200 (such as bonding the wafers or chips) may also be included before, which will not be described in detail in the present disclosure.

[0075] refer to Figure 2 The stacking structure may include a wafer stacking structure and a chip stacking structure, preferably a wafer stacking structure. Each layer of wafers or chips in the stacking structure 200 includes a substrate A and a wiring layer B, and the wiring layer B includes a plurality of metal wires 21. The purpose of the embodiment of the present disclosure is to connect the metal wires 21 corresponding to the positions of each layer by making a TSV to achieve electrical connection between the layers of wafers or chips. Figure 2 In the process, each wafer or chip is directly bonded, avoiding the cumbersome process of first making TSV and then making bumps in the related technology.

[0076] Figure 3 to Figure 8 is a schematic diagram of forming a through silicon via on the stacked structure 200 in step S2.

[0077] refer to Figure 1B In some embodiments, forming a through silicon via on the stack structure 200 may include:

[0078] Step S21, vertically forming m first blind holes with a first diameter and a length of L1n on the stacked structure, wherein the penetration position of each first blind hole in each layer of the wafer or chip is located between the metal wires, and the first diameter is smaller than the spacing between the metal wires, and L1n is smaller than the height L0 of the stacked structure, where n is a sequence number;

[0079] Step S22, etching a second blind hole H2n having a second diameter and a length L2n on the upper portion of the first blind hole H1n, wherein the sidewall of the second blind hole exposes end surfaces of a first number of the metal wires;

[0080] Step S23, filling the second blind hole with a mask material.

[0081] in, Figure 3 FIG. 1 is a schematic diagram of step S21 of vertically forming m first blind holes H1n having a first diameter D1n and a length L1n on the stacked structure. Figure 3 , the penetration position of each first blind hole H1n in each layer of wafer or chip is located between the metal wires 21, and the first diameter D1n is smaller than the spacing DLn of the metal wires, and the length L1n of the first blind hole is smaller than the height L0 of the stacked structure. The first diameter D1n of each first blind hole can be determined according to the spacing DLn of the corresponding metal wires, as long as the difference between D1n and DLn is greater than the preset safety distance to avoid etching the metal wires.

[0082] The first blind hole can be manufactured by, for example, coating, photolithography, developing, etching and other related processes, and the present disclosure does not impose any special limitation on this.

[0083] Figure 4 This is a flow chart of step S22 of etching a second blind hole having a second diameter and a length L2n on the upper portion of the first blind hole H1n.

[0084] refer to Figure 4 , step S22 may include:

[0085] Step S221, coating the inside of the m first blind holes and the upper surface of the stacked structure with a mask material;

[0086] Step S222, dry etching the masks on the upper portions of the m first blind holes to remove the masks having a length of L2n from top to bottom in the first blind holes H1n;

[0087] Step S223, forming a second blind hole having the second diameter and a length L2n at the portion of the first blind hole H1n where the mask is removed, so that the sidewall of the second blind hole exposes the end surface of the metal wire.

[0088] Figure 5 Schematic diagram of step S221 of coating the inside of m first blind holes and the upper surface of the stacked structure with a mask 22. The mask material may be, for example, SiN, SiO2, etc., and the coating mask may be, for example, deposited on the inside of each first blind hole and the upper surface of the stacked structure by a CVD (Chemical Vapor Deposition) process to form an inorganic thin film.

[0089] Figure 6A to Figure 6E 1 is a schematic diagram of sequentially dry-etching the masks on the upper portions of the m first blind holes to remove the masks having a length of L2n from top to bottom in the first blind hole H1n.

[0090] refer to Fig. 6AFirst, a mask with a width of Lw is removed from the upper surface of the stacked structure directly facing the nth first blind hole through a photolithography process, for example, by coating a photoresist 23 to locate the position for removing the mask.

[0091] refer to Figure 6B ,exist Fig. 6A After the process shown, a dry stripping process is used to remove the mask with a length of L2n from top to bottom in the first blind hole H1n. In this step, the mask removal length corresponding to each first blind hole can be determined according to the number of layers x of the wafer or chip to be connected.

[0092] refer to Figure 6C to Figure 6E Repeat the above process until the dry etching of m first blind holes is completed. Figure 6C , repeat the photolithography by applying the glue; Fig.6D , dry-etch the next first blind hole; Fig. 6E After completing the dry etching of all the first blind holes, the photoresist is removed.

[0093] FIG. 7A to FIG. 7D The schematic diagram of step S223 is to remove the mask in each first blind hole to form a second blind hole H2n with a second diameter D2n and a length L2n, so that the sidewall of the second blind hole H2n exposes the end surface of the metal wire. The second diameter D2n is greater than the corresponding spacing DLn of the metal wire.

[0094] refer to Fig. 7A First, the first blind hole H1n located in the x-layer wafer or chip substrate A can be widened to a second diameter D2n by a first wet etching process. The first wet etching process supports, for example, a substrate A having an etching width of D2n-D1n by pouring a first preset dose of a first etching solution into the first blind hole H1n. The type and dose of the first etching solution can be set according to the substrate type.

[0095] refer to Figure 7B ,exist Fig. 7A On the basis of the process shown, the portion of the first blind hole H1n located in the wiring layer B of the x-layer wafer or chip is widened to a second diameter D2n through a second wet etching process to expose the end surface of the metal wire 21, thereby forming a second blind hole H2n. The second wet etching process is, for example, to etch the dielectric portion of the wiring layer B with a width of D2n-D1n by injecting a second preset dose of a second etching solution into the first blind hole H1n. The type and dose of the second etching solution can be set according to the type of the dielectric, and the dielectric is, for example, SiO2 or Si3N4.

[0096] exist Fig. 7A and Figure 7BIn the embodiment, the second diameter D2n can be determined according to the spacing DLn of the metal wires, as long as the difference between D2n and DLn is within a preset range so as to expose the end surface of the metal wire 21.

[0097] Figure 7C and Fig.7D They are Fig. 7A and Figure 7B Schematic diagram of the cross-sectional changes of the second blind hole H2n during the manufacturing process shown. Figure 7C ,exist Fig. 7A In the process shown, the diameter of the blind hole in substrate A changes from small to large. Fig.7D ,exist Figure 7B In the process shown, after the blind hole diameter is enlarged, the middle part of the wiring layer B is etched away, exposing the end surface of the metal wire 21. Figure 7C and Fig.7D Taking the cross-sectional shape of the first blind hole and the second blind hole as a circle as an example, in other embodiments of the present disclosure, the cross-sectional shape of the first blind hole and the second blind hole may also include a polygon, an irregular shape, a parallelogram (rhombus or square), a rounded quadrilateral, etc., and the present disclosure does not impose any special limitation on this.

[0098] Figure 8 2 is a schematic diagram of filling the second blind hole with a mask material in step S23. The process of filling the mask material in step S23 is the same as that in step S221, and the disclosure will not repeat it here.

[0099] Fig. 9 and Fig.10 It is a schematic diagram of insulating part of the metal wire connected to the through silicon via in step S3.

[0100] refer to Figure 1C In some embodiments, step S3 may include:

[0101] Step S31, making a third blind hole having the second diameter and a length L3n on the upper portion of the second blind hole H2n, wherein the side wall of the third blind hole exposes the end surface of the metal wire;

[0102] Step S32, performing insulation treatment on the end surface of the metal wire in the third blind hole.

[0103] Fig. 9 Schematic diagram of step S31 of making a third blind hole having the second diameter and a length L3n on the upper part of the second blind hole H2n. For different wire connection schemes, the lengths of the third blind holes made in different second blind holes are not exactly the same. The mask filled in the second blind hole can be etched by a dry etching process to form the third blind hole.

[0104] Fig.10It is a schematic diagram of insulating the end face of the metal wire in the third blind hole in step S32. If a first number of metal wires are exposed on the side wall of the second blind hole, a second number of metal wires can be insulated in this step, wherein the second number is less than the first number, so as to form a third blind hole whose length is less than the second blind hole. In order to prevent the wire exposed on the upper part of the second blind hole from participating in the conduction and thus affecting the implementation of the wire connection scheme, in this step, the metal wire can be insulated by insulation treatment methods such as oxidation, qualitative change, phase change, dry / wet etching, laser / high temperature destruction and coating with an isolation layer. For example, an invalid solution is poured into each third blind hole to insulate the end face of the metal wire exposed on the side wall of the third blind hole. There can be multiple invalid solutions. In the embodiment of the present disclosure, a hydrogen peroxide solution is used. Those skilled in the art can set the insulation treatment method according to actual conditions.

[0105] Figure 11 to Figure 12G is a schematic diagram of the process of filling the through silicon via with a conductive material in step S4.

[0106] refer to Figure 1D In some embodiments, step S4 may include:

[0107] Step S41, removing the mask material in the first blind hole and the second blind hole;

[0108] Step S42, forming a dielectric isolation layer on the inner surfaces of the first blind hole, the second blind hole and the third blind hole;

[0109] Step S43, etching the dielectric isolation layer at the effective metal wire position by a plasma dry etching process to expose the end surface, a portion of the upper surface and the bottom of the first blind hole of the effective metal wire;

[0110] Step S44, sputtering a seed metal onto the inner wall and bottom of the first blind hole, the second blind hole and the third blind hole, wherein the seed metal comprises copper;

[0111] Step S45 , growing metal in the first blind hole, the second blind hole and the third blind hole, wherein the metal includes copper.

[0112] Fig.11 It is a schematic diagram of removing the mask material in the first blind hole, the second blind hole and the third blind hole in step S41.

[0113] refer to Fig.11 When the ineffective treatment of the metal wire is performed by an ineffective solution, each blind hole can be firstly cleaned with water and then heated to remove the ineffective solution. Then, the mask material of each blind hole is removed by using a wet etching process with different material selection ratios. In addition, the removal of all masks and ineffective solutions can be performed by other methods, which are not particularly limited in the present disclosure.

[0114] Figures 12A to 12G It is a schematic diagram of filling the first blind hole, the second blind hole and the third blind hole with conductive material in steps S42 to S45.

[0115] exist Fig. 12A In the embodiment, if the conductive material is to be filled into the first blind hole, the second blind hole and the third blind hole, it is first necessary to form a dielectric isolation layer 24 on the inner surfaces of the first blind hole, the second blind hole and the third blind hole. The process of forming the dielectric isolation layer 24 may be, for example, depositing an isolation medium such as SiCN on the surface of the etched material through a chemical vapor deposition process, so that the dielectric isolation layer 24 covers the inner surfaces of the first blind hole H1n, the second blind hole H2n and the third blind hole H3n and the upper surface of the stacked structure.

[0116] exist Fig. 12B In the process, the dielectric isolation layer is etched to expose the end surface of the metal wire 21 and the bottom of the first blind hole.

[0117] Fig. 12C yes Fig. 12B A magnified view of the process shown. Fig. 12C , the dielectric isolation layer 24 at the metal wire position can be etched by a plasma dry etching process to expose the end surface, part of the upper surface and the bottom of the first blind hole H1n of the effective metal wire 21. At this time, the lower surface of the metal wire and the dielectric isolation layer on the side wall of the second blind hole cannot be seen in the cross section of the second blind hole at the metal wire position.

[0118] Fig.12D It is a schematic diagram of sputtering the seed metal 25 on the inner wall and the bottom of the first blind hole, the second blind hole and the third blind hole. The seed metal 25 includes copper, for example. Fig.12E yes Fig.12D A magnified view of the process shown. Fig.12E The sputtering position of the seed metal 25 may include the side walls of the first blind hole, the second blind hole and the third blind hole, the upper surface and side surface of the metal wire end surface, and the bottom of the first blind hole, so that tantalum or copper can be re-covered on the metal wire so that the subsequently filled copper can be connected to the metal.

[0119] Fig.12F It is a schematic diagram of growing metal 26 in the first blind hole, the second blind hole and the third blind hole. In this process, the metal is, for example, copper or tungsten, and the process of growing the metal is, for example, electroplating.

[0120] Figure 12G yes Fig.12F A cross-sectional top view of the process shown.

[0121] Fig.13 It is a schematic diagram of the conductive path in the completed interconnect structure.

[0122] Referring to FIG. 14 , by insulating the metal wires on the upper portion of the second blind hole, these wires are prevented from participating in conduction, thereby realizing a complex interconnection structure in a multi-layer wafer or chip.

[0123] Figure 14A to Figure 14B is a schematic diagram of another step S5 of the interconnection method in an embodiment.

[0124] Step S5 may include Fig.14A The bottom layer of the stacked structure is grinded to expose the conductive material filled at the bottom of each through silicon via, and Fig. 14B The bumps 27 are shown formed on the surface of the conductive material. This process can prepare a structure that is interconnected with other stacked structures.

[0125] Through the above process, the different TSVs formed at the same time can realize electrical connection between metal wires in different layers of wafers or chips, overcoming the shortcomings of related technologies such as complex process, high cost and low yield when realizing electrical connection of stacked structures by making bumps, thereby improving the manufacturing efficiency of 3D integrated circuits.

[0126] Fig.15 It is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure.

[0127] refer to Fig.15 , the semiconductor structure 1500 may include:

[0128] A stacking structure 151, the stacking structure includes multiple layers of bonded wafers or chips, each layer of wafers or chips includes a substrate and a wiring layer, and the wiring layer includes multiple metal wires 152;

[0129] m through silicon vias (TSVs) are made by the above interconnection method, penetrating the stacked structure, and the center of the penetration position on each layer of wafer or chip is located between metal wires. The through silicon vias include:

[0130] The first portion H1n has a first diameter D1n smaller than the pitch DLn of the metal wires;

[0131] The second portion H2n has a second diameter D2n greater than the spacing DLn of the metal wires, is coupled to the upper surface of the first portion H1n and is aligned with the center of the first portion H1n, and has a sidewall intersecting with the first number of the metal wires 21;

[0132] The third portion H3n is formed after the second portion H2n and located above the second portion H2n, and is formed by performing invalidation treatment on a second number of the metal wires on the sidewalls of the second portion H2n, where the second number is smaller than the first number.

[0133] The main body of the through silicon via TSV includes metals such as copper and tungsten, and the outer insulating material 153 includes tantalum, tantalum nitride, silicon carbonitride, etc. The cross-section of the through silicon via TSV includes but is not limited to circle, quadrilateral (square, rectangle, parallelogram, rhombus), polygon and other irregular shapes.

[0134] The semiconductor structure provided by the embodiment of the present disclosure does not have bumps between the chips, and can complete multiple metal interconnect structures connecting chips in different layers through a single TSV process, thereby avoiding problems such as misalignment and connection defects that are easily caused by electrical connection between chips through bumps in related technologies, thereby improving the efficiency and yield of manufacturing 3D integrated circuits.

[0135] In addition, the above-mentioned figures are only schematic illustrations of the processes included in the method according to an exemplary embodiment of the present invention, and are not intended to be limiting. It is easy to understand that the processes shown in the above-mentioned figures do not indicate or limit the time sequence of these processes. In addition, it is also easy to understand that these processes can be performed synchronously or asynchronously, for example, in multiple modules.

[0136] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are to be considered exemplary only, and the true scope and concept of the present disclosure are indicated by the claims.

Claims

1. A method for interconnecting a semiconductor structure, characterized in that: include: Providing a stacked structure, the stacked structure comprising multiple layers of bonded wafers or chips, each layer of the wafer or chip comprising a substrate and a wiring layer, the wiring layer comprising a plurality of metal wires; Forming a through silicon via in the stacked structure, wherein the through silicon via is connected to a first number of the metal wires; Insulating a second number of the metal wires connected to the through silicon vias, the second number being smaller than the first number; Filling the through silicon via with a conductive material.

2. The interconnection method according to claim 1, characterized in that: The forming of a through silicon via in the stacked structure comprises: m first blind holes H1n having a first diameter and a length L1n are vertically formed on the stacked structure, wherein the penetration position of each first blind hole in each layer of the wafer or chip is located between the metal wires, and the first diameter is smaller than the spacing between the metal wires, and L1n is smaller than the height L0 of the stacked structure, wherein n is a sequence number; Etching a second blind hole H2n having a second diameter and a length L2n on the upper portion of the first blind hole H1n, wherein the sidewall of the second blind hole exposes end surfaces of a first number of the metal wires; The second blind hole is filled with a mask material.

3. The interconnection method according to claim 2, characterized in that: The insulating process of the second number of metal wires connected to the through silicon vias comprises: Etching a third blind hole H3n having the second diameter and a length L3n on the upper portion of the second blind hole H2n, wherein the sidewall of the third blind hole exposes end surfaces of a second number of the metal wires; The end surface of the metal wire in the third blind hole is insulated.

4. The interconnection method according to claim 2, characterized in that: The step of forming a second blind hole H2n having a second diameter and a length L2n on the upper portion of the first blind hole H1n comprises: Applying a mask material to the insides of the m first blind holes and the upper surface of the stacked structure; Performing dry etching on the masks on the upper portions of the m first blind holes to remove the masks having a length of L2n from top to bottom in the first blind holes H1n; A second blind hole H2n having the second diameter and a length L2n is formed at a portion of the first blind hole H1n where the mask is removed, so that the sidewall of the second blind hole exposes the end surface of the metal wire.

5. The interconnection method according to claim 4, characterized in that: The dry etching of the mask on the upper part of the m first blind holes to remove the mask with a length of L2n from top to bottom in the first blind hole H1n includes repeating the following steps: Removing a mask having a width L3 on the upper surface of the stacked structure directly facing the first blind hole H1n through a photolithography process; The mask having a length L2n is removed from top to bottom in the first blind hole H1n by a dry stripping process.

6. The interconnection method according to claim 4, characterized in that: The step of removing the masked portion in the first blind hole H1n to form the second blind hole H2n having the second diameter and the length L2n comprises: Widening the portion of the first blind hole H1n in the x-layer wafer or chip substrate to the second diameter by a first wet etching process, wherein the x-layer wafer or chip substrate is within the length range of the first blind hole removal mask; The first blind hole H1n is partially widened to the second diameter in the wiring layer of the x-layer wafer or chip through a second wet etching process to expose the end surface of the metal wire, thereby forming the second blind hole H2n.

7. The interconnection method according to claim 3, characterized in that: The filling of the conductive material in the through silicon via comprises: removing the mask material in the first blind hole and the second blind hole; Making a dielectric isolation layer on the inner surfaces of the first blind hole, the second blind hole and the third blind hole; Etching the dielectric isolation layer at the location of the effective metal wire by a plasma dry etching process to expose the end surface, a portion of the upper surface and the bottom of the first blind hole of the effective metal wire; Sputtering a seed metal onto inner walls and bottoms of the first blind hole, the second blind hole, and the third blind hole, wherein the seed metal comprises copper; A metal is grown in the first blind hole, the second blind hole and the third blind hole, wherein the metal includes copper.

8. The interconnection method according to claim 1, characterized in that: Also includes: Grinding the bottom layer of the stacked structure to expose the conductive material filled at the bottom of the through silicon via; Producing bumps on the surface of the conductive material.

9. The interconnection method according to claim 1, characterized in that: The cross-sectional shapes of the through silicon via include circular, polygonal and irregular shapes.

10. The interconnection method according to claim 1, characterized in that: The insulation treatment includes oxidation, quality change, phase change, dry / wet etching, laser / high temperature destruction and isolation layer coating on the end surface of the metal wire.

11. A semiconductor structure, characterized in that: include: A stacked structure, the stacked structure comprising multiple layers of bonded wafers or chips, each layer of the wafers or chips comprising a substrate and a wiring layer, the wiring layer comprising a plurality of metal wires; m through silicon vias, penetrating the stacked structure, the through silicon vias being located between the metal wires, and the through silicon vias comprising: A first portion having a first diameter smaller than a pitch of the metal wires; A second portion having a second diameter greater than the pitch of the metal wires, coupled to the upper surface of the first portion and aligned with the center of the first portion, and having a sidewall intersecting with a first number of the metal wires; The third portion is formed after the second portion and located above the second portion, and is formed by performing an invalidation treatment on a second number of the metal wires on the sidewall of the second portion, wherein the second number is smaller than the first number.

12. The semiconductor structure according to claim 11, wherein: The cross-sectional shapes of the through silicon via include circular, polygonal and irregular shapes.

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