Body bias circuit for current steering DAC switches

Abstract

A device comprising a digital-to-analog converter (DAC) and an independently controlled bias circuit coupled to the DAC. The DAC comprises at least a first transistor and a second transistor, wherein the first transistor and the second transistor are configured to provide an output signal for the DAC. The bias circuit comprises a third transistor having a body coupled to a source of the third transistor, and the source is coupled to a first transistor body and a second transistor body of the first transistor and the second transistor of the DAC. A current loop is coupled to the source and the drain of the transistor of the bias circuit, the transistor maintaining substantially the same current value in the bias circuit as in the DAC.

Description

Technical Field

[0001] The present invention relates generally to digital-to-analog converters (DACs), and more particularly to current steering and feedback DACs for applications such as delta-sigma modulators. Background Art

[0002] The DAC is part of the feedback loop in the ΔΣ modulator. Any nonlinearity in the DAC will directly degrade the linearity of the ΔΣ modulator at low and intermediate frequencies. Therefore, a highly linear DAC is required when used in high performance ΔΣ modulators.

[0003] The performance of modern integrated circuits is often limited by power consumption considerations. Integrated circuits typically use complementary metal oxide semiconductor (CMOS) transistor technology, such as n-channel metal oxide semiconductor (NMOS) and p-channel metal oxide semiconductor (PMOS) transistors. Typically, NMOS and PMOS integrated circuits have four terminals, including a drain, a source, a gate, and a body. The body terminal, sometimes referred to as a well terminal or a body terminal, can be biased to improve transistor performance. For example, a positive bias voltage can be applied to the body of a PMOS transistor, and a negative bias voltage can be applied to the body of an NMOS transistor to change the threshold voltage of each transistor and therefore the performance of each transistor. The body bias voltage should generally be adjusted in some way, because excessive bias voltages may cause current to leak through the P-well or N-well of the body biased transistor. The bias voltage can reduce or increase the effective threshold voltage of each transistor, and for an increased effective threshold voltage, the bias voltage reduces its leakage current. Any reduction in leakage current can also reduce power consumption.

[0004] The body bias voltage tends to be small, such as in the range of a few hundred millivolts. Large body bias voltages can have a significant negative impact on the performance of the device. The general convention is to connect the NMOS body to ground or the most negative supply, and the PMOS body to V DD (Usually the highest voltage available.) Increasing the NMOS body bias from ground to any higher voltage will lower the threshold voltage and therefore cause a slight increase in leakage, but the leakage current will be very small until the NMOS body bias is increased to the point where the diode between source and body turns on, which is the point where the leakage current becomes significant.

[0005] Usually the body bias voltage can be generated off-chip. However, this approach consumes some of the limited number of input-output pins in the integrated circuit. Therefore, for better design, an on-chip power supply can provide the body bias voltage to make room for other components in the very limited chip area and available power budget. Summary of the invention

[0006] According to a first aspect of the present invention, there is provided a device comprising:

[0007] A digital-to-analog converter (DAC), the digital-to-analog converter comprising:

[0008] a first transistor having a first transistor body; and

[0009] a second transistor having a second transistor body, the first transistor and the second transistor being configured to provide an output signal for the DAC; and

[0010] a bias circuit coupled to the DAC, the bias circuit comprising:

[0011] a third transistor having a source, a drain, and a transistor body coupled to its source, the source of the third transistor being coupled to the first transistor body of the first transistor and the second transistor body of the second transistor of the DAC; and

[0012] A current loop is coupled to the drain of the third transistor, the third transistor maintaining substantially the same current value in the bias circuit as in the DAC.

[0013] In one or more embodiments, the gate of the third transistor of the bias circuit is configured to receive a drain supply voltage that is independently controlled relative to the current loop.

[0014] In one or more embodiments, the bias circuit further includes an operational amplifier, an output of the operational amplifier being coupled to the drain of the third transistor.

[0015] In one or more embodiments, the operational amplifier includes a feedback loop in a source follower configuration.

[0016] In one or more embodiments, the input of the operational amplifier is configured to be coupled to the same common mode voltage source applied to the DAC.

[0017] In one or more embodiments, the DAC is a current steering DAC of a delta-sigma modulator circuit.

[0018] In one or more embodiments, the DAC is one DAC in an array of a plurality of DACs, and wherein the bias circuits are independently controlled, and one bias circuit in the plurality of bias circuits is matched one-to-one with a corresponding DAC.

[0019] In one or more embodiments, the transistor body of the third transistor of the bias circuit is formed in an electrically isolated well region in the bias circuit.

[0020] In one or more embodiments, the third transistor is a replica of the first transistor or the second transistor.

[0021] According to a second aspect of the present invention, there is provided a digital-to-analog converter (DAC) and a bias circuit macro unit cell, comprising:

[0022] a digital-to-analog converter (DAC) unit cell having at least a first transistor as a current switch, a cascode transistor, and a resistor coupled to the cascode transistor; and

[0023] a bias circuit coupled to the DAC unit cell, the bias circuit comprising:

[0024] A second transistor having a source, a drain, and a transistor body coupled to its source, the source of the second transistor being coupled to the body of the first transistor of the DAC unit cell.

[0025] In one or more embodiments, the bias circuit further comprises:

[0026] a third transistor coupled to the second transistor, a terminal of the third transistor being biased with a bias voltage from an external voltage source, and wherein a gate of the second transistor of the bias circuit is configured to receive a drain supply voltage supplied independently of a voltage supplied to the DAC unit cell.

[0027] In one or more embodiments, the bias circuit further includes an operational amplifier, an output of the operational amplifier coupled to the drain of the second transistor.

[0028] In one or more embodiments, the operational amplifier includes a feedback loop in a source follower configuration.

[0029] In one or more embodiments, the input of the operational amplifier is configured to be coupled to the same common mode voltage source applied to the DAC unit cell.

[0030] In one or more embodiments, the DAC unit cell is coupled to an analog-to-digital converter of a ΔΣ modulator circuit.

[0031] In one or more embodiments, the second transistor of the bias circuit is formed in an electrically isolated well region in the bias circuit.

[0032] In one or more embodiments, the second transistor of the bias circuit is an NMOS transistor.

[0033] In one or more embodiments, the bias circuit further comprises:

[0034] A pair of NMOS transistors, the pair of NMOS transistors and the second transistor form a current loop.

[0035] In one or more embodiments, the second transistor includes an NMOS transistor element, a PMOS transistor element, or a CMOS transistor element.

[0036] According to a third aspect of the present invention, there is provided a method for providing a low impedance body bias voltage, the method comprising:

[0037] applying a digital switching signal to a switching transistor of a digital-to-analog converter (DAC), the switching transistor having a transistor body; and

[0038] A current source is applied at the source of a bias transistor, the current source being common to the switching transistor and the bias transistor, the bias transistor forming part of a current loop connected to the same potential as the switching transistor, wherein a body of the bias transistor is coupled to its source, and wherein an output of the bias transistor is coupled to the transistor body of the switching transistor such that the transistor body of the switching transistor is maintained at substantially the same potential as its source.

[0039] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The present invention may be better understood, and its numerous features and advantages may become apparent to those skilled in the art by referencing the accompanying drawings. The use of the same reference numerals in different drawings indicates similar or identical items.

[0041] Figure 1 is a block diagram of an ADC including a delta-sigma modulator employing a DAC with a low output impedance circuit for body biasing, according to some embodiments.

[0042] Figure 2 According to some embodiments Figure 1 A block diagram of the DAC unit cell is shown in FIG.

[0043] Figure 3 is to apply the body bias voltage to Figure 2 Block diagram of the unit cell circuit.

[0044] Figure 4 is a block diagram of a method for providing a body bias voltage to a switching transistor of a DAC unit cell, according to some embodiments. DETAILED DESCRIPTION

[0045] Improvements to a feedback digital-to-analog converter (DAC) in a ΔΣ analog-to-digital converter (ADC) are described herein, including improvements to the linearity of the feedback DAC. According to some embodiments, the feedback DAC is a fully differential current steering DAC. To improve the linearity of the feedback DAC, in addition to using an existing cascode current source, resistive degeneration is added to further improve matching, further improve output impedance, and further improve overall linearity. A low output impedance circuit biases the switch body in the current steering DAC and enables the DAC to track changes in threshold voltage based on process and temperature changes without the use of digital control, calibration, or resistor ladders, and this allows the DAC to track changes in the DAC switch biased using the bias voltage.

[0046] Figure 1 1 is a block diagram of an ADC 100 including a ΔΣ modulator 101 according to some embodiments to show an illustrative application of improvements to a DAC or other circuit as further described herein. The ΔΣ modulator 101 has various components including a combiner 103, an integrator 104, a comparator 105, and a DAC 106 arranged in a negative feedback loop with the combiner 103. The integrator 104 is fed with the sum of the input signal introduced at the input 102 and the negated output of the DAC 106. In this configuration, the output of the integrator 105 is a ramp signal whose slope is proportional to its input. The integrator output is compared with a comparator reference signal to generate a 0 or 1. The binary output of the comparator 105 is clocked into a digital filter 107 such as a digital decimation filter on each edge of the ADC oversampling clock (not shown). The output signal is obtained at the output 108 of the digital filter 107. Each bit represents the direction of the ramp output of the integrator 104 relative to the comparator reference, and after a number of iterations, the bit stream resembles the quantized value of the input signal. The feedback loop operates so that the average output of the DAC 106 matches the input signal. The digital filter 107 averages the bit stream to output n-bit samples at the desired sampling rate. As further described herein, the DAC 106 includes a bias circuit 110 that matches the components of the DAC 106. The bias circuit 110 of the DAC 106 illustrates one of many applications for providing a low output impedance circuit to bias a switch body in a companion circuit.

[0047] Figure 22 is a block diagram of a DAC unit cell 200 according to some embodiments. The first transistor 205 and the second transistor 206 are coupled at their sources to a third transistor 210, which is cascaded in series with a fourth transistor 211, labeled M3 and M4, respectively. The fourth transistor 211 is coupled in series with the resistor 217 at one end of the resistor 217 and is coupled to ground at the other end of the resistor 217. The present specification does not limit the DAC unit cell 200 to such an arrangement. The cascode arrangement provides high gain, high bandwidth, and high stability for the DAC unit cell 200. In addition, the cascode arrangement provides a low component count in two transistors 210, 211 and a single resistor 217. Although a fixed number of cascode-connected transistors are shown and represented by the third transistor 210 and the fourth transistor 211, other numbers of components are possible.

[0048] At the other end of the DAC unit cell 200, the corresponding drains of the first transistor 205 and the second transistor 206 are coupled to corresponding current sources 201, 202, which in this illustrative embodiment are connected to a single source. In this embodiment, the DAC unit cell 200 is a current steering component for the ΔΣ modulator 100. The third transistor 210 and the fourth transistor 211 form a bias load, and the first transistor 205 and the second transistor 206 form a pair of current switches for the first current source 201 and the second current source 202, respectively. The first transistor 205 and the second transistor 206 serve as switches for the DAC unit cell 200.

[0049] The body (well) region 216 of the first transistor 205 and the second transistor 206 is electrically connected to an independently controlled body bias voltage BBIAS 209. By designing the body region 216, the magnitude of the body bias voltage BBIAS 209 is less than the magnitude of the power supply (not shown) provided to the DAC unit cell 200. Therefore, the body effect of the first transistor 205 and the second transistor 206 is reduced by this arrangement of components. Relatively speaking, the threshold voltage of the first transistor 205 and the second transistor 206 is reduced. The first (positive) output 214 and the second (negative) output 215 are differential outputs. However, in other applications or circuits, the outputs 214, 215 can also be configured as single-ended outputs.

[0050] The third transistor 210 and the fourth transistor 211 and the resistor 217 form a current source and direct the current in the desired direction in the DAC unit cell 200 according to the polarity of the complementary signals 207, 208. The third transistor 210 and the fourth transistor 211 and the resistor 217 provide a source degeneration resistance. In general, due to the nature of the cascode device and the degeneration resistor 217, the voltage at the drain of the first transistor 205 and the second transistor 206 and at their source generally needs to be high enough to keep all components properly biased. If the body bias voltage BBIAS 209 is connected to ground like many NMOS transistors, the threshold voltage becomes high due to the body effect such as at the body region 216, making the gate to source voltage V GS becomes high and reduces the voltage V at the source of the first transistor 205 and the second transistor 206 SS to keep the current source properly biased. The higher V GS A first bias voltage 212 is provided to the gate of the fourth transistor 211 , and a second bias voltage 213 is provided to the gate of the third transistor 210 to facilitate operation of the DAC unit cell 200 .

[0051] Bringing the source of the first transistor 205 and the source of the second transistor 206 to a high potential can be achieved, for example, by increasing their gate drive voltage or by reducing their threshold voltage. Since the gate drive voltage of the first transistor 205 and the second transistor 206 is already at the supply voltage, this voltage cannot be increased, which makes it possible to choose to adjust the design and operation of the DAC unit cell 200 to reduce the threshold voltage of each of the first transistor 205 and the second transistor 206. Its threshold voltage is reduced by reducing or offsetting the body effect of the first transistor 205 and the second transistor 206. In some cases, connecting the body of the transistors 205, 206 to their source has disadvantages because doing so increases the body capacitance at the source of the transistors 205, 206. Doing so also increases the sensitivity to distortion when driving the first transistor 205 and the second transistor 206. In embodiments having many DAC unit cells (e.g., 4, 8, 16), connecting the bodies of switch transistors 205, 206 to their sources would require that all switch pairs be located in their respective wells, which takes a considerable amount of area in the chip die, and such a large area is generally not available for such switches and corresponding unit cells.

[0052] In the DAC unit cell 200, one of the two switch transistors 205, 206 is always on because the DAC unit cell 200 is a fully differential circuit. This means that from the perspective of the switch transistors 205, 206, the potential at the gate of the switch transistors 205, 206 is substantially always at the drain supply voltage V DDIn the DAC unit cell 200, a body bias reference V is generated. DD -V GS (turned on) such that the body 216 of the switching transistors 205, 206 is maintained at substantially the same potential as the source (e.g., within 0.01%, within 0.5%, within 1.0%, and within 5% of each other), thereby substantially eliminating body effect and diode leakage current. The diode in question is formed between the diffusion region (source, drain) and the body 216.

[0053] Biasing the body or well of the NMOS transistor to a voltage above ground reduces the threshold voltage. However, the bias voltage cannot be raised too high because doing so may turn on leakage current at the diode interface between the body (p-side) and the source (n-side) of the switch, such as in the first switch transistor 205 and the second switch transistor 206. Instead, the circuit is provided with a low output impedance for the bias voltage to absorb any instantaneous switching current from the first switch transistor 205 and the second switch transistor 206. Having a low output impedance produces a circuit that achieves an available power budget as a design constraint for this circuit. For design reasons, a common body bias helps keep the area of ​​the component as small as possible.

[0054] Figure 3 Yes Figure 2 1 is a block diagram of a bias circuit 300 for supplying a bulk bias voltage BBIAS 209 to a DAC unit cell 200 of a DAC, and the bias circuit is common to the entire DAC including one or more DAC unit cells 200. The bias circuit 300 includes a regulation feedback loop that provides a low impedance bias voltage as the bulk bias voltage BBIAS 209. The DAC unit cell 200 and the bias circuit 300 together form a macro DAC unit cell. To generate a reference voltage, a replica circuit such as the bias circuit 300 is paired with another circuit such as the DAC unit cell 200. The bias circuit 300 includes a current loop 320 that maintains substantially the same current as the DAC unit cell 200.

[0055] According to some embodiments, the bias circuit 300 has about the same number of transistors as the DAC unit cell 200. For example, the bias circuit 300 includes seven transistors 301-307. In the illustrated embodiment, the first pair of PMOS transistors 301, 302 are located at the top of the current loop 320. The two pairs of NMOS transistors 303-306 are located at the bottom of the current loop 320. The first six transistors 301-306 form a current loop that maintains a current value through the seventh transistor 307 that is approximately the same as the current value maintained in the first transistor 205 by the DAC unit cell 200. That is, the first six transistors 301-306 are paired together with the first pair of transistors 301, 302 coupled together at the first end of the current loop 320. The first transistor 301 is coupled in series with the seventh transistor 307, the third transistor 303, and the fifth transistor 305 (respectively) along the left side or first side of the current loop 320. The second transistor 302, the fourth transistor 304, and the sixth transistor 306 are generally coupled in series along the left side or first side of the current loop 320. The fifth transistor and the sixth transistor share a ground connection at the second end of the current loop 320. In the bias circuit 300, the gates of the fifth transistor 305 and the sixth transistor 306 are coupled to the current loop 320 between the second transistor 302 and the fourth transistor 304.

[0056] The seventh transistor 307 acts as a replica switch and has its body connected to its source, as in the first position 321. The seventh transistor 307 also has its own well 322 in the bias circuit 300. The gate of the seventh transistor 307 is coupled to the drain supply voltage V DD The voltage is the same as the drain supply voltage V DD 312. For a single seventh transistor 307, the area overhead of the single transistor 307 and its corresponding bias circuit 300 is saved because there is one bias circuit 300 associated with the entire DAC corresponding to a single NMOS component in its own well of 16 pairs of switches, which makes the bias circuit 300 small compared to other arrangements of components. In particular, this area overhead is particularly saved when considering that the bias circuit 300 is paired with a group of DAC unit cells 200. For example, in a ΔΣ circuit including a DAC such as DAC 106, the bias circuit 300 will be provided to a group of 16 DAC unit cells 200.

[0057] The operational amplifier 310 is located between the first transistor 301 and the seventh transistor 307. A common mode voltage V is provided to the operational amplifier 310. CM311. A third bias voltage 313 is applied at the gate of the first transistor 301. The body of the first transistor 301 is connected to the gate of the second transistor 302. A fourth bias voltage 314 is applied at the body of the third transistor 303. The gate of the third transistor 303 is connected to the gate of the fourth transistor 304, and the gate of the fifth transistor 305 is connected to the gate of the sixth transistor 306.

[0058] Since the drains of the switching transistors 205, 206 in the DAC unit cell 200 are maintained at a constant common mode, the same common mode in the bias circuit 300 is maintained, which ensures the same gate-to-source voltage V GS , the same drain to source V DS and substantially the same current, making bias circuit 300 a good replica of DAC unit cell 200. Bias circuit 300 also includes a low output impedance achieved by a combination of op amp feedback loop 325 and source follower configuration. As long as the gain of op amp 310 is high, the output impedance of the bias is low. The V GS The combination of process and temperature and low output impedance makes the bias circuit 300 a good bias generator that prevents body effect and leakage current of the DAC unit cell 200. Specifically, to achieve the desired performance, the body bias voltage BBIAS 209 tracks the gate-to-source voltage V of the switching transistors 205, 206 of the DAC unit cell 200. GS , and essentially achieves the same effect as connecting the body to the sources of these transistors 205, 206 without requiring an actual connection between the body 216 and its source. This arrangement eliminates the transistor body effect and prevents leakage current from entering the transistor body 216.

[0059] Turning to the operation of the bias circuit 300, the common mode voltage V cM yes Figure 2 , which is a common-mode voltage at the output of the DAC unit cell. According to some embodiments, in a ΔΣ modulator using a current steering DAC such as the DAC unit cell 200, it is desired that the DAC output voltage remain constant, except for momentary switching effects. In other embodiments, such as in a stand-alone current steering DAC, a different reference may be required. The seventh transistor 307 is a replica of the first transistor 205, but its body is connected to its source as indicated at the first position 321. The operational amplifier 310 as a buffer maintains an arrangement on the seventh transistor 307 similar to the arrangement on the first transistor 205 and the second transistor 206 in the DAC unit cell 200 - maintaining a common-mode voltage V on the seventh transistor 307 cM325 including OP1 is a buffer that maintains VCM on 307. The buffer maintains a similar arrangement on the switching transistors 205, 206 and is not shown.

[0060] The use of the current loop 320 instead of using only the first transistor 301, the seventh transistor 307, the third transistor 303, and the sixth transistor 306 (also labeled M5, M1R, M7, and M10) helps maintain the current therein so that the minimum current is drawn from the operational amplifier 310 under steady state conditions. The operational amplifier 310 in the bias circuit 300 only needs to provide current for the momentary switching on the BBIAS 209 that biases the body of the switching transistors 205 and 206. Since the BBIAS 209 is taken from the source of the seventh transistor 307 and the drain of the seventh transistor 307 is connected to the buffer output, the bias circuit 300 provides a low impedance output. The gate of the seventh transistor 307 is connected to the drain supply voltage V DD , which is true for one of the first transistor 205 and the second transistor 206 at any time because the first transistor 205 and the second transistor 206 form a differential pair. In the case where the seventh transistor 307 has the same gate drive voltage, the same drain voltage, and the same current as the first transistor 205 and the second transistor 206, there is essentially a virtual short circuit between the source and the body of the first transistor 205 and the second transistor 206 because it is not a physical short circuit.

[0061] The bias circuit 300 allows the body bias of the switch (first transistor 205 and second transistor 206) to move as its source voltage varies through process and temperature, thereby substantially eliminating body effects and leakage currents. This is an advantage of using the bias circuit 300 instead of a fixed reference (e.g., fixed voltage, fixed current). And since the bias circuit 300 already provides a low output impedance, the bias circuit 300 does not require buffering. In addition, the bias circuit 300 does not require fine-tuning, calibration, or digital control because the bias circuit helps track changes rather than correcting changes after the fact. The lack of buffering helps achieve power and area design goals while providing necessary performance, such as ADC or DAC applications.

[0062] Figure 44 is a block diagram of a method 400 for providing a body bias voltage to a switching transistor of a DAC unit cell according to some embodiments. At block 401, a switching signal is applied to one or more switching transistors of a first circuit (such as a DAC unit cell 200). At block 402, an independent current source is applied at the source of the bias transistor, wherein the bias transistor body is coupled to its source. The output of the bias transistor is coupled to the body of each switching transistor. At block 403, a common mode voltage is applied to an operational amplifier, which is coupled to the drain side of the current loop containing the bias transistor. In some embodiments, in a source follower configuration, the operational amplifier includes a feedback loop. Method 400 illustrates coupling the bias circuit 300 to the DAC unit cell 200 and operating it simultaneously to provide a low output impedance and prevent body effects and leakage currents in the switching transistors 207, 208 in the DAC unit cell 200.

[0063] Broadly, according to some implementations, a method for low impedance body bias voltage is provided, wherein the method comprises applying a digital switching signal to a switching transistor of a DAC, the switching transistor having a transistor body, and applying a current source at a source of a bias transistor. The current source is common to the switching transistor and the bias transistor. The bias transistor forms part of a current loop that is connected to the same potential as the switching transistor. The body of the bias transistor is coupled to its source, and the output of the bias transistor is coupled to the transistor body of the switching transistor, which causes the transistor body of the switching transistor to be maintained at substantially the same potential as its source.

[0064] Figure 1-4 The configurations shown in are some of the many possible configurations for providing matching bias circuits to other circuits and illustrative methods for providing a body bias voltage to a switching transistor. The technology described herein is applicable to various configurations of components and various applications. Typically, a bias circuit provides a bias voltage to the substrate of a metal oxide semiconductor (MOS) transistor or other component. The body effect of the component is overcome by providing a low impedance body bias voltage, and substrate leakage current is also prevented by using a replica transistor so that the body bias reference voltage accurately tracks changes due to process and temperature variations. Conventional methods either connect the bias voltage to the power supply voltage, which may result in limited performance, or implement a low impedance reference to bias the body. Having a fixed reference requires sufficient power supply margin to provide a high reference, as well as sufficient safety margin between the bias and source voltages to prevent substrate leakage currents in the threshold voltage due to process and temperature variations. Bias circuit 300 overcomes these two limitations.

[0065] The technology is applicable to a device including a DAC and a bias circuit coupled to the DAC. The DAC includes a first transistor having a first transistor body and a second transistor having a second transistor body. The first transistor and the second transistor are configured to provide an output signal for the DAC. The third transistor has a source, a drain and a transistor body, wherein the transistor body is coupled to its source, and the source of the third transistor is coupled to the first transistor body of the first transistor of the DAC and the second transistor body of the second transistor. A current loop is coupled to the drain of the third transistor, and the third transistor maintains a current value in the bias circuit that is substantially the same as in the DAC. Optionally, the gate of the third transistor of the bias circuit is configured to receive a drain supply voltage that is independently controlled relative to the current loop. In some embodiments, the bias circuit includes an operational amplifier, whose output is coupled to the drain of the third transistor. In a source follower configuration, the operational amplifier may include a feedback loop. The input of the operational amplifier may be configured to be coupled to the same common-mode voltage source applied to the DAC. The DAC may be a current steering DAC of a ΔΣ modulator circuit. In some embodiments, the DAC is one DAC or one of a plurality of DACs in a DAC array, and the independently controlled bias circuit is one of a plurality of bias circuits that are matched one-to-one with the corresponding DAC. In some circuit designs, a transistor body of a third transistor of the bias circuit is formed in an electrically isolated well region in the bias circuit, and the third transistor is a replica of the first transistor or the second transistor.

[0066] The technology is also applicable to bias circuit macro unit cells. For example, a DAC unit cell has at least a first transistor as a current switch, a cascode transistor, and a resistor coupled to the cascode transistor. A bias circuit is coupled to the DAC unit cell, wherein the bias circuit includes a second transistor having a source, a drain, and a transistor body, and wherein the transistor body is coupled to its source, and the source of the second transistor is coupled to the body of the first transistor of the DAC unit cell. Optionally, the bias circuit includes a third transistor coupled to the second transistor, wherein the end of the third transistor is biased with a bias voltage from an external voltage source, and the gate of the third transistor of the bias circuit is configured to receive a drain supply voltage supplied independently of the voltage supplied to the DAC unit cell. In some embodiments, the output of the operational amplifier is coupled to the drain of the second transistor, and in a source follower configuration, the operational amplifier includes a feedback loop. In addition, the input of the operational amplifier can be configured to be coupled to the same common mode voltage source applied to the DAC unit cell. The DAC unit cell can be coupled to an analog-to-digital converter of a ΔΣ modulator circuit. The second transistor of the bias circuit can be an NMOS type transistor. The bias circuit may include a pair of NMOS transistors, wherein the pair of NMOS transistors and the second transistor form a current loop. The second transistor may include an NMOS transistor element, a PMOS transistor element, or a CMOS transistor element.

[0067] It should be noted that not all of the above-described activities or elements in the general description are required, a part of a particular activity, component, or device may not be required, and one or more additional activities may be performed or additional elements may be included in addition to those described. Further, the order in which the activities are listed is not necessarily the order in which the activities are performed. Moreover, these concepts have been described with reference to specific embodiments. However, those of ordinary skill in the art recognize that various modifications and changes may be made without departing from the scope of the present disclosure as listed in the following claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive, and all such modifications are intended to be included within the scope of the present disclosure.

[0068] Benefits, other advantages, and problem solutions have been described above with respect to specific embodiments. However, the benefits, advantages, problem solutions, and any one or more features that may make any benefit, advantage, or solution occur or become more obvious should not be interpreted as key, required, or essential features of any or all claims. In addition, the specific embodiments disclosed above are merely illustrative, as the disclosed subject matter can be modified and practiced in different but equivalent ways that are obvious to those skilled in the art who benefit from the teachings herein. Except as described in the following claims, there are no limitations on the details of the structure or design shown herein. Therefore, it is apparent that the specific embodiments disclosed above can be changed or modified, and all such changes are considered to be within the scope of the disclosed subject matter. Therefore, the protection sought herein is as described in the following claims.

Claims

1. A device, characterized in that: It includes: A digital-to-analog converter DAC, the digital-to-analog converter comprising: a first switching transistor having a first switching transistor body; as well as a second switch transistor having a second switch transistor body, the first switch transistor and the second switch transistor being configured to provide an output signal for the DAC; as well as a bias circuit coupled to the DAC and configured to provide a body bias voltage to the first switch transistor body and the second switch transistor body, the bias circuit comprising seven transistors: six of the seven transistors, including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, form a transistor device 320 including a first side coupled between a first terminal at a first end of the transistor device and a ground terminal at a second end of the transistor device, and a second side coupled between the first terminal and the ground terminal, and wherein the seventh transistor is a bias transistor; the transistor arrangement being configured to maintain a current value through a seventh transistor of the bias circuit substantially the same as a current value through a first switching transistor or a second switching transistor of the DAC, and; a first transistor of the bias circuit electrically coupled in series with a seventh transistor, a third transistor, and a fifth transistor of the bias circuit along a first side of the transistor arrangement, and a second transistor, a fourth transistor, and a sixth transistor of the bias circuit electrically coupled in series along the second side of the transistor arrangement, and a first transistor and a second transistor of the bias circuit electrically coupled together at a first end of the transistor arrangement, a fifth transistor and a sixth transistor of the bias circuit electrically coupled to ground at a second end of the transistor arrangement, and gates of the fifth transistor and the sixth transistor coupled to the transistor arrangement between the second transistor and the fourth transistor, wherein the bias transistor comprises a source, a drain, and a bias transistor body, and wherein the bias transistor body is coupled to its source, the source of the bias transistor being coupled to a first switching transistor body of a first switching transistor and a second switching transistor body of a second switching transistor of the DAC; Wherein the bias circuit further includes an operational amplifier having an output electrically coupled to a drain of the bias transistor, wherein the operational amplifier includes a feedback loop in a source follower configuration, and wherein the operational amplifier is configured to maintain a common mode voltage across the bias transistor.

2. The device according to claim 1, characterized in that The gate of the third transistor of the bias circuit is configured to receive a drain supply voltage that is independently controlled relative to a current loop.

3. The device according to claim 1, characterized in that In a source follower configuration, the operational amplifier includes a feedback loop.

4. The device according to claim 1, characterized in that The input of the operational amplifier is configured to be coupled to the same common-mode voltage source applied to the DAC.

5. The device according to claim 1, characterized in that The DAC is a current steering DAC of a ΔΣ modulator circuit.

6. The device according to claim 1, characterized in that The transistor body of the third transistor of the bias circuit is formed in an electrically isolated well region in the bias circuit.

7. The device according to claim 1, characterized in that The third transistor is a replica of the first transistor or the second transistor.

8. A method for providing a low impedance body bias voltage, characterized in that, The method comprises: applying a digital switching signal to a switching transistor of a digital-to-analog converter DAC, the switching transistor comprising a first switching transistor having a first switching transistor body and a second switching transistor having a second switching transistor body, the first switching transistor and the second switching transistor providing an output signal for the DAC; and providing a body bias voltage to the first switching transistor body and the second switching transistor body by a bias circuit, the bias circuit comprising seven transistors: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor, forming a transistor device 320, comprising a first side coupled between a first terminal at the first end of the transistor device and a ground terminal at the second end of the transistor device, and a second side coupled between the first terminal and the ground terminal, and wherein the seventh transistor is a bias transistor; maintaining, by the transistor means, a current value through a seventh transistor of the bias circuit substantially the same as a current value through a first switching transistor or a second switching transistor of the DAC, and; electrically coupling a first transistor of a bias circuit in series with a seventh transistor, a third transistor, and a fifth transistor of the bias circuit along a first side of a transistor arrangement, and electrically coupling a second transistor, a fourth transistor, and a sixth transistor of the bias circuit in series along the second side of the transistor arrangement; and electrically coupling a first transistor and a second transistor of the bias circuit together at a first end of the transistor arrangement, electrically coupling a fifth transistor and a sixth transistor of the bias circuit to ground at a second end of the transistor arrangement, coupling gates of the fifth transistor and the sixth transistor to the transistor arrangement between the second transistor and the fourth transistor, wherein the bias transistor includes a source, a drain, and a bias transistor body, and coupling the bias transistor body to its source, the source of the bias transistor being coupled to a first switch transistor body of a first switch transistor and a second switch transistor body of a second switch transistor of the DAC; An output of an operational amplifier in the bias circuit is electrically coupled to a drain of the bias transistor, wherein the operational amplifier includes a feedback loop in a source follower configuration, and a common mode voltage across the bias transistor is maintained by the operational amplifier.

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