Method and apparatus for increasing reactor processing batch size

Abstract

A method for increasing the batch size of a reaction chamber and a plasma processing apparatus using the method are provided. The method comprises: (a) processing a portion of a batch of wafers in the reaction chamber, wherein the processing causes at least some material to be deposited off-target on the interior surface of the reaction chamber; (b) performing a batch intermediate reaction chamber process to stabilize the off-target deposited material accumulated on the interior surface of the reaction chamber; and (c) processing another portion of the batch of wafers in the reaction chamber.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Patent Application No. 15 / 799,679, filed on October 31, 2017, entitled “METHODS AND APPARATUSES FOR INCREASING REACTOR PROCESSING BATCH SIZE,” which is incorporated herein by reference for all purposes. Background Art

[0003] Semiconductor processing is typically performed in dedicated processing equipment, where it is often desirable to obtain optimized and efficient production capacity. Such equipment may include a reaction chamber that accommodates batches of wafers during processing. The reaction chamber may also include various hardware pieces used in semiconductor processing (e.g., substrate supports, showerheads, etc.). In some cases, the reaction chamber may be treated, or seasoned, before the reaction chamber is used to process substrates. The reaction chamber treatment may take a number of different forms and may be performed for a variety of reasons. In addition, in some cases, the total number of wafers that can be processed by the reaction chamber between cleaning cycles may be limited due to the accumulation of off-target films deposited on various internal components of the reaction chamber, which requires that the processing be stopped and the chamber be closed for cleaning. Summary of the invention

[0004] Certain embodiments herein relate to a method of increasing a batch size of a reaction chamber, the method comprising: (a) processing a portion of a batch of wafers within the reaction chamber, wherein the processing causes at least some material to be deposited off-target on an interior surface of the reaction chamber; (b) performing a batch intermediate reaction chamber process to consolidate the off-target deposited material accumulated on the interior surface of the reaction chamber; and (c) processing another portion of the batch of wafers within the reaction chamber.

[0005] The method may further include repeating (b)-(c) until processing of the batch of wafers is completed.

[0006] In some embodiments, the reaction chamber batch size is the number of wafers that can be processed in the reaction chamber between reaction chamber cleaning cycles.

[0007] The method may further include: performing an aging treatment on an inner surface of the reaction chamber before performing the batch process in the reaction chamber.

[0008] In some embodiments, the aging the interior surfaces of the reaction chamber includes applying a coating of the same material as that used to be deposited on the batch of wafers during (a) or (c).

[0009] In some embodiments, (a) or (c) may include depositing a material on wafers in the batch of wafers.

[0010] In some embodiments, the aging treatment includes applying a coating on interior surfaces of the reaction chamber by atomic layer deposition (ALD) when no wafer is present in the reaction chamber.

[0011] The method may further include cleaning the interior surface of the reaction chamber after (c) is completed.

[0012] The method may further include: (d) cleaning the inner surface of the reaction chamber after the processing of the batch of wafers is completed.

[0013] In some embodiments, (b) is performed at specified intervals of the total batch accumulation limit of the batch of wafers. In addition, the specified intervals can be determined empirically. In addition, the specified intervals can occur before a detrimental level of material accumulation on the interior surfaces of the chamber that results in material delamination and wafer defects and / or particle generation.

[0014] In some embodiments, the total batch accumulation limit is the thickness of accumulated material on the interior surfaces of the reaction chamber, beyond which processing is compromised, necessitating cleaning of the reaction chamber before further processing.

[0015] In some embodiments, (b) comprises a deposited film bonded to a material accumulated on an interior surface of the reaction chamber. In addition, the compressibility of the deposited film can be enhanced by adjusting any one or more of the group consisting of: radio frequency (RF) power level, reaction chamber pressure, or RF treatment time.

[0016] In some embodiments, wherein (b) includes: after the material accumulates to a specified thickness, exposing the material accumulated on the interior surface of the reaction chamber to a plasma. In addition, the plasma exposure can be performed at a pressure in the range of 2 torr to 10 torr to promote the diffusion of the plasma into the film deposited on the interior surface of the reaction chamber. In addition, the plasma can be ignited on a faceplate of a showerhead within the reaction chamber. In addition, the plasma can be derived from any one of the group consisting of: hydrogen, helium, argon, or a nitrogen-containing source. In addition, exposure to the plasma can remove about The film is deposited on the accumulated material on the interior surface of the reaction chamber. Moreover, the sweep can be disabled so that the plasma can be evenly dispersed throughout the reaction chamber. In some embodiments, the plasma has a frequency of 400 kHz.

[0017] In some embodiments, the deposited film stabilizes the material on the interior surface of the reaction chamber. In addition, the exposure to the plasma can densify the deposited film to stabilize the material on the interior surface of the reaction chamber. In addition, the compressibility of the film can be increased by a method selected from the group consisting of: applying a radio frequency (RF) power in the range of 2 kW-7 kW, applying a high voltage in the range of 2 Torr-10 Torr, or using an RF plasma time of 0.2 seconds (s)-10 s.

[0018] The method may further include: (d) grounding the reaction chamber. In addition, grounding the reaction chamber may facilitate diffusion of plasma to the outside of the reaction chamber. In some embodiments, a showerhead configured to deliver deposition gas to the batch of wafers is powered. In addition, in some embodiments, a pedestal configured to support the batch of wafers is powered. In addition, the plasma used to perform (d) may be supplied by a remote plasma cleaning unit. The remote plasma cleaning unit may be mounted on the reaction chamber.

[0019] Another aspect includes a plasma processing apparatus for processing a substrate. The apparatus may include a reaction chamber including: an interior chamber surface, a substrate support for supporting a substrate within the reaction chamber, and an exhaust port for removing material from the reaction chamber; a remote plasma chamber including: a plasma generator for generating plasma within the remote plasma chamber, an inlet for delivering a gas to the remote plasma chamber, an outlet for providing the plasma generated in the remote plasma chamber to the reaction chamber; and a controller configured to execute instructions for: processing a portion of a batch of wafers within the reaction chamber; performing a batch intermediate reaction chamber process to stabilize material accumulated on the interior surface of the reaction chamber due to batch processing; and processing another portion of the batch of wafers within the chamber.

[0020] In some embodiments, the plasma processing apparatus is remote from the reaction chamber.

[0021] In some embodiments, the controller is further configured to execute instructions for: (d) cleaning the interior surface of the reaction chamber after (c) is completed.

[0022] These and other aspects will be further described below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1A simplified diagram of a reaction chamber for processing a substrate using plasma delivered from a remote source is shown.

[0024] Figure 2 show Figure 1 A reaction chamber having a coating covering an interior surface of the chamber.

[0025] Figure 3 is a process flow diagram that depicts operations for a method according to the disclosed embodiments.

[0026] Figure 4A-4B is a process flow diagram that depicts operations for a method according to the disclosed embodiments.

[0027] Figure 5A-5B is an exemplary graph presenting sample operating conditions for a method according to the disclosed embodiments.

[0028] Figure 6 is an exemplary graph presenting sample operating conditions for a method according to the disclosed embodiments.

[0029] Figure 7 is a schematic diagram of an exemplary processing tool for performing certain disclosed embodiments.

[0030] Figure 8 is a schematic diagram of another exemplary processing tool for performing certain disclosed embodiments. DETAILED DESCRIPTION

[0031] In the following description, many specific details are set forth to provide a thorough understanding of the embodiments presented. The embodiments disclosed herein may be implemented without some or all of these specific details. In other cases, well-known processing operations are not described in detail to avoid unnecessarily obscuring the disclosed embodiments. In addition, although the disclosed embodiments will be described in conjunction with specific embodiments, it should be understood that the specific embodiments are not intended to limit the disclosed embodiments.

[0032] In this application, the terms "wafer" and "substrate" are used interchangeably. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm, or 300 mm, or 450 mm. Unless otherwise specified, the processing details described herein (e.g., flow rates, power levels, etc.) are related to processing a substrate of 300 mm diameter, or related to handling a chamber configured to process a substrate of 300 mm diameter, and can be appropriately scaled for substrates or chambers of other sizes. The chambers described herein can be used to process workpieces that can be of various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that can be processed in a chamber prepared according to certain embodiments include various objects, such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical components, micromechanical devices, etc.

[0033] introduce

[0034] In semiconductor manufacturing, it is desirable to achieve efficient reactor chamber productivity. Conventionally, batches of wafers are supplied to a reactor chamber for processing (e.g., deposition) therein on (multiple) wafers. However, unintentional off-target deposition of material on various internal chamber surfaces (e.g., sidewalls of the reactor chamber) may result in eventual particle generation, for example, when such material is stripped onto the wafer being processed in the chamber. Such off-target material stripping is undesirable because it may contaminate the wafer being processed, thereby reducing the overall quality of the processed batch of wafers.

[0035] Traditionally, a complete cleaning of the interior of a reaction chamber is performed once the reaction chamber batch size is reached, i.e., the maximum number of wafers that can be processed in a reaction chamber before the processed wafers are substantially likely to be contaminated by particle generation resulting from off-target deposition that has accumulated in the chamber. Performing such a cleaning requires removing from the reaction chamber the contents contained therein for processing, thereby potentially reducing throughput and preventing the processing of larger batches of wafers within a given time.

[0036] Increasing the batch size of a reaction chamber will increase productivity (or throughput) by enabling additional wafers to be processed in the reaction chamber between required cleaning cycles. Such an increase can be achieved through one or more of the methods disclosed herein, namely the application of a batch-increase accumulation sequence (BIAS)-related process, which describes a process that utilizes an intermediate (or batch-intermediate) chamber process to briefly interrupt conventional wafer processing to stabilize off-target material deposited on internal reaction chamber components (e.g., chamber interior sidewalls) to prevent such material from delaminating or otherwise generating particles that contaminate the wafers being processed.

[0037] As used herein and elsewhere throughout this disclosure, flaking may refer to a form of particle generation caused by partial or complete disintegration of off-target deposited material on the interior surfaces of a reaction chamber onto a batch of wafers being processed in the reaction chamber. Flaking is an undesirable condition and may compromise the quality of the batch being processed by introducing defects and / or other particles to the wafers. In addition to flaking, a "peeling" phenomenon may be observed. Peeling describes a specific type of peeling in which the top exposed surface of the off-target deposited material separates uniformly from the interior walls to which it is attached and falls onto the wafer during processing.

[0038] Reaction Chamber

[0039] Figure 1 A simplified example diagram of a reaction or processing chamber is presented in conjunction with which processes and apparatuses according to the present disclosure may be implemented. Processing chamber 102 includes chamber walls 103, chamber floor 104, and chamber ceiling 105. A substrate support 106 is positioned within processing chamber 102, and substrate 107 is seated on substrate support 106. Processing chamber 102 also includes an inlet 108 and an exhaust outlet 109. In some embodiments, a remote plasma source 110 is disposed above processing chamber 102. Remote plasma source 110 includes a plasma generator (not shown) for generating plasma within the remote plasma source. The plasma generator includes hardware (e.g., coils, electrodes, etc.) for generating plasma, which may be an inductively coupled plasma (ICP), a capacitively coupled plasma (CCP), or a microwave generated plasma, etc. Remote plasma source 110 is separated from processing chamber 102 by a showerhead 111 having a plurality of showerhead holes 112. The remote plasma source 110 has an inlet 113 for providing a gas for generating the remote plasma.

[0040] In a typical case, a stack of wafers (e.g., one, two, or four wafers) is processed sequentially within the processing chamber 102, such as for deposition to be performed on the wafers. For example, four wafers enter the processing chamber 102, undergo processing, and are then removed. Next, an additional four unprocessed wafers may be introduced into the processing chamber 102 for processing. This manner of transferring a stack of wafers until a total target amount or "batch" is reached between required chamber cleaning cycles may be referred to as "batch processing." Wafers are processed sequentially at one or more stations (e.g., 1, 2, or 4 stations) until a reaction chamber batch size (e.g., limit) is reached. The application of BIAS enables the reaction chamber batch size to be expanded by intermediate processing of off-target deposited materials to prevent such materials from interfering with subsequent wafer processing. Thus, by applying BIAS, a large number of wafers may be processed before temporarily interrupting wafer processing to dispose of or clean residue accumulation on the interior surfaces of the reaction chamber, where the residue accumulates due to off-target deposition on the interior surfaces of the reaction chamber.

[0041] Figure 2 Explain that after the following processing Figure 1 2: The interior component surfaces of the apparatus are coated, for example, by applying an undercoat (UCT) such as coating 220 and "aged", as further described below. Generally, "aging" refers to the treatment of the interior surfaces of a reaction chamber to prepare for processing wafers within the reaction chamber. In some embodiments, the aging treatment may involve applying a silicon oxide (SiO2) coating or UCT to the interior surfaces. In other embodiments, the silicon oxide (SiO x ), nitride, tungsten, or other suitable materials (such as dielectric materials) may be used in the aging process, depending on what is deposited in the reaction chamber.

[0042] The depicted coating 220 may also represent the accumulation of off-target deposited material during wafer processing in the reaction chamber. The term "accumulation" as used herein and elsewhere in the present disclosure generally describes the buildup of off-target deposited material on the interior surfaces of the reaction chamber. Likewise, the term "normal accumulation" describes the conventional accumulation process during processing of batches of wafers in a reaction chamber, which is cleaned when the maximum reaction chamber batch size is reached. The substrate 107 (e.g., wafer) is not shown in this figure, and the thickness of the coating 220 is exaggerated for illustrative purposes. In addition, the coating 220 may be present Figure 2 In some embodiments, the low composite material coating 220 covers only the surfaces inside the processing chamber 102.

[0043] Processing of substrates 107, such as semiconductor wafers, may involve deposition thereon by various processes, such as atomic layer deposition (ALD). During wafer processing, a specified number of wafers, such as one, two, or four wafers, may be processed in the processing chamber 102 and then cycled out so that new, unprocessed wafers can enter. After a certain amount of time spent processing a large number of wafers, material that was intended to be deposited on the wafers may begin to accumulate in unintended locations, such as on the chamber walls 103. As a result, such off-target deposited material may begin to generate particles that, for example, peel off from the chamber walls 103 and fall (or otherwise move) onto the substrate 107 and contaminate the wafer processing.

[0044] Therefore, implementation Figure 4A-4B 5A-5B can fix or stabilize such off-target deposited materials on the chamber walls. Such stabilization of off-target deposited materials can allow for additional continued processing of the substrate 107 until a final chamber wall 103 cleaning cycle must be performed to remove and remove the off-target deposited materials. In general, a cleaning cycle refers to the removal of unwanted off-target deposited materials from various internal reactor components (such as sidewalls). The reaction chamber is typically cleaned so that wafer processing in the reaction chamber can be restarted. Chamber cleaning can be wet (using liquid chemicals) or dry (for example, using plasma). In addition, chamber cleaning (commonly referred to as "plasma cleaning") can be performed by providing plasma to the reaction chamber to clean off-target deposited materials on the interior surfaces of the reaction chamber. Plasma cleaning can be performed using in-situ or remote plasma.

[0045] Figure 3 An exemplary process flow 300 is shown for addressing problems caused by off-target deposition on interior surfaces of a reaction chamber during wafer batch processing. The process 300 begins at operation 302, which involves providing one or more wafers to a reaction chamber, such as a processing chamber, such as Figure 1 shown.

[0046] In some embodiments, multiple wafers may be admitted to a reaction chamber for sequential processing at multiple stations and then removed from the reaction chamber upon completion of processing. In other embodiments, the chamber may be configured to process one wafer at a time. Such processing of multiple wafers may be collectively referred to as "batch processing," wherein a "batch" of wafers refers to the total number of wafers that may be processed in a reaction chamber between reaction chamber cleaning cycles before the reactor needs to be shut down for complete cleaning, wherein the reactor is shut down for complete cleaning in order to continue processing the wafers without the risk of process drift and / or wafer contamination due to particle generation, such as stripping of off-target deposited material accumulated on internal reactor components (particularly sidewalls) due to wafer processing in the reaction chamber. In general, a cleaning cycle involves completely shutting down the reaction chamber to provide complete cleaning before continuing to process the wafers without the risk of contamination due to particle generation, such as stripping of accumulated off-target deposited material deposited on internal reactor components (particularly sidewalls) due to previous wafer processing in the reaction chamber. In general, a cleaning cycle involves completely shutting down the reaction chamber to provide complete cleaning before continuing to process the wafers without the risk of contamination due to particle generation, such as stripping of accumulated off-target deposited material deposited on internal reactor components (particularly sidewalls) due to previous wafer processing in the reaction chamber.

[0047] In a typical batch processing process, the desired processing capacity may be limited by the continued accumulation of off-target material on the interior surfaces of the reaction chamber during batch wafer processing. Operation 306, performed after initial processing of a portion of the batch wafers, addresses the problem of off-target deposition by performing a batch intermediate reaction chamber process to stabilize off-target material deposited on, for example, the sidewalls of the reaction chamber. Any wafers in the reaction chamber may be removed from the reaction chamber before the batch intermediate processing of operation 306 begins to avoid undesirable contamination from the batch intermediate processing. In some embodiments, the batch intermediate processing may involve one or more different processing variations that may be used in the process. Figure 4A-4B After the intermediate processing of the batch of wafers in the reaction chamber at operation 306 is completed, another portion of the batch of wafers may be processed in the reaction chamber at operation 308 before the process 300 ends at operation 310 .

[0048] Thus, the batch intermediate chamber processing performed at operation 306 can increase the total number of wafers that can be processed in the chamber between required cleaning cycles, thereby effectively increasing the batch size of wafers to be processed. Therefore, the process 300 including operation 306 (also referred to as a batch increase accumulation procedure (BIAS)) is needed to increase the total operating throughput of wafers processed in a given chamber by extending the availability or life of the chamber between required cleaning cycles (e.g., where accumulated off-target deposited material is removed from adhering to the sidewalls of the chamber).

[0049] Figure 4A A comprehensive process flow 400 is shown, which is based on reference Figure 4ABIAS is described as a specific implementation of the general process described above. Figure 4B Will combine Figure 4A Several specific types of batch intermediate chamber treatments are discussed and described, and shown, such as those performed at operation 306 in process flow 300, and similarly performed at operation 412 in process flow 400. After operation 402 is initiated, it will be understood by those skilled in the art that the interior surfaces of the reaction chamber may be prepared or aged by depositing a thin film thereon by conventional deposition methods or via atomic layer deposition (ALD). The thin film deposited at the aging operation 404 may be referred to as a "pre-coating," or as an "undercoating" (UCT), and in some embodiments may include a dielectric such as silicon oxide (SiO2) or other oxide suitable for deposition. In addition, silicon oxide may be deposited as a UCT by ALD in a relatively short period of time to control the thickness of the film deposited during 500 to 1,200 ALD cycles, for example, at a minimum. To maximum value within the range of to Inside.

[0050] ALD is a cyclic process of nominally self-limiting steps that results in small and numerical changes in film thickness. The process is characterized by smoothness and conformality. The concept of an "ALD cycle" is relevant to the discussion of many embodiments herein. In general, an ALD cycle is a minimum set of operations for performing a surface deposition reaction. The result of a cycle is the production of at least a portion of a silicon-containing film layer, for example, on a substrate surface. Typically, an ALD cycle includes operations to deliver and adsorb at least one reactant to a substrate surface, and then react the adsorbed reactant with one or more reactants to form a portion of the film layer. The cycle may include certain auxiliary operations, such as removing one of the reactants or byproducts and / or disposing of the deposited portion of the film. In general, a cycle includes an example of a unique sequence of operations. For example, an ALD cycle may include the following operations: (i) delivering / adsorbing a silicon-containing precursor; (ii) sweeping a silicon-containing precursor from a chamber; (iii) delivering a second reactant and plasma; and (iv) sweeping a plasma from a chamber. Various flow rate ranges for precursors, process gases and / or reagents suitable for generating and coating various types of UCTs by ALD are shown in Figure 5A , where the column is labeled "UCT". The flow rate in standard cubic centimeters per minute (sccm) for the ALD process used to apply UCT and additional various batch intermediate process coatings may include Figure 5ASpecific ranges shown in . For example, a precursor selected from BTBAS (bis-tert-butylaminosilane), BDEAS (bis(diethylamino)silane) ((Et2N)2SiH2), or DIPAS (diisopropylaminosilane) can be flowed into the reaction chamber at a volume flow rate of 500-3,000 sccm to form and coat the interior surface of the reaction chamber with a UCT such as silicon oxide (SiO2) (such as silicate glass). Other suitable exemplary precursors (or reactants) for generating silicon-containing UCTs may include various other bis-alkylaminosilanes, wherein the alkyl groups thereof may contain 1-6 carbon groups. Moreover, each amino group may be mono- or di-substituted with an alkyl group. In addition, in certain embodiments, variants of alkenyl and alkynyl groups may be used as precursors or reactants for generating silicon-containing UCTs. In some cases or configurations, different alkyl groups may be used on the molecule (for example, one or more amines may be substituted with methyl groups, and one or more other amines may be substituted with ethyl groups). In certain embodiments, one or more alkyl groups may provide steric hindrance to the silane core. Likewise, a carrier gas such as argon (Ar) gas may be flowed into the reaction chamber to generate UCT as needed.

[0051] Next, after conditioning the chamber to coat the UCT as described above at operation 404, a portion of the batch of wafers is provided to the chamber for processing therein. As previously described with respect to process flow 300, a batch may refer to the maximum number of wafers that can be processed by the chamber between required chamber cleaning cycles. A portion of the batch may be any number less than the entire batch. In some embodiments, the batch may be divided into equal portions, such as representing one-half, one-third, one-quarter, etc. of the batch, and these portions may be empirically associated with a cumulative limit that is just less than the limit at which the wafers being processed may be substantially contaminated by particle generation due to accumulated off-target deposition in the chamber. In a particular example, the batch may be divided into four equal portions, and after completing their processing, 25%, 50%, 75%, and 100% of the batch are complete. Operation 408 involves processing a portion of the batch of wafers, and may involve (as previously described) sequentially processing multiple groups of wafers (e.g., each group is one, two, to four wafers) so that they are cycled in and out of the chamber for processing. In some embodiments, processing at operation 408 may involve one or more techniques performed on a portion of a batch of wafers, including deposition via an ALD process.

[0052] After the processed wafer is removed from the reaction chamber, processing of the portion is temporarily interrupted to perform batch intermediate processing of the reaction chamber at operation 412. The batch intermediate processing stabilizes off-target material that was inadvertently deposited on the interior surfaces of the reaction chamber during processing of the portion at operation 408.

[0053] One of the benefits of BIAS is that it increases the net throughput of a reactor by increasing the maximum batch size that can be processed by the reactor between mandatory cleaning cycles. Relatively large batch sizes mean that more of the reactor time is available for processing wafers therein rather than for frequently interrupting processing to complete comprehensive auxiliary operations (such as chamber cleaning). Thus, implementing BIAS results in increased throughput as well as reduced defectivity observed in a batch (e.g., that may be caused by frequent processing interruptions to clean the reactor).

[0054] Figure 4B Several variations of a particular type of processing that may be performed at operation 412 are shown. For example, variation A may be used to secure or seal in place off-target deposited material attached to the sidewalls of the reaction chamber, for example, by coating (e.g., depositing) a highly compressible film that bonds the off-target deposited material to the surface to which it is attached (e.g., the sidewalls and / or other internal components of the reaction chamber) to prevent future delamination or decomposition of the off-target deposited material that may interfere with batch wafer processing.

[0055] During batch processing, such a film may be deposited at every set of pre-specified intervals (e.g., at 25%, 50%, or 75% of the total batch limit of the process), such intervals may be determined empirically. Alternatively, batch intermediate processing may be performed at every regular time interval (e.g., every unit time elapsed from the start of processing). In addition, given that the accumulation of off-target material on the interior surfaces of the reaction chamber tends to be proportional to the number of wafers processed therein since the most recent cleaning cycle, the interval at which the batch intermediate chamber coating may be applied may be selected based on a measurement of the accumulated off-target material. Such a measurement may be implemented in addition to or in lieu of applying the batch intermediate chamber coating at a specific fraction of the total batch limit.

[0056] Typical methods for increasing the compressibility of a film or coating coated to incorporate an off-target deposited material by batch intermediate processing of Variation A (a subset of operation 412) include, but are not limited to, coating the film by ALD under the following conditions: high radio frequency (RF) power of 2 kW-7 kW, high voltage of 2 Torr (T)-10 Torr, longer RF time (0.2 s-10 s), or coating the film by other methods apparent to one skilled in the art. Furthermore, in certain embodiments, one or more of the mentioned techniques may be combined in any combination as desired to increase the compressibility of the film.

[0057] Figure 5AA more comprehensive list of exemplary processing conditions is provided in (under the heading "Batch Intermediate - 1 / 2"). For example, suitable batch intermediate processing conditions for applying a compressible film coating at, for example, 50% of the total batch cumulative limit may include precursor flow at a volume flow rate of 500 sccm to 3,000 sccm. Suitable precursors for forming and applying silicon oxide coatings may include silicon-containing substances selected from the group including: BTBAS (bis-tert-butylaminosilane), BDEAS (bis(diethylamino)silane) ((Et2N)2SiH2), or DIPAS (diisopropylaminosilane), which are flowed into the reaction chamber at a volume flow rate of 500-3,000 sccm to form and coat the interior surfaces of the reaction chamber of a UCT such as silicon oxide (SiO2) (e.g., silicate glass). Other suitable exemplary precursors (or reactants) for generating silicon-containing UCTs may include various other bis(alkylamino)silanes, wherein the alkyl groups thereof may contain 1-6 carbon groups. Furthermore, each amino group may be mono- or di-substituted with an alkyl group. In addition, in certain embodiments, variants of alkenyl and alkynyl groups may be used as precursors or reactants for generating silicon-containing UCTs. In some cases or configurations, different alkyl groups may be used on the molecule (e.g., one or more amines may be substituted with methyl groups, and one or more other amines may be substituted with ethyl groups). In certain embodiments, one or more alkyl groups may provide steric hindrance to the silane core. A carrier gas such as argon (Ar) gas may also be flowed into the reaction chamber as required to generate the UCT. In addition, in certain embodiments, the oxygen-containing material may be selected from a group comprising nitrous oxide (N2O) gas and / or oxygen (O2) gas, and may be flowed into the reaction chamber.

[0058] Subsequent purge operations using nitrogen (N2) gas in the illustrated range (e.g., 5,000 sccm-50,000 sccm) can be used to evacuate process reagents from the reaction chamber as needed. In certain embodiments, a second purge operation can be performed at a flow rate range similar to the first purge. The total reaction chamber pressure can be maintained between 1 T and 10 T during deposition (e.g., ALD) and purge operations.

[0059] Likewise, the step timings for deposition and associated purge operations are shown below the approximate flow rate ranges. The dosing timings represent precursor dosing times in seconds; PDP represents post-dosing purge time (e.g., inert gas flow purge time) to remove deposition precursors from the wafer reaction area in the chamber; RF time refers to the period of time that radio frequency (RF) plasma power is on in the presence of reactants during deposition operations; and RF purge time refers to the duration of purge in the absence of reactants or plasma power following RF plasma driven deposition. Additional chamber processing parameters that may be used for adjustment during ALD and purge operations include chamber temperature and power settings. For example, ampoule temperature refers to the temperature of the reactants as they enter the chamber, and may be in the range of 20°C-80°C; gas line temperature refers to the temperature of the process gas as it is delivered to the reaction chamber through the gas line, and may be in the range of 20°C-85°C; susceptor ("ped") temperature refers to the temperature of the susceptor that holds the wafer(s) intended for processing, and may be in the range of 20°C-550°C, depending on the processing application and the requirements of the deposited film; chamber temperature refers to the internal temperature of the reaction chamber during ALD and related purge processes, and may be set in the range of 20°C-85°C; and the top plate temperature may be set in the range of 20°C-85°C.

[0060] Acceptable power settings include Figure 5A , within a specific range of power settings for various chamber components, such as the showerhead ("SHD") and the pedestal ("ped"), both of which may be provided at the frequency ranges shown. In addition, in certain embodiments, a post-treatment process may be provided with Figure 5A The ALD and related purge processes shown in the batch intermediate-1 / 2 process are combined and applied at the approximate power levels, gas species flowing into the reaction chamber, frequencies and time intervals shown.

[0061] In some embodiments, rather than applying a compressible film to coat and seal the off-target deposited materials as described above, the accumulated off-target deposited materials on the interior surface of the reaction chamber may be exposed to a plasma, for example, as shown in Variation B. The plasma exposure may be performed at a low pressure at desired intervals (e.g., 25%, 50%, or 75%) of the total batch accumulation limit, for example, to allow the plasma to more easily diffuse into the off-target deposited materials to secure these materials in place, thereby preventing them from falling onto the batch wafers during processing. For example, suitable reaction chamber processing conditions for Variation B, and optional post-treatment, may be as follows: Figure 5B The plasma can be used in the same manner as for deposition (eg Figure 5AThe plasma may be generated in the same manner as shown in the "Processing" column of FIG. 1 and may be delivered to a processing chamber between a showerhead (which may be powered) and a pedestal (which may be grounded). Additionally, in certain embodiments, the plasma generated as described above may be diffused to improve the quality of material deposited on a carrier ring, which may be positioned within the reaction chamber to hold the wafer during processing. The carrier ring may be made of a high impedance ceramic and positioned or configured to focus the plasma power onto a grounded pedestal.

[0062] In some embodiments, after the plasma treatment described in Variation B, a thin film (e.g., less than 100 μm) may be deposited on the plasma treated off-target deposition material on the interior surface of the reaction chamber. ), as shown in Variation C. In addition, Variation C may involve initially applying a non-dosed (e.g., without the flow of reactive precursors or deposition reagents) oxidizing plasma treatment provided at low pressure. In addition, the plasma provided to first stabilize the off-target deposition material may be generated by argon (Ar) or a mixture of argon and oxygen (O2), which may be obtained from, for example, Figure 1 and 2 Thus, variation C can be accomplished by selecting and applying certain processing parameters (as previously described in Figure 5A The ALD process may involve short reactant flow times to deposit thin films (e.g., less than 100 μm). ).

[0063] In the conventional process of Variation C, chemicals (e.g., reactive materials) for deposition on the substrate 107 may flow out of the showerhead 111. The inert gas used to generate the plasma for Variation C is generally difficult to ignite. Therefore, electrical power may be provided to ignite the inert gas at the faceplate of the showerhead 111. In addition, in such a case, the secondary purge (e.g., which is used to purge gases and / or other materials from the reaction chamber) is turned off so that the plasma can be evenly dispersed outward throughout the processing chamber.

[0064] Next, after exposing the off-target deposition material to plasma as described above, a thin film (e.g., less than ) to fix or solidify the deposited material outside the target in place. Such coatings may include silicon oxide or another suitable oxide. In addition, in some embodiments, additional post-deposition thin film treatments may be performed, such as annealing or plasma treatment.

[0065] Figure 5BVariation D shown may be implemented in combination with any of Variations A, B, and C, and involves grounding the reaction chamber so that the plasma ignited therein eventually diffuses to the outer region of the reaction chamber (e.g., toward the sidewalls). Figure 1 and 2 The base or support of the substrate 107 shown is grounded, while the nozzle that transports the material toward the substrate for deposition thereon is powered. Here, according to variant D and contrary to the conventional configuration, the base can be powered and the nozzle is grounded. For example, it can be selectively applied Figure 5B The parameters shown in the column of "Batch Intermediate-4" shown to result in the reaction chamber being grounded, for example, the susceptor can be operated at a power level in the range of 500W-7kW. This configuration provided by Variation D can assist in targeting areas within the reaction chamber for plasma activation, directionality of coating, and bombardment; for example, toward the sidewalls of the reaction chamber having off-target material deposited thereon. Such a plasma can then diffuse toward areas outside the reaction chamber after being used to treat or dispose of the off-target deposited material on the chamber sidewalls and other chamber components.

[0066] After successful completion of one or more of Variations A to D and / or combinations of Variations A to D (which together constitute the batch intermediate chamber processing at operation 412), another portion of the batch of wafers is placed in the chamber at operation 414 for processing in the chamber at operation 416. Decision operation 420 determines whether the chamber batch size limit has been reached during operations 408 and 416 (for processing the initial portion of the batch of wafers and any additional portions). For example, if the decision result is "no", the process workflow 400 returns to operation 412 to perform additional batch intermediate processing and deposition, thereby allowing additional portions of the batch of wafers to be processed. Therefore, it should be understood by those skilled in the art that the use of BIAS and batch intermediate processing at operation 412 in the process workflow 400 results in an increase in batch size, thereby allowing additional wafers to be processed between mandatory chamber cleaning cycles.

[0067] Eventually, and possibly after multiple executions of the batch intermediate chamber processing operation 412, a total batch accumulation limit will be reached at operation 420, where the interior surfaces of the chamber will have (or may exceed) a threshold amount of off-target material deposited on the interior surfaces of the chamber, resulting in a "yes" result at operation 420. Therefore, the processing workflow 400 will proceed to terminal operation 422, where a chamber clean is performed.

[0068] As mentioned earlier, Figure 5A and 5BA chart is shown providing various exemplary process parameter data values ​​corresponding to various wafer processing and batch intermediate chamber processing operations. The values ​​shown are intended to represent parameters used in various BIAS-related processes described above, but are not exhaustive and are not limiting. Process values ​​and / or parameters may be adjusted as needed to achieve specific wafer processing capacity goals.

[0069] The various individual parameters are listed vertically in Figure 5A and 5B Also, as previously described, the volumetric flow rates of precursors, reactants, and / or inert purge materials into and out of the reaction chamber are provided in units of seem. Figure 5A and 5B The step timing shown in is as previously described, such as batching time, etc. Likewise, the remaining temperature, power level, and parameters included in the optional post-processing settings are as previously described, for example, corresponding to one or more of the following: coating of UCT, or batch intermediate processing performed by any one or more of the variants AD.

[0070] Figure 5A Also shown are approximate parameter setting ranges suitable for batch wafer processing, listed under the "Processing" column. Batch processing may be performed using ALD techniques as previously described to deposit films of desired thickness thereon, and may involve the flow of precursor and reagent species in the amounts and / or combinations shown.

[0071] The remaining columns of UCT, Batch Intermediate-1 / 2, Batch Intermediate-3, and Batch Intermediate-4 represent the application of the primer layer during the pre-treatment aging treatment of the reaction chamber and Variations A to D, respectively. That is, the column header "UCT" indicates the operating conditions or settings for generating and applying the pre-treatment aging treatment primer layer on the interior reaction chamber surface. Likewise, in certain embodiments, the column header "Batch Intermediate-1 / 2" indicates the settings for Variation A; the column header "Batch Intermediate-3" indicates the settings for Variation B; and the column header "Batch Intermediate-4" indicates the settings for Variation D. Variation C can be performed by selectively combining the setting ranges provided in the column headers "Batch Intermediate-1 / 2" and "Batch Intermediate-3".

[0072] Figure 6 Another diagram showing exemplary processing parameters for a remote cleaning recipe that can be used to perform a remote clean of a reaction chamber at, for example, the end of the processing workflow 400 at operation 422. The abbreviations HP and LP stand for "high pressure" and "low pressure," respectively (and are also reflected in Figure 6). Various formulations of materials for generating plasmas used for cleaning can be used. After successfully removing off-target deposited material from the interior surfaces of the reaction chamber through a complete cleaning cycle, the BIAS process as shown in process workflow 300 or 400 can be restarted to process additional batches of wafers as needed.

[0073] equipment

[0074] Figure 7 A schematic diagram depicting an embodiment of an atomic layer deposition (ALD) processing station 700 having a processing chamber 702. The processing station 700 may be used to perform certain disclosed embodiments. For example, while the processing station 700 may be generally used to deposit films on a substrate by atomic layer deposition (ALD), the processing station 700 may be used in certain configurations to, for example, perform atomic layer etching (ALE) or atomic layer cleaning (ALC) to etch or clean, respectively, carbon-containing materials in a patterning scheme. In some embodiments, the processing station 700 may be used for ALE, ALC, and ALD, or in some embodiments, several processing stations in a multi-station tool may include a station for ALE or ALC and a station for ALD so that a substrate may be transferred between an ALC station and an ALD station without breaking vacuum.

[0075] The processing chamber 702 is used to maintain a low pressure environment. A plurality of ALD processing stations can be included in a generally low pressure processing tool environment. For example, Figure 8 One embodiment of a multi-station processing tool 800 is depicted. In some embodiments, one or more hardware parameters of the processing station 700 (including those discussed in detail below) can be programmatically adjusted by one or more computer controllers 750.

[0076] The processing station 700 is in fluid communication with a reactant delivery system 701a to deliver a process gas to a distribution showerhead 706. The reactant delivery system 701a includes a mixing vessel 704 for mixing and / or conditioning a process gas (e.g., an oxygen-containing gas or an inert gas) for delivery to the showerhead 706. One or more mixing vessel inlet valves 720 can control the introduction of the process gas into the mixing vessel 704.

[0077] For example, Figure 7Embodiments include a vaporization point 703, which is used to vaporize liquid reactants to be supplied to the mixing container 704. In some embodiments, deposition chemicals can be provided as vaporized liquid reactants. After performing ALE or ALC in the processing chamber 702, deposition chemicals can be used to form patterned carbonaceous materials so that conformal films can be deposited on the patterned carbonaceous materials by ALD. In some embodiments, the vaporization point 703 can be a heated evaporator. The saturated reactant vapor produced from such an evaporator will condense in the downstream delivery pipeline. Incompatible gases exposed to condensed reactants will produce small particles. These small particles may block pipelines, hinder valve operation, contaminate substrates, etc. Some methods for dealing with these problems involve cleaning and / or emptying the delivery pipeline to remove residual reactants. However, cleaning the delivery pipeline will increase the processing station cycle time and reduce the processing station throughput. Therefore, in some embodiments, the delivery pipeline downstream of the vaporization point 703 can be heat traced. In some embodiments, the mixing container 704 can also be heat traced. In one non-limiting example, the conduit downstream of vaporization point 703 has an increasing temperature profile extending from about 100° C. to about 150° C. at mixing vessel 704 .

[0078] In some embodiments, a liquid precursor or a liquid reactant may be injected into a liquid injector ( Figure 7 703). For example, the liquid injector can inject a pulse of liquid reactant into the carrier gas stream upstream of the mixing vessel 704. In one embodiment, the liquid injector can vaporize the reactant by flashing the liquid from a higher pressure to a lower pressure. In another example, the liquid injector can atomize the liquid into dispersed droplets that are then vaporized in a heated delivery pipe. Smaller droplets can vaporize faster than larger droplets, thereby reducing the delay between liquid injection and completion of vaporization. Faster vaporization can reduce the length of the pipeline downstream of the vaporization point 703. In one embodiment, the liquid injector can be loaded directly into the mixing vessel 704. In another embodiment, the liquid injector can be loaded directly into the spray head 706.

[0079] In some embodiments, a liquid flow controller (LFC) can be set upstream of the vaporization point 703 to control the mass flow rate of the liquid for vaporization and delivery to the processing chamber 702. For example, the LFC can include a thermal mass flow meter (MFM) located downstream of the LFC. Then the plunger valve of the LFC can be adjusted in response to a feedback control signal provided by a proportional integral differential (PID) controller that communicates electrically with the MFM. However, it can take one second or more to use feedback control to stabilize the liquid flow. This can extend the time of dosing liquid reactants. Therefore, in some embodiments, the LFC can be dynamically switched between feedback control mode and direct control mode. In some embodiments, this can be performed by disabling the sensing pipeline of the PID controller and the LFC.

[0080] Showerhead 706 distributes processing gas toward substrate 712. Figure 7 In the illustrated embodiment, substrate 712 is located below showerhead 706 and is shown as being disposed on a chuck or pedestal 708. Showerhead 706 can be positioned at a distance between 350 mils (0.35 inches) and 700 mils (0.7 inches) to achieve a desired degree of ion directionality provided (or distributed) by showerhead 706 toward substrate 712. In some embodiments, a lower, or smaller gap between showerhead 706 and pedestal 708 can be employed to maintain the directionality of ions distributed from showerhead 706. However, under low pressure conditions (e.g., less than 10 mT, or 0.01 Torr), a higher, or larger gap may be required to achieve stable distribution of ionized plasma from showerhead 706. In some embodiments, the chamber may include multiple chucks or pedestals. Showerhead 706 can have any suitable shape and can have any suitable number and arrangement of ports to distribute processing gas to substrate 712.

[0081] In some embodiments, the pedestal 708 can be raised or lowered to expose the substrate 712 to the volume between the substrate 712 and the showerhead 706. In some embodiments, the pedestal 708 can be temperature controlled via a heater 710. During operation of the various disclosed embodiments, the pedestal 708 can be set to any suitable temperature, such as between about 25° C. to about 650° C., or between about 35° C. to about 100° C. It should be understood that in some embodiments, the pedestal height can be programmatically adjusted by a suitable computer controller 750.

[0082] In another case, during the plasma activation performed in certain disclosed embodiments, adjusting the height of the pedestal 708 can allow the plasma density to be varied. For example, the plasma can be ignited while an inert gas is flowing to the substrate 712 via the showerhead 706 to remove the modified core material after the core material is exposed to the oxygen-containing gas. After the processing stage is completed, the pedestal 708 can be lowered during another substrate transfer stage to allow the substrate 712 to be removed from the pedestal 708.

[0083] In some embodiments, the position of the showerhead 706 can be adjusted relative to the base 708 to change the volume space between the substrate 712 and the showerhead 706. In addition, it should be understood that the vertical position of the base 708 and / or the showerhead 706 can be changed by any suitable mechanism within the scope of the present disclosure. In some embodiments, the base 708 may include a rotation axis for rotating the orientation of the substrate 712. It should be understood that in some embodiments, one or more of these exemplary adjustments can be performed programmatically by one or more appropriate computer controllers 750. The computer controller 750 may include the following reference Figure 7 Any of the features described for controller 750.

[0084] In some embodiments where plasma can be used as described above, the showerhead 706 and the base 708 are electrically connected to a radio frequency (RF) power source 714 and a matching network 716 to provide power to the plasma. In some embodiments, the energy of the plasma can be controlled by controlling one or more of the pressure of the processing station, the concentration of the gas, the RF source power, the RF source frequency, and the plasma power pulse timing. For example, the RF power source 714 and the matching network 716 can be operated at any suitable power to form a plasma with a component of a desired free radical substance. Similarly, the RF power source 714 can provide RF power of any appropriate frequency. In some embodiments, the RF power source 714 can be configured to control a high-frequency RF power source and a low-frequency RF power source that are independent of each other. Exemplary low-frequency RF frequencies can include, but are not limited to, frequencies between 0kHz and 500kHz. Exemplary high-frequency RF frequencies can include, but are not limited to, frequencies between 1.8MHz and 2.45GHz, for example, frequencies greater than about 13.56MHz, or greater than 27MHz, or greater than 40MHz, or greater than 60MHz. It will be appreciated that any suitable parameters may be adjusted discretely or continuously to provide plasma energy for surface reactions.

[0085] In some embodiments, the plasma can be monitored in situ by one or more plasma monitors. In one case, the plasma power can be monitored by one or more voltage and current sensors (e.g., VI probes). In another case, the plasma density and / or the concentration of the process gas can be measured by one or more optical emission spectrometer sensors (OES). In some embodiments, one or more plasma parameters can be adjusted programmatically based on the measurement results from such an in-situ plasma monitor. For example, an OES sensor can be used in a feedback loop to provide programmatic control of the plasma power. In some embodiments, using certain disclosed embodiments, an OES sensor can be used to set the endpoint to stop etching after a certain time. It should be understood that in some embodiments, other monitors can be used to monitor plasma and other processing characteristics. Such monitors may include, but are not limited to, infrared (IR) monitors, acoustic monitors, and pressure sensors.

[0086] In some embodiments, instructions for controller 750 may be provided via input / output control (IOC) sequencing instructions. In one example, instructions for setting the conditions of a processing stage may be included in a corresponding recipe stage of a processing recipe. In some cases, the processing recipe stages may be arranged in sequence so that all instructions for a processing stage are executed simultaneously with the processing stage. In some embodiments, instructions for setting one or more reactor parameters may be included in a recipe stage. For example, a first recipe stage may include: instructions for setting the flow rate of an inert gas and / or a reaction gas (e.g., an oxygen-containing gas) for the first recipe stage, instructions for setting the flow rate of a carrier gas (such as argon), and a time delay instruction. A subsequent second recipe stage may include: instructions for adjusting or stopping the flow rate of an inert gas and / or a reaction gas for the second recipe stage, instructions for adjusting the flow rate of a carrier or purge gas, and a time delay instruction. The third recipe stage may include instructions for adjusting the flow rate of a second gas (e.g., argon) for the third recipe stage, instructions for adjusting the flow rate of a carrier gas or a purge gas, instructions for igniting a plasma at a low plasma power between about 250 W and about 750 W for a four-station processing tool, and a time delay instruction. A subsequent fourth recipe stage may include instructions for adjusting or stopping the flow rate of an inert gas and / or a reactant gas for the third recipe stage, and instructions for adjusting the flow rate of a carrier gas or a purge gas, and a time delay instruction. Such recipes may be used to etch carbon-containing materials (e.g., core materials) on a substrate to produce vertical sidewalls that intersect the underlying surface to be etched at an intersection of about 90°±5°. Additional recipes may also be performed in succession and may be used to deposit a conformal film on the patterned core material by ALD. For example, to deposit a conformal film of silicon oxide on a patterned core material, an additional recipe stage may include: instructions for setting a flow rate of a silicon-containing precursor, and another additional recipe stage may include: instructions for setting a flow rate of an oxygen-containing reactant for the additional recipe stage; and a time delay instruction. It should be understood that within the scope of the present disclosure, these recipe stages may be further subdivided and / or repeated in any suitable manner.

[0087] Additionally, in some embodiments, pressure control for the processing station 700 may be provided by a butterfly valve 718. Figure 7 In the embodiment shown in FIG. 1 , the butterfly valve 718 is connected to the downstream vacuum pump ( Figure 7 However, in some embodiments, the pressure control process station 700 can also be adjusted by changing the flow rate of one or more gases introduced into the process station 700.

[0088] As described above, one or more processing stations may be included in a multi-station processing tool. Figure 8A schematic diagram of one embodiment of a multi-station processing tool 800 is shown having an inbound load lock 802 and an outbound load lock 804, either or both of which may contain a remote plasma source ( Figure 8 802). The robot 806 at atmospheric pressure is configured to move wafers from a wafer box loaded by a wafer boat 808 into an inbound load lock 802 via an atmospheric port 810. Figure 8 The wafer is then placed on a pedestal 812 in the inbound load lock 802 by a robot 806 (not shown), the atmosphere port 810 is closed, and the inbound load lock 802 is evacuated. When the inbound load lock 802 includes a remote plasma source, the wafer can be exposed to remote plasma treatment in the inbound load lock 802 before being introduced into the processing chamber 814. In addition, the wafer can also be heated in the inbound load lock 802, for example to remove moisture and adsorbed gases. Next, the chamber transfer port 816 leading to the processing chamber 814 is opened, and another robot (not shown) places the wafer into the reactor on a pedestal at the first station shown in the reactor for processing. Although in Figure 8 The embodiment depicted in FIG. 1 includes a load lock, but it should be understood that in some embodiments, wafers may be allowed to enter the processing station directly.

[0089] The depicted processing chamber 814 includes four processing stations, Figure 8 In the embodiment shown, the stations are numbered 1 to 4. Each station has a heated susceptor (shown as 818 for station 1) and a gas line inlet. It should be understood that in some embodiments, each processing station may have different or multiple uses. For example, in some embodiments, the processing station may be switchable between ALC, ALD and plasma-enhanced ALD processing modes. In some embodiments, exposure to the deposition precursor and exposure to the second reactant and plasma are performed in the same station. Additionally or alternatively, in some embodiments, the processing chamber 814 may include a matching pair of one or more ALD and plasma-enhanced ALD processing stations. Although the processing chamber 814 depicted includes 4 stations, it is understood that the processing chamber described in the present disclosure may have any appropriate number of stations. For example, in some embodiments, the processing chamber may have 5 or more stations, while in other embodiments, the processing chamber may have 3 or fewer stations.

[0090] Figure 8 One embodiment of a wafer handling system 890 for transferring wafers within the processing chamber 814 is depicted. In some embodiments, the wafer handling system 890 can transfer wafers between various processing stations and / or between a processing station and a load lock. It should be understood that any suitable wafer handling system can be used. Non-limiting examples include a wafer turntable and a robot for handling wafers. Figure 8 Also depicted is one embodiment of a system controller 850 for controlling processing conditions and hardware states of the processing tool 800. The system controller 850 may include one or more memory devices 856, one or more mass storage devices 854, and one or more processors 852. The processor 852 may include a computer or CPU, analog and / or digital input / output connections, a stepper motor controller board, etc.

[0091] In some embodiments, the system controller 850 controls all activities of the processing tool 800. The system controller 850 executes system control software 858 stored in the mass storage device 854, loaded into the memory device 856, and executed by the processor 852. Alternatively, the control logic can be hard-coded in the controller 850. Application-specific integrated circuits, programmable logic devices (e.g., field programmable gate arrays, or FPGAs), etc. can be used for these purposes. In the following discussion, whether "software" or "code" is used, functionally equivalent hard-coded logic can be used instead. The system control software 858 can include instructions for controlling timing, mixing of gases, gas flow rates, chamber and / or station pressures, chamber and / or station temperatures, wafer temperatures, target power levels, RF power levels, substrate pedestals, chucks and / or susceptor positions, and other parameters of specific processing performed by the processing tool 800. The system control software 858 can be configured in any appropriate manner. For example, various processing tool component subroutines or control objects can be written to control the operation of processing tool components used to perform various processing tool processes. The system control software 858 may be coded in any suitable computer readable programming language.

[0092] In some embodiments, the system control software 858 may include input / output control (IOC) sequencing instructions for controlling the various parameters described above. Other computer software and / or programs associated with the system controller 850 and stored in the mass storage device 854 and / or the memory device 856 may be employed in some embodiments. Examples of programs or program segments for this purpose include substrate positioning programs, process gas control programs, pressure control programs, heater control programs, and plasma control programs.

[0093] The substrate positioning program may contain program code for the processing tool components used to load the substrate into the pedestal 818 and control the spacing between the other parts of the processing tool 800 and the substrate.

[0094] The process gas control program may include code for controlling gas composition (e.g., silicon-containing gas, oxygen-containing gas, and sweep gas as described herein) and flow rate and optionally code for flowing gas into one or more process stations prior to deposition to stabilize the pressure in the process station. The pressure control program may include code for controlling the pressure within a process station by adjusting, for example, a throttle valve in an exhaust system of the process station, gas flow into the process station, and the like.

[0095] The heater control program may contain code for controlling the flow of current to a heating unit used to heat the substrate.Alternatively, the heater control program may control the delivery of a heat transfer gas (such as helium) toward the substrate.

[0096] A plasma control program may include code for setting RF power levels applied to process electrodes within one or more process stations according to embodiments herein.

[0097] The pressure control program may include code for maintaining the pressure within the reaction chamber according to embodiments herein.

[0098] In some embodiments, there may be a user interface associated with the system controller 850. The user interface may include a display screen, a graphical software display of apparatus and / or processing conditions, and user input devices such as a pointing device, keyboard, touch screen, microphone, and the like.

[0099] In some embodiments, the parameters adjusted by the system controller 850 may relate to process conditions. Non-limiting examples include process gas composition and flow rate, temperature, pressure, plasma conditions (e.g., RF bias power level), etc. These parameters may be provided to the user in the form of a recipe, which may be entered using the user interface.

[0100] Signals for monitoring the process may be provided from various process tool sensors by analog and / or digital input connections of the system controller 850. Signals for controlling the process may be output via analog and / or digital output connections of the process tool 800. Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (e.g., manometers), thermocouples, etc. Appropriately programmed feedback and control algorithms may be used with the data from these sensors to maintain process conditions.

[0101] The system controller 850 may provide program instructions for performing the above-described deposition process. The program instructions may control various process parameters, such as DC power level, RF bias power level, pressure, temperature, etc. The instructions may control these parameters to operate the in-situ deposition of the film stack according to the various embodiments described herein.

[0102] The system controller 850 will typically include one or more memory devices and one or more processors configured to execute instructions so that the apparatus will perform the methods described in accordance with the disclosed embodiments. A machine-readable medium containing instructions for controlling processing operations in accordance with the disclosed embodiments may be coupled to the system controller 850.

[0103] In some implementations, the system controller 850 is part of a system, which can be part of the above examples. Such a system can include a semiconductor processing device, which includes one or more processing tools, one or more processing chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems can be integrated with electronic devices for controlling their operations before, during, and after processing semiconductor wafers or substrates. The electronic device can be referred to as a "controller", which can control various elements or subcomponents of one or more systems. Depending on the processing conditions and / or the type of system, the system controller 850 can be programmed to control any of the processes disclosed herein, including controlling process gas delivery, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer in and out of tools and other transfer tools and / or load locks connected to or connected to a specific system through an interface.

[0104] In a broad sense, the system controller 850 refers to an electronic device having various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, and the like. The integrated circuit may include a chip in the form of firmware that stores program instructions, a digital signal processor (DSP), a chip defined as an application specific integrated circuit (ASIC), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). The program instructions may be instructions transmitted to the system controller 850 in the form of various separate settings (or program files) that define operating parameters for performing a particular process on or for a semiconductor wafer or system. In some embodiments, the operating parameters may be part of a recipe defined by a process engineer for completing one or more processing steps during the preparation of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0105] In some implementations, the system controller 850 may be part of or coupled to a computer that is integrated with, coupled to, or connected to the system through a network, or a combination thereof. For example, the system controller 850 may be in the "cloud" or all or part of a wafer fab host system, thereby allowing remote access to wafer processing. The computer may enable remote access to the system to monitor the current progress of a manufacturing operation, check the history of past manufacturing operations, check trends or performance standards for multiple manufacturing operations, change parameters of the current process, set processing steps to follow the current process, or start a new process. In some examples, a remote computer (e.g., a server) may provide a processing recipe to the system through a network, which may include a local network or the Internet. The remote computer may include a user interface that allows input or programming of parameters and / or settings, which are then transmitted from the remote computer to the system. In some examples, the system controller 850 receives instructions in the form of data that specify parameters for each processing step to be performed during one or more operations. It should be understood that the parameters may be for the type of process to be performed and the type of tool to which the system controller 850 is configured to connect or control the tool type. Thus, as described above, the system controller 850 can be distributed, for example, by including one or more discrete controllers that are networked together and work toward a common goal (e.g., the processing and control described herein). An example of a distributed controller for these purposes can be one or more integrated circuits on the chamber that communicate with one or more remote integrated circuits (e.g., at the platform level or as part of a remote computer), which combine to control the processing within the chamber.

[0106] Example systems may include, but are not limited to, plasma etching chambers or modules, deposition chambers or modules, spin cleaning chambers or modules, metal plating chambers or modules, cleaning chambers or modules, chamfer edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, ALD chambers or modules, atomic layer cleaning chambers (ALC) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing system that may be associated with or used in the preparation and / or manufacture of semiconductor wafers.

[0107] As described above, depending on the one or more processing steps to be performed by the tool, the system controller 850 can communicate with one or more other tool circuits or modules, other tool components, combination tools, other tool interfaces, adjacent tools, adjacent tools, tools located throughout the factory, a host computer, another controller, or tools used in material handling to move containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing facility.

[0108] Suitable apparatus for performing the methods disclosed herein are further discussed and described in U.S. patent application Ser. No. 13 / 084,399, filed on April 11, 2011, entitled “PLASMA ACTIVATED CONFORMAL FILM DEPOSITION” (now U.S. Patent No. 8,728,956); U.S. patent application Ser. No. 13 / 084,305, filed on April 11, 2011, entitled “SILICON NITRIDE FILMS AND METHODS,” each of which is incorporated herein in its entirety.

[0109] The apparatus / processes described herein can be used in conjunction with photolithographic patterning tools or processes, e.g., for preparing or manufacturing semiconductor devices, displays, LEDs, photovoltaic panels, etc. Typically, though not necessarily, these tools / processes will be used or operated together in a common manufacturing facility. Photolithographic patterning of films typically involves some or all of the following operations, each of which enables multiple available tools: (1) applying photoresist on a workpiece (i.e., substrate) using a spin coating or spray coating tool; (2) curing the photoresist using a hot plate or oven or UV curing tool; (3) exposing the photoresist to visible light or ultraviolet light or x-rays using a tool such as a wafer stepper; (4) developing the resist to selectively remove the resist and thereby pattern it using a tool such as a wet bench; (5) transferring the resist pattern to an underlying film or workpiece by using a dry or plasma assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper.

[0110] in conclusion

[0111] Although the above embodiments have been described in some detail for the purpose of clarity of understanding, it is apparent that certain variations and modifications may be implemented within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems and devices of the embodiments of the present invention. Therefore, the embodiments of the present invention should be considered illustrative rather than restrictive, and the embodiments are not limited to the details given herein.

Claims

1. A method for increasing a batch size of a reaction chamber, the method comprising: (a) processing a portion of a batch of wafers within the reaction chamber, wherein the processing results in ex-target deposition of at least some material on interior surfaces of the reaction chamber; (b) performing a batch intermediate chamber process to stabilize the off-target deposition material accumulated on the interior surface of the chamber; and (c) processing another portion of the batch of wafers within the reaction chamber, Wherein (b) comprises depositing a film bonded to the material accumulated on the interior surface of the reaction chamber.

2. The method according to claim 1, further comprising: (b) to (c) are repeated until the processing of the batch of wafers is completed.

3. The method of claim 1, wherein the chamber batch size is the number of wafers that can be processed in the chamber between chamber cleaning cycles.

4. The method according to claim 1, further comprising: Prior to batch processing in the reaction chamber, the interior surface of the reaction chamber is subjected to an aging treatment.

5. The method according to claim 4, wherein the aging treatment of the inner surface of the reaction chamber comprises: A coating of the same material as that used to be deposited on the batch of wafers during (a) or (c) is applied.

6. The method of claim 1, wherein (a) or (c) comprises depositing material on wafers in the batch of wafers.

7. The method of claim 4, wherein the aging treatment comprises applying a coating on the interior surface of the reaction chamber by atomic layer deposition (ALD) when no wafer is present in the reaction chamber.

8. The method according to claim 1, further comprising: (d) After (c) is completed, cleaning the interior surfaces of the reaction chamber.

9. The method according to claim 2, further comprising: (d) After processing of the batch of wafers is completed, cleaning the interior surface of the reaction chamber.

10. The method of claim 1, wherein (b) is performed at specified intervals of a total batch cumulative limit of the batch of wafers.

11. The method of claim 10, wherein the total batch accumulation limit is the thickness of accumulated material on the interior surface of the reaction chamber, beyond which processing is compromised, necessitating cleaning of the reaction chamber before further processing. The method of claim 10 , wherein the specified interval is determined empirically.

13. The method of claim 10, wherein the specified interval occurs prior to a deleterious level of material accumulation on the interior surfaces of the reaction chamber that results in delamination of the material and wafer defects and / or particle generation.

14. The method of claim 1, wherein the compressibility of the film is enhanced by adjusting any one or more selected from the group consisting of: radio frequency (RF) power level, reaction chamber pressure, or RF treatment time.

15. The method of claim 1, wherein (b) further comprises: After the material accumulates to a specified thickness, the material accumulated on the interior surface of the reaction chamber is exposed to plasma.

16. The method of claim 15, wherein the plasma exposure is performed at a pressure in the range of 1 Torr to 10 Torr to promote diffusion of plasma into a film deposited on the material accumulated on the interior surface of the reaction chamber.

17. The method of claim 15, wherein the plasma is ignited on a faceplate of a showerhead within the reaction chamber.

18. The method according to claim 15, further comprising: Sweeping is disabled to allow the plasma to be evenly dispersed throughout the reaction chamber.

19. The method of claim 15, wherein the plasma is derived from any one of the group consisting of: hydrogen, helium, argon, or a nitrogen-containing source.

20. The method of claim 15, wherein exposure to the plasma A film of about 100 microns or less is deposited on the material accumulated on the interior surface of the reaction chamber.

21. The method of claim 20, wherein the deposited film stabilizes the material on the interior surface of the reaction chamber.

22. The method of claim 20, wherein the exposure to the plasma densifies the deposited film to stabilize the material on the interior surfaces of the reaction chamber.

23. The method of claim 14, wherein the compressibility of the film is increased by a method selected from the group consisting of: applying a radio frequency (RF) power in the range of 2 kW-7 kW, applying a high voltage in the range of 2 Torr-10 Torr, or using an RF plasma time of 0.2 s-10 s.

24. The method of claim 14, further comprising: (d) grounding the reaction chamber.

25. The method of claim 24, wherein grounding the reaction chamber promotes diffusion of plasma toward a sidewall of the reaction chamber to an outside of the reaction chamber.

26. The method of claim 25, wherein a showerhead configured to deliver a deposition gas to the batch of wafers is powered.

27. The method of claim 25, wherein a susceptor configured to support the batch of wafers is powered.

28. The method of claim 9, wherein the plasma used to perform (d) is supplied by a remote plasma cleaning unit.

29. The method of claim 28, wherein the remote plasma cleaning unit is mounted on the reaction chamber.

30. The method of claim 15, wherein the plasma has a frequency of 400 kHz.

31. A plasma processing apparatus for processing a substrate, the apparatus comprising: A reaction chamber comprising: Internal chamber surface, a substrate support for supporting a substrate within the reaction chamber, and an exhaust port for removing material from the reaction chamber; A remote plasma chamber comprising: a plasma generator for generating plasma in the remote plasma chamber, an inlet for delivering a gas to the remote plasma chamber, an outlet for providing the plasma generated in the remote plasma chamber to the reaction chamber; and A controller configured to execute instructions for: (a) processing a portion of a batch of wafers within the reaction chamber, wherein the processing results in ex-target deposition of at least some material on interior surfaces of the reaction chamber; (b) performing batch intermediate chamber processing to stabilize off-target deposition material accumulated on interior surfaces of the chamber; and (c) processing another portion of the batch of wafers within the reaction chamber, Wherein (b) comprises depositing a film bonded to the material accumulated on the interior surface of the reaction chamber.

32. The plasma processing apparatus of claim 31, wherein the remote plasma chamber is separate from the reaction chamber.

33. The plasma processing apparatus of claim 31 , wherein the controller is further configured to execute instructions for: (d) After (c) is completed, cleaning the interior surface of the reaction chamber.

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