Method for manufacturing a plurality of semiconductor chips and semiconductor chip

Abstract

A method for producing a plurality of semiconductor chips (100), the method comprising step A), wherein a semiconductor substrate (1) is provided, the semiconductor substrate having a plurality of integrated electronic circuits (2) on the upper side (10) of the semiconductor substrate (1). In step B), a sacrificial layer (3) is applied to one side of the semiconductor substrate. In step C), holes (30) are introduced into the sacrificial layer, so that at least one hole is produced above each electronic circuit. In step D), the semiconductor substrate with the sacrificial layer is previously pasted onto a carrier (5), wherein an adhesive layer (4) is used between the sacrificial layer and the carrier and wherein the adhesive layer fills the holes, so that a retaining element (40) consisting of the adhesive layer is produced in the holes. In step E), the semiconductor substrate is thinned. In step F), separation trenches (6) are introduced between the electronic circuits, the separation trenches extending from the side of the electronic circuit facing away from the carrier to the sacrificial layer and penetrating the thinned semiconductor substrate. In step G), the sacrificial layer is removed in the region between the electronic circuit and the carrier.

Description

Technical Field

[0001] A method for producing a plurality of semiconductor chips is specified. Furthermore, a semiconductor chip is specified. Summary of the invention

[0002] The object to be achieved is to specify a method which enables parallel mounting of a plurality of semiconductor chips. Another object to be achieved is to specify a semiconductor chip produced by means of the method.

[0003] The object is achieved in particular by a method for producing a plurality of semiconductor chips and a semiconductor chip. Advantageous embodiments and developments are the subject of the following description.

[0004] According to at least one embodiment, the method comprises a step A), in which a semiconductor substrate is provided, which has a plurality of integrated electronic circuits on a top side of the semiconductor substrate.

[0005] The semiconductor substrate preferably extends along the main extension plane. The upper side of the semiconductor substrate can extend substantially parallel to the main extension plane. The semiconductor substrate is, for example, a silicon substrate. The electronic circuits are arranged side by side on the upper side.

[0006] Each electronic circuit may include one or more electronic devices connected to each other. For example, the electronic circuit includes one or more transistors and / or one or more diodes and / or one of a plurality of resistors and / or one or more capacitors. The transistor may be a field effect transistor or a bipolar transistor.

[0007] The electronic circuit is integrated into the semiconductor substrate. That is, the electronic components of the electronic circuit are partially integrated into the semiconductor substrate. In each electronic circuit, a region of the semiconductor substrate is formed, in particular a region directly below the upper side, forming a functional component of at least one electronic component. Therefore, during normal operation of the electronic circuit, a current or carrier transport occurs in said region of the semiconductor substrate. In particular, the semiconductor substrate can include an n-doped region and / or a p-doped region below the upper side, which is, for example, a component of a transistor or a diode.

[0008] The semiconductor substrate can be formed in a connected, preferably single connected manner. The semiconductor substrate spans a plurality of electronic circuits and connects the electronic circuits to one another. In other words, the electronic circuits are provided in the wafer composite.

[0009] The lateral extent of the semiconductor substrate measured parallel to the main plane of extension is, for example, between 100 mm and 500 mm inclusive.

[0010] The electronic circuits include, in particular, wiring layers formed on the upper side of the semiconductor substrate. Each wiring layer includes, for example, an electrically insulating material, such as an oxide, in particular silicon oxide. Conductive tracks, in particular metal conductive tracks, are embedded in the electrically insulating material (ILD: interlayer dielectrics). The conductive tracks can be electrically connected to the semiconductor substrate. A portion of the conductive tracks and the semiconductor substrate can form a transistor, a diode or a resistor in the electronic circuit. Capacitors in the electronic circuit are formed, for example, within the wiring layers by conductive tracks spaced apart from one another. The thickness of the wiring layers is, for example, between 3 μm and 15 μm, inclusive of limit values.

[0011] The wiring layers of the electronic circuits can first be connected, that is, a connected wiring layer is formed on the upper side of the semiconductor substrate. In the area between the electronic circuits, the connected wiring layer then preferably has no printed conductors. For example, the wiring layer is formed there only by an electrically insulating material.

[0012] Alternatively, the interconnecting wiring layer can also be formed of a metal, such as aluminum or titanium or copper or tungsten, in the region between the electronic circuits. The metal is then preferably electrically insulated from the printed conductors of the electronic circuits. Preferably, the interconnecting wiring layer is formed of a metal over its entire thickness in the region.

[0013] According to at least one embodiment, the method comprises a step B), wherein a sacrificial layer is applied to one side of the semiconductor substrate. For example, the sacrificial layer can be applied to the electronic circuit. Alternatively, the sacrificial layer can be applied to the underside of the semiconductor substrate opposite the electronic circuit.

[0014] The sacrificial layer comprises, for example, silicon or silicon oxide or consists of one of these materials. The sacrificial layer is preferably applied as a connected, in particular singly connected layer, which extends over a plurality of electronic circuits or over all electronic circuits. The thickness of the sacrificial layer is, for example, between 100 nm and 1 μm, inclusive.

[0015] According to at least one embodiment, the method comprises a step C), in which a plurality of holes are introduced into the sacrificial layer, so that at least one hole is produced above each electronic circuit. The hole preferably completely penetrates the sacrificial layer. The hole can be introduced, for example, by means of a photolithographic mask and an etching method. For example, exactly one hole or a plurality of holes, for example a maximum of 20 holes or a maximum of 10 holes, are introduced in the region of each electronic circuit.

[0016] According to at least one embodiment, in step D), the semiconductor substrate is previously bonded together with the electronic circuit and the sacrificial layer to a carrier, wherein an adhesive layer is used between the sacrificial layer and the carrier and wherein the adhesive layer fills the hole so that a holding element consisting of the adhesive layer is produced in the hole. The adhesive layer can first be introduced onto the sacrificial layer and into the hole. The adhesive layer is applied to the side of the sacrificial layer facing away from the electronic circuit. The adhesive layer is preferably formed in a continuous manner.

[0017] The size of the holding element substantially corresponds to the size of the hole in the sacrificial layer. For example, the holding elements each have a diameter of at most 10 μm or at most 5 μm or at most 3 μm, measured along the main extension plane. Alternatively or additionally, the diameter of each holding element is at least 0.5 μm or at least 1 μm. The holding elements are, for example, cylindrical. The height of each holding element, measured as an extension perpendicular to the main extension plane of the semiconductor substrate, is, for example, between 100 nm and 1 μm, inclusive.

[0018] The adhesive layer comprises, for example, benzocyclobutene, BCB for short, and / or an epoxide-based adhesive. Alternatively, the adhesive layer consists of one of these materials. The epoxide-based adhesive preferably has a glass transition temperature of at least 250° C. The semiconductor substrate is connected to the carrier in a material-fitting manner via the adhesive layer. For this purpose, the adhesive is, for example, hardened.

[0019] The carrier can include or consist of a semiconductor material or glass. The lateral extent of the carrier is preferably at least as great as the lateral extent of the semiconductor substrate, so that the semiconductor substrate can be placed on the carrier over its entire surface. The lateral extent is defined here as the extension parallel to the respective main extension plane of the semiconductor substrate or carrier.

[0020] According to at least one embodiment, the method comprises a step E), in which the semiconductor substrate is thinned, that is to say its thickness is reduced. For example, the semiconductor substrate is ground and / or polished and / or etched for this purpose. For example, the semiconductor substrate is thinned to a target thickness of between 3 μm and 30 μm, limit values ​​included. Prior to this, the thickness of the semiconductor substrate is, for example, at least 100 μm or at least 500 μm.

[0021] According to at least one embodiment, the method comprises a step F), in which separation trenches are introduced between the electronic circuits. The separation trenches extend from the side of the electronic circuit facing away from the carrier to the sacrificial layer and penetrate the thinned semiconductor substrate. The sacrificial layer is exposed in the region of the separation trenches. The separation trenches can be introduced, for example, in the form of a grid, so that each electronic circuit is completely surrounded laterally, that is to say along the main extension plane, by connected separation trenches. The width of the separation trenches is, for example, between 1 μm and 20 μm, inclusive.

[0022] In particular, the separation trenches define the size of the semiconductor chips produced by the method. For example, the lateral extension of each semiconductor chip or the lateral extension of the mesh surrounded by the separation trenches is at least 10 μm or at least 50 μm. Alternatively or additionally, the lateral extension is at most 1000 μm or at most 300 μm or at most 200 μm. Each semiconductor chip or each mesh surrounded by the separation trenches can have an area of ​​at least 10 μm×10 μm and / or at most 1000 μm×1000 μm.

[0023] The separation trenches extend in particular through the thinned semiconductor substrate and through the interconnecting wiring layers, so that after the introduction of the separation trenches the electronic circuits are no longer connected to one another via the semiconductor substrate or the interconnecting wiring layers. The electronic circuits are then preferably connected to one another only via the second carrier.

[0024] By introducing the separation trenches, the interconnected semiconductor substrate together with the interconnected wiring layers applied thereon is thus divided into a plurality of semiconductor chips. Each semiconductor chip then comprises an electronic circuit, a part of the interconnected semiconductor substrate and the wiring layers.

[0025] According to at least one embodiment, the method comprises a step G), in which the sacrificial layer is removed in the region between the electronic circuit and the carrier, so that the electronic circuit is held on the second carrier via the holding element, in particular only via the holding element. For example, at least 80% or at least 90% or at least 99% of the sacrificial layer is removed from the region between the electronic circuit and the carrier.

[0026] The holding elements form a point-shaped mechanical support below each electronic circuit. In the areas next to the holding elements, the electronic circuits are not connected to the carrier, so that the electronic circuits are arranged in these areas suspended above the carrier without mechanical support. In other words, the electronic circuits are mechanically connected to the carrier via the holding elements only in a small area fraction of the total area of ​​the electronic circuits, for example up to 10%. This enables the electronic circuits to be easily removed from the carrier. However, until the electronic circuits are removed from the carrier, they remain connected to each other in their original configuration due to the carrier.

[0027] The sacrificial layer is removed in particular by etching away the sacrificial layer. To this end, the etchant can reach the sacrificial layer via the separation trenches.

[0028] In at least one embodiment, the method comprises a step A) for manufacturing a plurality of semiconductor chips, wherein a semiconductor substrate is provided, the semiconductor substrate having a plurality of integrated electronic circuits on the upper side of the semiconductor substrate. In step B), a sacrificial layer is applied to one side of the semiconductor substrate. In step C), a hole is introduced into the sacrificial layer so that at least one hole is generated via each electronic circuit. In step D), the semiconductor substrate and the sacrificial layer are previously pasted to a carrier, wherein an adhesive layer is used between the sacrificial layer and the carrier and wherein the adhesive layer fills the hole so that a retaining element consisting of the adhesive layer is generated in the hole. In step E), the semiconductor substrate is thinned. In step F), a separation trench is introduced between the electronic circuits, the separation trench extending from the side of the electronic circuit facing away from the carrier to the sacrificial layer and penetrating the thinned semiconductor substrate. In step G), the sacrificial layer in the region between the electronic circuit and the carrier is removed so that the electronic circuit is retained on the carrier via a retaining element.

[0029] The use of a sacrificial layer structured with holes and filling these holes with an adhesive layer to produce a holding element results in the electronic circuit being only fixed to the carrier via the holding element after the sacrificial layer has been removed. The holding element thus forms a support or a pillar between the carrier and the electronic circuit. Therefore, only very little force is required to peel the electronic circuit from the carrier. Until the peeling, the electronic circuit is still arranged in its original configuration, that is to say in its original arrangement and at its original spacing from one another. As a result, a plurality of electronic circuits can be mounted or printed in parallel, wherein easy peeling from the carrier is ensured.

[0030] According to at least one embodiment, steps A) to G) are performed as separate steps sequentially and in a given order.

[0031] According to at least one embodiment, after step G), the contact surface between the holding element and the electronic circuit is at least 0.1% or at least 1% of the entire surface of the electronic circuit facing the carrier. Alternatively or additionally, the contact surface is a maximum of 10% or a maximum of 8% or a maximum of 5% of the entire surface of the electronic circuit facing the carrier. The remainder of the surface facing the carrier is arranged suspended above the carrier and is not mechanically connected to the carrier. This small share of the contact surface in the total area of ​​the electronic circuit ensures that the electronic circuit can be easily removed from the carrier.

[0032] According to at least one embodiment, in order to carry out step F), an intermediate step F1) is carried out, in which a photoresist layer is applied to the side of the electronic circuit facing away from the carrier. The photoresist layer can be a positive or negative photoresist.

[0033] According to at least one embodiment, an intermediate step F2) is performed in order to perform step F), in which the photoresist layer is structured with grooves, wherein the grooves are formed at the locations where the separation grooves are to be produced later. The grooves in the photoresist layer completely penetrate the photoresist layer and define the locations of the separation grooves to be formed later. In particular, the grooves in the photoresist layer are thus also formed around the electronic circuit and, for example, form a grid.

[0034] According to at least one embodiment, an intermediate step F3) is performed for performing step F), in which an etching method for producing separation trenches is applied in the region of the trenches. For example, a dry-chemical or wet-chemical etching method is applied. The etchant then passes through the trenches to the material connecting the electronic circuit and can etch the separation trenches into said material.

[0035] According to at least one embodiment, steps F1), F2) and F3) are performed in the given order.

[0036] According to at least one embodiment, the carrier is a transparent carrier, for example a glass carrier. "Transparent" here means transparent for visible light. The transparent carrier can advantageously identify structures of the electronic circuit. Such structures can be, for example, metallic contact structures or markings. These structures can be used to adjust the separation grooves or trenches. For example, a device with backside adjustment is used for this purpose.

[0037] Alternatively, however, it is also possible to form the carrier from an opaque material, such as silicon. The position of the structure that passes through the material of the semiconductor substrate or through the material of the carrier can then be determined by means of an infrared camera and adjustments can be made to the separation trenches or trenches based thereon. In this case, a device with front-side adjustment can be used.

[0038] According to at least one embodiment, an anisotropic, fluorine-based etching process is performed in step F) to produce the separation trenches. The etching process can be, for example, dry chemical. In particular, such an etching process is suitable for penetrating the semiconductor substrate. In this case, for example, fluorine-containing gases such as SF6 are used. This etching process is also known as the Bosch process. In this case, a fluorine-containing polymer is formed in the region of the penetrated semiconductor substrate, which forms a lateral etching stop layer. By this etching method, separation trenches with particularly steep side walls can be produced.

[0039] In order to make the interconnected wiring layer penetrate in the area between the electronic circuits by means of the separation trench, another etching agent, such as hydrofluoric acid, can be used. It is particularly advantageous that, as has been explained above, the interconnected wiring layer is formed of metal in the area between the electronic circuits and where the separation trench is to be formed. Therefore, the separation trench can then be formed through the metal. Metals are generally easier to etch than, for example, oxides. Aluminum or titanium are suitable as metals, for example. Then the metal can be selectively etched for the oxide surrounding the interconnected connection layer.

[0040] According to at least one embodiment, a dry chemical etching method is used to remove the sacrificial layer in step G). For example, the same anisotropic, fluorine-based etching process is used to remove the sacrificial layer as in step F). For example, SF6 or XeF2 is used as an etchant.

[0041] According to at least one embodiment, the etchant used in step G) reaches the sacrificial layer via the separation trenches. The etchant removes, for example, at least 80% or at least 90% or at least 99% of the sacrificial layer in the region between the electronic circuit and the carrier.

[0042] According to at least one embodiment, between two, in particular between each two electronic circuits and / or in the region of the electronic circuits, an insulating trench extends from the upper side of the semiconductor substrate into the semiconductor substrate. The insulating trench extends into the semiconductor substrate, for example, by at least 3 μm or at least 4 μm or at least 5 μm. Alternatively or additionally, the depth of the insulating trench is a maximum of 10 μm or a maximum of 9 μm or a maximum of 8 μm. The width of the insulating trench is, for example, between 1 μm and 3 μm, inclusive. Preferably, the insulating trench extends deeper into the semiconductor substrate than the electronic functional region of the electronic circuit, in particular than the n-type and / or p-type doped region of the semiconductor substrate. Such an insulating trench is also referred to as a deep trench isolation.

[0043] In the region of the electronic circuit, for example between two adjacent transistors of the electronic circuit, the insulation trench can also be formed to be not too deep. Such so-called shallow trench isolations have, for example, a depth of at most 3 μm or at most 2 μm.

[0044] The insulation trench can extend laterally completely around the electronic circuit and define the lateral extent of the electronic circuit.

[0045] According to at least one embodiment, the insulating trench is filled with an electrically insulating material, such as silicon oxide. For example, the electrically insulating material of the wiring layer fills the insulating trench.

[0046] According to at least one embodiment, in step E), the semiconductor substrate is thinned until the insulation trenches, in particular the electrically insulating material of the insulation trenches, are exposed. The exposed insulation trenches can then be used as orientation points for adjusting the separation trenches.

[0047] In addition to the function as an orientation point, the insulating trench can also provide electrical insulation between electronic components within an electronic circuit. For example, the insulating trench is spaced at least 5 μm or at most 8 μm from the electronic component.

[0048] In order to make the electrically insulating material or the insulation trench visible within the insulation trench after thinning the semiconductor substrate, a further etchant can be used which has different etching rates for the electrically insulating material and the material of the semiconductor substrate.

[0049] According to at least one embodiment, in step F), a separation trench is formed through the exposed insulation trench. Advantageously, it is then not necessary to etch through the semiconductor material of the semiconductor substrate, but only through the electrically insulating material, such as silicon oxide.

[0050] According to at least one embodiment, two insulating trenches are formed between two electronic circuits, in particular between each two electronic circuits, which laterally delimit a separation region of the semiconductor substrate. In particular, the separation region is separated from the electronic circuits on both sides by the insulating trenches. For example, after thinning the semiconductor substrate, the separation region is electrically insulated from the remaining region of the semiconductor substrate by the insulating trenches.

[0051] According to at least one embodiment, in step F), a separation trench is formed through the separation region. The insulation trench can limit the separation trench to its width during its formation, since the material in the insulation trench is not or less eroded by the etchant used than the semiconductor material in the separation region, for example.

[0052] According to at least one embodiment, each electronic circuit has a first contact structure arranged above the upper side, which is used to electrically contact the circuit. "Above the upper side" means here that the contact structure is arranged outside the semiconductor substrate. The first contact structure is formed, for example, in a wiring layer of the electronic circuit. The first contact structure is preferably metallic. The first contact structure can be electrically insulated and spaced apart from the upper side of the semiconductor substrate by a layer composed of an electrically insulating material. The electrically insulating layer is especially formed of an oxide, preferably silicon oxide. The thickness of the electrically insulating layer is, for example, at most 1 μm.

[0053] According to at least one embodiment, the method comprises a step E1) following step E), in which a contact hole is introduced into the thinned semiconductor substrate so that the first contact structure is exposed. The contact hole is introduced, for example, from the side of the thinned semiconductor substrate facing away from the electronic circuit and completely penetrates the thinned semiconductor substrate. The introduction of the contact hole can be carried out, for example, via an etching process. For this purpose, for example, an etching mask produced via a photolithography process is used. The diameter of the contact hole is, for example, between 2 μm and 10 μm, inclusive.

[0054] After the contact hole is formed from the semiconductor substrate, the optional electrically insulating layer between the first contact structure and the top side can also be etched through. For this purpose, a further etchant can be used for etching through the semiconductor substrate.

[0055] According to at least one embodiment, the method comprises a step E2) following step E), in which an electrically conductive material, in particular a metal, is introduced into the contact hole. The electrically conductive material is preferably in direct electrical and mechanical contact with the first contact structure. The electronic circuit can then be electrically contacted via the electrically conductive material from the side of the thinned semiconductor substrate facing away from the electronic circuit.

[0056] Before the electrically insulating material is introduced, the inner wall of the contact hole can be passivated by means of a passivation layer. In the bottom region, the passivation layer is removed again, so that the first contact structure is exposed. Only then is the conductive material filled into the contact hole.

[0057] Preferably, steps E1) and E2) are performed before step F).

[0058] According to at least one embodiment, the semiconductor substrate comprises first contact regions in the region below the first contact structure, which are laterally surrounded by electrically insulating delimiting trenches. The contact regions have or consist of the semiconductor material of the semiconductor substrate. Each delimiting trench can completely surround the corresponding contact region laterally. Each delimiting trench can be formed in a connected manner. The delimiting trench is filled with an electrically insulating material, such as an oxide, in particular silicon oxide, for example. The delimiting trench extends from the upper side of the semiconductor substrate into the semiconductor substrate. The depth and width of the delimiting trench can be selected here as the depth and width of the insulating trench defined above. In particular, the delimiting trench is also a so-called deep trench insulation.

[0059] According to at least one embodiment, in step E), the semiconductor substrate is thinned until the delimiting trenches and the contact regions enclosed thereby are exposed. In a top view of the bottom side of the thinned semiconductor substrate facing away from the circuit, each contact region is then surrounded by a continuous track delimiting the trench. The contact regions observed in the top view of the bottom side have, for example, a diameter of a maximum of 50 μm or a maximum of 30 μm.

[0060] According to at least one embodiment, the method comprises a step E3) following step E), in which an electrically conductive material is applied to the thinned semiconductor substrate in the contact region. Thus, at the bottom side of the thinned semiconductor substrate facing away from the circuit, the contact region is electrically conductively connected to the electrically conductive material. At the top side, the contact region is electrically conductively connected to the first contact structure. Thus, the first contact structure can be contacted via the bottom side of the thinned semiconductor substrate. The delimiting trench serves for electrical insulation between the contact region and the remaining semiconductor material of the semiconductor substrate.

[0061] In order to increase the electrical conductivity of the contact region from the bottom to the top of the thinned semiconductor substrate, a metallic via can be or has been introduced in the contact region, which via is made of tungsten or aluminum, for example. The metallic via through the thinned semiconductor substrate is then completely surrounded laterally by the delimiting trench. The diameter of such a metallic via is, for example, between 1 μm and 10 μm inclusive. The metallic via can be produced, for example, by a CVD method.

[0062] Preferably, step E3) is performed before step F).

[0063] According to at least one embodiment, the method comprises a step E4) following step E), in which an optoelectronic component is applied to the bottom side of the thinned semiconductor substrate facing away from the circuit. In this case, the optoelectronic component is electrically conductively connected to the electronic circuit via an electrically conductive material. The optoelectronic component can be, for example, an LED chip or a laser diode chip. The lateral extension of the component is, for example, between 10 μm and 80 μm, inclusive. Step E4) is preferably performed before step F).

[0064] According to at least one embodiment, after step A) and before step B), the semiconductor substrate with the electronic circuit is first applied to the auxiliary carrier. After application, the electronic circuit is preferably arranged between the auxiliary carrier and the semiconductor substrate. Then step E) is performed. After step E), steps B), C), D), F) and G) are then performed, in particular in this order. The sacrificial layer and the adhesive layer are preferably applied to the side of the thinned semiconductor substrate facing away from the auxiliary carrier.

[0065] According to at least one embodiment, the auxiliary carrier is removed again after step D) and preferably after step F).

[0066] According to at least one embodiment, each electronic circuit comprises a region of a semiconductor substrate or a thinned semiconductor substrate and an electronic component formed by means of the region of the semiconductor substrate. In particular, each electronic circuit comprises at least one, preferably a plurality of such electronic components.

[0067] According to at least one embodiment, each electronic circuit comprises a wiring layer on the semiconductor substrate. The wiring layer is used to contact the electronic components. The wiring layer comprises, for example, a plurality of printed conductors, which are embedded in an electrically insulating material.

[0068] According to at least one embodiment, each electronic circuit comprises a second contact structure on the side of the wiring layer facing away from the semiconductor substrate. The electronic circuit can be electrically contacted via the second contact structure. The second contact structure comprises or consists of Al, for example.

[0069] According to at least one embodiment, the wiring layers of the electronic circuit are connected in step A) and form connected wiring layers.

[0070] In accordance with at least one embodiment, the interconnecting wiring layer is embodied metallically in the region of the separating trenches to be formed.

[0071] According to at least one embodiment, in step F), the separating trenches are formed through the interconnected wiring layers.

[0072] According to at least one embodiment, a dielectric layer is introduced between the sacrificial layer and the bonding layer after step C). The dielectric layer is preferably single-connected. The dielectric layer comprises, for example, Al2O3 or SiO2 or SiN x or consist of one of these materials.

[0073] According to at least one embodiment, the dielectric layer partially fills the hole and separates the holding element from the semiconductor substrate. When the electronic circuit is peeled off from the holding element, the boundary surface between the dielectric layer and the holding element is preferably torn off afterwards. This is more protective of the electronic circuit.

[0074] Preferably, a second dielectric layer, in particular a single-continuous layer, is formed between the sacrificial layer and the semiconductor substrate. In the region of the hole, the dielectric layer can then directly adjoin the second dielectric layer. The second dielectric layer preferably comprises a different material than the dielectric layer.

[0075] According to at least one embodiment, the method comprises a step H), which preferably follows step G) and in which the electronic circuit is detached from the carrier, so that individual semiconductor chips independent of one another are produced. Each semiconductor chip comprises an electronic circuit, preferably exactly one electronic circuit.

[0076] Furthermore, a semiconductor chip is provided. The method described here is particularly suitable for producing such a semiconductor chip. That is to say, all features disclosed in conjunction with the semiconductor chip are also disclosed for the method and vice versa.

[0077] In accordance with at least one embodiment, the semiconductor chip includes a semiconductor substrate with an integrated electronic circuit on a top side of the semiconductor substrate.

[0078] According to at least one embodiment, an electronic circuit includes a wiring layer on an upper side of a semiconductor substrate.

[0079] According to at least one embodiment, the electronic circuit has a first contact structure in a wiring layer.

[0080] According to at least one embodiment, the first contact structure is electrically conductively connected to a contact region of the semiconductor substrate. Preferably, the contact region comprises or consists of a semiconductor material of the semiconductor substrate.

[0081] In accordance with at least one embodiment, the contact region extends completely from the top side of the semiconductor substrate through the semiconductor substrate to a bottom side opposite the top side.

[0082] In accordance with at least one embodiment, the contact region is electrically conductively connected to an electrically conductive material, preferably a metallic material, on the underside.

[0083] According to at least one embodiment, the contact region is laterally completely surrounded by an electrically insulating delimiting trench, which extends from the upper side to the lower side of the semiconductor substrate. The delimiting trench is filled, for example, with an electrically insulating material such as an oxide, in particular silicon oxide. The delimiting trench can be formed by a deep trench insulation.

[0084] According to at least one embodiment, the semiconductor chip comprises an optoelectronic component on the underside of the semiconductor substrate. The optoelectronic component is electrically conductively connected to the electronic circuit via the conductive material and the contact region. Along the main extension plane of the semiconductor substrate, the electronic component overlaps the electronic circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0085] Below, the method for producing a plurality of semiconductor chips described here and the semiconductor chip described here are explained in detail based on exemplary embodiments with reference to the drawings. The same reference numerals here describe the same elements in the individual drawings. However, the relationships that are true to scale are not shown here, but rather individual elements may be shown exaggeratedly for a better understanding.

[0086] The accompanying drawings show:

[0087] Figures 1A to 1G The different positions in a first embodiment of the method are shown;

[0088] Figures 2A to 2C shows different positions in a second embodiment of the method;

[0089] Figures 3A to 3E shows different positions in a third embodiment of the method;

[0090] Figures 4A to 4E shows different positions in a fourth embodiment of the method;

[0091] Figure 5A and5B A perspective view showing one embodiment of a semiconductor chip;

[0092] Figures 6A to 6G shows different positions in a fifth embodiment of the method;

[0093] Figure 7 The positions in a sixth exemplary embodiment of the method are shown. DETAILED DESCRIPTION

[0094] exist Figure 1A 1 shows a first position in a first exemplary embodiment of the method. A semiconductor substrate 1 having an upper side 10 is provided. A plurality of integrated electronic circuits 2 arranged laterally side by side are formed at or on the upper side 10. The electronic circuits 2 are partially integrated into the semiconductor substrate 1. In particular, the electronic circuits 2 include electronic components 201, such as transistors and / or diodes, which are partially formed by n-doped and / or p-doped regions below the upper side 10 of the semiconductor substrate 1. The semiconductor substrate 1 is, for example, a silicon substrate.

[0095] Each electronic circuit 2 further comprises a wiring layer 202 on the upper side 10 of the semiconductor substrate 1. The wiring layers 202 of different electronic circuits 2 are first formed in a connected manner. Each wiring layer 202 comprises an electrically insulating material 204, for example silicon oxide, in which a plurality of printed conductors 205 are embedded. On the side facing away from the semiconductor substrate 1, each electronic circuit 2 comprises a second contact structure 203. The electronic circuit 2 can be contacted from the outside via the second contact structure. In the region between two electronic circuits 2, the wiring layers 202 are connected to each other via the electrically insulating material 204.

[0096] exist Figure 1B 3 shows a second position in the method, in which a sacrificial layer 3, for example composed of silicon, is applied to the side of the electronic circuit 2 facing away from the semiconductor substrate 1. The sacrificial layer 3 is penetrated by a plurality of holes 30. In this case, at least one such hole 30 is provided in the sacrificial layer 3 in the region of each electronic circuit 2.

[0097] exist Figure 1C 3 shows a third step of the method. An adhesive layer 4, which is composed of BCB, is applied to the side of the sacrificial layer 3 facing away from the semiconductor substrate 1. The adhesive layer 4 fills the hole 30 in the sacrificial layer 3, thereby producing a retaining element 40 composed of the material of the adhesive layer 4 in the hole 30. The semiconductor substrate 1 with the electronic circuit 2 is glued to the carrier 5 by means of the adhesive layer 4. The carrier 5 is composed of glass, for example.

[0098] In the method Figure 1DIn the fourth position shown in FIG. 1 , the semiconductor substrate 1 is thinned. For this purpose, the semiconductor substrate 1 is ground off or polished or etched, for example, from the side facing away from the carrier 5 . For example, the semiconductor substrate 1 is thinned to a target thickness of between 5 μm and 20 μm, inclusive. Figure 1D In the embodiment, the carrier 5 is a component for stabilizing the electronic circuit 2 .

[0099] exist Figure 1E 5. The fifth position of the method is shown in FIG. A photoresist layer 7 is applied on the side of the electronic circuit 2 facing away from the carrier 5. The photoresist layer 7 is structured to have grooves 70. The grooves 70 are formed in the region between the electronic circuits 2. In addition, separation grooves 6 are respectively formed between the electronic circuits 2. In order to separate the semiconductor substrate 1, an anisotropic, dry chemical and fluorine-based etching process is used, for example, by using the structured photoresist layer 7 as an etching mask. In order to penetrate the material of the connection wiring layer 202 by means of the separation grooves 6, different etchants are used, for example.

[0100] exist Figure 1E It can be seen in FIG. 2 that the separating trenches 6 extend as far as the sacrificial layer 3 , so that the sacrificial layer 3 is exposed in the region of the separating trenches 6 .

[0101] exist Figure 1F , a sixth position of the method is shown in which the sacrificial layer 3 is removed in the region below the electronic circuit 2. Furthermore, a retaining element 40 remains, via which the electronic circuit 2 is fixed to the carrier 5. The contact surface between the electronic circuit 2 and the retaining element 40 arranged thereunder is, for example, a maximum of 10% of the entire surface of the electronic circuit 2 facing the carrier 5. The electronic circuit 2 is fixed to the carrier 5 weakly but stably by the retaining element 40.

[0102] For example, an anisotropic etching process is used again to remove the sacrificial layer 3. The etchant used for this purpose can reach the sacrificial layer 3 via the separation trenches 6. The etchant removes at least 99% of the sacrificial layer 3 in the area below the electronic circuit 2.

[0103] exist Figure 1G , the seventh step of the method is shown in FIG. The electronic circuit 2 is peeled off from the carrier 5. In addition, individual semiconductor chips 100 remain. The semiconductor chips each include a section of a thinned semiconductor substrate 1 and an electronic circuit 2 integrated therein. The electronic circuit 2 each includes a wiring layer 202 and a plurality of electronic components 201. The side of the thinned semiconductor substrate 1 facing away from the wiring layer 202 forms the bottom side 17 of the semiconductor chip 100.

[0104] exist Figure 2A The first position of the second embodiment of the method is shown in Figure 1A, a semiconductor substrate 1 is shown with a plurality of electronic circuits 2 formed on a top side 10. From the top side 10, an insulation trench 11 extends into the semiconductor substrate 1. The insulation trench 11 is filled with an electrically insulating material, in particular an electrically insulating material 204 of a wiring layer 202.

[0105] On the one hand, the insulating trench 11 is formed in the region between two transistors 201 of the electronic circuit 2 and electrically insulates the transistors 201 from each other. On the other hand, the insulating trench 11 is formed in the region between each two electronic circuits 2. In the present case, two insulating trenches 11 spaced apart from each other are formed between the two electronic circuits 2. A separation region 16 made of the material of the semiconductor substrate 1 is provided between the two insulating trenches 11.

[0106] The insulation trench 11 has, for example, a depth of between 5 μm and 8 μm, inclusive, a width of between 2 μm and 3 μm, inclusive, and a distance from the nearest transistor 201 or the nearest electronic circuit 2 of between 5 μm and 8 μm, inclusive.

[0107] In the method Figure 2B In the second position shown in FIG, the semiconductor substrate 1 together with the electronic circuit 2 is again applied to the carrier 5. A sacrificial layer 3 and an adhesive layer 4 are formed between the carrier 5 and the semiconductor substrate 1. In addition, the semiconductor substrate 1 is thinned again. In this case, the semiconductor substrate 1 is thinned until the insulation trench 11 is exposed and the electrically insulating material in the insulation trench 11 becomes visible at the bottom 17 of the semiconductor substrate 1 facing away from the carrier 5. Optionally, a decorative etching process can also be applied, which has a different etching rate for the electrically insulating material in the region of the insulation trench 11 than for the semiconductor material of the semiconductor substrate 1. As a result, a visible height difference between the insulation trench 11 and the semiconductor substrate 1 can be generated at the bottom 17.

[0108] exist Figure 2C The third step of the method is shown in . The photoresist layer 7 structured by means of trenches 70 is used as an etching mask in order to form separation trenches 6 between electronic circuits 2 . The exposed insulation trenches 11 can be used as orientation points for positioning the trenches 70 .

[0109] In the present case, the separation trenches 6 are formed through the insulation trenches 11. This avoids the semiconductor material of the thinned semiconductor substrate 1 being etched through and the risk of damaging the semiconductor substrate 1. Alternatively, however, it is also possible to form the separation trenches 6 between the insulation trenches 11 and through the separation region 16. In order to form the separation trenches 6, only the semiconductor material of the semiconductor substrate 1 is etched. The insulation trenches 11 are lateral passivations to protect the electronic circuit 2 from the etching agent.

[0110] exist Figure 3A1 shows a first position of a third exemplary embodiment of the method. A semiconductor substrate 1 having an electronic circuit 2 formed at an upper side 10 is provided. The electronic circuit 2 comprises a first contact structure 200 in the region above the upper side 10, that is to say within the wiring layer 202. The first contact structure is electrically insulated from the semiconductor substrate 1, for example, by an insulating layer, such as a field oxide layer.

[0111] exist Figure 3B 2 shows a second stage of the method, in which the semiconductor substrate 1 is mounted on a carrier 5, and a sacrificial layer 3 and an adhesive layer 4 are formed between the carrier 5 and the semiconductor substrate 1. The semiconductor substrate 1 is thinned to a target thickness.

[0112] exist Figure 3C A third step of the method is shown in . A contact hole 12 is introduced into the thinned semiconductor substrate 1 . The contact hole 12 is located in this case, in particular in the region of the semiconductor substrate 1 , above the first contact structure 200 . The first contact structure 200 is exposed in the contact hole 12 .

[0113] exist Figure 3D 1 shows a fourth step of the method. An electrically conductive material 13 in the form of a metal layer is introduced into the contact hole 12. The electrically conductive material 13 is in direct contact with the first contact structure 200. Furthermore, the electrically conductive material 13 extends from the first contact structure 200 to the underside 17 of the thinned semiconductor substrate 1 opposite the upper side 10. The electronic circuit 2 can be electrically contacted via the underside 17. A passivation layer 130 is formed between the electrically conductive material 13 and the semiconductor material of the semiconductor substrate 1.

[0114] exist Figure 3E The fifth step of the method is shown in . Separating trenches 6 between the electronic circuits 2 are again formed by means of the photoresist layer 7 and the trenches 70 in the photoresist layer 7. The sacrificial layer 3 is removed below the electronic circuits 2, so that the electronic circuits 2 are held on the carrier 5 only via the holding elements 40.

[0115] exist Figure 4A 1 shows a first position of a fourth exemplary embodiment of the method. The electronic circuit 2 again comprises a first contact structure 200 on the upper side 10 of the semiconductor substrate 1. A contact region 14 of the semiconductor substrate 1 is formed below the first contact structure 200. That is, the contact region 14 consists of the semiconductor material of the semiconductor substrate 1. The contact region 14 is laterally completely surrounded by a delimiting trench 15. The delimiting trench 15 extends from the upper side 10 into the semiconductor substrate 1 and is filled with an electrically insulating material, such as silicon oxide.

[0116] exist Figure 4B 4 shows a second step of the method, in which the semiconductor substrate 1 is again mounted on the carrier 5 by means of the adhesive layer 4. A sacrificial layer 3 is formed between the adhesive layer 4 and the electronic circuit 2.

[0117] exist Figure 4C , a third position of the method is shown, in which the semiconductor substrate 1 is thinned to such an extent that the delimiting trench 15 and the contact region 14 surrounded by it are exposed. On the underside 17 of the thinned semiconductor substrate 1, an electrically conductive material 13 in the form of a metal layer is applied. The metal layer is in electrically conductive contact with the contact region 14. The contact region 14 thus forms a via through the semiconductor substrate 1, which is insulated from the remaining semiconductor material of the semiconductor substrate 1 by the insulating delimiting trench 5. Via the electrically conductive material 13 and the contact region 14, the electronic circuit 2 can be contacted from the underside 17. Except in the region of the contact region 14, the electrically conductive material 13 is electrically insulated from the semiconductor material of the semiconductor substrate 1 by the passivation layer 130.

[0118] exist Figure 4D 1 shows a fourth step of the method. An optoelectronic component 8, for example an LED chip 8, is applied to the bottom 17. The optoelectronic component 8 is connected to the electronic circuit 2 via an electrically conductive material 13 and a contact region 14. The electronic component 8 comprises a semiconductor layer sequence 80 which emits radiation during operation.

[0119] exist Figure 4E The fifth step of the method is shown in . Separating trenches 6 are again formed in the region between the electronic circuits 2 . The sacrificial layer 3 below the electronic circuits 2 can then be removed again with the aid of the separating trenches 6 .

[0120] exist Figure 5A and 5B FIG. 1 is a perspective view of an embodiment of a semiconductor chip 100. The semiconductor chip 100 may be formed by combining Figures 4A to 4E The method described is used for manufacturing. For this purpose, in particular, the electronic circuit 2 together with the optoelectronic components 8 applied thereon are removed from the carrier 5. The semiconductor chip 100 comprises a plurality of optoelectronic components 8, which are arranged on the electronic circuit 2 and are electrically conductively connected to the electronic circuit 2. By peeling the electronic circuit 2 off the carrier 5, the second contact structure 203 of the electronic circuit 2 is exposed and can be used for electrical contacting of the semiconductor chip 100.

[0121] exist Fig. 6A The first position of the fifth exemplary embodiment of the method is shown in FIG. The semiconductor substrate 1 together with the electronic circuit 2 applied thereon corresponds to Figure 1A The semiconductor substrate in together with the electronic circuit applied thereon.

[0122] In the method Figure 6B In the second position shown in FIG. 1 , the semiconductor substrate 1 together with the electronic circuit 2 is previously applied to an auxiliary carrier 9. The auxiliary carrier 9 consists, for example, of silicon. On the auxiliary carrier 9, the semiconductor substrate 1 is bonded by means of a further adhesive layer 90, for example a thermal release layer or a UV release layer or a BCB layer with a laser release sacrificial layer, such as SiN xTemporarily fixed.

[0123] exist Figure 6C 3. The third stage of the method is shown in FIG. The semiconductor substrate 1 is thinned to a target thickness. An oxide layer 31 is applied to the side of the thinned semiconductor substrate 1 facing away from the auxiliary carrier 9. A sacrificial layer 3 is again formed on the oxide layer 31, which has holes 30 introduced therein.

[0124] exist Fig.6D The fourth step of the method is shown in . The auxiliary carrier 9 with the electronic circuit 2 located thereon and the thinned semiconductor substrate 1 is applied to the carrier 5. Between the electronic circuit 2 and the carrier 5, a sacrificial layer 3 and an adhesive layer 4 with a retaining element 40 are again formed.

[0125] exist Fig. 6E A fifth stage of the method is shown in FIG. 9 . The auxiliary carrier 9 is peeled off. The electronic circuit 6 is held by the carrier 5 .

[0126] In the method Fig. 6F In the sixth position shown in FIG. 8 , separation trenches 6 are again introduced between the electronic circuits 2 by means of a structured photoresist layer 7 .

[0127] In the method Figure 6G In the seventh position shown in FIG. 1 , the sacrificial layer 3 beneath the electronic circuit 2 is removed.

[0128] 1 to 4, the thinned semiconductor substrate 1 always faces away from the carrier 5. With the method of FIG6, the thinned semiconductor substrate 1 faces the carrier 5. Depending on the method used, the electronic circuit 2 can be printed or mounted beforehand together with the thinned semiconductor substrate 1 or together with the wiring layer 202.

[0129] exist Figure 7 The position of the seventh embodiment is shown in FIG. The position corresponds to Fig.6D Here, a dielectric layer 32 is introduced between the sacrificial layer 3 and the adhesive layer 4. The dielectric layer 32 is currently single-connected and comprises, for example, Al2O3 or SiO2 or SiN x Or made of one of these materials. The dielectric layer 32 partially fills the hole 30 and separates the holding element 40 from the semiconductor substrate 1. When the electronic circuit 2 and the holding element 40 are peeled off, the boundary surface between the dielectric layer 32 and the holding element 40 is preferably torn off. This is to further protect the electronic circuit 2.

[0130] Such a dielectric layer 32 can be used in each of the described embodiments.

[0131] This application claims the priority of German patent application 10 2017 125 276.2, the disclosure content of which is incorporated herein by reference.

[0132] The present invention is not limited to this by the description based on the exemplary embodiments. Rather, the present invention includes any new features and any combination of features, which in particular includes any combination of features in the exemplary embodiments, even if these features or these combinations themselves are not exhaustively presented in the exemplary embodiments.

[0133] Reference numerals list

[0134] 1 Semiconductor substrate

[0135] 2 Electronic Circuits

[0136] 3 Sacrificial layer

[0137] 4 Adhesive layer

[0138] 5 Carrier

[0139] 6 Separation groove

[0140] 7 Photoresist layer

[0141] 8 Optoelectronic components

[0142] 9 Auxiliary carrier

[0143] 10 upper side

[0144] 11Insulation groove

[0145] 12 contact holes

[0146] 13. Conductive Materials

[0147] 14Contact Area

[0148] 15 Limiting groove

[0149] 16 Separation Area

[0150] 17 Lower side

[0151] 30 Hole in sacrificial layer 3

[0152] 31 Oxide layer

[0153] 32 Dielectric layer

[0154] 40 holding element

[0155] 70 Additional adhesive layer

[0156] 80 Semiconductor layer sequence

[0157] 100 Semiconductor Chip

[0158] 130 Passivation layer

[0159] 200 First contact structure

[0160] 201 Transistor

[0161] 202 Wiring Layer

[0162] 203 Second contact structure

[0163] 204 Electrical insulating materials

[0164] 205 Printed conductor

Claims

1. A method for manufacturing a plurality of semiconductor chips (100), the method comprising the following steps: A) providing a semiconductor substrate (1) having a plurality of integrated electronic circuits (2) on an upper side (10) of the semiconductor substrate (1); B) applying a sacrificial layer (3) to one side of the semiconductor substrate (1); C) introducing holes (30) into the sacrificial layer (3) such that at least one hole (30) is produced above each electronic circuit (2); D) bonding the semiconductor substrate (1) with the sacrificial layer (3) to a carrier (5) beforehand, wherein an adhesive layer (4) is used between the sacrificial layer (3) and the carrier (5), and wherein the adhesive layer (4) fills the hole (30), so that a retaining element (40) formed by the adhesive layer (4) is produced in the hole (30); E) thinning the semiconductor substrate (1); F) introducing a separation trench (6) between the electronic circuits (2), the separation trench extending from the side of the electronic circuit (2) facing away from the carrier (5) to the sacrificial layer (3) and penetrating the thinned semiconductor substrate (1); G) Removing the sacrificial layer (3) in the region between the electronic circuit (2) and the carrier (5), so that the electronic circuit (2) is held on the carrier (5) via the holding element (40).

2. The method according to claim 1, Therein, after step G), the contact area between the holding element (40) and the electronic circuit (2) is at least 0.1% and at most 10% of the entire area of ​​the electronic circuit (2) facing the carrier (5).

3. The method according to claim 1 or 2, In order to implement the step F), the following intermediate steps are performed: F1) applying a photoresist layer (7) to the side of the electronic circuit (2) facing away from the carrier (5); F2) structuring the photoresist layer (7) to have trenches (70), wherein the trenches (70) are formed where the separation trenches (6) are to be produced later; F3) Producing the separation trench (6) in the region of the trench (70) by etching.

4. The method according to claim 1 or 2, The carrier (5) is a transparent carrier.

5. The method according to claim 1 or 2, In order to produce the separation trenches ( 6 ), an anisotropic fluorine-based etching process is carried out in step F).

6. The method according to claim 1 or 2, wherein - using a dry chemical etching method in step G) for removing the sacrificial layer (3), The etchant used for this purpose reaches the sacrificial layer (3) via the separating trenches (6).

7. The method according to claim 1 or 2, wherein - between two electronic circuits (2) and / or in the region of the electronic circuits (2), an insulation trench (11) extends from the upper side (10) into the semiconductor substrate (1), - filling the insulating trench (11) with an electrically insulating material, - In step E), the semiconductor substrate (1) is thinned until the insulating trench (11) is exposed.

8. The method according to claim 7, wherein - forming an insulating trench (11) between two electronic circuits (2), In step F), the separation trench (6) is formed through the exposed insulation trench (11).

9. The method according to claim 7, wherein - forming two insulation trenches (11) between the two electronic circuits (2), said insulation trenches laterally delimiting the separation region (16) of the semiconductor substrate (1), In step G), the separating trench ( 6 ) is formed through the separating region ( 16 ).

10. The method according to claim 1 or 2, wherein - each electronic circuit (2) has a first contact structure (200) arranged on the upper side (10) for electrical contacting of the circuit (2), - the method further comprises the step following step (E): E1) introducing a contact hole (12) into the thinned semiconductor substrate (1) so that the first contact structure (200) is exposed, E2) introducing a conductive material (13) into the contact hole (12).

11. The method according to claim 1 or 2, wherein - each electronic circuit (2) has a first contact structure (200) arranged on the upper side (10) for electrical contacting of the circuit (2), - in the region below the first contact structure (200), the semiconductor substrate (1) comprises in each case a contact region (14) which is laterally surrounded by an electrically insulating delimiting trench (15), - in step E), the semiconductor substrate (1) is thinned until the delimiting trench (15) and the contact region (14) are exposed, - the method further comprises the step following step E): E3) Applying an electrically conductive material (13) in the contact region (14) onto the thinned semiconductor substrate (1).

12. The method according to claim 10, The method further comprises the step following step E): E4) Applying an optoelectronic component (8) to the thinned underside (17) of the semiconductor substrate (1) facing away from the electronic circuit (2), wherein the optoelectronic component (8) is electrically conductively connected to the electronic circuit (2) via the electrically conductive material (13).

13. The method according to claim 1 or 2, wherein - after step A) and before step B), the semiconductor substrate (1) with the electronic circuit (2) is first applied to an auxiliary carrier (9), and then step E) is carried out, After step D), the auxiliary carrier (9) is removed again.

14. The method according to claim 1 or 2, Each electronic circuit (2) comprises: - a region of the semiconductor substrate (1) and an electronic device (201) formed by means of the region of the semiconductor substrate (1), - a wiring layer (202) on the semiconductor substrate (1) for contacting the device (201), A second contact structure (203) on the side of the wiring layer facing away from the semiconductor substrate (1), wherein the electronic circuit (2) can be electrically contacted via the second contact structure (203).

15. The method according to claim 14, wherein - the wiring layers (202) of the electronic circuit (2) are connected in step A) and form connected wiring layers, - the interconnecting wiring layer is formed metallically in the region of the separating trenches (6) to be formed, In step F), the separation trench (6) is formed through the interconnected wiring layers.

16. The method according to claim 1 or 2, wherein - after step C), introducing a dielectric layer between the sacrificial layer (3) and the adhesive layer (4), The dielectric layer partially fills the hole (30) and separates the holding element (40) from the semiconductor substrate (1).

17. The method according to claim 1 or 2, The method further comprises the steps of: H) separating the electronic circuit (2) from the carrier (5), so that individual semiconductor chips (100) separated from one another are produced.

18. A semiconductor chip (100), comprising: - a semiconductor substrate (1) having an integrated electronic circuit (2) on the upper side (10) of the semiconductor substrate (1), wherein the electronic circuit (2) comprises a wiring layer (202) on the upper side (10) of the semiconductor substrate (1) and a first contact structure (200) in the wiring layer (202), - the first contact structure (200) is electrically conductively connected to a contact region (14) of the semiconductor substrate (1), the contact region (14) extends completely from the upper side (10) of the semiconductor substrate (1) through the semiconductor substrate (1) to a lower side (17) opposite the upper side (10), the contact region (14) is electrically conductively connected to the electrically conductive material (13) on the bottom side (17), the contact region (14) is laterally completely surrounded by an electrically insulating delimiting trench (15), the contact region extending from the upper side (10) to the lower side (17) of the semiconductor substrate (1), An optoelectronic component (8) on the underside (17) of the semiconductor substrate (1), wherein the optoelectronic component (8) is electrically conductively connected to the electronic circuit (2) via the electrically conductive material (13) and the contact region (14).

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