Semiconductor memory device

Abstract

A semiconductor memory device is provided. The semiconductor memory device includes a common source line, a substrate on the common source line, a plurality of gate electrodes arranged on the substrate and spaced apart from each other in a first direction perpendicular to a top surface of the common source line, a plurality of insulating films arranged between the plurality of gate electrodes, a plurality of channel structures penetrating through the plurality of gate electrodes and the plurality of insulating films in the first direction, and a plurality of remaining sacrificial films arranged on the substrate and spaced apart from each other in the first direction, wherein the plurality of gate electrodes are disposed on opposite sides of the plurality of remaining sacrificial films.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2018-0162155, filed on December 14, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] The inventive concept relates to a semiconductor memory device and a manufacturing method thereof, and more particularly, to a semiconductor memory device having a three-dimensional structure and a method of manufacturing the same. BACKGROUND

[0003] Information and communication devices having multi-functional characteristics employ memory devices having high capacity and high integration density. As memory cell size decreases, operating circuitry and / or wiring structures included in the memory device become more complex. Accordingly, a memory device having increased integration density can foresee a decrease in its electrical characteristics. SUMMARY

[0004] According to one exemplary embodiment of the inventive concept, a semiconductor memory device is provided, the semiconductor memory device including a common source line, a base on the common source line, a plurality of gate electrodes arranged on the base and spaced apart from each other in a first direction perpendicular to a top surface of the common source line, a plurality of insulating films arranged between the plurality of gate electrodes, a plurality of channel structures penetrating through the plurality of gate electrodes and the plurality of insulating films in the first direction, and a plurality of remaining sacrificial films arranged on the base and spaced apart from each other in the first direction, wherein the plurality of gate electrodes are disposed on opposite sides of the plurality of remaining sacrificial films.

[0005] According to another exemplary embodiment of the inventive concept, a semiconductor memory device is provided, the semiconductor memory device including a base, a box structure on the base, and a plurality of vias penetrating through the box structure, wherein the box structure includes a plurality of remaining sacrificial films spaced apart from each other in a first direction perpendicular to a top surface of the base and a plurality of insulating films arranged between the plurality of remaining sacrificial films.

[0006] According to still another exemplary embodiment of the inventive concept, there is provided a semiconductor memory device including: a substrate; first and second gate stack structures extending in a horizontal direction on the substrate and including a plurality of gate electrode layers stacked in a vertical direction, the plurality of gate electrode layers having an electrically conductive property; a plurality of channel structures penetrating through one of the first and second gate stack structures in the vertical direction; a remaining sacrificial film stack structure disposed between the first and second gate stack structures and including a plurality of sacrificial films stacked in the vertical direction, the plurality of sacrificial films having an insulating property; and a common source line tap wiring provided on the remaining sacrificial film stack structure.

[0007] According to still another exemplary embodiment of the inventive concept, there is provided a method of manufacturing a semiconductor memory device. The method includes forming a common source line and a substrate on a peripheral circuit including a peripheral transistor; forming an initial stack structure including sacrificial films and insulating films alternately stacked on the substrate; forming channel structures penetrating through the initial stack structure; and forming first and second word line cuts penetrating through the initial stack structure and extending in a first direction on the substrate, the first word line cut having a different length from the second word line cut in the first direction.

[0008] According to one exemplary embodiment of the inventive concept, there is provided a semiconductor memory device including: a common source line provided on an insulating layer; a substrate stacked with the common source line; a gate stack provided on the substrate; a sacrificial film structure provided on the substrate, wherein the gate stack is provided on opposite sides of the sacrificial film structure; a first via penetrating the sacrificial film structure and electrically connected to a transistor; and a second via penetrating the sacrificial film structure and contacting the common source line. BRIEF DESCRIPTION OF DRAWINGS

[0009] The above and other features of the inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

[0010] FIG. 1 is a block diagram of a semiconductor memory device according to an exemplary embodiment of the inventive concept;

[0011] FIG. 2 is a schematic perspective view of a semiconductor memory device according to an exemplary embodiment of the inventive concept;

[0012] FIG. 3 is a circuit diagram for explaining an operation of a semiconductor memory device according to an exemplary embodiment of the inventive concept;

[0013] FIG. 4is a plan view of a semiconductor memory device according to exemplary embodiments of the inventive concept;

[0014] FIG. 5A and FIG. 5B is FIG. 4 is an enlarged plan view of a respective portion of the semiconductor memory device of

[0015] FIG. 6A , FIG. 6B , FIG. 6C and FIG. 6D is a sectional view taken along line I-I' and line II-II' in FIG. 4

[0016] FIG. 7A , FIG. 7B , FIG. 7C and FIG. 7D is a plan view of a semiconductor memory device according to exemplary embodiments of the inventive concept;

[0017] FIG. 8 is a flowchart of a method of manufacturing a semiconductor memory device according to exemplary embodiments of the inventive concept; and

[0018] FIG. 9A , FIG. 9B , FIG. 9C , FIG. 9D , FIG. 9E , FIG. 9F , FIG. 9G , FIG. 9H , FIG. 9I , FIG. 9J and FIG. 9K are sectional views of stages in a method of manufacturing a semiconductor memory device according to exemplary embodiments of the inventive concept. DETAILED DESCRIPTION

[0019] FIG. 1 is a block diagram of a semiconductor memory device 10 according to exemplary embodiments of the inventive concept. The semiconductor memory device 10 can include a memory cell array 50 and a peripheral circuit 60. According to exemplary embodiments of the inventive concept, the semiconductor memory device 10 can further include a data input / output circuit or an input / output interface.

[0020] ​The memory cell array 50 can be connected to string selection lines SSL, word lines WL, ground selection lines GSL, and bit lines BL. The peripheral circuit 60 can include control logic 61, a row decoder 62, and a page buffer 63. According to an exemplary embodiment of the inventive concept, the memory cell array 50 can be connected to the row decoder 62 through the string selection lines SSL, the word lines WL, and the ground selection lines GSL. The memory cell array 50 can be connected to the page buffer 63 through the bit lines BL and to a common source line (CSL) driver 64 through the common source lines CSL.

[0021] The memory cell array 50 can include a plurality of memory cells. According to an exemplary embodiment of the inventive concept, the memory cells of the memory cell array 50 can include flash memory cells. Hereinafter, it is assumed in the description of the following embodiments that the memory cells are NAND flash memory cells, but the inventive concept is not limited thereto. For example, the memory cells can include resistive memory cells such as resistive random access memory (ReRAM) cells, phase change RAM (PRAM) cells, or magnetic RAM (MRAM) cells.

[0022] The memory cell array 50 can include a plurality of blocks, for example, a first block BLK1 to a z-th block BLKz. Each block can have a planar structure or a three-dimensional (3D) structure. According to an exemplary embodiment of the inventive concept, the memory cell array 50 can contain at least one of an SLC block including single-level cells (SLCs), an MLC block including multi-level cells (MLCs), a TLC block including triple-level cells (TLCs), and a QLC block including quad-level cells (QLCs). According to an exemplary embodiment of the inventive concept, some of the first block BLK1 to the z-th block BLKz can be SLC blocks, while other blocks can be MLC blocks, TLC blocks, or QLC blocks.

[0023] The peripheral circuit 60 can receive an address ADDR, a command CMD, and a control signal CTRL from outside the semiconductor memory device 10. According to an exemplary embodiment of the inventive concept, the peripheral circuit 60 can transmit or receive data DATA to or from an external device of the semiconductor memory device 10. According to an exemplary embodiment of the inventive concept, the peripheral circuit 60 can further include various sub-circuits such as a voltage generator circuit that generates various voltages for operations of the semiconductor memory device 10 and an error correction circuit that corrects errors in data read from the memory cell array 50.

[0024] Control logic 61 can control all operations of the semiconductor memory device 10. Control logic 61 can control the semiconductor memory device 10 to perform memory operations corresponding to commands CMD provided from the memory controller. Control logic 61 can generate various internal control signals used in the semiconductor memory device 10 in response to a control signal CTRL provided from the memory controller. According to an exemplary embodiment of the inventive concept, control logic 61 can control the voltage levels of the word line WL and bit line BL during memory operations (such as programming or erasing operations).

[0025] The row decoder 62 can select at least one of the first block BLK1 to the z-th block BLKz in response to the address ADDR provided from the memory controller. The row decoder 62 can select at least one word line of the memory block selected in response to the address ADDR.

[0026] The row decoder 62 can send voltages for memory operations to selected word lines of the selected memory block. For example, during a programming operation, the row decoder 62 can send programming and verification voltages to the selected word lines and pass voltages to the unselected word lines. Furthermore, the row decoder 62 can select some string select lines (SSL) in response to the address ADDR.

[0027] Page buffer 63 can be connected to memory cell array 50 via bit line BL. Page buffer 63 can operate as a write driver or a sense amplifier. For example, during a programming operation, page buffer 63 can operate as a write driver and apply a voltage to bit line BL to store data in memory cell array 50. During a read operation, page buffer 63 can operate as a sense amplifier and read data stored in memory cell array 50.

[0028] CSL driver 64 can be connected to memory cell array 50 via common-source line CSL. CSL driver 64 can apply common-source voltage to common-source line CSL under the control of control logic 61.

[0029] FIG. 2 This is an illustrative representation of an exemplary embodiment based on the inventive concept. FIG. 1 A view of the structure of a semiconductor memory device 10. The semiconductor memory device 10 may include a memory cell array 50 and peripheral circuitry 60. The components of the semiconductor memory device 10 may be formed using semiconductor manufacturing processes.

[0030] Reference FIG. 1 and FIG. 2, the semiconductor memory device 10 can include a first semiconductor device layer L1 and a second semiconductor device layer L2. According to an exemplary embodiment of the inventive concept, the second semiconductor device layer L2 can be arranged on the first semiconductor device layer L1 in a first direction (e.g., a Z direction). According to an exemplary embodiment of the inventive concept, FIG. 1 The memory cell array 50 in the second semiconductor device layer L2 can be formed in the second semiconductor device layer L2, FIG. 1 The peripheral circuit 60 in the second semiconductor device layer L2 can be formed in the first semiconductor device layer L1.

[0031] The first semiconductor device layer L1 can include a lower substrate. The first semiconductor device layer L1 can include patterns of semiconductor elements (e.g., transistors) and wirings for the semiconductor elements on the lower substrate. For example, the circuits described above with respect to the control logic 61, the row decoder 62, the page buffer 63, and the CSL driver 64 can be formed in the first semiconductor device layer L1. FIG. 1 The circuits described above with respect to the control logic 61, the row decoder 62, the page buffer 63, and the CSL driver 64 can be formed in the first semiconductor device layer L1.

[0032] The second semiconductor device layer L2 can include at least one conductive layer and an upper substrate on the conductive layer. According to an exemplary embodiment of the inventive concept, a top surface of each of the upper substrate and the lower substrate can be substantially perpendicular to the first direction, e.g., the Z direction, but the inventive concept is not limited thereto. According to an exemplary embodiment of the inventive concept, the upper substrate can include a plurality of layers. The second semiconductor device layer L2 can include the memory cell array 50 on the upper substrate. According to an exemplary embodiment of the inventive concept, the at least one conductive layer can operate as a common source for the memory cell array 50.

[0033] According to an exemplary embodiment of the inventive concept, a conductive pattern can be formed in the second semiconductor device layer L2 to connect the memory cell array 50 to the peripheral circuit 60 in the first semiconductor device layer L1. According to an exemplary embodiment of the inventive concept, the word line WL can extend in a second direction (e.g., an X direction) perpendicular to the first direction (e.g., the Z direction). According to an exemplary embodiment of the inventive concept, the bit line BL can extend in a third direction (e.g., a Y direction) perpendicular to the first direction (e.g., the Z direction). The first direction (e.g., the Z direction), the second direction (e.g., the X direction), and the third direction (e.g., the Y direction) can be substantially perpendicular to each other. The term "vertical direction" used hereinafter can refer to a direction substantially parallel to the first direction (e.g., the Z direction), and the term "vertical level" can refer to a height in the first direction (e.g., the Z direction). In addition, the term "horizontal direction" can refer to a direction perpendicular to the first direction (e.g., the Z direction) but inclined with respect to the second direction (e.g., the X direction) and the third direction (e.g., the Y direction).

[0034] The memory cells of the memory cell array 50 can be accessed via word lines WL and bit lines BL. The word lines WL and the bit lines BL can be electrically connected to the peripheral circuit 60 formed in the first semiconductor device layer L1.

[0035] Accordingly, the semiconductor memory device 10 can have a structure in which the memory cell array 50 and the peripheral circuit 60 are arranged in a first direction (e.g., the Z direction), for example, a peripheral-over-cell or a cell-over-peripheral (COP) structure. According to exemplary embodiments of the inventive concept, all circuits except the memory cell array 50 can be arranged below the memory cell array 50, and thus, the COP structure can effectively reduce a horizontal area. Accordingly, the number of memory cells integrated into the semiconductor memory device 10 can be increased.

[0036] According to exemplary embodiments of the inventive concept, the semiconductor memory device 10 can further include a plurality of pads (or "bonding pads") for electrical connection to external circuits. For example, the semiconductor memory device 10 can include a plurality of pads for inputting / outputting a command CMD, an address ADDR, and a control signal CTRL received from an external device or a plurality of pads for inputting / outputting data. The pads can be arranged adjacent to the peripheral circuit 60.

[0037] FIG. 3 is a circuit diagram illustrating an equivalent circuit of a first memory block BLK1 among first to z-th blocks BLK1 to BLKz in FIG. 1 according to exemplary embodiments of the inventive concept. Referring to FIG. 3 , the first memory block BLK1 can be implemented as a NAND flash memory having a vertical structure. Like the first memory block BLK1, each of second to z-th blocks BLK2 to BLKz (see FIG. 1 ) can be implemented as a NAND flash memory. The first memory block BLK1 can include a plurality of NAND strings NS11, NS12, NS13, NS21, NS22, and NS23, a plurality of ground select lines (e.g., a first ground select line GSL1 and a second ground select line GSL2), a plurality of string select lines (e.g., a first string select line SSL1 and a second string select line SSL2), a plurality of word lines (e.g., first to eighth word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7, and WL8), a plurality of bit lines (e.g., first to third bit lines BL1, BL2, and BL3, and a common source line CSL. The number of NAND strings, word lines, bit lines, ground select lines, and string select lines can vary in various ways according to exemplary embodiments of the inventive concept.

[0038] According to example embodiments of the inventive concepts, the NAND strings NS11-NS23 can be connected between the first-third bit lines BL1-BL3 and the common source line CSL. Each NAND string (e.g., NAND string NS11) can include a string select transistor SST, a plurality of memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8, a first ground select transistor GST1, and a second ground select transistor GST2 connected in series.

[0039] NAND strings commonly connected to a single bit line can form a single column. For example, NAND strings NS11 and NS21 commonly connected to the first bit line BL1 can form a first column, NAND strings NS12 and NS22 commonly connected to the second bit line BL2 can form a second column, and NAND strings NS13 and NS23 commonly connected to the third bit line BL3 can form a third column.

[0040] NAND strings connected to a single string select line can form a single row. For example, NAND strings NS11, NS12, and NS13 connected to the first string select line SSL1 can correspond to a first row, and NAND strings NS21, NS22, and NS23 connected to the second string select line SSL2 can correspond to a second row.

[0041] The string select transistor SST can be connected to a respective one of the first and second string select lines SSL1-SSL2. The memory cells MC1-MC8 can be connected to the first-eighth word lines WL1-WL8, respectively. The first and second ground select transistors GST1 and GST2 can be connected to the ground select lines GSL1 and GSL2, respectively. The string select transistor SST can be connected to a respective one of the first-third bit lines BL1-BL3. The first ground select transistor GST1 can be connected to the common source line CSL.

[0042] According to example embodiments of the inventive concepts, word lines arranged at the same level (e.g., WL1) can be connected to each other. According to example embodiments of the inventive concepts, string select lines SSL1 and SSL2 arranged at the same level can be separate from each other. For example, when programming memory cells connected to the first word line WL1 and included in the NAND strings NS11, NS12, and NS13 corresponding to the first row, the first word line WL1 and the first string select line SSL1 are selected. According to example embodiments of the inventive concepts, there is one ground select line (e.g., GSL1 or GSL2) at one level, but the inventive concepts are not limited thereto. For example, there can be separate ground select lines at one level.

[0043] FIG. 4is a plan view of a semiconductor memory device 10 according to exemplary embodiments of the inventive concept. FIG. 5A and FIG. 5B is FIG. 4 is a plan view of a respective portion of the semiconductor memory device 10. For example, FIG. 5A and FIG. 5B are plan views of a first word line contact structure WCS1 and a second word line contact structure WCS2, respectively, of the semiconductor memory device 10. FIG. 4 the line II-II' in FIG. 5B may correspond to the line II-II' in FIG. 6A to FIG. 6D is a cross-sectional view taken along the line I-I' and the line II-II' in FIG. 4 is a cross-sectional view taken along the line I-I' and the line II-II' in FIG. 6A to FIG. 6D is a cross-sectional view according to different embodiments of the inventive concept.

[0044] Referring to FIG. 4 to FIG. 6A , the semiconductor memory device 10 can include a first semiconductor device layer L1 including a peripheral circuit and a second semiconductor device layer L2 including an array of memory cells. The semiconductor memory device 10 can have a structure in which the second semiconductor device layer L2 is stacked on the first semiconductor device layer L1.

[0045] The first semiconductor device layer L1 can include a lower base 101, peripheral transistors 111 and 112 on the lower base 101, peripheral circuit wiring electrically connected to the peripheral transistors 111 and 112, and a lower insulating layer 160 covering the peripheral transistors 111 and 112 and the peripheral circuit wiring. According to exemplary embodiments of the inventive concept, the lower insulating layer 160 can include an insulating material. According to exemplary embodiments of the inventive concept, the lower insulating layer 160 can include silicon oxide, silicon nitride, or silicon oxynitride, but is not limited thereto.

[0046] According to exemplary embodiments of the inventive concept, the lower base 101 can include a semiconductor base including a semiconductor material such as single-crystal silicon or single-crystal germanium. Trenches and an isolation layer 102 filling the trenches can be formed to define active regions and non-active regions in the lower base 101.

[0047] According to exemplary embodiments of the inventive concept, the peripheral transistors 111 and 112 can form a peripheral circuit 60 in FIG. 1 According to exemplary embodiments of the inventive concept, some of the peripheral transistors (e.g., the peripheral transistor 112) can form a peripheral circuit 60 in FIG. 1The CSL driver 64 is described. According to an exemplary embodiment of the inventive concept, the peripheral transistor 112 can be connected to the common source line CSL through a wiring formed in the first semiconductor device layer L1 and a wiring formed in the second semiconductor device layer L2. According to an exemplary embodiment of the inventive concept, the peripheral transistor 112 can provide a common source voltage to an upper substrate to be described below through the common source line CSL.

[0048] The peripheral circuit wiring can include a plurality of peripheral conductive patterns 140 sequentially stacked on the lower substrate 101. The peripheral circuit wiring can further include a plurality of peripheral vias 130 connecting the peripheral transistors 111 and 112 to the peripheral conductive patterns 140 located at different levels. Although it is shown that the peripheral circuit wiring includes the peripheral conductive patterns 140 located at three levels and the peripheral vias 130 connecting the peripheral conductive patterns 140 to each other, the inventive concept is not limited thereto. The peripheral circuit wiring can include peripheral conductive lines located at one level, two levels, or four or more levels and vias connecting the peripheral conductive lines to each other.

[0049] According to an exemplary embodiment of the inventive concept, the peripheral conductive patterns 140 and the peripheral vias 130 can include a conductive material. According to an exemplary embodiment of the inventive concept, the peripheral conductive patterns 140 and the peripheral vias 130 can include tungsten, tantalum, cobalt, nickel, tungsten silicide, tantalum silicide, cobalt silicide, or nickel silicide. According to an exemplary embodiment of the inventive concept, the peripheral conductive patterns 140 and the peripheral vias 130 can include polysilicon.

[0050] The second semiconductor device layer L2 can include the common source line CSL, an upper substrate 201 on the common source line CSL, a stack structure SS, an O-N box ONB, and an upper insulating layer 260. The stack structure SS and the O-N box ONB are disposed on the upper substrate 201. The upper insulating layer 260 covers the stack structure SS, the O-N box ONB, the upper substrate 201. According to an exemplary embodiment of the inventive concept, the second semiconductor device layer L2 can further include a wiring for allowing the stack structure SS to operate as a memory cell array (50) in the lower substrate 101. FIG. 1

[0051] The common source line CSL can be disposed on the first semiconductor device layer L1. According to an exemplary embodiment of the inventive concept, the common source line CSL can be flat. According to an exemplary embodiment of the inventive concept, the common source line CSL can include tungsten (W) or a tungsten compound. According to an exemplary embodiment of the inventive concept, the common source line CSL can be partially etched, and thus, a lower portion of the intermediate insulating film 205 can be disposed in an etched portion of the common source line CSL to be surrounded by the common source line CSL.

[0052] ​According to an exemplary embodiment of the inventive concept, the upper substrate 201 can be a support layer for supporting the stack structure SS and the O-N box ONB. According to an exemplary embodiment of the inventive concept, the upper substrate 201 can include a plurality of layers, but is not limited thereto. For example, the upper substrate 201 can be a single layer. According to an exemplary embodiment of the inventive concept, the upper substrate 201 can include a first upper substrate layer 201a on a common source line CSL, a second upper substrate layer 201b on the first upper substrate layer 201a, and a third upper substrate layer 201c on the second upper substrate layer 201b. According to an exemplary embodiment of the inventive concept, the first upper substrate layer 201a can be in contact with the second upper substrate layer 201b. According to an exemplary embodiment of the inventive concept, the second upper substrate layer 201b can be in contact with the third upper substrate layer 201c. According to an exemplary embodiment of the inventive concept, the second upper substrate layer 201b can include an opening exposing a top surface of the first upper substrate layer 201a. According to an exemplary embodiment of the inventive concept, the third upper substrate layer 201c can partially contact the first upper substrate layer 201a via the opening.

[0053] According to an exemplary embodiment of the inventive concept, the intermediate insulating film 205 can extend to the same level as a top surface of the upper substrate 201. According to an exemplary embodiment of the inventive concept, the intermediate insulating film 205 can be surrounded by the first upper substrate layer 201a to the third upper substrate layer 201c. According to an exemplary embodiment of the inventive concept, the intermediate insulating film 205 can be in contact with the first upper substrate layer 201a to the third upper substrate layer 201c.

[0054] According to an exemplary embodiment of the inventive concept, the first upper substrate layer 201a to the third upper substrate layer 201c can include polysilicon. According to an exemplary embodiment of the inventive concept, the first upper substrate layer 201a to the third upper substrate layer 201c can include a doped polysilicon film. According to an exemplary embodiment of the inventive concept, the first upper substrate layer 201a to the third upper substrate layer 201c can be doped with approximately the same concentration as each other.

[0055] The first upper substrate layer 201a to the third upper substrate layer 201c can include a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon germanium substrate, or an epitaxial thin film substrate obtained through selective epitaxial growth (SEG). The first upper substrate layer 201a to the third upper substrate layer 201c can include silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or a mixture thereof.

[0056] A stack structure SS can be disposed on the upper substrate 201. The stack structure SS can include a plurality of gate electrodes 240 spaced apart from each other in a first direction (e.g., a Z direction). According to an exemplary embodiment of the inventive concept, in order of starting from the upper substrate 201, the gate electrodes 240 can correspond to the first ground select transistor GST1, the second ground select transistor GST2, the memory cells MC1 to MC8, and the string select transistor SST, which have been described with reference to FIGS. 1 to 3. FIG. 3 The first ground select transistor GST1 and the second ground select transistor GST2, the memory cells MC1 to MC8, and the string select transistor SST described above are described. Although eight gate electrodes 240 are shown as operating as memory cells in FIG. 6A FIG. 4, the inventive concept is not limited thereto. For example, various numbers of gate electrodes 240 (e.g., 4, 16, 32, or 64 gate electrodes 240) can operate as memory cells.

[0057] According to an exemplary embodiment of the inventive concept, at least one dummy gate electrode can also be disposed between the gate electrode 240 corresponding to the second ground select transistor GST2 (see FIG. 3 ) and the gate electrode 240 corresponding to the memory cell MC1. Alternatively, at least one dummy gate electrode can be disposed between the gate electrode 240 corresponding to the string select transistor SST (see FIG. 3 ) and the gate electrode 240 corresponding to the memory cell MC8. In this case, the inter-cell interference between adjacent gate electrodes 240 can be reduced.

[0058] According to an exemplary embodiment of the inventive concept, the gate electrodes 240 can include a conductive material. According to an exemplary embodiment of the inventive concept, the gate electrodes 240 can include tungsten, tantalum, cobalt, nickel, tungsten silicide, tantalum silicide, cobalt silicide, or nickel silicide. According to an exemplary embodiment of the inventive concept, the gate electrodes 240 can include polysilicon. According to an exemplary embodiment of the inventive concept, the first to third via holes 271, 273, and 277, the word line contact via hole 275, the bit line contact via hole 283, the first to third upper conductive via holes 282, 285, and 287, the first upper conductive pattern 284, and the second upper conductive pattern 290, and the dummy bit line contact via hole 283D, which will be described below, can include at least one of the materials exemplarily mentioned above in relation to the gate electrodes 240.

[0059] The first portion 230a of each insulating film 230 can be disposed between adjacent gate electrodes 240. Accordingly, the stack structure SS can include the gate electrodes 240 and the first portions 230a of each insulating film 230. According to an exemplary embodiment of the inventive concept, a first upper insulating layer 261 and a second upper insulating layer 263 can be disposed on the stack structure SS. The first upper insulating layer 261 and the second upper insulating layer 263 can include an insulating material.

[0060] According to an exemplary embodiment of the inventive concept, the plurality of channel structures 250 can penetrate through the first upper insulating layer 261 and the stack structure SS in a first direction (e.g., the Z direction). According to an exemplary embodiment, the channel structures 250 can penetrate at least a portion of the upper substrate 201. According to an exemplary embodiment of the inventive concept, the channel structures 250 can penetrate at least a portion of the first upper substrate layer 201a. Accordingly, a respective top surface of the channel structures 250 can form a plane with a top surface of the first upper insulating layer 261, and a respective bottom surface of the channel structures 250 can be located at a lower level than a top surface of the first upper substrate layer 201a. Adjacent channel structures 250 can be spaced apart from each other by a certain distance in a second and third direction (e.g., the X and Y directions).

[0061] According to an exemplary embodiment of the inventive concept, each channel structure 250 can include a plurality of layers. According to an exemplary embodiment of the inventive concept, each channel structure 250 can include a gate insulating film 251, a channel layer 253, and a buried insulating film 255.

[0062] According to an exemplary embodiment of the inventive concept, the gate insulating film 251 can have a conformal thickness. According to an exemplary embodiment of the inventive concept, the gate insulating film 251 can form a bottom surface and an outer surface of each channel structure 250. Accordingly, the gate insulating film 251 can insulate the channel layer 253 from the gate electrode 240.

[0063] According to an exemplary embodiment of the inventive concept, the gate insulating film 251 can include a plurality of layers having a conformal thickness. According to an exemplary embodiment of the inventive concept, the gate insulating film 251 can include a tunnel insulating layer, a charge storage layer, and a blocking insulating layer. In this case, a blocking metal layer can also be disposed between the gate insulating film 251 and the gate electrode 240. The tunnel insulating layer can include silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, or tantalum oxide. The charge storage layer can be a region that stores electrons that tunnel from the channel layer 253. The charge storage layer can include silicon nitride, boron nitride, silicon boron nitride, or polysilicon doped with an impurity. The blocking insulating layer can include a single layer or a stack layer thereof, the single layer including silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, or tantalum oxide. However, the material of the blocking insulating layer is not limited thereto, but can include a dielectric material having a high dielectric constant.

[0064] According to an exemplary embodiment of the inventive concept, the gate insulating film 251 can not be at the same level as the second upper substrate layer 201b. This is because the gate insulating film 251 is partially removed by a replacement process of the second upper substrate layer 201b. Accordingly, the channel layer 253 can be in contact with the second upper substrate layer 201b.

[0065] According to an example embodiment of the inventive concept, the channel layer 253 can partially fill an inner space defined by the gate insulating film 251. The channel layer 253 formed on an inner surface of the gate insulating film 251 can have a conformal thickness. According to an example embodiment of the inventive concept, a top portion of the channel layer 253 can be thicker than a sidewall of the channel layer 253.

[0066] According to an example embodiment of the inventive concept, a space defined by the channel layer 253 can be filled with a buried insulating film 255. A top surface of the buried insulating film 255 can be covered by a top portion of the channel layer 253. According to an example embodiment of the inventive concept, a top surface of the channel layer 253 can serve as a pad for electrically connecting to the bit line contact via 283. In some cases, a separate contact pad can be disposed on the top surface of the channel layer 253.

[0067] Although the gate insulating film 251 is shown to cover a bottom surface of the channel layer 253 in FIG. 6A , the inventive concept is not limited thereto. For example, the gate insulating film can expose the bottom surface of the channel layer, and can form only a sidewall of the channel structure. In this case, the semiconductor pattern grown from the upper base by the SEG can be in contact with the bottom surface of the channel layer, and the channel layer can not be directly connected to the upper base.

[0068] According to an example embodiment of the inventive concept, the bit line contact via 283 can be connected to the upper conductive pattern corresponding to the bit line BL among the second upper conductive patterns 290 through the first upper conductive pattern 284 and the second upper conductive via 285. Accordingly, the channel structure 250 can be electrically connected to the bit line BL.

[0069] According to an example embodiment of the inventive concept, the first dummy channel structure 250D1 can penetrate through the stack structure SS. According to an example embodiment of the inventive concept, the first dummy channel structure 250D1 can be disposed between the channel structures 250. According to an example embodiment of the inventive concept, the selection line cut SLC can overlap the first dummy channel structure 250D1 in a vertical direction. Accordingly, the first dummy channel structure 250D1 can have a structure resulting from partially removing a top portion of each of the channel structures 250. According to an example embodiment of the inventive concept, the first dummy channel structure 250D1 can not be connected to the bit line BL.

[0070] According to an example embodiment of the inventive concept, the first word line cut WLC1 can penetrate through the first upper insulating layer 261, the second upper insulating layer 263, and the stack structure SS in a first direction (e.g., the Z direction). According to an example embodiment of the inventive concept, the first word line cut WLC1 can partially penetrate the first upper base layer 201a.

[0071] According to an example embodiment of the inventive concept, the first word line cut fill film WLCI1 can fill an inner space of the first word line cut WLC1. According to an example embodiment of the inventive concept, the first word line cut fill film WLCI1 can include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. According to an example embodiment of the inventive concept, the first word line cut fill film WLCI1 can insulate gate electrodes 240 arranged at one vertical level. According to an example embodiment of the inventive concept, the first word line cut fill film WLCI1 can insulate gate electrodes 240 and dummy gate electrodes 240D adjacent to each other and located at the same vertical level.

[0072] According to an example embodiment of the inventive concept, the plurality of dummy gate electrodes 240D can be spaced apart from the gate electrodes 240 and the first word line cut fill film WLCI1 is located between the dummy gate electrodes 240D and the gate electrodes 240. According to an example embodiment of the inventive concept, the dummy gate electrodes 240D can be spaced apart from each other in the first direction (e.g., the Z direction).

[0073] According to an example embodiment of the inventive concept, the plurality of remaining sacrifice films 220R can be separated from the gate electrodes 240 and the first word line cut fill film WLCI1 is located between the remaining sacrifice films 220R and the gate electrodes 240. According to an example embodiment of the inventive concept, the remaining sacrifice films 220R can be spaced apart from each other in the first direction (e.g., the Z direction). According to an example embodiment of the inventive concept, the second portions 230b of each insulating film 230 can be arranged between adjacent remaining sacrifice films 220R, and the third portions 230c of each insulating film 230 can be arranged between adjacent dummy gate electrodes 240D.

[0074] According to an example embodiment of the inventive concept, the remaining sacrifice films 220R and the second portions 230b of the corresponding insulating films 230 can form an O-N box ONB. According to an example embodiment of the inventive concept, the first via 271 and the second via 273 can penetrate through the O-N box ONB in the first direction (e.g., the Z direction). According to an example embodiment of the inventive concept, a length of each of the first via 271 and the second via 273 in the first direction (e.g., the Z direction) can be greater than a length of the stack structure SS in the first direction (e.g., the Z direction). Accordingly, the first via 271 and the second via 273 can be in contact with the remaining sacrifice films 220R and the insulating films 230.

[0075] According to exemplary embodiments of the inventive concept, the first via hole 271 can also penetrate a portion of the middle insulating film 205 and the lower insulating layer 160. According to exemplary embodiments of the inventive concept, the first via hole 271 can be connected to the peripheral transistor 111 via the peripheral wiring layer. According to exemplary embodiments of the inventive concept, the second via hole 273 can be connected to the common source line CSL. According to exemplary embodiments of the inventive concept, a top of the common source line CSL can be partially etched during a process of forming the second via hole 273, and thus, the common source line CSL can have a recessed structure. Accordingly, a bottom surface of the second via hole 273 can be located at a lower level than a top surface of the common source line CSL.

[0076] According to exemplary embodiments of the inventive concept, the second via hole 273 can be connected to the common source line tap wiring CTW through the first upper conductive via to the third upper conductive vias 282, 285, and 287, and the first and second upper conductive patterns 284 and 290. According to exemplary embodiments of the inventive concept, one of the bit lines BL can be connected to the common source line tap wiring CTW through the third upper conductive via 287. According to exemplary embodiments of the inventive concept, the bit line BL connected to the common source line tap wiring CTW can be used as a wiring of the common source line CSL and thus, operates differently from the other bit lines BL.

[0077] According to exemplary embodiments of the inventive concept, the second dummy channel structure 250D2 can penetrate through the dummy gate electrode 240D. According to exemplary embodiments of the inventive concept, the second dummy channel structure 250D2 can have a similar structure to the channel structure 250. For example, the dummy gate insulating layer 251D, the dummy channel layer 253D, and the dummy buried insulating layer 255D of the second dummy channel structure 250D2 can have the same structure as the gate insulating film 251, the channel layer 253, and the buried insulating film 255 of each of the channel structures 250, respectively. According to exemplary embodiments of the inventive concept, the second dummy channel structure 250D2 can be connected to the second upper conductive pattern 290, which is a bit line BL, through the dummy bit line contact via 283D and the second upper conductive via 285. Accordingly, the second dummy channel structure 250D2 can be electrically connected to the bit line BL, but can not operate as a memory cell because the dummy gate electrode 240D does not operate as a gate of the ground transistor, the memory cell, and the string selection transistor.

[0078] As described below, the stack of the gate electrode 240 and the dummy gate electrode 240D can have a stepped shape. Although FIG. 6A Only the stepped shape of the dummy gate electrode 240D and the dummy word line contact via 275D in contact therewith is illustrated in FIG. 2B, but the stepped shape of the gate electrode 240 and the word line contact via 275 in contact therewith is the same as in FIG. 2A. FIG. 6AThe two are substantially the same as those shown. According to an exemplary embodiment of the inventive concept, the dummy word line contact via 275D can be connected to the second upper conductive pattern 290 via the first upper conductive via 282, the first upper conductive pattern 284, and the second upper conductive via 285.

[0079] Similarly, refer to FIG. 5A and FIG. 6A The word line contact via 275 can be connected to the second upper conductive pattern 290 through the first upper conductive via 282, the first upper conductive pattern 284, and the second upper conductive via 285. The second upper conductive pattern 290 corresponds to the first ground select line GSL1 and the second ground select line GSL2, the first word line WL1 to the eighth word line WL8, and the first string select line SSL1 and the second string select line SSL2, respectively.

[0080] According to an exemplary embodiment of the inventive concept, the upper insulating layer 260 may cover the common source line CSL, the upper substrate 201, the stacked structure SS, the ON box ONB, and the wiring disposed thereon. According to an exemplary embodiment of the inventive concept, the upper insulating layer 260 may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0081] According to an exemplary embodiment of the inventive concept, the third via 277 can partially penetrate the upper insulating layer 260 and the lower insulating layer 160. According to an exemplary embodiment of the inventive concept, the third via 277 can be connected to peripheral circuit wiring via the first upper conductive via to the third upper conductive via 282, 285, and 287, and the first upper conductive pattern 284 and the second upper conductive pattern 290. According to an exemplary embodiment of the inventive concept, the third via 277 can be connected to a corresponding reference... FIG. 1 The peripheral transistor 112 of the described CSL driver 64. Therefore, the peripheral transistor 112 can be electrically connected to the common source line CSL.

[0082] Reference FIG. 4 In this layout, the stacked structures SS can be separated from each other by cutting WLC1 with a first word line extending in a second direction (e.g., the X direction). According to an exemplary embodiment of the inventive concept, the length of each of the stacked structures SS in the second direction (e.g., the X direction) can be less than the length of the first word line cutting WLC1 in the second direction (e.g., the X direction).

[0083] According to an example embodiment of the inventive concept, the O-N box ONB can be located between adjacent stack structures SS. The stack structures SS can be separated from the O-N box ONB and have the first word line cut fill films WLCI1 located therebetween. The O-N box ONB can include the remaining sacrificial films 220R having a flat shape and spaced apart from each other in a first direction (e.g., Z direction) and the second portions 230b of the corresponding insulating films 230. Each of the second portions 230b of the insulating films 230 can be located between adjacent remaining sacrificial films 220R.

[0084] The intermediate insulating film 205 and a portion of the upper substrate 201 can be located under the O-N box ONB. Accordingly, the O-N box ONB can be in contact with a top surface of the intermediate insulating film 205 and a top surface of the third upper substrate layer 201c. According to an example embodiment of the inventive concept, the first via 271 can penetrate through the intermediate insulating film 205. According to an example embodiment of the inventive concept, the second via 273 can be spaced apart from the intermediate insulating film 205 in a horizontal direction.

[0085] When a distance between two first word line cut fill films WLCI1 separated from each other and having the stack structure SS located therebetween is referred to as a first distance D1 and a distance between the O-N box ONB and the first word line cut fill film WLCI1 adjacent to the O-N box ONB is referred to as a second distance D2, the first distance D1 can be greater than the second distance D2. According to an example embodiment of the inventive concept, the first distance D1 can be about 1350 nm and the second distance D2 can be about 1000 nm, but the inventive concept is not limited thereto. The second distance D2 can be a maximum distance for a replacement process in which a sacrificial film is removed and a gate electrode is formed. Since the first word line cut fill films WLCI1 extend substantially in parallel to each other, the first distance D1 is a minimum horizontal (e.g., third direction, e.g., Y direction) linear distance between adjacent first word line cut fill films WLCI1. Similarly, the second distance D2 is a minimum horizontal (e.g., third direction, e.g., Y direction) linear distance between the O-N box ONB and the first word line cut fill film WLCI1 adjacent to the O-N box ONB.

[0086] According to an example embodiment of the inventive concept, the first word line contact structure WCS1 can be formed at an end of the stack structure SS in a second direction (e.g., X direction), which is detailed in FIG. 5A Although the first word line contact structure WCS1 is formed at an end of the stack structure SS in a second direction (e.g., X direction) and in FIG. 4The first word line contact structure WCS1 is not formed at the opposite ends, but the inventive concept is not limited thereto. For example, the first word line contact structure WCS1 may be formed at each of the opposite ends of the stacked structure SS in a second direction (e.g., the X direction).

[0087] The gate electrode 240 at the top layer can be separated by a selectively wire-cut SLC. According to an exemplary embodiment of the inventive concept, the selectively wire-cut SLC can extend in a second direction (e.g., the X direction) and can completely separate the gate electrode 240 at the top layer. According to an exemplary embodiment of the inventive concept, the length of the selectively wire-cut SLC in the second direction (e.g., the X direction) can be less than the length of the first word wire-cut WLC1 in the second direction (e.g., the X direction).

[0088] According to an exemplary embodiment of the inventive concept, a plurality of dummy gate electrodes 240D may be arranged between first word-cut filler films WLCI1 adjacent to the ON cell ONB. The plurality of dummy gate electrodes 240D may be spaced apart from each other along a first direction (e.g., the Z direction). According to an exemplary embodiment of the inventive concept, the dummy gate electrodes 240D may surround the ON cell ONB. According to an exemplary embodiment of the inventive concept, the length of the dummy gate electrode 240D in a third direction (e.g., the Y direction) may be greater than the length of the gate electrode 240 in a third direction (e.g., the Y direction), but the inventive concept is not limited thereto. According to an exemplary embodiment of the inventive concept, the length of each of the dummy gate electrodes 240D in a second direction (e.g., the X direction) may be substantially the same as the length of each of the gate electrodes 240 located at the same level as each of the dummy gate electrodes 240D in the second direction (e.g., the X direction).

[0089] According to an exemplary embodiment of the inventive concept, the second word line contact structure WCS2 can be formed at the end of each dummy gate electrode 240D, which in FIG. 5B The details are shown below. Although the second word line contact structure WCS2 is formed at the end of each dummy gate electrode 240D in the second direction (e.g., the X direction), and FIG. 4 The second word line contact structure WCS2 is not formed at the opposite ends, but the inventive concept is not limited thereto. For example, the second word line contact structure WCS2 may be formed at both ends of the stacked structure SS or may not be formed at all.

[0090] According to example embodiments of the inventive concepts, a second word line cut WLC2 and a second word line cut fill film WLCI2 filling the second word line cut WLC2 can be disposed at each of opposite end portions of each dummy gate electrode 240D in a second direction (e.g., X direction). According to example embodiments of the inventive concepts, the second word line cut WLC2 can extend in the second direction (e.g., X direction). According to example embodiments of the inventive concepts, a length of the second word line cut WLC2 in the second direction (e.g., X direction) can be less than a length of the first word line cut WLC1 in the second direction (e.g., X direction). According to example embodiments of the inventive concepts, the second word line cut WLC2 can be shorter than the stack structure SS in the second direction (e.g., X direction). According to example embodiments of the inventive concepts, the second word line cut WLC2 can be shorter than the O-N box ONB in the second direction (e.g., X direction). According to example embodiments of the inventive concepts, the second word line cut WLC2 can penetrate through a portion of each dummy gate electrode 240D in a first direction (e.g., Z direction). The portion of each dummy gate electrode 240D is adjacent to an end portion of each dummy gate electrode 240D in the second direction (e.g., X direction).

[0091] According to example embodiments of the inventive concepts, a single second word line cut fill film WLCI2 can be located between adjacent first word line cut fill films WLCI1, although the inventive concepts are not limited thereto. For example, at least two second word line cut fill films WLCI2 can be located between adjacent first word line cut fill films WLCI1. The number of second word line cut fill films WLCI2 between adjacent first word line cut fill films WLCI1 can vary depending on the size of the O-N box ONB. The number of second word line cut fill films WLCI2 at the end portions of each dummy gate electrode 240D in the second direction (e.g., X direction) can be different from the number of second word line cut fill films WLCI2 at the opposite end portions of each dummy gate electrode 240D. According to example embodiments of the inventive concepts, a distance between each second word line cut fill film WLCI2 and the O-N box ONB in the second direction (e.g., X direction) can be a second distance D2.

[0092] According to example embodiments of the inventive concepts, the common source line tap wiring CTW can extend in the second direction (e.g., X direction). According to example embodiments of the inventive concepts, a length of the common source line tap wiring CTW in the second direction (e.g., X direction) can be greater than a length of the common source line CSL in the second direction (e.g., X direction), although the inventive concepts are not limited thereto. The length of the common source line tap wiring CTW in the second direction (e.g., X direction) can be equal to or less than the length of the common source line CSL in the second direction (e.g., X direction).

[0093] According to an example embodiment of the inventive concept, the common source line tap wiring CTW can protrude outward from the common source line CSL in a second direction (e.g., the X direction). Although both ends of the common source line tap wiring CTW in the second direction (e.g., the X direction) protrude from the common source line CSL, FIG. 4 According to an example embodiment of the inventive concept, only one end of the common source line tap wiring CTW in the second direction (e.g., the X direction) can protrude from the common source line CSL.

[0094] According to an example embodiment of the inventive concept, the common source line tap wiring CTW can extend over the O-N box ONB. According to an example embodiment of the inventive concept, the common source line tap wiring CTW can be electrically connected to the plurality of second vias 273. Accordingly, the resistance of the common source line CSL can be reduced, and thus the noise characteristics of the semiconductor memory device 10 can be improved. According to an example embodiment of the inventive concept, the common source line tap wiring CTW can not be vertically stacked with the first via 271 and the intermediate insulating film 205.

[0095] The horizontal area of the lower base 101 can be greater than the horizontal area of each of the common source line CSL and the upper base 201. According to an example embodiment of the inventive concept, the entire area of each of the common source line CSL and the upper base 201 can be vertically stacked with the lower base 101. According to an example embodiment of the inventive concept, the horizontal area of the common source line CSL can be equal to the horizontal area of the upper base 201, but the inventive concept is not limited thereto. According to an example embodiment of the inventive concept, the horizontal area of the common source line CSL can be greater than the horizontal area of the upper base 201. According to an example embodiment of the inventive concept, the horizontal area of the stack structure SS can be less than the horizontal area of the upper base 201.

[0096] Referring to FIG. 5A , the first word line contact structure WCS1 can have a stepped structure in which the gate electrode 240 located at a lower level protrudes farther in the second direction (e.g., the X direction) than the gate electrode 240 located at an upper level. According to an example embodiment of the inventive concept, the first word line contact structure WCS1 can have a stepped structure in both the second direction (e.g., the X direction) and the third direction (e.g., the Y direction). According to an example embodiment of the inventive concept, the word line contact via 275 can be formed on the stepped structure. According to an example embodiment of the inventive concept, each word line contact via 275 can contact a portion of the gate electrode 240 that protrudes farther than the gate electrode 240 located at an upper level in the second direction (e.g., the X direction) or the third direction (e.g., the Y direction).

[0097] As described below, the first upper conductive pattern 284 and the second upper conductive pattern 290 can be disposed above the stack structure SS. According to an exemplary embodiment of the inventive concept, each of the second upper conductive patterns 290 can extend in the second direction (e.g., the X direction). According to an exemplary embodiment of the inventive concept, each of the second upper conductive patterns 290 extending over the first word line contact structure WCS1 can correspond to the first ground select line GSL1 and the second ground select line GSL2, which have been described with reference to FIG. 3 one of the first ground select line GSL1 and the second ground select line GSL2, the first word line WL1 to the eighth word line WL8, and the first string select line SSL1 and the second string select line SSL2 described above.

[0098] According to an exemplary embodiment of the inventive concept, the second upper conductive patterns 290 respectively corresponding to the first ground select line GSL1 and the second ground select line GSL2 can be sequentially connected to the two gate electrodes 240 disposed at the bottom of the stack structure SS. According to an exemplary embodiment of the inventive concept, the second upper conductive patterns 290 corresponding to each of the first string select line SSL1 and the second string select line SSL2 can be connected to the gate electrodes 240 located at the top level of the stack structure SS. According to an exemplary embodiment of the inventive concept, the second upper conductive patterns 290 respectively corresponding to the first word line WL1 to the eighth word line WL8 can be sequentially connected to the gate electrodes 240 respectively located at the third level to the tenth level from the bottom of the stack structure SS.

[0099] Referring to FIG. 5A and FIG. 5B , the second word line contact structure WCS2 can have a similar structure to the first word line contact structure WCS1. However, the dummy gate electrode 240D of the second word line contact structure WCS2 does not operate as a gate of a memory cell. Accordingly, the dummy word line contact via 275D and the second upper conductive pattern 290 in the second word line contact structure WCS2 can not perform a circuit operation for driving a memory cell. Thus, the dummy word line contact via 275D and the second upper conductive pattern 290 can be completely or partially omitted from the second word line contact structure WCS2.

[0100] FIG. 6B to FIG. 6D are cross-sectional views for explaining semiconductor memory devices according to different embodiments of the inventive concept, and correspond to FIG. 6A cross-sectional views of FIG. 4 to FIG. 6A . Redundant descriptions given with reference to will be omitted, and the following description will mainly focus on the differences.

[0101] FIG. 6B Referring to FIG. 6A , unlike , the common source line CSL can not be over-etched, but can be in contact with the second via 273. Accordingly, a bottom surface of the second via 273 can be located at the same level as a top surface of the common source line CSL. In this case, the second via 273 can be in contact with the common source line CSL.FIG. 6B In the middle, the second through hole 273 does not reach the lower insulating layer 160.

[0102] Reference FIG. 6C ,and FIG. 6A and FIG. 6B Unlike other vias, the second via 273 may not contact the common source line CSL. Therefore, the bottom surface of the second via 273 can be located at a vertical level above the top surface of the common source line CSL. According to an exemplary embodiment of the inventive concept, the upper substrate 201 can be located between the second via 273 and the common source line CSL. For example, in FIG. 6C In this configuration, the second via 273 may partially protrude into the first upper substrate layer 201a. In this case, the upper substrate 201 may comprise polysilicon doped with a high concentration of impurities, and thus the second via 273 may be electrically connected to the common source line CSL.

[0103] Reference FIG. 6D ,and FIG. 6A to FIG. 6C Alternatively, a through-hole liner 274 can be provided around the side surface of the second through-hole 273. Therefore, the second through-hole 273 can be separated from the remaining sacrificial film 220R and the insulating film 230. According to an exemplary embodiment of the inventive concept, the through-hole liner 274 can contact the remaining sacrificial film 220R and the insulating film 230.

[0104] FIG. 7A to FIG. 7D These are plan views of semiconductor memory devices 10a, 10b, 10c, and 10d according to different embodiments of the inventive concept. References will be omitted. FIG. 4 to FIG. 6A Given the redundant descriptions provided, the following description will focus primarily on the differences.

[0105] The outline of the intermediate insulating film 205 and the outline of the ON box ONB are in FIG. 4 On the plan view, they share one different side, and the outline of the intermediate insulating film 205 can be seen in FIG. 7A The semiconductor memory device 10a is included in the outline of the ON cell ONB in ​​a plan view. Therefore, the outlines of each of the intermediate insulating film 205 and the ON cell ONB can have a quadrilateral shape, and each side of the intermediate insulating film 205 can be shorter than the corresponding side of the ON cell ONB.

[0106] exist FIG. 7B In the semiconductor memory device 10b, a plurality of intermediate insulating films 205 can be separated from each other below the ON cell ONB. According to an exemplary embodiment of the inventive concept, when viewed from above, the intermediate insulating films 205 can be separated from each other and the common source tap wiring CTW is located therebetween.

[0107] exist FIG. 7C In the semiconductor memory device 10c, the following can be omitted FIG. 4the second word line cut WLC2 and the second word line cut fill film WLCI2. Thus, the O-N box ONB and the intermediate insulating film 205 can have the same length in the second direction (e.g., the X direction), and the length of the O-N box ONB and the intermediate insulating film 205 can be substantially the same as the length of the stack structure SS in the second direction (e.g., the X direction).

[0108] FIG. 7D The semiconductor memory device 10d can include a plurality of second word line cuts WLC2 and second word line cut fill films WLCI2 that fill the second word line cuts WLC2, respectively, between two first word line cuts WLC1. Thus, the length of the O-N box ONB in the third direction (e.g., the Y direction) can be greater than when a single second word line cut is provided. According to example embodiments of the inventive concepts, the distance between adjacent second word line cuts WLC2 can be the same as or different from the distance between adjacent first word line cuts WLC1.

[0109] FIG. 8 is a flowchart of a method of manufacturing a semiconductor memory device according to example embodiments of the inventive concepts. FIG. 9A to FIG. 9K is a cross-sectional view of a stage in a method of manufacturing a semiconductor memory device according to example embodiments of the inventive concepts. For example, FIG. 9A to FIG. 9K corresponding to FIG. 6A .

[0110] Referring to FIG. 8 and FIG. 9A in operation P10, a common source line and an upper base can be formed on the peripheral circuit. According to example embodiments of the inventive concepts, the forming of the common source line and the upper base can include forming the peripheral circuit and forming the common source line CSL, the first upper base layer 201a, and the upper base sacrificial layer 204.

[0111] The forming of the peripheral circuit can include forming the isolation layer 102 in the lower base 101, forming the p-well region and the n-well region in the lower base 101 in sequence (or in reverse sequence) by performing a first ion implantation process using a photoresist pattern on the lower base 101, forming the peripheral transistor, and forming the peripheral circuit wiring by patterning a conductive material and providing an insulating material.

[0112] According to an exemplary embodiment of the inventive concept, polysilicon doped with a first impurity can be used to form a common source line CSL, a first upper base layer 201a, and an upper base sacrificial layer 204 on the peripheral circuit using chemical vapor deposition, atomic layer deposition, or physical vapor deposition. According to an exemplary embodiment of the inventive concept, the upper base sacrificial layer 204 can include an insulating material. According to an exemplary embodiment of the inventive concept, the upper base sacrificial layer 204 can include silicon oxide, silicon nitride, or silicon oxynitride. According to an exemplary embodiment of the inventive concept, the upper base sacrificial layer 204 can have a higher etch selectivity than the insulating film (230) described below. FIG. 9D

[0113] Thereafter, referring to FIG. 9B , the upper base sacrificial layer 204 can be patterned and partially removed, and a third upper base layer 201c can be conformally disposed. Accordingly, the third upper base layer 201c can be in contact with the first upper base layer 201a in a portion in which the upper base sacrificial layer 204 is partially removed.

[0114] Thereafter, referring to FIG. 9C , intermediate insulating films 205 and 206 can be formed. The formation of the intermediate insulating films 205 and 206 can include etching the common source line CSL, the first upper base layer 201a, the upper base sacrificial layer 204, and the third upper base layer 201c so that a top surface of the lower insulating layer 160 is exposed, providing an insulating material to fill an opening formed by the etching, and performing planarization so that a top surface of the third upper base layer 201c is exposed.

[0115] Referring to FIG. 8 and FIG. 9D , in operation P20, an initial stack structure PSS including a sacrificial film 220 and an insulating film 230 can be formed on the third upper base layer 201c. According to an exemplary embodiment of the inventive concept, the initial stack structure PSS can have a similar stepped structure to the stack structure SS described above. According to an exemplary embodiment of the inventive concept, the initial stack structure PSS can include the insulating film 230 and the sacrificial film 220 alternately stacked. In this case, one of the insulating films 230 can be disposed directly on the third upper base layer 201c. According to an exemplary embodiment of the inventive concept, the insulating film 230 can have a different material from the sacrificial film 220. According to an exemplary embodiment of the inventive concept, the insulating film 230 and the sacrificial film 220 can have a high etch selectivity. For example, when the insulating film 230 includes silicon oxide, the sacrificial film 220 can include undoped polysilicon or silicon nitride. When the insulating film 230 includes silicon nitride, the sacrificial film 220 can include undoped polysilicon or silicon oxide. When the insulating film 230 includes undoped polysilicon, the sacrificial film 220 can include silicon nitride or silicon oxide.

[0116] ​According to exemplary embodiments of the inventive concepts, the upper insulating layer 260 can be formed to cover the staircase structure. The upper insulating layer 260 can include an insulating material. When the upper insulating layer 260 includes the same material as the intermediate insulating film 205, the upper insulating layer 260 and the intermediate insulating film 205 can form an integrated structure. Hereinafter, it is assumed that the intermediate insulating film 205 is integrated into the upper insulating layer 260. Similarly, the intermediate insulating film 206 can be integrated into the lowermost insulating film 230.

[0117] Referring to FIG. 8 , FIG. 9E and FIG. 9F , in operation P30, the channel structure 250 and the second dummy channel structure 250D2 can be formed. For example, a first upper insulating layer 261 can be disposed on the initial stack structure PSS, and a plurality of channel holes CH can be formed in the first upper insulating layer 261 and the initial stack structure PSS using a photoresist. According to exemplary embodiments of the inventive concepts, the channel holes CH can extend to the first upper base layer 201a. Thereafter, a gate insulating material film, a channel material film, and a buried insulating material film can be subsequently disposed, and the material films filling the channel holes CH can be separated by performing a back-etching process to expose a top surface of the first upper insulating layer 261. Thereafter, a top portion of the buried insulating material film in the channel holes CH can be removed, and the same material as the channel material film can be deposited such that the buried insulating material film 255 and the dummy buried insulating layer 255D can be completely covered by the channel layer 253 and the dummy channel layer 253D, respectively. Thus, a pad for contacting a bit line contact via 283 can be formed thereon. FIG. 6A

[0118] Referring to FIG. 8 and FIG. 9G , in operation P40, a word line cut can be formed. Although only the first word line cut WLC1 is illustrated in FIG. 9G , the second word line cut WLC2 illustrated in FIG. 4 may be formed at the same time.

[0119] According to exemplary embodiments of the inventive concepts, a second upper insulating layer 263 can be formed on the first upper insulating layer 261, and then the first word line cut WLC1 can be formed. A word line cut liner 265l can be disposed on the first word line cut WLC1, and a lower portion of the word line cut liner 265l can be removed using a back-etching process. Thus, an upper base sacrificial layer 204 in FIG. 9F may be exposed. According to exemplary embodiments of the inventive concepts, the word line cut liner 265l can include a material having a higher etching selectivity than the upper base sacrificial layer 204. According to exemplary embodiments of the inventive concepts, the word line cut liner 265l can protect the sacrificial film 220 in the initial stack structure PSS during a process of removing the upper base sacrificial layer 204.​

[0120] According to exemplary embodiments of the inventive concept, the upper base recess 204R can be formed by selectively removing the upper base sacrificial layer 204. At this time, a portion of the gate insulating film 251 and a portion of the dummy gate insulating layer 251D located at the same level as the upper base recess 204R can also be removed together. Since the third upper base layer 201c is in partial contact with the first upper base layer 201a, the first upper base layer 201a and the third upper base layer 201c and the initial stack structure PSS disposed thereon can be prevented from collapsing.

[0121] Thereafter, referring to FIG. 9H , a second upper base layer 201b filling the upper base recess 204R can be provided. As described above, the second upper base layer 201b can include polysilicon doped with impurities at approximately the same concentration as the first upper base layer 201a and the third upper base layer 201c. Since the gate insulating film 251 and the dummy gate insulating layer 251D have been partially removed as described above with reference to FIG. 9G , the second upper base layer 201b can be in contact with the channel layer 253. Accordingly, a charge transfer path for allowing the channel structure 250 to function as a memory cell can be formed.

[0122] Thereafter, referring to FIG. 8 and FIG. 9I , in operation P50, each of the sacrificial films 220 is partially removed, and in operation P60, gate electrodes can be formed. For example, the word line cut pad 265l in FIG. 9H may be removed, and the sacrificial film 220 can be selectively removed. According to exemplary embodiments of the inventive concept, the sacrificial film 220 has a higher etching selectivity than the insulating film 230 and the first to third upper base layers 201a, 201b, and 201c, and thus can be easily removed. At this time, a portion of each of the sacrificial films 220 spaced apart from each of the first and second word line cuts WLC1 and WLC2 (see FIG. 4 ) by a distance farther than the second distance D2 can not be removed, so that a remaining sacrificial film 220R and an O-N box ONB including the remaining sacrificial film 220R can be formed.

[0123] According to exemplary embodiments of the inventive concept, the gate electrodes 240 and the dummy gate electrodes 240D can be formed in spaces resulting from the partial removal of each of the sacrificial films 220. According to exemplary embodiments of the inventive concept, after the gate electrodes 240 are formed, a select line cut SLC can be formed to separate the uppermost one of the gate electrodes 240, and a recess space can be filled with an insulating material.

[0124] Thereafter, referring to FIG. 9JA first word line cut fill film WLCI1may be provided in the first word line cut WLC1. According to exemplary embodiments of the inventive concepts, a second word line cut fill film WLCI2may also be provided in the FIG. 4

[0125] Thereafter, reference is made to FIG. 9K A top insulating layer 260 can be additionally provided to cover the resulting structure, and first through third via holes 271, 273, and 277, and a dummy word line contact via hole 275D can be formed. According to exemplary embodiments of the inventive concepts, the word line contact via hole 275 in FIG. 5A

[0126] According to exemplary embodiments of the inventive concepts, the first via hole 271 can penetrate through the O-N box ONB and the middle insulating film 205 to connect to the peripheral circuitry wiring. According to exemplary embodiments of the inventive concepts, the second via hole 273 can penetrate through the O-N box ONB to connect to the common source line CSL. According to exemplary embodiments of the inventive concepts, the third via hole 277 can partially penetrate through the top insulating layer 260 and the bottom insulating layer 160 to connect to the peripheral wiring. Thus, the third via hole 277 can be electrically connected to the peripheral transistor 112.

[0127] Thereafter, reference is made to FIG. 6A A wiring process can be performed on the resulting structure. Thus, the common source line CSL can be electrically connected to the peripheral transistor 112 through the second via hole 273, a common source line tap wiring CTW, and the third via hole 277.

[0128] Exemplary embodiments of the inventive concepts provide semiconductor memory devices having enhanced noise characteristics and reliability, and methods of manufacturing the same.

[0129] While the inventive concepts have been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details can be made therein without departing from the spirit and scope of the inventive concepts as defined by the following claims.​​

Claims

1. A semiconductor memory device comprising: a common source line; a base on the common source line; a plurality of gate electrodes arranged on the base and spaced apart from each other in a first direction perpendicular to a top surface of the common source line; a plurality of insulating films arranged between the plurality of gate electrodes; a plurality of channel structures penetrating through the plurality of gate electrodes and the plurality of insulating films in the first direction; a plurality of remaining sacrificial films arranged on the base and spaced apart from each other in the first direction, wherein the plurality of remaining sacrificial films are sacrificial films that are not removed in a replacement process in which sacrificial films are removed and gate electrodes are formed; and a common source line tap wiring provided on the plurality of remaining sacrificial films, wherein the plurality of gate electrodes are provided on opposite sides of the plurality of remaining sacrificial films, wherein the semiconductor memory device further comprises an intermediate insulating film penetrating through the base and stacked with the plurality of remaining sacrificial films, wherein the common source line is spaced apart from the plurality of remaining sacrificial films in the first direction with the base interposed therebetween, wherein the semiconductor memory device further comprises a plurality of second vias penetrating through the base, the plurality of remaining sacrificial films, and the plurality of insulating films and spaced apart from the intermediate insulating film in a horizontal direction, and wherein the plurality of second vias are electrically connected to the common source line tap wiring and the common source line.

2. The semiconductor memory device according to claim 1, wherein, Each of the plurality of remaining sacrificial films is located at the same level from the base as a respective one of the plurality of gate electrodes.

3. The semiconductor memory device according to claim 1, wherein, The plurality of remaining sacrificial films comprise a different material from the plurality of gate electrodes.

4. The semiconductor memory device according to claim 3, wherein, The plurality of remaining sacrificial films comprise silicon nitride and the plurality of gate electrodes comprise an electrically conductive material.

5. The semiconductor memory device of claim 1, wherein, A portion of one of the plurality of insulating films is located between adjacent ones of the plurality of remaining sacrificial films.

6. The semiconductor memory device of claim 1, wherein, The common source line is provided on opposite sides of a lower portion of the intermediate insulating film.

7. The semiconductor memory device of claim 6, further comprising a plurality of first vias penetrating through the intermediate insulating film, the plurality of remaining sacrificial films, and the plurality of insulating films.

8. The semiconductor memory device of claim 7, wherein, The plurality of second vias are in contact with the common source line.

9. A semiconductor memory device comprising: a base; a box structure on the base; a common source line tap wiring provided on the box structure; and a plurality of vias penetrating through the box structure, wherein the box structure comprises: a plurality of remaining sacrificial films spaced apart from each other in a first direction perpendicular to a top surface of the base, wherein the plurality of remaining sacrificial films are sacrificial films that are not removed in a replacement process in which sacrificial films are removed and gate electrodes are formed; and a plurality of insulating films arranged between the plurality of remaining sacrificial films, wherein the semiconductor memory device further comprises an intermediate insulating film penetrating through the base and stacked with the plurality of remaining sacrificial films, and the common source line is spaced apart from the plurality of remaining sacrificial films in the first direction with the base interposed therebetween. ​ The plurality of through-holes includes a second through-hole that penetrates through the substrate, the plurality of remaining sacrificial films, and the plurality of insulating films and is spaced apart from the intermediate insulating film in the horizontal direction, and The second through-hole is electrically connected to the common source line tap wiring and the common source line.

10. The semiconductor memory device of claim 9, wherein, The plurality of remaining sacrificial films includes a different material from the plurality of insulating films.

11. The semiconductor memory device of claim 10, wherein, The plurality of remaining sacrificial films includes silicon nitride, and the plurality of insulating films includes silicon oxide.

12. The semiconductor memory device of claim 9, wherein, The plurality of through-holes is in contact with the plurality of remaining sacrificial films and the plurality of insulating films.

13. The semiconductor memory device of claim 9, wherein, At least one of the plurality of through-holes includes: An insulating liner that contacts the plurality of remaining sacrificial films and the plurality of insulating films; and A conductive via that is covered with the insulating liner.

14. A semiconductor memory device, the semiconductor memory device comprising: a substrate; a first gate stack structure and a second gate stack structure that extend in a horizontal direction on the substrate and include a plurality of gate electrode layers that are stacked in a vertical direction, the plurality of gate electrode layers having electrical conductivity; a plurality of channel structures that penetrate through one of the first gate stack structure and the second gate stack structure in the vertical direction; a remaining sacrificial film stack structure that is disposed between the first gate stack structure and the second gate stack structure and includes a plurality of sacrificial films that are stacked in the vertical direction, the plurality of sacrificial films having insulating properties, wherein the plurality of sacrificial films are sacrificial films that are not removed in a replacement process in which a sacrificial film is removed and a gate electrode is formed; and a common source line tap wiring that is provided on the remaining sacrificial film stack structure, wherein the semiconductor memory device further includes an intermediate insulating film that penetrates through the substrate and is superposed with a portion of the remaining sacrificial film stack structure, and the common source line is spaced apart from the remaining sacrificial film stack structure in a first direction, the substrate being interposed between the common source line and the remaining sacrificial film stack structure, wherein the semiconductor memory device further includes a second through-hole that penetrates through the substrate, the remaining sacrificial film stack structure, and is spaced apart from the intermediate insulating film in the horizontal direction, and wherein the second through-hole is electrically connected to the common source line tap wiring and the common source line.

15. The semiconductor memory device according to claim 14, the intermediate insulating film penetrating through the common source line.

16. The semiconductor memory device according to claim 15, the semiconductor memory device further comprising: a peripheral circuit region disposed under the common source line and having a peripheral transistor formed therein; and a first through-hole electrically connected to the peripheral transistor and penetrating through the remaining sacrificial film stack structure and the intermediate insulating film.

17. The semiconductor memory device according to claim 14, the semiconductor memory device further comprising a third through-hole that extends in the vertical direction and is in contact with a portion of the common source line tap wiring.

18. A semiconductor memory device, the semiconductor memory device comprising: a common source line provided on an insulating layer; a substrate superposed with the common source line; a gate electrode stack provided on the substrate; ​ a sacrificial film structure disposed on the substrate, wherein the sacrificial film structure includes a sacrificial film that is not removed in a replacement process in which the sacrificial film is removed and a gate electrode is formed, the gate electrode stack being disposed on opposite sides of the sacrificial film structure; a common source line tap wiring disposed on the sacrificial film structure, a first via that penetrates the sacrificial film structure and electrically connects to the transistor; and a second via that penetrates the sacrificial film structure and the substrate and contacts the common source line, wherein the semiconductor memory device further includes an intermediate insulating film that penetrates through the substrate and is superposed with the sacrificial film structure, wherein the second via is spaced apart from the intermediate insulating film in a horizontal direction, and wherein the second via is electrically connected to the common source line tap wiring.

19. The semiconductor memory device of claim 18, wherein, The common source line is planar.

20. The semiconductor memory device of claim 18, wherein, The second via penetrates the substrate.

21. The semiconductor memory device of claim 18, wherein, The first via penetrates an insulating film between openings in the common source line. The second via penetrates the substrate. The first via penetrates an insulating film between openings in the common source line.

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