Printed Circuit Board

Abstract

The present disclosure provides a printed circuit board, comprising: an insulating material including a cavity formed in the insulating material; a first electronic component disposed in the cavity and including a groove; and a second electronic component disposed in the groove of the first electronic component.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2018-0163382, filed on Dec. 17, 2018, the disclosure of which is incorporated herein by reference in its entirety for all purposes. Technical Field

[0002] The following description relates to a printed circuit board. Background Art

[0003] The amount of data managed by electronic devices increases to implement various functions of electronic devices. As a result, the electronic components required in electronic devices have become various and are increasing in number. As the number of electronic components included in electronic devices increases, the number of necessary passive components may also increase. Summary of the invention

[0004] This summary is provided to introduce selected concepts in a simplified form and further describe the concepts in the following detailed description. This summary is neither intended to define key features or essential features of the claimed subject matter nor to be used as an aid in determining the scope of the claimed subject matter.

[0005] In one general aspect, a printed circuit board includes: an insulating material including a cavity formed in the insulating material; a first electronic component disposed in the cavity and including a slot; and a second electronic component disposed in the slot of the first electronic component.

[0006] The first electronic component may include a dielectric layer and an insulating layer, the internal electrode is formed in the dielectric layer, the insulating layer is laminated on the dielectric layer, and the groove may pass through at least a portion of the insulating layer.

[0007] The groove may expose a surface of the dielectric layer.

[0008] The groove may pass through a portion of the insulating layer.

[0009] The first electronic component may include a pair of external electrodes disposed on a surface of the first electronic component and a width of the groove may be equal to or smaller than a distance between the pair of external electrodes.

[0010] The external electrode and the groove may not overlap in a thickness direction of the printed circuit board.

[0011] The printed circuit board may include an adhesive member attached to the second electronic component and disposed on a bottom surface of the groove.

[0012] The adhesive member may correspond to an external electrode of the second electronic component.

[0013] The thickness of the first electronic component may be greater than the thickness of the second electronic component.

[0014] The thickness of the second electronic component may be equal to or greater than the thickness of the groove.

[0015] A surface of the second electronic component may protrude from a surface of the insulating material.

[0016] The insulating material may include a first layer in which the cavity is formed, and a second layer laminated on the first layer, and the first electronic element may contact a surface of the second layer.

[0017] The printed circuit board may include a build-up layer laminated on the insulating material and filling the cavity.

[0018] The printed circuit board may include: a first via hole penetrating the build-up layer and electrically connected to the first electronic component; and a second via hole penetrating the build-up layer and electrically connected to the second electronic component.

[0019] A thickness of the first via hole may be greater than a thickness of the second via hole.

[0020] The printed circuit board may include: a filling layer filling the cavity; and a build-up layer laminated on the filling layer and the insulating material.

[0021] The printed circuit board may include: a circuit disposed on the filling layer; and a via hole penetrating the filling layer and configured to electrically connect the circuit to the first electronic component or the second electronic component.

[0022] The printed circuit board may include a through via hole penetrating the insulating material in a thickness direction of the printed circuit board.

[0023] The second electronic component may include a plurality of electronic components.

[0024] Other features and aspects will be apparent from the following detailed description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a diagram illustrating a printed circuit board according to an example.

[0026] Figure 2 is a diagram illustrating a printed circuit board according to an example.

[0027] Figure 3 is a diagram illustrating a printed circuit board according to an example.

[0028] Figure 4 is a diagram illustrating a printed circuit board according to an example.

[0029] Figure 5 is a diagram illustrating a printed circuit board according to an example.

[0030] Figure 6 is a diagram illustrating a printed circuit board according to an example.

[0031] Figure 7 is a diagram illustrating a printed circuit board according to an example.

[0032] Figure 8 is a diagram illustrating a printed circuit board according to an example.

[0033] Fig. 9 is a diagram showing the arrangement of a first electronic component and a second electronic component.

[0034] Fig.10 is a diagram illustrating a method for manufacturing a first electronic component.

[0035] Fig.11 is shown for manufacturing Figure 1 Schematic diagram of a method for printing a circuit board.

[0036] Fig.12 is shown for manufacturing Figure 8 Schematic diagram of a method for printing a circuit board.

[0037] Fig.13 and Fig.14 is a diagram illustrating a package using a printed circuit board according to an example.

[0038] In all drawings and detailed description, the same reference numerals refer to the same elements. The drawings may not be drawn to scale, and the relative sizes, proportions, and depictions of the elements in the drawings may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0039] The following specific embodiments are provided to help the reader gain a comprehensive understanding of the methods, devices and / or systems described herein. However, after understanding the disclosure of the present application, various changes, modifications and equivalents of the methods, devices and / or systems described herein will be apparent. For example, the order of operations described herein is merely an example, and is not limited to the order set forth herein, but in addition to the operations that must occur in a particular order, changes that will be apparent after understanding the disclosure of the present application may be made. In addition, in order to improve clarity and brevity, descriptions of features known in the art may be omitted.

[0040] The features described herein may be implemented in different forms and will not be interpreted as being limited by the examples described herein. Rather, the examples described herein are provided only to illustrate some of the many possible ways of implementing the methods, devices and / or systems described herein that will be apparent after understanding the disclosure of the present application.

[0041] Here, note that the use of the term "may" with respect to an example or embodiment (e.g., with respect to what an example or embodiment may include or implement) means that there is at least one example or embodiment that includes or implements such features, but all examples and embodiments are not limited thereto.

[0042] Throughout the specification, when an element such as a layer, a region, or a substrate is described as being “located”, “connected to”, or “coupled to” another element, the element may be directly “located”, “connected to”, or “coupled to” another element, or one or more other elements may be present in between. In contrast, when an element is described as being “directly located”, “directly connected to”, or “directly coupled to” another element, there may be no other elements in between.

[0043] As used herein, the term "and / or" includes any one and any combination of any two or more of the associated listed items.

[0044] Although terms such as "first," "second," and "third" may be used herein to describe various members, components, regions, layers, or portions, these members, components, regions, layers, or portions are not limited by these terms. Rather, these terms are only used to distinguish one member, component, region, layer, or portion from another member, component, region, layer, or portion. Thus, without departing from the teachings of the examples described herein, a first member, component, region, layer, or portion referred to may also be referred to as a second member, component, region, layer, or portion.

[0045] For ease of description, spatially relative terms such as "above", "on", "below", and "below" may be used herein to describe the relationship of one element to another element as shown in the drawings. These spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientations depicted in the drawings. For example, if the device in the drawings is flipped, an element described as being "above" or "on" relative to another element will then be "below" or "below" relative to the other element. Thus, the term "above" includes both above and below orientations depending on the spatial orientation of the device. The device may also be positioned in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative terms used herein will be interpreted accordingly.

[0046] The terms used herein are only used to describe various examples and are not used to limit the present disclosure. Unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. The terms "comprise", "include" and "have" list the existence of the stated features, quantities, operations, components, elements and / or their combinations, but do not exclude the existence or addition of one or more other features, quantities, operations, components, elements and / or their combinations.

[0047] Due to manufacturing techniques and / or tolerances, the shapes shown in the drawings may vary. Therefore, the examples described herein are not limited to the specific shapes shown in the drawings, but include changes in shapes that occur during manufacturing.

[0048] The features of the examples described herein can be combined in various ways that will be apparent after understanding the disclosure of the present application. In addition, although the examples described herein have various configurations, other configurations that will be apparent after understanding the disclosure of the present application are also feasible.

[0049] Figure 1 is a diagram illustrating a printed circuit board according to an example.

[0050] Reference Figure 1 The printed circuit board includes an insulating material 100 , a first electronic component 200 , and a second electronic component 300 .

[0051] The insulating material 100 is a plate-like structure made of a non-conductive material. The insulating material 100 may be made of a material including a resin, and the resin included in the insulating material 100 may be selected from various thermosetting resins, thermoplastic resins, and the like such as epoxy resin, polyimide (PI) resin, BT resin, liquid crystal polymer (LCP), and the like. However, the material of the insulating material 100 is not limited thereto. Specifically, the insulating material 100 may be a prepreg (PPG) or an ABF film.

[0052] The insulating material 100 may include a fiber-reinforced material (e.g., a prepreg) or a filler. The fiber-reinforced material may include a glass material, and the glass material may be at least one of glass filaments, glass fibers, and glass fabrics classified according to thickness. The prepreg may have a structure in which epoxy resin is immersed in the glass material. The filler may be an inorganic filler or an organic filler.

[0053] The inorganic filler can be at least one selected from silica (SiO2), alumina (Al2O3), silicon carbide (SiC), barium sulfate (BaSO4), talc, clay, mica powder, aluminum hydroxide (Al(OH)3), magnesium hydroxide (Mg(OH)2), calcium carbonate (CaCO3), magnesium carbonate (MgCO3), magnesium oxide (MgO), boron nitride (BN), aluminum borate (AlBO3), barium titanate (BaTiO3) and calcium zirconate (CaZrO3).

[0054] The insulating material 100 has a cavity 110. That is, the cavity 110 opened to the upper surface of the insulating material 100 is formed in the insulating material 100. The cavity 110 may be open to the upper surface of the insulating material 100, but may not be open to the side surface of the insulating material 100. The cavity 110 may partially pass through the insulating material 100 in the thickness direction instead of passing through the entire insulating material 100. The cavity 110 may have a rectangular parallelepiped shape.

[0055] The first electronic component 200 may be located in the cavity 110 and may contact the bottom surface of the cavity 110. The first electronic component 200 may be a passive device such as a capacitor. In this case, the first electronic component 200 may be a multilayer ceramic capacitor (MLCC).

[0056] The first electronic component 200 may include: a dielectric layer 210, including an inner electrode 211 ( Fig.10 The groove 221 may be formed on the upper surface of the first electronic element 200; an insulating layer 220 stacked on the dielectric layer 210; and an external electrode 230.

[0057] The dielectric layer 210 may be formed using a ceramic material. The internal electrode 211 is formed in the dielectric layer 210. The dielectric layer 210 may be formed by repeatedly laminating dielectric sheets and the internal electrode 211 alternately. The dielectric sheet may be a ceramic sheet. The internal electrode 211 may be formed using a material including a metal such as nickel (Ni). The internal electrode 211 may be cured after applying the nickel paste. The internal electrode 211 may include a positive electrode and a negative electrode.

[0058] The insulating layer 220 may be laminated on the dielectric layer 210 and may be formed using a material including a resin such as epoxy resin. The thickness of the insulating layer 220 is smaller than that of the dielectric layer 210.

[0059] Grooves 221 may be formed in the insulating layer 220. Figure 1 As shown in , the groove 221 may be formed at the center of the insulating layer 220 , and the upper surface of the dielectric layer 210 may be exposed through the groove 221 .

[0060] A pair of external electrodes 230 may be formed to cover the dielectric layer 210 and the insulating layer 220, and may be electrically connected to the internal electrode 211. When the internal electrode 211 includes a positive electrode and a negative electrode, one of the pair of external electrodes 230 may be connected to the internal electrode 211 being the positive electrode, and the other of the pair of external electrodes 230 may be connected to the internal electrode 211 being the negative electrode. The external electrodes 230 electrically connect the first electronic component 200 to an external structure.

[0061] The pair of external electrodes 230 may be spaced apart from each other. The pair of external electrodes 230 may be located at both ends of the first electronic component 200 to cover an upper surface of the insulating layer 220 , a side surface of the dielectric layer 210 , and a bottom surface of the dielectric layer 210 .

[0062] The width of the groove 221 in the insulating layer 220 may be the same as the distance between the pair of external electrodes 230 , and the external electrode 230 may not cover the groove 221 .

[0063] Fig.10 is a diagram illustrating a method for manufacturing a first electronic component.

[0064] Reference Fig.10 , a dielectric layer 210 is provided by repeatedly and alternately laminating dielectric sheets and internal electrodes. Here, the dielectric layer 210 may be sintered. A plurality of internal electrodes 211 are arranged to be vertically spaced apart from each other. A portion of the plurality of internal electrodes 211 is exposed to one side surface of the dielectric layer 210 to serve as a positive electrode, and the remaining portion of the plurality of internal electrodes 211 is exposed to the other side surface of the dielectric layer 210 to form a negative electrode.

[0065] Reference Fig.10 In FIG. 2( b ), an insulating layer 220 is formed on the dielectric layer 210 .

[0066] Reference Fig.10 As shown in FIG. 2( c ), a groove 221 is formed in the insulating layer 220. The groove 221 of the insulating layer 220 can be formed by laser processing, photolithography, or the like.

[0067] Reference Fig.10 As shown in FIG. 2(d), a pair of external electrodes 230 are formed to surround the upper surface of the insulating layer 220, the side surface of the dielectric layer 210, and the lower surface of the dielectric layer 210. One of the pair of external electrodes 230 contacts the positive electrode, and the other of the pair of external electrodes 230 contacts the negative electrode. The external electrodes 230 do not cover the grooves 221.

[0068] Return to reference Figure 1, the second electronic component 300 is located in the cavity 110 and contacts the first electronic component 200. The second electronic component 300 may be inserted into the groove 221 and formed on the upper surface of the first electronic component 200 or formed adjacent to the upper surface of the first electronic component 200.

[0069] The second electronic component 300 may be a passive device such as a capacitor. The second electronic component 300 may be a multilayer ceramic capacitor (MLCC). The second electronic component 300 may include a dielectric layer 310 including an inner electrode therein and an outer electrode 320 formed on a surface of the dielectric layer 310 to be electrically connected to the inner electrode.

[0070] When the groove 221 is formed in the insulating layer 220 of the first electronic component 200, the second electronic component 300 may be inserted into the groove 221 of the insulating layer 220. The lower portion of the second electronic component 300 may be surrounded by the insulating layer 220. The thickness of the second electronic component 300 may be equal to or greater than the thickness of the groove 221. The upper surface of the second electronic component 300 may protrude from the upper surface of the first electronic component 200, but may not protrude from the upper surface of the cavity 110. The upper surface of the second electronic component 300 may be located on the same plane as the upper surface of the insulating material 100 and the upper surface of the cavity 110.

[0071] The second electronic component 300 may not contact the external electrode 230 of the first electronic component 200. Specifically, the external electrode 320 of the second electronic component 300 is spaced or isolated from the external electrode 230 of the first electronic component 200.

[0072] The size of the second electronic component 300 may be smaller than the size of the first electronic component 200. Specifically, the thickness of the second electronic component 300 may be smaller than the thickness of the first electronic component 200. The width of the second electronic component 300 may be smaller than the width of the first electronic component 200. The width of the second electronic component 300 may be smaller than the width of the groove 221 of the insulating layer 220.

[0073] The adhesive member Ad may be formed on the bottom surface of the groove 221 of the first electronic component 200 to contact the second electronic component 300. Figure 1 As shown in , when the dielectric layer 210 of the first electronic component 200 is exposed through the groove 221 of the insulating layer 220, the adhesive member Ad is formed on the upper surface of the dielectric layer 210 of the first electronic component 200. The adhesive member Ad may be formed to correspond to the area of ​​the lower surface of the second electronic component 300. The adhesive member Ad may be formed using a non-conductive material having adhesiveness.

[0074] Fig. 9is a diagram showing the arrangement of a first electronic component 200 and a second electronic component 300. The first electronic component 200 and the second electronic component 300 are passive components having the same structure, and each of the first electronic component 200 and the second electronic component 300 has a pair of external electrodes at both ends thereof. In each electronic component, a line connecting a pair of external electrodes is called an external electrode connection line.

[0075] like Fig. 9 As shown in FIG. 1 (a), the external electrode connection line of the first electronic component 200 may be perpendicular to the external electrode connection line of the second electronic component 300. This arrangement is feasible when the long width of the second electronic component 300 is smaller than the short width of the first electronic component 200. Fig. 9 In Figure (a), the circular mark on the external electrode is the contact portion of the first via hole V1 or the second via hole V2.

[0076] like Fig. 9 As shown in FIG. 2( b ), the external electrode connection lines of the first electronic component 200 may be located on the same plane as the external electrode connection lines of the second electronic component 300 and the external electrode connection lines of the first electronic component 200 may be parallel to the external electrode connection lines of the second electronic component 300 .

[0077] like Fig. 9 As shown in FIG. 2( c ), the external electrode connection lines of the first electronic component 200 may be positioned to be inclined with respect to the external electrode connection lines of the second electronic component 300 .

[0078] like Fig. 9 Figure (d) to Fig. 9 As shown in FIG. (f) in FIG. 2 , the second electronic component 300 may be formed in plurality. That is, a plurality of second electronic components 300 may be located on one first electronic component 200. In this case, a plurality of second electronic components 300 are inserted into one slot 221 of the first electronic component 200. Alternatively, the slot 221 of the first electronic component 200 may be formed in plurality to correspond to the plurality of second electronic components 300. The second electronic component 300 may be formed in three or more.

[0079] The size of the first electronic component 200 and the second electronic component 300 may be determined according to the size of the first electronic component 200 and the second electronic component 300. Fig. 9 Figure (a) to Fig. 9 FIG. 5 shows an arrangement of the first electronic component 200 and the second electronic component 300 in FIG. 5 (f).

[0080] The printed circuit board may also include a build-up layer, circuits, internal vias IV, through vias PV, etc. (see Fig.13 and Fig.14 ).

[0081] The accumulation layer may be formed on the upper surface and / or the lower surface of the insulating material 100 and made of a material including a resin. The resin included in the accumulation layer may be at least one selected from a thermosetting resin, a thermoplastic resin, etc., specifically, may be at least one selected from an epoxy resin, a polyimide (PI) resin, a BT resin, a liquid crystal polymer (LCP), etc. However, the material of the accumulation layer is not limited thereto.

[0082] The build-up layer may include a fiber reinforcement material or a filler. As a specific build-up layer, prepreg (PPG) and ABF film may be used. The build-up layer may be made of a material that is the same as or different from that of the insulating material 100.

[0083] The build-up layer positioned on the upper surface of the insulating material 100 may be referred to as a first build-up layer 410 , and the build-up layer positioned on the lower surface of the insulating material 100 may be referred to as a second build-up layer 420 .

[0084] The first accumulation layer 410 may be stacked on the upper surface of the insulating material 100 and may fill the cavity 110. Filling the inside of the cavity 110 means that after the first electronic component 200 and the second electronic component 300 are inserted into the cavity 110, the remaining space of the cavity 110 is filled with the first accumulation layer 410. By filling the cavity 110 with the first accumulation layer 410, the first electronic component 200 and the second electronic component 300 may be fixed.

[0085] Second buildup layer 420 may be laminated on the lower surface of insulating material 100 and have the same thickness as a portion of first buildup layer 410 located on the upper surface of insulating material 100. Each of first buildup layer 410 and second buildup layer 420 may be formed thinner than insulating material 100.

[0086] The circuit provides a path for transmitting an electrical signal, and is formed using at least one selected from copper, silver, palladium, aluminum, nickel, titanium, gold, and platinum.

[0087] The circuit formed on the upper surface of the insulating material 100 may be referred to as a first circuit C1, and the circuit formed on the upper surface of the first accumulation layer 410 may be referred to as a second circuit C2. After the first circuit C1 is formed on the upper surface of the insulating material 100, the first accumulation layer 410 is formed on the insulating material 100 and the second circuit C2 is formed on the first accumulation layer 410. A portion of the second circuit C2 may be located on the upper surface of the first electronic component 200 and the upper surface of the second electronic component 300.

[0088] The first circuit C1 and the second circuit C2 may be electrically connected through the internal via IV. The second circuit C2 and the first electronic component 200 may be electrically connected through the first via V1, and the first via V1 may pass through the first accumulation layer 410 to contact the external electrode 230 of the first electronic component 200. The second circuit C2 and the second electronic component 300 may be electrically connected through the second via V2, and the second via V2 may pass through the first accumulation layer 410 to contact the external electrode 320 of the second electronic component 300. The thickness of the first via V1 may be greater than the thickness of the second via V2. A portion of the first via V1 may be located inside the cavity 110.

[0089] The circuit formed on the lower surface of the insulating material 100 may be referred to as a third circuit C3, and the circuit formed on the lower surface of the second accumulation layer 420 may be referred to as a fourth circuit C4. The third circuit C3 and the fourth circuit C4 may be electrically connected through the internal via IV. Figure 1 All of the first to fourth circuits C1 to C4 are shown in FIG. 1 , but some of them may be omitted if necessary.

[0090] like Fig.13 As shown in , the through via PV passes through the insulating material 100 to electrically connect the first circuit C1 and the third circuit C3.

[0091] Each of the first via V1, the second via V2, the internal via IV, and the through via PV may be formed using at least one material selected from copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), and platinum (Pt), and may be formed using the same metal as the circuit.

[0092] Figures 2 to 8 2 is a diagram showing various examples of printed circuit boards. Hereinafter, in the description of various printed circuit boards, description of contents overlapping with those of the above-mentioned printed circuit boards may be omitted.

[0093] Reference Figure 2 , the printed circuit board includes Figure 1 The insulating material 100 , the first electronic component 200 , and the second electronic component 300 of the printed circuit board are the same as the insulating material 100 , the first electronic component 200 , and the second electronic component 300 .

[0094] In this example, the printed circuit board includes a filling layer 120 that fills the cavity 110, instead of filling the cavity with the first build-up layer 410. The first build-up layer 410 is formed on the upper surface of the insulating material 100 and the upper surface of the filling layer 120. The filling layer 120 may be formed using the same material as the first build-up layer 410 and may not be integrated with the first build-up layer 410 to form a bonding interface. The filling layer 120 may also be formed using a material different from that of the first build-up layer 410. The first electronic component 200 and the second electronic component 300 may be fixed by the filling layer 120.

[0095] The total height of the first electronic component 200 and the second electronic component 300 may be less than the height of the cavity 110. An upper surface of the second electronic component 300 may be positioned lower than an upper surface of the insulating material 100.

[0096] The first circuit C1 is formed on the upper surface of the insulating material 100 and the upper surface of the filling layer 120, and the first circuit C1 is electrically connected to the first electronic component 200 and / or the second electronic component 300. That is, the via V1' connecting the first circuit C1 and the first electronic component 200 may pass through the filling layer 120 to contact the external electrode 230 of the first electronic component 200. The via V2' connecting the first circuit C1 and the second electronic component 300 may pass through the filling layer 120 to contact the external electrode 320 of the second electronic component 300. The via V1' for connecting the first circuit C1 to the first electronic component 200 and the via V2' for connecting the first circuit C1 to the second electronic component 300 are all formed inside the cavity 110. The thickness of the via V1' connecting the first circuit C1 and the first electronic component 200 may be greater than the thickness of the via V2' connecting the first circuit C1 and the second electronic component 300.

[0097] The first circuit C1 and the second circuit C2 may be electrically connected through the internal via IV. The internal via IV may have a stacked via structure with the via V1' connecting the first circuit C1 and the first electronic component 200. The internal via IV may also have a stacked via structure with the via V2' connecting the first circuit C1 and the second electronic component 300.

[0098] Reference Figure 3 The printed circuit board includes an insulating material 100 , a first electronic component 200 , and a second electronic component 300 , wherein the first electronic component 200 includes a dielectric layer 210 , an insulating layer 220 , and an external electrode 230 , and the insulating layer 220 has a groove 221 formed therein.

[0099] In this example, with Figure 1Unlike a printed circuit board of a semiconductor device, the width of the groove 221 is smaller than the distance between the pair of external electrodes 230. The groove 221 may be formed at a central portion between the pair of external electrodes 230. The width of the groove 221 may be the same as the width of the second electronic component 300. In this case, the surface of the second electronic component 300 (or the external electrode 320 of the second electronic component 300) may contact the insulating layer 220.

[0100] Reference Figure 4 The printed circuit board includes an insulating material 100 , a first electronic component 200 and a second electronic component 300 , wherein the first electronic component 200 includes a dielectric layer 210 , an insulating layer 220 and an external electrode 230 , wherein the insulating layer 220 has a groove 221 formed therein.

[0101] and Figure 1 Unlike the printed circuit board of FIG. 2 , the thickness of the groove 221 is less than the thickness of the insulating layer 220. In this example, the groove 221 passes through a portion of the thickness of the insulating layer 220. The upper surface of the dielectric layer 210 is not exposed through the bottom surface of the groove 221 and the insulating layer 220 is also formed on the bottom surface of the groove 221. The adhesive member Ad is formed on the insulating layer 220 located on the bottom surface of the groove 221. Here, the thickness of the groove 221 can be understood as the depth of the groove 221 in the stacking direction of the first electronic component 200 and the second electronic component 300.

[0102] Reference Figure 5 The printed circuit board includes an insulating material 100, a first electronic component 200 and a second electronic component 300, wherein the first electronic component 200 includes a dielectric layer 210, an insulating layer 220 and an external electrode 230, wherein the insulating layer 220 has a groove 221 formed therein, and an adhesive member Ad is formed on a bottom surface of the groove 221.

[0103] In this example, the area of ​​the bonding member Ad is smaller than Figure 1 The adhesive member Ad may be formed to have an area smaller than that of the lower surface of the second electronic component 300. The adhesive member Ad may be formed to correspond to the external electrode 320 located on the lower surface of the second electronic component 300.

[0104] Reference Figure 6 The printed circuit board includes an insulating material 100 , a first electronic component 200 , and a second electronic component 300 .

[0105] In this example, the thickness of the second electronic component 300 may be equal to or less than the thickness of the groove 221. The upper surface of the second electronic component 300 may be located below the upper surface of the first electronic component 200. Specifically, when the upper surface of the second electronic component 300 is located on the same plane as the upper surface of the first electronic component 200, the thickness of the first via hole V1 that electrically connects the second circuit C2 and the first electronic component 200 may be the same as the thickness of the second via hole V2 that electrically connects the second circuit C2 and the second electronic component 300. In addition, when the upper surface of the second electronic component 300 is located below the upper surface of the first electronic component 200, the thickness of the second via hole V2 may be greater than the thickness of the first via hole V1.

[0106] Reference Figure 7 The printed circuit board includes an insulating material 100 , a first electronic component 200 , and a second electronic component 300 .

[0107] In this example, the upper surface of the second electronic component 300 protrudes from the upper surface of the cavity 110. That is, the upper surface of the second electronic component 300 is positioned higher than the upper surface of the insulating material 100. In this case, the upper surface of the second electronic component 300 is positioned lower than the upper surface of the first accumulation layer 410. The thickness of the first via hole V1 is greater than the thickness of the second via hole V2 and a portion of the first via hole V1 is located inside the cavity 110, while the entire second via hole V2 is located above the cavity 110.

[0108] Reference Figure 8 The printed circuit board includes an insulating material 100, a first electronic component 200 and a second electronic component 300, wherein the insulating material 100 includes a plurality of layers.

[0109] The insulating material 100 may include a first layer 111 and a second layer 112. A cavity 110 is formed in the first layer 111 and the cavity 110 completely passes through the first layer 111 in a vertical direction. The second layer 112 is laminated below the first layer 111 to expose an upper surface of the second layer 112 through the cavity 110. That is, the first electronic component 200 contacts the upper surface of the second layer 112.

[0110] The insulating material 100 may include three or more layers. In this case, the cavity 110 may be formed only on one layer, and other layers may be sequentially stacked on the one layer. Other features except that the insulating layer 100 includes a plurality of layers are similar to those of the reference Figure 1 The other features described are the same.

[0111] Fig.11 is shown for manufacturing Figure 1 Schematic diagram of a method for printing a circuit board.

[0112] Reference Fig.11, a cavity 110 is formed in an insulating material 100. The cavity 110 passes through a portion of the insulating material 100. A first circuit C1 and a third circuit C3 may be formed on the upper surface and the lower surface of the insulating material 100, respectively.

[0113] Reference Fig.11 , the first electronic component 200 and the second electronic component 300 are inserted into the cavity 110. The first electronic component 200 is first inserted into the cavity 110, and then the second electronic component 300 is inserted into the groove 221 of the first electronic component 200. Alternatively, the first electronic component 200 and the second electronic component 300 may be inserted into the cavity 110 after the second electronic component 300 is inserted into the groove 221 of the first electronic component 200.

[0114] Reference Fig.11 In FIG. (c), the first accumulation layer 410 is stacked on the upper surface of the insulating material 100, and the first accumulation layer 410 can fill the cavity 110. A second circuit C2 is formed on the first accumulation layer 410. The second circuit C2 includes a first via V1 connecting the first electronic component 200 and the second circuit C2 and a second via V2 connecting the second electronic component 300 and the second circuit C2.

[0115] An internal via IV is formed in the first buildup layer 410 to connect the first circuit C1 and the second circuit C2. A second buildup layer 420 may be laminated on the lower surface of the insulating material 100. A fourth circuit C4 may be formed on the second buildup layer 420. An internal via IV is formed in the second buildup layer 420 to connect the third circuit C3 and the fourth circuit C4.

[0116] Fig.12 is shown for manufacturing Figure 8 Schematic diagram of a method for printing a circuit board.

[0117] Reference Fig.12 , a cavity 110 is formed in a first layer 111 of an insulating material 100, and a tape T is attached to the bottom surface of the first layer 111. The cavity 110 is covered by the tape T. A circuit may be formed on the upper surface of the first layer 111, but is not shown in the drawing.

[0118] Reference Fig.12 As shown in FIG. (b), the first electronic component 200 and the second electronic component 300 are inserted into the cavity 110. The first electronic component 200 is first inserted into the cavity 110, and then the second electronic component 300 is inserted into the groove 221 of the first electronic component 200. Optionally, the first electronic component 200 and the second electronic component 300 may be inserted into the cavity 110 after the second electronic component 300 is inserted into the groove 221 of the first electronic component 200. The tape T may support the first electronic component 200.

[0119] Reference Fig.12 In FIG. 1( c ), a first accumulation layer 410 including a metal layer 411 is stacked on the first layer 111 , and the first accumulation layer 410 may fill the inside of the cavity 110 .

[0120] Reference Fig.12 In FIG. 5( d ), the tape T is removed. After the tape T is removed, the first electronic component 200 and the second electronic component 300 may be fixed by the first build-up layer 410 .

[0121] Reference Fig.12 In FIG. (e), the second layer 112 is stacked below the first layer 111, and a second build-up layer 420 including a metal layer 421 is stacked on a lower surface of the second layer 112. Before the second build-up layer 420 is stacked on the bottom surface of the second layer 112, a circuit may be formed on the bottom surface of the second layer 112.

[0122] Reference Fig.12 , the metal layer 411 of the first build-up layer 410 is patterned to form a circuit C2, and the metal layer 421 of the second build-up layer 420 is also patterned to form a circuit C4.

[0123] Fig.13 and Fig.14 is a diagram illustrating a package using a printed circuit board according to an example.

[0124] Reference Fig.13 , the package may include a printed circuit board on which an electronic component is mounted and in which an electronic component is embedded. The electronic component mounted on the printed circuit board may be an active component (IC, etc.), and the first electronic component 200 and the second electronic component 300 embedded in the printed circuit board may be passive components. Each of the first electronic component 200 and the second electronic component 300 may be formed in plurality.

[0125] Although in reference Fig.13 and Fig.14 Use reference in the package Figure 1 printed circuit board, but can be used in Figures 2 to 8 Any printed circuit board according to various examples shown in .

[0126] Reference Fig.13, a first build-up layer 410 is stacked on the upper surface of the insulating material 100, a second build-up layer 420 is stacked on the lower surface of the insulating material 100, and a plurality of build-up layers 510 may be stacked on the first build-up layer 410, and a plurality of build-up layers 520 may be stacked below the second build-up layer 420. The number of build-up layers may be variously determined as needed. Solder resists 610 and 620 are stacked on the outermost build-up layer. Solder resists 610 and 620 partially expose the outermost circuits CA and CB.

[0127] The electronic component E may be mounted in a flip-chip manner on the outermost circuit CA exposed by the solder resist 610 using a solder member S such as solder. An underfill U may be formed in a gap between the electronic component E and the printed circuit board due to the height of the solder member S. The electronic component E may be a CPU, but is not limited thereto.

[0128] like Fig.14 As shown in FIG. 1 , a package may include an interposer 1. The interposer 1 is mounted on a printed circuit board, and an underfill U may be formed in a gap below the interposer 1.

[0129] The interposer 1 is mounted on the outermost circuit CA exposed by the solder resist 610 using a solder member S such as solder, and a plurality of electronic components E1 and E2 are mounted on the interposer 1 by means of a solder member S such as solder. The interposer 1 may be formed using a silicon material. The electronic component E1 may be an application specific integrated circuit (ASIC), a graphics processing unit (GPU), etc., and the electronic component E2 may be a high bandwidth memory (HBM), but is not limited thereto. On the other hand, the plurality of electronic components E1 and E2 may be integrally molded on the interposer 1 by means of a molding material M such as an epoxy molding compound (EMC).

[0130] If a printed circuit board having such electronic components is used, parasitic inductance and impedance can be reduced, and power integrity can be improved because the distance between the electronic components and the electronic components is reduced. In addition, since the electronic components are embedded in the printed circuit board, the space occupied by the electronic components located on the printed circuit board can be increased. The overall thickness of the package can also be reduced.

[0131] Although the present disclosure includes specific examples, it will be apparent after understanding the disclosure of the present application that various changes in form and detail may be made to these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein will be understood only as descriptive, and not for limiting purposes. The description of the features or aspects in each example will be considered applicable to similar features or aspects in other examples. If the described techniques are performed in a different order, and / or if the components in the described system, architecture, device or circuit are replaced or added in a different manner and / or by other components or their equivalents, suitable results may be obtained. Therefore, the scope of the present disclosure is not limited by specific embodiments but by claims and their equivalents, and all variations within the scope of the claims and their equivalents will be understood to be included in the present disclosure.

Claims

1. A printed circuit board, comprising: an insulating material, including a cavity formed in the insulating material; a first electronic component disposed in the cavity, comprising a dielectric layer, an insulating layer, and an external electrode, wherein the insulating layer is disposed on an upper surface of the dielectric layer, the external electrode is disposed on a side surface of the dielectric layer and extends to the upper surface of the insulating layer, so that at least a portion of the insulating layer is disposed between the upper surface of the dielectric layer and the external electrode, and the first electronic component is provided with a groove, the groove passing through at least a portion of the insulating layer; a second electronic component disposed in the groove of the first electronic component; a build-up layer laminated on the insulating material and filling the cavity; a first via hole passing through the build-up layer and electrically connected to the first electronic component; as well as a second via hole passing through the build-up layer and electrically connected to the second electronic component, and Wherein, the thickness of the first via hole is greater than the thickness of the second via hole.

2. The printed circuit board according to claim 1, wherein: The first electronic component also includes an internal electrode formed in the dielectric layer.

3. The printed circuit board according to claim 2, wherein: The groove exposes the upper surface of the dielectric layer.

4. The printed circuit board according to claim 2, wherein: The groove passes through a portion of the insulating layer.

5. The printed circuit board according to claim 2, wherein: The first electronic component includes a pair of external electrodes, the pair of external electrodes are disposed on a surface of the first electronic component and the width of the groove is equal to or smaller than a distance between the pair of external electrodes.

6. The printed circuit board according to claim 5, wherein: The external electrode and the groove do not overlap in a thickness direction of the printed circuit board. 7 . The printed circuit board of claim 1 , further comprising an adhesive member attached to the second electronic component and disposed on a bottom surface of the groove.

8. The printed circuit board according to claim 7, wherein: The bonding member corresponds to the external electrode of the second electronic component.

9. The printed circuit board according to claim 1, wherein: The thickness of the first electronic component is greater than the thickness of the second electronic component.

10. The printed circuit board according to claim 9, wherein: The thickness of the second electronic component is equal to or greater than the thickness of the groove.

11. The printed circuit board according to claim 1, wherein: A surface of the second electronic component protrudes from a surface of the insulating material.

12. The printed circuit board according to claim 1, wherein: The insulating material includes: a first layer in which the cavity is formed; and a second layer laminated on the first layer, wherein the first electronic component is in contact with a surface of the second layer. 13 . The printed circuit board according to claim 1 , further comprising a through via hole penetrating the insulating material in a thickness direction of the printed circuit board.

14. The printed circuit board according to claim 1, wherein: The second electronic component includes a plurality of electronic components.

15. The printed circuit board according to claim 1, wherein The first electronic component is a first capacitor, and the second electronic component is a second capacitor.

16. The printed circuit board according to claim 15, wherein The first capacitor is a first multilayer ceramic capacitor, and the second capacitor is a second multilayer ceramic capacitor.

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