A trimming circuit

Abstract

The present invention provides a trimming circuit, which is applied to an integrated circuit with a power supply terminal (VCC), a ground terminal (GND), an input voltage port IN1, and an input voltage port IN2, and includes a test mode circuit and an efuse circuit. The test mode circuit is used to test the integrated circuit operating parameters; the efuse circuit is used for internal repair of the integrated circuit, and the test mode circuit outputs a test signal and then outputs a trimming signal after being processed by the efuse circuit. This trimming circuit adds an efuse circuit on the basis of the test circuit, performs complex and regular excitation on several input pins of the chip, causes the chip to enter the trimming circuit mode, and then burns the efuse. Compared with the direct probe needle burning before packaging, the test complexity and test cost have great advantages, and the chip packaging size and production cost are reduced.

Description

Technical Field

[0001] The invention relates to the field of integrated circuit chip testing, and in particular to a trimming circuit. Background Art

[0002] With the advancement of semiconductor process technology, device size is getting smaller and smaller, circuit complexity is getting higher and higher, and semiconductors are becoming more susceptible to impurities or defects, because the failure of a metal wire, a resistor, or a MOS tube will cause the failure of the entire chip. This directly leads to a decrease in chip manufacturing yield, which greatly increases the cost of a single chip after mass production. Therefore, how to improve chip yield and reduce chip failure is becoming more and more important.

[0003] Fuses have always been key components used to repair circuits. Traditionally, most chip manufacturers have adopted laser-fuse technology, which burns out fuses by emitting lasers of a fixed duration and intensity (empirical values ​​obtained through a large number of tests).

[0004] With the development of semiconductor technology, laser-fuse technology has several defects:

[0005] 1. The improvement of technology has not made the size of laser fuse smaller. The size of laser depends on the size of laser beam spot. Secondly, in order to protect the surrounding devices from being damaged, laser fuse and surrounding devices must maintain a certain distance. Therefore, laser fuse has not enjoyed the dividend brought by technological progress. On the contrary, the size of electric fuse has become smaller with the advancement of technology.

[0006] 2. Laser-fuse burning requires a special laser machine and corresponding testing process. The testing process is divided into two rounds of testing: the first round of high-temperature testing and the second round of low-temperature testing. Both rounds of testing require before-and-after comparisons to determine whether the burning is successful. The burning process is also prone to cause storage unit failure. The complexity of the process and high-frequency failures have resulted in low test efficiency and test success rate, resulting in an increase in test costs. Summary of the invention

[0007] The present invention provides a trimming circuit, which is applied to an integrated circuit with a power supply terminal (VCC), a ground terminal (GND), an input voltage port IN1, and an input voltage port IN2, and comprises a test mode circuit and an efuse circuit. The test mode circuit is used to test the integrated circuit operation parameters; the efuse circuit is used for internal repair of the integrated circuit, and the test mode circuit outputs a test signal and then outputs a trimming signal after being processed by the efuse circuit.

[0008] This type of trimming circuit adds an efuse circuit on the basis of the test circuit, excites several input pins of the chip in a complex and regular manner, puts the chip into the trimming circuit mode, and then burns the efuse. Compared with the probe needle burning before direct packaging, it has great advantages in test complexity and test cost, and reduces the chip packaging size and production cost.

[0009] Preferably, the efuse circuit uses poly efuse (polycrystalline silicon fuse). Compared with the traditional metal fuse, poly efuse does not need to open a window in the passivation layer to accelerate the diffusion of the fuse material after burning, because polyefuse uses the high temperature when the current flows to cause the melting of silicide, which has relatively little destructive power, does not generate much heat, and has little effect on the surrounding circuits.

[0010] Further, the test mode circuit includes an SR latch 1, a counter, a serial / parallel unit, and an SR latch 2. The input end of the SR latch 1 is respectively connected to the comparator CMP1 and the comparator CMP2, and the input ends of the comparator CMP1 and the comparator CMP2 are respectively connected to the integrated circuit power supply end (VCC) and the input voltage port IN1; the input end of the counter is connected to the output end of the SR latch 1, and the output end of the counter is connected to the serial / parallel unit input end, and finally outputs a counting signal; the SR latch 2 receives the signal calculated by the comparator CMP1 and the comparator CMP3 through the AND gate and1, and the output signal of the SR latch 2 and the output signal of the comparator CMP2 are output after calculation by the NOR gate nor, and the input end of the comparator CMP3 is respectively connected to the integrated circuit power supply end (VCC) and the input voltage port IN2.

[0011] Furthermore, the test mode circuit also includes a D flip-flop, which is connected to the comparator CMP4 via the AND gate and2, the trigger terminal of the D flip-flop is connected to the comparator CMP3, the other input terminal of the AND gate and2 is connected to the output signal of the NOR gate nor, the output signal of the D flip-flop and the output signal of the NOR gate nor are calculated and output by the AND gate and3, the input terminal of the comparator CMP4 is respectively connected to the input voltage port IN1 and the integrated circuit power supply terminal (VCC), and the output signal of the test mode circuit terminal is calculated and output by the serial / parallel unit output signal, the NOR gate nor, and the output signal of the AND gate and3 via the AND gate and4.

[0012] Furthermore, the serial / parallel unit is composed of logic elements.

[0013] The present invention further provides an integrated circuit, comprising a power supply terminal (VCC), a ground terminal (GND), an input voltage port IN1, an input voltage port IN2, and the trimming circuit according to any one of claims 1-5. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 Schematic diagram of integrated circuit in the embodiment

[0015] Figure 2 Schematic diagram of the circuit block diagram in the embodiment

[0016] Figure 3 Schematic diagram of the excitation signal applied to the chip pin in the embodiment

[0017] Figure 4 Schematic diagram of poly efuse circuit in the embodiment DETAILED DESCRIPTION

[0018] The specific implementation of the present invention will be further described below through specific examples in conjunction with the accompanying drawings.

[0019] Example:

[0020] like Figure 2 As shown, this embodiment describes a trimming circuit, which is mainly used in integrated circuits with a power supply terminal (VCC), a ground terminal (GND), an input voltage port IN1, and an input voltage port IN2, including a test mode circuit and an efuse circuit. The test mode circuit is used to test the operating parameters of the integrated circuit; the efuse circuit is used for internal repair of the integrated circuit, and the test mode circuit outputs a test signal and then processes the efuse circuit to output a trimming signal. In this embodiment, the efuse circuit uses poly efuse. Compared with the laser fusing technology, the electron migration characteristics of the electric fuse (efuse) can be used to generate a much smaller fuse structure. Whether it is the wafer-level CP test stage before the integrated circuit packaging or the FT test stage after the packaging, the chip is applied with an on-chip voltage (generally about 5V). A 20mA current lasting 1ms is sufficient to burn out a single poly efuse, thereby adjusting the parameters of certain technical indicators to achieve the purpose of repairing the chip.

[0021] By combining programming circuits, reading circuits, and poly efuse, the number of peripheral pins can be further reduced. Setting up redundant circuits for burning can also ensure the chip's operation after it has worked for a long time and aged.

[0022] In addition, poly efuse can also cut off or connect certain functional modules inside the chip at will without affecting the normal operation of other modules, thereby achieving some functional circuit verification work, or shutting down some problematic modules, thereby improving the product yield.

[0023] The test mode circuit includes SR latch 1, counter, serial / parallel unit, SR latch 2, comparators CMP1, CMP2, CMP3, CMP4, the input terminals of comparators CMP1, CMP2, CMP4 are respectively connected to the integrated circuit power supply terminal (VCC) and input voltage port IN1, and the input terminal of comparator CMP3 is respectively connected to the integrated circuit power supply terminal (VCC) and input voltage port IN2. The input terminals of SR latch 1 are respectively connected to comparators CMP1 and CMP2, and the output terminals thereof are connected to the input terminals of the counter, and the output terminals of the counter are connected to the input terminals of the serial / parallel unit, and finally the counting signal TM is output. <x>.

[0024] SR latch 2 receives the signals calculated by comparator CMP1 and comparator CMP3 through AND gate and1, and its output signal and the output signal of comparator CMP2 are output after being calculated by NOR gate nor.

[0025] The test mode circuit also includes a D flip-flop, which is connected to a comparator CMP4 via an AND gate and2, a trigger terminal of the D flip-flop is connected to a comparator CMP3, another input terminal of the AND gate and2 is connected to the output signal of the NOR gate nor, the output signal of the D flip-flop and the output signal of the NOR gate nor are calculated and output by the AND gate and3, the input terminal of the comparator CMP4 is respectively connected to an input voltage port IN1 and an integrated circuit power supply terminal (VCC), and the output signal of the test mode circuit terminal is calculated and output by the AND gate (and4) based on the output signal of the serial / parallel unit, the NOR gate (nor), and the output signal of the AND gate (and3).

[0026] Figure 1 The schematic diagram of an integrated circuit using the above-mentioned trimming circuit is shown in FIG.

[0027] (VCC), input voltage port IN1, input voltage port IN2, ground terminal (GND). The integrated circuit in this embodiment is preset with 12 test modes. Of course, in actual applications, other number of test modes can also be preset, which can be 1-12 or more. The following is an explanation of test mode setting and adjustment based on 12 test modes.

[0028] Figure 3 The schematic diagram of the excitation signal applied to the pin of the above integrated circuit is as follows. When the chip is tested, the chip is powered on, the power pin voltage rises from 0 to VCC, the SR latch 2 is reset, and the output is low; the input voltage port IN1 rises from 0 to VCC, the input voltage port IN2 rises from 0 to VCC+a, the output of the comparator CMP3 changes from low to high, and the output TM_OK of the SR latch 2 changes from low to high; the input voltage port IN1 rises from VCC to VCC+a, a is an empirical preset value, the output of the comparator CMP2 changes from low to high, the signal passes through the SR latch 1, the counter, and the serial / parallel unit, and finally the output TM1 (the first test mode) changes from low to high, and the TM1 test mode is entered, and the input voltage port IN2 decreases from VCC+a to 0; the input voltage port IN1 decreases from VCC+a to VCC-a, the output of the comparator CMP2 changes from high to low, the signal passes through the SR latch 1, the counter, and the serial / parallel circuit, so that the output changes from high to low, and the TM1 test mode is exited.

[0029] The input voltage port IN1 rises from VCC-a to VCC, and then to VCC+a. The output of comparator CMP2 changes from low to high. The signal passes through SR latch 1, counter, and serial / parallel unit, and finally outputs TM2 (the second test mode) from low to high, entering TM2 test mode.

[0030] Repeat the above test settings until the 12th test mode TM12 is completed and changes from low to high.

[0031] During adjustment, the input voltage port IN1 decreases from VCC+a to VCC+b, where b is an empirical preset value and can be set to any value according to the actual application. The output of the comparator CMP1 changes from high to low, the output of inv1 changes from low to high, and the output TM_OK of the NOR gate nor changes from high to low; at this time, the output of the AND gate and2 is high, and then the input voltage port IN2 increases from 0 to VCC+a, and the high level output of the AND gate and2 is transmitted to the output of the D flip-flop.

[0032] The input voltage port IN2 increases from VCC+b to VCC+a, the output of comparator CMP2 changes from low to high, the output of inv1 changes from high to low, TM_OK changes from low to high, and PF_OK, TM12 are also high, which eventually makes SEL6 change from low to high. (In the 7th test mode, SEL1=1, so in the 12th test mode, SEL6=1), SEL6 is the input signal of the efuse circuit, when the input voltage port IN1 decreases from VCC+a to 0, SEL6 changes from high to low, and the time when SEL6 maintains a high level is the programming time.

[0033] The circuit diagram of Poly efuse is as follows Figure 4 , the W / L of M1 and M2 is 1:1, and the W / L of M3 and M4 is 1:1. <6> =1 duration is about 1ms. During this time, M5 is turned on, and a 20mA current flows from the power supply end through the poly efuse and M5 to the ground. The resistance of the poly efuse will increase from 100ohm to 10Mohm. The resistance selected by R_REF only needs to be between 100ohm and 10Mohm. Assuming R_RES=20Kohm, before burning, R_RES>Refuse, the output PF of the comparator <x-6>= 0; After programming is complete, R_RES <Refuse, the output PF of the comparator <x-6>=1,PF <x-6>Complete the adjustment of technical parameters.

[0034] The above embodiments only list preferred specific technical solutions and technical means, and do not exclude other replacement forms of equivalent technical means that can solve the technical problem within the scope of the claims of the present invention, which should also be understood as the content required to be protected by the present invention. The size of the circuit components, the distance between the components, the number of test and adjustment modes used in the above embodiments are all for the convenience of public understanding and are used for illustration, and are not intended to limit the scope of protection of the present invention. < / x>

Claims

1. A trimming circuit, applied to an integrated circuit having a power supply terminal (VCC), a ground terminal (GND), a first input voltage port IN (1), and a second input voltage port IN (2), characterized in that: It includes a test mode circuit and an efuse circuit, wherein the test mode circuit is used to test the operating parameters of the integrated circuit; the efuse circuit is used for internal repair of the integrated circuit, and the test mode circuit outputs a test signal which is processed by the efuse circuit and then outputs a trimming signal; The test mode circuit comprises a first SR latch (1), a counter, a serial / parallel unit, a second SR latch (2), a first comparator CMP (1), a second comparator CMP (2), a third comparator CMP (3), a fourth comparator CMP (4) and a D flip-flop; The input terminals of the first comparator CMP(1), the second comparator CMP(2) and the fourth comparator CMP(4) are all connected to the first input voltage port IN(1) and the power supply terminal (VCC); the input terminals of the third comparator CMP(3) are respectively connected to the second input voltage port IN(2) and the power supply terminal (VCC); The output ends of the first comparator CMP (1) and the second comparator CMP (2) are both connected to the input end of the first SR latch (1); the input end of the counter is connected to the output end of the first SR latch (1), and the output end of the counter is connected to the input end of the serial / parallel unit; The second SR latch (2) receives the signal output by the first comparator CMP (1) and the third comparator CMP (3) and calculated by the first AND gate (and1) and the trigger signal (CHIP_ON), ​​the signal output by the second comparator CMP (2) is calculated by the first NOT gate (inv1) and then output, the signal output by the first NOT gate (inv1) and the signal output by the second SR latch (2) are calculated by the NOR gate (nor) and then output; The signal output by the NOR gate (nor) is calculated by the second NOT gate (inv2) and then output; The signal output by the second NOT gate (inv2) and the signal output by the fourth comparator CMP (4) are calculated by the second AND gate (and2) and then output; the input end of the D flip-flop is connected to the output end of the third comparator CMP (3) and the output end of the second AND gate (and2); the signal output by the NOR gate (nor) and the signal output by the D flip-flop are calculated by the third AND gate (and3) and then output; The signal output by the serial / parallel unit, the signal output by the NOR gate (nor) and the signal output by the third AND gate (and3) are calculated by a fourth AND gate (and4) to output the test signal.

2. The trimming circuit according to claim 1, characterized in that: The efuse circuit includes a polysilicon fuse.

3. The trimming circuit according to claim 1, characterized in that: The serial / parallel unit is composed of logic elements.

4. An integrated circuit, characterized in that: An integrated circuit comprising a power supply terminal (VCC), a ground terminal (GND), a first input voltage port IN1, a second input voltage port IN2, and a trimming circuit as claimed in any one of claims 1 to 3.

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