Semiconductor devices

Abstract

The present invention provides a novel semiconductor device. The back gate voltage of a transistor having a gate and a back gate is adjusted according to the operating temperature. The operating temperature is measured by a temperature detection circuit. The temperature detection circuit outputs the temperature information as a digital signal. The digital signal is input to a voltage control circuit. The voltage control circuit outputs a first voltage corresponding to the digital signal. The back gate voltage is determined by a voltage obtained by adding the first voltage to a reference voltage.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] In addition, one embodiment of the present invention relates to an object, a method or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a product or a composition of matter. One embodiment of the present invention relates to a driving method thereof or a manufacturing method thereof.

[0003] Note that in this specification, etc., a semiconductor device refers to any device that can operate by utilizing semiconductor characteristics. A memory device, a display device, an electro-optical device, a power storage device, a semiconductor circuit, and an electronic device may include a semiconductor device. Background Art

[0004] As semiconductor thin films that can be used for transistors, silicon-based semiconductor materials are widely known, and as other materials, oxide semiconductors (OS: Oxide Semiconductor) have attracted attention. As oxide semiconductors, for example, it is known that in addition to single metal oxides such as indium oxide and zinc oxide, there are also multinary metal oxides. Among multinary metal oxides, research on In-Ga-Zn oxide (hereinafter also referred to as IGZO) is particularly hot.

[0005] Through the study of IGZO, CAAC (c-axis aligned crystalline: c-axis oriented crystal) structure and nc (nanocrystalline: nanocrystalline) structure, which are neither single crystal nor amorphous, were discovered in oxide semiconductors (see non-patent documents 1 to 3). Non-patent documents 1 and 2 disclose a technology for manufacturing transistors using an oxide semiconductor having a CAAC structure. Non-patent documents 4 and 5 disclose an oxide semiconductor having a lower crystallinity than a CAAC structure and a nc structure and also having tiny crystals.

[0006] A transistor using IGZO for an active layer has an extremely low off-state current (see Non-Patent Document 6), and LSIs and displays utilizing this characteristic are known (see Non-Patent Documents 7 and 8).

[0007] In addition, various semiconductor devices using a transistor including an oxide semiconductor in a channel formation region (hereinafter also referred to as an “OS transistor”) have been proposed.

[0008] Patent Document 1 discloses an example of using OS transistors in DRAM (Dynamic Random Access Memory). Since the leakage current (off-state current) of OS transistors in the off state is extremely small, it is possible to manufacture DRAM with a low refresh frequency and low power consumption.

[0009] In addition, a nonvolatile memory using an OS transistor is disclosed in Patent Document 2. Unlike flash memory, these nonvolatile memories have no limit on the number of times they can be rewritten, so high-speed operation can be achieved more easily and power consumption is low.

[0010] In a memory using the above OS transistor, the off-state current can be reduced by increasing the threshold voltage of the OS transistor, thereby improving the data retention characteristics of the memory. Patent document 2 discloses an example in which a second gate is provided in the OS transistor to control the threshold voltage of the OS transistor, thereby reducing the off-state current.

[0011] In order for the memory to retain data for a long period of time, a predetermined negative potential needs to be constantly applied to the second gate of the OS transistor. Patent Documents 2 and 3 disclose examples of the configuration of a circuit for driving the second gate of the OS transistor.

[0012] [Prior technical literature]

[0013] [Patent Document]

[0014] [Patent Document 1] Japanese Patent Application Publication No. 2013-168631

[0015] [Patent Document 2] Japanese Patent Application Publication No. 2012-069932

[0016] [Patent Document 3] Japanese Patent Application Publication No. 2012-146965

[0017] [Non-patent literature]

[0018] [Non-patent document 1] S. Yamazaki et al., "SID Symposium Digest of Technical Papers", 2012, volume 43, issue 1, p. 183-186

[0019] [Non-patent document 2] S. Yamazaki et al., "Japanese Journal of Applied Physics", 2014, volume 53, Number 4S, p. 04ED18-1-04ED18-10

[0020] [Non-patent document 3] S. Ito et al., "The Proceedings of AM-FPD'13 Digest of Technical Papers", 2013, p.151-154

[0021] [Non-patent document 4] S. Yamazaki et al., "ECS Journal of Solid State Science and Technology", 2014, volume 3, issue 9, p. Q3012-Q3022

[0022] [Non-patent document 5] S. Yamazaki, “ECS Transactions”, 2014, volume 64, issue 10, p. 155-164

[0023] [Non-patent document 6] K. Kato et al., "Japanese Journal of Applied Physics", 2012, volume 51, p.021201-1-021201-7

[0024] [Non-patent document 7] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, pp. T216-T217

[0025] [Non-patent document 8] S.Amano et al., "SID Symposium Digest of Technical Papers", 2010, volume 41, issue 1, p.626-629 Summary of the invention

[0026] Technical problem to be solved by the invention

[0027] One of the purposes of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another purpose of one embodiment of the present invention is to provide a semiconductor device with high operating speed. Another purpose of one embodiment of the present invention is to provide a semiconductor device capable of retaining data for a long period of time. Another purpose of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption. Another purpose of one embodiment of the present invention is to provide a novel semiconductor device.

[0028] The description of multiple purposes does not interfere with each other. One mode of the present invention does not necessarily have to achieve all of the above purposes. Purposes other than the above can be naturally known from the description of the specification, drawings, claims, etc., and these purposes can also become the purpose of one mode of the present invention.

[0029] Solutions to technical problems

[0030] One embodiment of the present invention is a semiconductor device including a first circuit, a second circuit, a third circuit, a fourth circuit and an output terminal. The first circuit has a function of supplying a voltage to the second circuit. The second circuit has a function of supplying a first voltage to the output terminal and a function of maintaining the voltage of the output terminal. The third circuit has a function of measuring temperature information and a function of supplying a digital signal corresponding to the temperature information to the fourth circuit. The fourth circuit has a function of outputting a second voltage corresponding to the digital signal. The voltage of the output terminal is a total voltage of the first voltage and the second voltage.

[0031] The fourth circuit preferably includes a plurality of capacitors. The plurality of capacitors are electrically connected to the output terminals, respectively. In addition, the plurality of capacitors preferably have different capacitance values.

[0032] Effects of the Invention

[0033] According to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with high operating speed can be provided. In addition, according to one embodiment of the present invention, a semiconductor device capable of retaining data for a long period of time can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. In addition, according to one embodiment of the present invention, a novel semiconductor device can be provided.

[0034] Note that the description of these effects does not prevent the existence of other effects. In addition, one mode of the present invention does not need to have all of the above effects. One mode of the present invention does not need to have all of the above effects. In addition, the description of the specification, drawings, and claims, etc. clearly has effects other than the above effects, and effects other than the above effects can be obtained from the description of the specification, drawings, and claims, etc.

[0035] BRIEF DESCRIPTION OF THE DRAWINGS

[0036] [FIG. 1] A diagram illustrating a structural example of a semiconductor device;

[0037] [FIG. 2] A diagram illustrating electrical characteristics of a transistor;

[0038] [Fig. 3] A diagram illustrating a configuration example of a voltage generating circuit;

[0039] [ Fig. 4 ] A diagram illustrating a configuration example of a voltage holding circuit;

[0040] [ Figure 5 ] A diagram illustrating a configuration example of a temperature detection circuit;

[0041] [ Fig. 6 ] is a diagram illustrating an example of a change in voltage VBias with respect to a temperature change;

[0042] [ Figure 7 ] A timing diagram illustrating an example of operation of a semiconductor device;

[0043] [ Figure 8 ] A diagram illustrating an example of a structure of a storage device;

[0044] [ Fig. 9 ] A diagram illustrating an example of a structure of a cell array;

[0045] [Fig. 10] A circuit diagram illustrating a structural example of a memory cell;

[0046] [ Fig.11 ] A diagram illustrating an example of a structure of a storage device;

[0047] [ Fig.12 ] A diagram illustrating an example of a structure of a storage device;

[0048] [Fig. 13] A diagram illustrating a structural example of a transistor;

[0049] [Fig. 14] A diagram illustrating a structural example of a transistor;

[0050] [Fig. 15] A diagram illustrating a structural example of a transistor;

[0051] Fig. 16 is a diagram illustrating an example of an electronic component;

[0052] [ Fig.17 ] A diagram illustrating an example of an electronic device;

[0053] [Fig. 18] A diagram illustrating an application example of a storage device.

[0054] Modes for Carrying Out the Invention

[0055] The embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and a person skilled in the art can easily understand that the mode and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments and examples shown below.

[0056] Note that in the invention structure described below, the same reference numerals are used in common in different drawings to represent the same parts or parts with the same function, and repeated description is omitted. In addition, when representing parts with the same function, the same hatching is sometimes used without adding a reference numeral.

[0057] Note that in each of the drawings described in this specification, the size of each component, the thickness of a layer, and a region may be exaggerated for the sake of clarity. Therefore, the present invention is not limited to the sizes in the drawings.

[0058] In this specification, a high power supply voltage is sometimes referred to as an “H level” (also referred to as “VDD” or “H potential”), and a low power supply voltage is sometimes referred to as an “L level” (also referred to as “GND” or “L potential”).

[0059] In addition, the following embodiments and examples in this specification can be combined as appropriate. In addition, when a plurality of structural examples are shown in one embodiment, these structural examples can be combined as appropriate.

[0060] In this specification, etc., metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors, etc. For example, when a metal oxide is used in a semiconductor layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In addition, an OS transistor may be referred to as a transistor comprising a metal oxide or an oxide semiconductor. In this specification, etc., a metal oxide comprising nitrogen is sometimes also referred to as a metal oxide.

[0061] Unless otherwise specified, the transistors described in this specification and the like are enhancement-type (normally off) n-channel field effect transistors, and therefore, their threshold voltage (also referred to as "Vth") is greater than 0V.

[0062] (Implementation Method 1)

[0063] <Semiconductor Device 100>

[0064] Figure 1A and Figure 1B1 is a circuit diagram showing a structural example of a semiconductor device 100 according to one embodiment of the present invention. The semiconductor device 100 includes a voltage generating circuit 110, a voltage holding circuit 120, a temperature detecting circuit 130, and a voltage control circuit 140. The node between the voltage holding circuit 120 and the voltage control circuit 140 is referred to as a node ND. The voltage holding circuit 120 and the voltage control circuit 140 are electrically connected to an output terminal VOUT via the node ND.

[0065] In addition, the semiconductor device 100 is electrically connected to the second gates of the plurality of transistors M11 through the output terminal VOUT. The transistor M11 is a transistor including a first gate (also referred to as a "front gate" or simply referred to as a "gate") and a second gate (also referred to as a "back gate"). The first gate and the second gate have overlapping regions across the semiconductor layer. The second gate has, for example, a function of controlling the threshold voltage of the transistor M11.

[0066] The transistor M11 represents a transistor used in various circuits included in a storage device, a pixel device, a computing device, etc. For example, it represents a transistor included in a NOR type or NAND type storage device. In addition, for example, it represents a transistor included in a display device such as a liquid crystal display device or an EL display device. In addition, for example, it represents a transistor included in a CPU (Central Processing Unit), a GPU (Graphic Processing Unit) or an FPGA (Field Programmable Gate Array).

[0067] Although Figure 1A and Figure 1B Although three transistors M11 are shown in FIG. 1 , one embodiment of the present invention is not limited thereto, and more transistors M11 may be connected to the semiconductor device 100 .

[0068] Here, the temperature dependency of Id-Vg characteristics, which is one of the electrical characteristics of a transistor, will be described. Figure 2A and Figure 2B An example of Id-Vg characteristics, which are one of the electrical characteristics of a transistor, is shown. The Id-Vg characteristics represent changes in drain current (Id) with respect to changes in gate voltage (Vg). Figure 2A and Figure 2B The horizontal axis of shows Vg on a linear scale. Figure 2A and Figure 2B The vertical axis shows Id in a logarithmic scale.

[0069] Figure 2A The Id-Vg characteristics of the OS transistor are shown. Figure 2BId-Vg characteristics of a transistor using silicon for a semiconductor layer in which a channel is formed (also referred to as a “Si transistor”) are shown. Figure 2A and Figure 2B Both are Id-Vg characteristics of n-channel transistors.

[0070] like Figure 2A As shown in Figure 1, even when the OS transistor is working at high temperature, the off-state current is not easy to increase. As the operating temperature of the OS transistor increases, the Vth drifts in the negative direction and the on-state current increases. Figure 2B As shown in Figure 1, as the temperature of the Si transistor increases, the off-state current increases. As the temperature of the Si transistor increases, the Vth drifts in the positive direction and the on-state current decreases.

[0071] Therefore, by using an OS transistor as the transistor M11, the power consumption of the entire semiconductor device including the transistor M11 can be reduced even when operating at a high temperature.

[0072] In addition, the semiconductor device 100 has a function of writing a voltage VBG to the second gate of the transistor M11 and maintaining the voltage. For example, when a negative potential is applied as the voltage VBG, the transistor M11 can drift the Vth in the positive direction while maintaining the negative potential of the second gate. Even when operating at a high temperature, a high Vth can be maintained. For example, when the transistor M11 is used as a selection transistor of a memory cell, the charge of a capacitor used as a memory can be maintained for a long period of time.

[0073] [Voltage generating circuit 110]

[0074] Figure 3A and Figure 3B 1 shows an example of a circuit configuration of the voltage generating circuit 110. The above circuit diagram is a step-down charge pump, where GND is input to the input terminal IN and VBG0 is output from the output terminal OUT. Here, as an example, the number of stages of the basic circuit of the charge pump circuit is 4, but one embodiment of the present invention is not limited to this, and a charge pump circuit having any number of stages can also be configured.

[0075] Figure 3A The voltage generating circuit 110 a shown includes transistors M21 to M24 and capacitors C21 to C24 .

[0076] The transistors M21 to M24 are connected in series between the input terminal IN and the output terminal OUT, and are connected so that the gates and the first electrodes thereof function as diodes. The gates of the transistors M21 to M24 are connected to the capacitors C21 to C24, respectively.

[0077] CLK is input to the first electrodes of the capacitors C21 and C23 of the odd-numbered stages, and CLKB is input to the first electrodes of the capacitors C22 and C24 of the even-numbered stages. CLKB is an inverted clock signal obtained by inverting the phase of CLK.

[0078] The voltage generating circuit 110a has a function of stepping down the GND input to the input terminal IN to generate VBG0. The voltage generating circuit 110a can generate a negative potential only by receiving CLK and CLKB.

[0079] The transistors M21 to M24 may be formed using OS transistors. The use of OS transistors is preferred because the reverse current of the diode-connected transistors M21 to M24 can be reduced.

[0080] Figure 3B The voltage generating circuit 110b shown in the figure is composed of transistors M31 to M34 which are p-channel transistors. For other components, refer to the description of the voltage generating circuit 110a.

[0081] The voltage generating circuit 110 may use not only a step-down charge pump but also a step-up charge pump. Alternatively, the voltage generating circuit 110 may use both a step-down charge pump and a step-up charge pump.

[0082] [Voltage holding circuit 120]

[0083] The voltage holding circuit 120 includes a transistor M12 (see Figure 1A ). A first terminal (one of the source and the drain) of the transistor M12 is electrically connected to the voltage generating circuit 110, and a second terminal (the other of the source and the drain) of the transistor M12 is electrically connected to the node ND.

[0084] The voltage holding circuit 120 has a function of supplying the voltage VBG0 generated by the voltage generating circuit 110 to the node ND by turning on the transistor M12. When the threshold voltage of the transistor M12 is set to Vth1 and the transistor M12 is turned on, a voltage of VBG0+Vth1 or more is preferably applied to the gate of the transistor M12. In addition, the voltage holding circuit 120 has a function of turning off the transistor M12 and holding the voltage of the node ND.

[0085] When a negative potential is supplied as the voltage VBG0, a transistor having a first gate and a second gate can be used as the transistor M12, and the first gate and the second gate can be electrically connected to the second terminal (see Figure 4A). At this time, the transistor M12 has a diode function. In addition, when the voltage output from the transistor M12 is recorded as voltage VBG1, the following relationship holds: VBG1=VBG0+Vth1. The negative potential of the write node ND can be maintained by setting the first terminal of the transistor M12 to GND.

[0086] exist Figure 4A In the transistor M12 shown, after supplying a negative potential to the node ND, the first terminal is set to GND, and Vg becomes 0 V. Therefore, it is preferable that Id (also called "cutoff current") is small when Vg is 0 V. By making the cutoff current sufficiently small, the negative potential written to the node ND can be maintained for a long time.

[0087] The channel length of transistor M12 is preferably greater than the channel length of transistor M11. For example, when the channel length of transistor M11 is less than 1 μm, the channel length of transistor M12 is greater than 1 μm, more preferably greater than 3 μm, further preferably greater than 5 μm, and further preferably greater than 10 μm. By extending the channel length of transistor M12, transistor M12 is not affected by the short channel effect and the cut-off current can be suppressed. In addition, the withstand voltage between the source and drain of transistor M12 can be increased. When the withstand voltage between the source and drain of transistor M12 is high, the connection between the voltage generating circuit 110 that generates a high voltage and transistor M11 can be facilitated.

[0088] As the transistor M12, it is preferred to use an OS transistor or a transistor using a wide bandgap semiconductor in the channel formation region. The OS transistor or the transistor using a wide bandgap semiconductor has a small cutoff current and a high withstand voltage between the source and the drain. Note that in this specification, a wide bandgap semiconductor refers to a semiconductor with a bandgap of 2.2 eV or more. For example, silicon carbide, gallium nitride, diamond, etc. can be cited.

[0089] The transistor M12 is required to have a cut-off current smaller than that of the transistor M11. On the other hand, the transistor M11 is required to have an on-state current larger than that of the transistor M12. In this way, when transistors with different required properties are formed on the same substrate, different semiconductors are used to form each transistor. The transistor M12 preferably uses a semiconductor having a larger band gap than the transistor M11 for the channel formation region. In addition, the transistor M11 preferably uses a semiconductor having a higher electron mobility than the transistor M12 for the channel formation region.

[0090] In addition, the voltage holding circuit 120 may be composed of a plurality of transistors M12 connected in series (see Figure 4B and Figure 4C ).

[0091] [Temperature detection circuit 130]

[0092] The temperature detection circuit 130 includes a temperature sensor 131 and an analog-to-digital conversion circuit (also referred to as “ADC”) 132 (see Figure 5 ).

[0093] The temperature sensor 131 has a function of sensing the temperature of the semiconductor device 100 and outputting an analog signal VA corresponding to the temperature. The temperature sensor 131 may be, for example, a temperature measuring resistor made of platinum, nickel or copper, a thermistor, a thermocouple, an IC temperature sensor or the like.

[0094] The analog-to-digital conversion circuit 132 has a function of converting the analog signal VA into an n-bit (n is an integer greater than or equal to 1) digital signal VD. The digital signal VD is output from the temperature detection circuit 130 and supplied to the voltage control circuit 140 .

[0095] By converting the temperature information of the analog signal measured by the temperature detection circuit 130 into a digital signal and outputting it, the signal attenuation and noise caused by wiring resistance and parasitic capacitance can be reduced. Therefore, even if the temperature detection circuit 130 is set at a position far away from the voltage control circuit 140, the temperature information can be accurately transmitted to the voltage control circuit 140.

[0096] [Voltage control circuit 140]

[0097] As reference Figure 2A As described, the lower the temperature of the OS transistor, the more Vth drifts in the positive direction, and the on-state current decreases. As a result, the operating speed of the circuit decreases. In addition, the higher the temperature, the more Vth drifts in the negative direction, and the cut-off current increases. This is the main reason for the narrowing of the temperature range in which the circuit can operate. By applying a correction voltage corresponding to the operating temperature to the node ND using the voltage control circuit 140, the voltage output by the output terminal VOUT of the semiconductor device 100 can be corrected, thereby expanding the temperature range in which the circuit electrically connected to the output terminal VOUT can operate.

[0098] The voltage control circuit 140 includes a logic circuit 145 and a voltage generating circuit 146 (see Figure 1B ). The logic circuit 145 has a function of supplying the digital signal (temperature information) supplied by the temperature detection circuit 130 to the voltage generation circuit 146. For example, the serial signal supplied by the temperature detection circuit 130 is converted into a parallel signal and supplied to the voltage generation circuit 146. In addition, the logic circuit 145 has a function of converting the n-bit digital signal supplied by the temperature detection circuit 130 into an m-bit (m is an integer greater than 1) digital signal and supplying it to the voltage generation circuit 146.

[0099] The voltage generating circuit 146 has a function of converting the m-bit digital signal supplied from the logic circuit 145 into a 2-bit digital signal. m level voltage and output function. Figure 1B An example in which m is 4 is shown. Figure 1B The medium voltage generating circuit 146 includes a buffer BF1 , a buffer BF2 , a buffer BF3 , a buffer BF4 , a capacitor C1 , a capacitor C2 , a capacitor C4 , and a capacitor C8 .

[0100] The 4-bit digital signal output by the logic circuit 145 is supplied to the inputs of the buffers BF1 to BF4. Specifically, the first bit of the 4-bit digital signal is input to the buffer BF1, the second bit is input to the buffer BF2, the third bit is input to the buffer BF3, and the fourth bit is input to the buffer BF4.

[0101] One electrode of the capacitor C1 is electrically connected to the output of the buffer BF1, and the other electrode is electrically connected to the output terminal OUT. One electrode of the capacitor C2 is electrically connected to the output of the buffer BF2, and the other electrode is electrically connected to the output terminal OUT. One electrode of the capacitor C4 is electrically connected to the output of the buffer BF3, and the other electrode is electrically connected to the output terminal OUT. One electrode of the capacitor C8 is electrically connected to the output of the buffer BF4, and the other electrode is electrically connected to the output terminal OUT.

[0102] The voltage outputted from the output terminal OUT of the voltage control circuit 140 is referred to as “voltage VBias.” The output terminal OUT of the voltage control circuit 140 is electrically connected to the node ND of the semiconductor device 100 .

[0103] The voltage applied to the node ND by the voltage control circuit 140 is determined by the ratio of the combined capacitance of the capacitors C1, C2, C4, and C8 to the parasitic capacitance generated at the node ND. The capacitance value of the capacitor C1 is preferably sufficiently greater than the capacitance value of the parasitic capacitance. Specifically, the capacitance value of the capacitor C1 is preferably 5 times or more, and more preferably 10 times or more, the capacitance value of the parasitic capacitance.

[0104] In addition, the capacitance values ​​of capacitor C1, capacitor C2, capacitor C4, and capacitor C8 may all be the same capacitance value, but preferably, the capacitance values ​​of at least some of the capacitors are different or the capacitance values ​​of all the capacitors are different. In this embodiment, the capacitance value of capacitor C2 is twice the capacitance value of capacitor C1, the capacitance value of capacitor C4 is four times the capacitance value of capacitor C1, and the capacitance value of capacitor C8 is eight times the capacitance value of capacitor C1. Thus, 16 levels of voltage can be supplied to node ND by voltage control circuit 140.

[0105] FIG. 6A to FIG. 6CAn example of voltage change of voltage VBias with respect to temperature change is shown. FIG. 6A to FIG. 6C The horizontal axis shows temperature on a linear scale. FIG. 6A to FIG. 6C The vertical axis of VBias shows the voltage VBias in a linear scale. When the transistor M11 is an OS transistor, the magnitude of the voltage VBias preferably decreases as the operating temperature of the transistor M11 increases (see Fig. 6A ). In addition, depending on the purpose or application, the voltage VBias can be increased as the operating temperature increases (refer to Figure 6B ). In addition, the magnitude of the voltage VBias may also change nonlinearly with respect to temperature changes (see Figure 6C ). The voltage change of the voltage VBias with respect to the temperature change can be set by the logic circuit 145 .

[0106] <Operation Example of Semiconductor Device 100>

[0107] Figure 7 1 is a timing chart for explaining an operation example of the semiconductor device 100. In this embodiment, an operation example under the following conditions is described: the transistor M11 is an OS transistor, and the voltage VBias changes linearly in the range of 0 V to 7.5 V when the operating temperature changes in the range of 100° C. to −50° C. In addition, the voltage VBG changes to −3 V when the operating temperature is 20° C.

[0108] The temperature detection circuit 130 outputs a 4-bit digital signal VD. In the present embodiment, when the operating temperature is 100°C, "0000" is output as the digital signal VD, and when the operating temperature is -50°C, "1111" is output.

[0109] In addition, when the output of the buffer BF1 connected to one electrode of the capacitor C1 changes from the L potential to the H potential, the potential of the other electrode of the capacitor C1 rises by 0.5 V. In addition, when the output of the buffer BF2 connected to one electrode of the capacitor C2 changes from the L potential to the H potential, the potential of the other electrode of the capacitor C2 rises by 1.0 V. In addition, when the output of the buffer BF3 connected to one electrode of the capacitor C4 changes from the L potential to the H potential, the potential of the other electrode of the capacitor C4 rises by 2.0 V. In addition, when the output of the buffer BF4 connected to one electrode of the capacitor C8 changes from the L potential to the H potential, the potential of the other electrode of the capacitor C8 rises by 4.0 V.

[0110] [Period T0]

[0111] Period T0 is a reset period. During period T0, each output of buffer BF1 to buffer BF4 outputs an L potential (0V). In addition, voltage VBG0 is set to -7V, and transistor M12 is turned on. As a result, voltage VBG becomes -7V. During period T0, temperature detection circuit 130 can stop outputting digital signal VD. In addition, the operation of temperature detection circuit 130 can also be stopped.

[0112] [Period T1]

[0113] During the period T1, the transistor M12 is turned off, and the voltage of the node ND is kept at -7 V. Thus, the voltage VBG is kept at -7 V.

[0114] [Period T2]

[0115] During the period T2, the temperature detection circuit 130 supplies the digital signal VD (temperature information) to the voltage control circuit 140. For example, "1000" is supplied to the voltage control circuit 140 as the digital signal VD indicating 20°C.

[0116] The logic circuit 145 inputs a potential corresponding to the digital signal VD to the buffers BF1 to BF4. Specifically, when the digital signal VD is "1000", the buffers BF1 to BF3 are controlled so that the outputs are at an L potential and the outputs of the buffers BF4 are at an H potential.

[0117] Thus, the potential of the voltage control circuit 140 rises by 4 V. As a result, the voltage of the node ND changes from -7 V to -3 V, and the voltage VBG changes to -3 V.

[0118] [Period T3]

[0119] During the period T3, the temperature detection circuit 130 supplies the digital signal VD (temperature information) to the voltage control circuit 140. For example, "0101" is supplied to the voltage control circuit 140 as the digital signal VD indicating 50°C.

[0120] As in period T2, logic circuit 145 inputs a potential corresponding to digital signal VD to buffers BF1 to BF4. When digital signal VD is "0101", the output of buffer BF1 becomes H potential, the output of buffer BF2 becomes L potential, the output of buffer BF3 becomes H potential, and the output of buffer BF4 becomes L potential. As a result, voltage VBG becomes -4.5V.

[0121] [Period T4]

[0122] During the period T4, the temperature detection circuit 130 supplies the digital signal VD (temperature information) to the voltage control circuit 140. For example, "1100" is supplied to the voltage control circuit 140 as the digital signal VD indicating -20°C.

[0123] As in the period T2 and the period T3, the logic circuit 145 inputs a potential corresponding to the digital signal VD to the buffers BF1 to BF4. When the digital signal VD is "1100", the output of the buffer BF1 becomes an L potential, the output of the buffer BF2 becomes an L potential, the output of the buffer BF3 becomes an H potential, and the output of the buffer BF4 becomes an H potential. As a result, the voltage VBG becomes -1.0V.

[0124] In this way, the voltage VBG can be changed in response to temperature changes. In addition, without considering the temperature change of the electrical characteristics of the transistor M11, a larger voltage than required is applied to the second gate of the transistor M11. When a larger voltage than required is applied to the second gate of the transistor M11 for a long time, the electrical characteristics of the transistor M11 deteriorate and the reliability may be reduced. One method of the present invention can change the voltage applied to the second gate of the transistor M11 in response to temperature changes. Thus, only the minimum required voltage can be applied to the second gate of the transistor M11. One method of the present invention can improve the reliability of a semiconductor device including the transistor M11.

[0125] Alternatively, a reset period (period T0 ) may be provided at regular intervals to refresh the voltage of the node ND.

[0126] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0127] (Implementation Method 2)

[0128] In this embodiment, a memory device using the semiconductor device 100 described in Embodiment 1 will be described.

[0129] <Storage Device>

[0130] Figure 8 The memory device 300 includes a peripheral circuit 311, a cell array 401, and a semiconductor device 100. The peripheral circuit 311 includes a row decoder 321, a word line driver circuit 322, a bit line driver circuit 330, an output circuit 340, and a control logic circuit 360.

[0131] The word line driving circuit 322 has a function of supplying a potential to the wiring WL. The bit line driving circuit 330 includes a column decoder 331, a precharge circuit 332, an amplifier circuit 333, and a write circuit 334. The precharge circuit 332 has a function of precharging the wiring SL (not shown) and the like. The amplifier circuit 333 has a function of amplifying a data signal read out by the wiring BIL or the wiring RBL. In addition, the wiring WL, the wiring SL, the wiring BIL, and the wiring RBL are wirings connected to the memory cell 411 in the cell array 401, and will be described in detail later. The amplified data signal is output to the outside of the storage device 300 as a digital data signal RDATA through the output circuit 340.

[0132] The memory device 300 is supplied from the outside with a low power supply voltage (VSS) as a power supply voltage, a high power supply voltage (VDD) for the peripheral circuit 311 , and a high power supply voltage (VIL) for the cell array 401 .

[0133] Control signals (CE, WE, RE), address signal ADDR, and data signal WDATA are also input from the outside to the memory device 300. The address signal ADDR is input to the row decoder 321 and the column decoder 331, and WDATA is input to the write circuit 334.

[0134] The control logic circuit 360 processes input signals (CE, WE, RE) from the outside to generate control signals for the row decoder 321 and the column decoder 331. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signals processed by the control logic circuit 360 are not limited thereto, and other control signals may be input as needed.

[0135] The above-mentioned circuits and signals can be used appropriately as needed.

[0136] OS transistors can be used as transistors constituting the cell array 401. In addition, OS transistors can be used as transistors constituting the peripheral circuit 311. By using OS transistors as the cell array 401 and the peripheral circuit 311, the cell array 401 and the peripheral circuit 311 can be manufactured using the same manufacturing process, thereby reducing manufacturing costs.

[0137] [Structural example of cell array]

[0138] Fig. 9 4 shows an example of the structure of the cell array 401. The cell array 401 has m (m is an integer greater than or equal to 1) memory cells 411 in one column and n (n is an integer greater than or equal to 1) memory cells 411 in one row, for a total of m×n memory cells 411. The memory cells 411 are arranged in rows and columns. Fig. 9The address of the memory cell 411 is also marked, and the memory cell 411 located at the address [1, 1], [m, 1], [i, j], [1, n], [m, n] (i is an integer greater than 1 and less than m, and j is an integer greater than 1 and less than n) is shown. In addition, the number of wirings connecting the cell array 401 and the word line driving circuit 322 is determined by the structure of the memory cell 411 and the number of memory cells 411 in one column. In addition, the number of wirings connecting the cell array 401 and the bit line driving circuit 330 is determined by the structure of the memory cell 411 and the number of memory cells 411 in one row.

[0139] [Structural example of storage unit]

[0140] FIG. 10A to FIG. 10E A structural example of the storage unit 411A to the storage unit 411E which can be used for the above-described storage unit 411 is shown.

[0141] [DOSRAM]

[0142] Fig. 10A An example of a circuit structure of a DRAM type memory cell 411A is shown. In this specification and the like, a DRAM using an OS transistor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 411A includes a transistor M11 and a capacitor CA.

[0143] The first terminal of the transistor M11 is connected to the first terminal of the capacitor CA, the second terminal of the transistor M11 is connected to the wiring BIL, the gate of the transistor M11 is connected to the wiring WL, and the back gate of the transistor M11 is connected to the wiring BGL. The second terminal of the capacitor CA is connected to the wiring GNDL. The wiring GNDL is a wiring that provides a low-level potential (also called a reference potential).

[0144] Wiring BIL is used as a bit line, and wiring WL is used as a word line. Wiring BGL is used as wiring for applying a potential to the back gate of transistor M11. In addition, wiring BGL is electrically connected to output terminal VOUT of semiconductor device 100. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M11 can be increased or decreased.

[0145] Data writing and reading are performed by applying a high-level potential to the wiring WL to turn on the transistor M11 and electrically connect the wiring BIL and the first terminal of the capacitor CA.

[0146] In addition, the memory cell in the memory device 300 is not limited to the memory cell 411A, and the circuit structure may be changed.

[0147] When the transistor M11 is used in a memory cell, the transistor M11 is preferably an OS transistor. In addition, the semiconductor layer of the OS transistor is preferably an oxide semiconductor containing any one of indium, element M (element M is aluminum, gallium, yttrium or tin), and zinc. In particular, an oxide semiconductor composed of indium, gallium and zinc is preferably used.

[0148] The OS transistor using an oxide semiconductor containing indium, gallium, and zinc has the characteristic of extremely small off-state current. By using an OS transistor as the transistor M11, the leakage current of the transistor M11 can be made very low. In other words, the transistor M11 can be used to maintain written data for a long time, thereby reducing the refresh frequency of the memory cell. In addition, the refresh work of the memory cell can be omitted. In addition, since the leakage current is very low, multi-value data or analog data can be maintained for the memory cell 411A, the memory cell 420, and the memory cell 430.

[0149] By using an OS transistor as the transistor M11, a DOSRAM can be configured.

[0150] [NOSRAM]

[0151] Fig. 10B A circuit configuration example of a memory cell 411B of a gain cell type (also referred to as a "2Tr1C type") including two transistors and one capacitor is shown. The memory cell 411B includes a transistor M11, a transistor M3, and a capacitor CB.

[0152] The first terminal of the transistor M11 is connected to the first terminal of the capacitor CB, the second terminal of the transistor M11 is connected to the wiring WBL, the gate of the transistor M11 is connected to the wiring WL, and the back gate of the transistor M11 is connected to the wiring BGL. The second terminal of the capacitor CB is connected to the wiring BL. The first terminal of the transistor M3 is connected to the wiring RBL, the second terminal of the transistor M3 is connected to the wiring SL, and the gate of the transistor M3 is connected to the first terminal of the capacitor CB.

[0153] Wiring WBL is used as a write bit line, wiring RBL is used as a read bit line, and wiring WL is used as a word line. Wiring BL is used as a wiring for applying a predetermined potential to the second terminal of capacitor CB. When data is written or data is retained, wiring BL is preferably applied with a reference potential.

[0154] The wiring BGL is used as a wiring for applying a potential to the back gate of the transistor M11. The wiring BGL is electrically connected to the output terminal VOUT of the semiconductor device 100. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M11 can be increased or decreased.

[0155] Data is written by applying a high-level potential to the wiring WL to turn on the transistor M11 so that the wiring WBL is electrically connected to the first terminal of the capacitor CB. Specifically, when the transistor M11 is in the on state, a potential corresponding to the information to be recorded is applied to the wiring WBL to write the potential to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WL to turn the transistor M11 into a non-conductive state, thereby maintaining the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3.

[0156] The data is read out by applying a predetermined potential to the wiring BL and the wiring SL. Since the current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3, the potential held by the first terminal of the capacitor CB (or the gate of the transistor M3) can be read out by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, the information written in the storage cell can be read out from the potential held by the first terminal of the capacitor CB (or the gate of the transistor M3). Alternatively, it can be known whether the storage cell is written with information.

[0157] In addition, the memory cell in the above-mentioned memory device 300 is not limited to the memory cell 411B, and the circuit structure may be changed appropriately.

[0158] For example, a structure in which the wiring WBL and the wiring RBL are combined into one wiring BIL may be adopted. Fig. 10C An example of the circuit structure of the memory cell in this case is shown. In the memory cell 411C, the wiring WBL and the wiring RBL of the memory cell 411B are combined into one wiring BIL, and the second terminal of the transistor M11 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 411C operates by combining the write bit line and the read bit line into one wiring BIL.

[0159] The transistor M11 of the memory cell 411B is preferably an OS transistor. A memory device using a 2Tr1C type memory cell using an OS transistor as the transistor M11 such as the memory cell 411B and the memory cell 411C is called a NOSRAM (Non-volatile Oxide Semiconductor Random Access Memory).

[0160] In addition, the channel formation region of the transistor M3 preferably contains silicon. In particular, the silicon may be amorphous silicon, polycrystalline silicon, or low temperature polycrystalline silicon (LTPS: Low Temperature Poly-Silicon) (hereinafter also referred to as Si transistor). Since the field effect mobility of Si transistors is sometimes higher than that of OS transistors, Si transistors are more suitable for use as readout transistors.

[0161] In addition, when an OS transistor is used as the transistor M3, the memory cell can be formed of a unipolar circuit.

[0162] in addition, Fig. 10D The circuit configuration example of a memory cell 411D of a gain cell type of three transistors and one capacitor (also referred to as a "3Tr1C type") is shown. The memory cell 411D includes a transistor M11, a transistor M5, a transistor M6, and a capacitor CC.

[0163] The first terminal of transistor M11 is connected to the first terminal of capacitor CC, the second terminal of transistor M11 is connected to wiring BIL, the gate of transistor M11 is connected to wiring WL, and the back gate of transistor M11 is electrically connected to wiring BGL. The second terminal of capacitor CC is electrically connected to the first terminal of transistor M5 and wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitor CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RL.

[0164] The wiring BIL serves as a bit line, the wiring WL serves as a write word line, and the wiring RL serves as a read word line.

[0165] The wiring BGL is used as a wiring for applying a potential to the back gate of the transistor M11. The wiring BGL is electrically connected to the output terminal VOUT of the semiconductor device 100. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M11 can be increased or decreased.

[0166] Data is written by applying a high-level potential to the wiring WL to turn on the transistor M11 so that the wiring BIL is connected to the first terminal of the capacitor CC. Specifically, when the transistor M11 is in the on state, a potential corresponding to the information to be recorded is applied to the wiring BIL to write the potential to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WL to turn the transistor M11 into a non-conductive state, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0167] The data is read out by precharging the wiring BIL to a predetermined potential, then making the wiring BIL electrically floating and applying a high level potential to the wiring RL. By making the wiring RL a high level potential, the transistor M6 becomes conductive, and the wiring BIL and the second terminal of the transistor M5 become electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5, but the potential of the second terminal of the transistor M5 and the potential of the wiring BIL will change in accordance with the potential maintained by the first terminal of the capacitor CC (or the gate of the transistor M5). Here, the potential maintained by the first terminal of the capacitor CC (or the gate of the transistor M5) can be read out by reading out the potential of the wiring BIL. In other words, the information written into the storage cell can be read out from the potential maintained by the first terminal of the capacitor CC (or the gate of the transistor M5). Alternatively, it can be known whether the storage cell is written with information.

[0168] In addition, the circuit structure of the memory cell in the above-mentioned memory device 300 may be changed appropriately.

[0169] It is also preferable to use an OS transistor as the transistor M11 of the memory cell 411D. The 3Tr1C-type memory cell 411D using an OS transistor as the transistor M11 is one form of the NOSRAM described above.

[0170] The channel formation regions of the transistors M5 and M6 described in this embodiment preferably contain silicon. In particular, the silicon may be amorphous silicon, polycrystalline silicon, or low-temperature polycrystalline silicon. Since the field effect mobility of a Si transistor is sometimes higher than that of an OS transistor, a Si transistor is more suitable for use as a readout transistor.

[0171] In addition, when OS transistors are used as the transistors M5 and M6, the memory cell can be formed of a unipolar circuit.

[0172] [oxSRAM]

[0173] Fig. 10E An example of a circuit structure of a SRAM (Static Random Access Memory) type memory cell 411E using an OS transistor is shown. In this specification, etc., an SRAM using an OS transistor is referred to as an oxSRAM. Fig. 10E The memory cell 411E shown is a SRAM type memory cell capable of backup.

[0174] The memory cell 411E includes transistors M7 to M10, transistors MS1 to MS4, capacitors CD1 and CD2. In addition, transistors M7 and M8 are equivalent to transistor M11. Transistors M7 to M10 are transistors including back gates. Transistors MS1 and MS2 are p-channel transistors, and transistors MS3 and MS4 are n-channel transistors.

[0175] The first terminal of the transistor M7 is connected to the wiring BIL, and the second terminal of the transistor M7 is connected to the first terminal of the transistor MS1, the first terminal of the transistor MS3, the gate of the transistor MS2, the gate of the transistor MS4, and the first terminal of the transistor M10. The gate of the transistor M7 is connected to the wiring WL, and the back gate of the transistor M7 is connected to the wiring BGL1.

[0176] The first terminal of transistor M8 is connected to wiring BILB, and the second terminal of transistor M8 is connected to the first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and the first terminal of transistor M9. The gate of transistor M8 is connected to wiring WL, and the back gate of transistor M8 is connected to wiring BGL2.

[0177] The second terminal of the transistor MS1 is electrically connected to the wiring VDL. The second terminal of the transistor MS2 is electrically connected to the wiring VDL. The second terminal of the transistor MS3 is electrically connected to the wiring GNDL. The second terminal of the transistor MS4 is connected to the wiring GNDL.

[0178] The second terminal of transistor M9 is connected to the first terminal of capacitor CD1, the gate of transistor M9 is connected to wiring BRL, and the back gate of transistor M9 is connected to wiring BGL3. The second terminal of transistor M10 is connected to the first terminal of capacitor CD2, the gate of transistor M10 is connected to wiring BRL, and the back gate of transistor M10 is connected to wiring BGL4.

[0179] A second terminal of the capacitor CD1 is connected to the wiring GNDL, and a second terminal of the capacitor CD2 is connected to the wiring GNDL.

[0180] The wiring BIL and the wiring BILB are used as bit lines, the wiring WL is used as a word line, and the wiring BRL is a wiring for controlling the conduction state and the non-conduction state of the transistor M9 and the transistor M10.

[0181] The wirings BGL1 to BGL4 are used as wirings for applying potentials to the back gates of the transistors M7 to M10 , respectively.

[0182] The wirings BGL1 to BGL4 are electrically connected to the output terminal VOUT of the semiconductor device 100. In addition, a plurality of semiconductor devices 100 may be provided for the memory device 300, and the wirings BGL1 to BGL4 may be electrically connected to different semiconductor devices 100. By applying an arbitrary potential to the wirings BGL1 to BGL4, the threshold voltages of the transistors M7 to M10 may be increased or decreased.

[0183] The wiring VDL is a wiring for supplying a high-level potential, and the wiring GNDL is a wiring for supplying a low-level potential.

[0184] Data is written by applying a high level potential to the wiring WL and a high level potential to the wiring BRL. Specifically, when the transistor M10 is turned on, a potential corresponding to the information to be recorded is applied to the wiring BIL and written to the second terminal side of the transistor M10.

[0185] The memory cell 411E forms an inverter loop using transistors MS1 to MS2, so the inverted signal of the data signal corresponding to the potential is input to the second terminal side of the transistor M8. Since the transistor M8 is in the on state, the potential applied to the wiring BIL, that is, the inverted signal of the signal input to the wiring BIL is output to the wiring BILB. In addition, since the transistors M9 and M10 are in the on state, the potential of the second terminal of the transistor M7 and the potential of the second terminal of the transistor M8 are respectively maintained by the first terminal of the capacitor CD2 and the first terminal of the capacitor CD1. Then, by applying a low-level potential to the wiring WL and applying a low-level potential to the wiring BRL to make the transistors M7 to M10 non-conductive, the potential of the first terminal of the capacitor CD1 and the potential of the first terminal of the capacitor CD2 are maintained.

[0186] Data is read out by the following method: first, the wiring BIL and the wiring BILB are precharged to a predetermined potential, and then a high-level potential is applied to the wiring WL and the wiring BRL, whereby the potential of the first terminal of the capacitor CD1 is refreshed by the inverter loop of the storage unit 411E and output to the wiring BILB. In addition, the potential of the first terminal of the capacitor CD2 is refreshed by the inverter loop of the storage unit 411E and output to the wiring BIL. Since the wiring BIL and the wiring BILB are changed from the precharged potential to the potential of the first terminal of the capacitor CD2 and the potential of the first terminal of the capacitor CD1, respectively, the potential held by the storage unit can be read from the potential of the wiring BIL or the wiring BILB.

[0187] In addition, OS transistors are preferably used as transistors M7 to M10. By using OS transistors as transistors M7 to M10, the memory cell 411E can be used to hold written data for a long time, thereby reducing the refresh frequency of the memory cell 411E. In addition, the refresh operation of the memory cell 411E can be omitted. In addition, since the leakage current is very low, multi-value data or analog data can be held in the memory cell 411E.

[0188] In addition, the channel formation regions of transistors MS1 to MS4 preferably contain silicon. In particular, the silicon may be amorphous silicon, polycrystalline silicon, or low-temperature polycrystalline silicon. Since the field effect mobility of Si transistors is sometimes higher than that of OS transistors, Si transistors are more suitable for use as transistors in inverters.

[0189] In addition, by using OS transistors in memory cells, information written to the memory cells can be retained for a long time even when power supply to the memory cells is stopped. Thus, power supply to part or all of the peripheral circuit 311 can be stopped during a period when information reading and writing is not required.

[0190] One semiconductor device 100 may be electrically connected to all the memory cells. Alternatively, a plurality of semiconductor devices 100 may be provided for the memory device 300 so that each column or each plurality of columns of memory cells may be electrically connected to one semiconductor device 100. Alternatively, each row or each plurality of rows of memory cells may be electrically connected to one semiconductor device 100. Alternatively, a plurality of memory cells in the cell array may be divided into a plurality of blocks, and a semiconductor device 100 may be provided in each block or each plurality of blocks.

[0191] The storage unit described in this embodiment can be used as a storage element such as a register or a cache memory in a CPU or a GPU.

[0192] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0193] (Implementation 3)

[0194] In this embodiment, a cross-sectional structure example of the storage device 300 is described with reference to the drawings.

[0195] <Configuration Example of Storage Device>

[0196] Fig.11 A partial cross section of the storage device 300 is shown. Fig.11 The memory device 300 shown includes a layer 310 and a layer 320 stacked on a substrate 231 . Fig.11The case where a single crystal semiconductor substrate (for example, a single crystal silicon substrate) is used as the substrate 231 is shown.

[0197] [Layer 310]

[0198] exist Fig.11 In FIG. 2 , layer 310 includes transistor 233 a , transistor 233 b , and transistor 233 c on substrate 231 . Fig.11 A cross section of the transistor 233a, the transistor 233b, and the transistor 233c in the channel length direction is shown.

[0199] Channels of the transistor 233a, the transistor 233b, and the transistor 233c are formed in a portion of the substrate 231. When the integrated circuit is required to operate at high speed, a single crystal semiconductor substrate is preferably used as the substrate 231.

[0200] The transistor 233a, the transistor 233b, and the transistor 233c are electrically isolated from each other by the element isolation layer 232. The element isolation layer can be formed by a LOCOS (Local Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, or the like.

[0201] In addition, an insulating layer 234 is provided on the substrate 231, and insulating layers 235 and 237 are provided on the transistors 233a, 233b, and 233c. An electrode 238 is buried in the insulating layer 237. The electrode 238 is electrically connected to one of the source and the drain of the transistor 233a through a contact plug 236.

[0202] In addition, insulating layers 239 , 240 , and 241 are provided on the electrode 238 and the insulating layer 237 , and an electrode 242 is buried in the insulating layers 239 , 240 , and 241 . The electrode 242 is electrically connected to the electrode 238 .

[0203] In addition, insulating layers 243 and 244 are provided on the electrode 242 and the insulating layer 241 , and an electrode 245 is buried in the insulating layers 243 and 244 . The electrode 245 is electrically connected to the electrode 242 .

[0204] In addition, insulating layers 246 and 247 are provided on the electrode 245 and the insulating layer 244 , and an electrode 249 is buried in the insulating layers 246 and 247 . The electrode 249 is electrically connected to the electrode 245 .

[0205] In addition, insulating layers 248 and 250 are provided on the electrode 249 and the insulating layer 247 , and an electrode 251 is buried in the insulating layers 248 and 250 . The electrode 251 is electrically connected to the electrode 249 .

[0206] [Layer 320]

[0207] Layer 320 is disposed on layer 310. Layer 320 includes a transistor 368a, a transistor 368b, a capacitor 369a, and a capacitor 369b. Fig.11 The cross section of the transistor 368a and the transistor 368b in the channel length direction is shown. The transistor 368a and the transistor 368b are transistors including a back gate.

[0208] The transistor 368a and the transistor 368b correspond to the transistor M11 described in the above embodiment. Therefore, an oxide semiconductor which is a type of metal oxide is preferably used as the semiconductor layer of the transistor 368a and the transistor 368b. That is, the transistor 368a and the transistor 368b are preferably OS transistors.

[0209] The transistor 368a and the transistor 368b are provided on the insulating layer 361 and the insulating layer 362. In addition, the insulating layer 363 and the insulating layer 364 are provided on the insulating layer 362. The back gates of the transistor 368a and the transistor 368b are buried in the insulating layer 363 and the insulating layer 364. The insulating layer 365 and the insulating layer 366 are provided on the insulating layer 364. In addition, the electrode 367 is buried in the insulating layer 361 to the insulating layer 366. The electrode 367 is electrically connected to the electrode 251.

[0210] Insulating layers 371, 372, and 373 are formed over the transistor 368a, the transistor 368b, the capacitor 369a, and the capacitor 369b, and an electrode 375 is formed over the insulating layer 373. The electrode 375 is electrically connected to the electrode 367 through a contact plug 374.

[0211] In addition, insulating layers 376, 377, 378, and 379 are provided on the electrode 375. In addition, an electrode 380 is buried in the insulating layers 376 to 379. The electrode 380 and the electrode 375 are electrically connected.

[0212] In addition, an insulating layer 381 and an insulating layer 382 are provided on the electrode 380 and the insulating layer 379 .

[0213] <Deformation Example>

[0214] Fig.12 A cross section of a portion of a memory device 300A is shown. The memory device 300A is a modified example of the memory device 300. The memory device 300A includes a layer 310A and a layer 320. An insulating substrate (eg, a glass substrate) is used as a substrate 231 of the memory device 300A.

[0215] Layer 310A includes transistor 268a, transistor 268b, and capacitor 269a. Thin film transistors (e.g., OS transistors) are used as transistors in layer 310A. Layer 310A can be made into a unipolar integrated circuit by using OS transistors as transistors in layer 310A. By making all transistors in memory device 300A OS transistors, memory device 300A can be made into a unipolar memory device.

[0216] <Constitution Materials>

[0217] [Substrate]

[0218] Although there are no major restrictions on the materials that can be used for the substrate, the substrate must have at least a sufficiently high heat resistance to withstand the subsequent heat treatment. For example, as a substrate, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate made of silicon germanium, etc., etc. can be used. In addition, an SOI substrate or a substrate having semiconductor elements such as strained transistors or FIN-type transistors arranged on a semiconductor substrate can also be used. In addition, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium nitride, indium phosphide, silicon germanium, etc. that can be used for high electron mobility transistors (HEMT: High Electron Mobility Transistor) can also be used. In other words, the substrate is not only a supporting substrate, but can also be a substrate on which other devices such as transistors are formed.

[0219] In addition, as the substrate, a glass substrate such as barium borosilicate glass and aluminum borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. can be used. In addition, as the substrate, a flexible substrate can be used. When a flexible substrate is used, transistors and capacitors can be directly manufactured on the flexible substrate, or transistors and capacitors can be manufactured on other manufacturing substrates and then peeled off and transferred to the flexible substrate. In addition, in order to peel off transistors and capacitors from the manufacturing substrate and transfer them to the flexible substrate, it is preferred to provide a peeling layer between the manufacturing substrate and the transistors and capacitors.

[0220] As the flexible substrate, for example, metal, alloy, resin or glass, or fibers thereof can be used. The lower the linear expansion coefficient of the flexible substrate used as the substrate, the more deformation caused by the environment is suppressed, so it is preferred. For example, a flexible substrate with a linear expansion coefficient of 1×10 -3 / K or less, 5×10 -5 / K or less or 1×10 -5 / K or less. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic resin, etc. In particular, aramid has a low linear expansion coefficient and is therefore suitable for flexible substrates.

[0221] [Insulation layer]

[0222] The insulating layer is a single layer or a stack of the following materials, and the material is selected from aluminum nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon oxynitride, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, etc. In addition, a material mixed with multiple materials of oxide materials, nitride materials, oxynitride materials, and oxynitride materials can also be used.

[0223] In this specification, etc., nitrogen oxide refers to a compound in which the nitrogen content is greater than the oxygen content. In addition, oxynitride refers to a compound in which the oxygen content is greater than the nitrogen content. In addition, for example, the content of each element can be measured using Rutherford backscattering spectroscopy (RBS: Rutherford Backscattering Spectrometry) or the like.

[0224] In addition, when an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer, in order to prevent the hydrogen concentration in the semiconductor layer from increasing, it is preferable to reduce the hydrogen concentration in the insulating layer. Specifically, the hydrogen concentration in the insulating layer measured by secondary ion mass spectrometry (SIMS) is 2×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 5×10 18 atoms / cm 3 In particular, it is preferable to reduce the hydrogen concentration in the insulating layer in contact with the semiconductor layer.

[0225] In order to prevent the nitrogen concentration in the semiconductor layer from increasing, it is preferable to reduce the nitrogen concentration in the insulating layer. Specifically, the nitrogen concentration in the insulating layer measured by SIMS is 5×10 19 atoms / cm 3 Below, preferably 5×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 the following.

[0226] The insulating layer preferably has fewer defects in at least the region in contact with the semiconductor layer, and typically the signal observed by the electron spin resonance method (ESR) is preferably smaller. For example, as the above signal, an E' center observed when the g value is 2.001 can be cited. The E' center is caused by a dangling bond of silicon. For example, when a silicon oxide layer or a silicon oxynitride layer is used as the insulating layer, a spin density of 3×10 17 spins / cm 3 Below, preferably 5×10 16 spins / cm 3 The following silicon oxide layer or silicon oxynitride layer.

[0227] Sometimes, in addition to the above signals, a signal caused by nitrogen dioxide (NO2) is observed. This signal is split into three signals due to the nuclear spin of N, each with a g value of 2.037 or more and 2.039 or less (first signal), a g value of 2.001 or more and 2.003 or less (second signal), and a g value of 1.964 or more and 1.966 or less (third signal).

[0228] For example, it is preferable to use a signal derived from nitrogen dioxide (NO2) with a spin density of 1×10 17 spins / cm 3 Above and below 1×10 18 spins / cm 3 insulation layer.

[0229] Nitrogen dioxide (NO2) and other nitrogen oxides (NO x ) forms an energy level in the insulating layer. This energy level is located in the energy gap of the oxide semiconductor layer. x ) diffuses to the interface between the insulating layer and the oxide semiconductor layer, sometimes this energy level captures electrons on the insulating layer side. As a result, the captured electrons remain near the interface between the insulating layer and the oxide semiconductor layer, thereby causing the threshold voltage of the transistor to drift in the positive direction. Therefore, by using a film with a low content of oxynitride as the insulating layer, the drift of the threshold voltage of the transistor can be reduced.

[0230] As nitrogen oxides (NO x For example, an insulating layer with a low release amount of ammonia can be a silicon oxynitride layer. The silicon oxynitride layer has a lower release amount of ammonia than nitrogen oxides (NO x ) release, typically 1×10 18 Molecules / cm 3 Above and 5×10 19Molecules / cm 3 Note that the above-mentioned ammonia release amount is the total amount in the range of the heat treatment temperature in TDS being 50° C. to 650° C. or 50° C. to 550° C.

[0231] Since nitrogen oxides (NO x ) reacts with ammonia and oxygen, so by using an insulating layer that releases a lot of ammonia, nitrogen oxides (NO x ).

[0232] At least one of the insulating layers in contact with the oxide semiconductor layer is preferably formed using an insulating layer that releases oxygen by heating. Specifically, it is preferable to use an insulating layer whose oxygen release amount converted to oxygen atoms when TDS analysis is performed (wherein the layer surface temperature is heated to 100° C. to 700° C., preferably 100° C. to 500° C.) is 1.0×10 18 atoms / cm 3 Above, 1.0×10 19 atoms / cm 3 Above, or 1.0×10 20 atoms / cm 3 Note that oxygen released by heating is also referred to as "excess oxygen" in this specification and the like.

[0233] The insulating layer containing excess oxygen can also be formed by adding oxygen to the insulating layer. As the oxygen addition treatment, heat treatment in an oxygen atmosphere, plasma treatment, etc. can be used. Alternatively, oxygen addition can be performed by ion implantation, ion doping, plasma immersion ion implantation, etc. Examples of the gas used for the oxygen addition treatment include 16 O2 or 18 Oxygen gas such as O2, nitrous oxide gas, ozone gas, etc. Oxygen-containing gas. In this specification, the process of adding oxygen is also referred to as "oxygen doping process." The oxygen doping process can also be performed while heating the substrate.

[0234] As the insulating layer, a heat-resistant organic material such as polyimide, acrylic resin, benzocyclobutene resin, polyamide, epoxy resin, etc. can be used. In addition to the above-mentioned organic materials, low-k materials, siloxane resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can also be used. In addition, the insulating layer can also be formed by stacking a plurality of insulating layers formed of these materials.

[0235] Siloxane resins are equivalent to resins containing Si-O-Si bonds formed using siloxane materials as starting materials. Siloxane resins may also use organic groups (such as alkyl groups or aryl groups) or fluorine groups as substituents. In addition, the organic groups may also include fluorine groups.

[0236] There is no particular limitation on the method for forming the insulating layer. Note that a baking process may be required depending on the material used for the insulating layer. In this case, the baking process of the insulating layer can be combined with other heat treatment processes to efficiently manufacture the transistor.

[0237] [electrode]

[0238] As the conductive material for forming the electrode, a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, etc. can be used. In addition, a semiconductor with high conductivity represented by polycrystalline silicon containing impurity elements such as phosphorus, a silicide such as nickel silicide, etc. can also be used.

[0239] In addition, a conductive material containing the above-mentioned metal element and oxygen can also be used. In addition, a conductive material containing the above-mentioned metal element and nitrogen can also be used. For example, a conductive material containing nitrogen such as titanium nitride and tantalum nitride can be used. In addition, indium tin oxide (ITO: Indium Tin Oxide), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium gallium zinc oxide, and indium tin oxide added with silicon can also be used. In addition, indium gallium zinc oxide containing nitrogen can also be used.

[0240] In addition, a plurality of conductive layers formed of the above-mentioned materials may be stacked for use. For example, a laminated structure may be formed by combining a material containing the above-mentioned metal element with a conductive material containing oxygen. In addition, a laminated structure may be formed by combining a material containing the above-mentioned metal element with a conductive material containing nitrogen. In addition, a laminated structure may be formed by combining a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen. In addition, a laminated structure may be formed by combining a conductive material containing nitrogen and a conductive material containing oxygen.

[0241] In addition, when an oxide semiconductor is used as the semiconductor layer and a stacked structure of a material containing the above-mentioned metal element and a conductive material containing oxygen is used as the gate, it is preferable to provide a conductive material containing oxygen on one side of the semiconductor layer. By providing a conductive material containing oxygen on one side of the semiconductor layer, oxygen released from the conductive material can be easily supplied to the semiconductor layer.

[0242] In addition, as an electrode, for example, a highly embedded conductive material such as tungsten or polysilicon can be used. In addition, a combination of a highly embedded conductive material and a barrier layer (diffusion prevention layer) such as a titanium layer, a titanium nitride layer, or a tantalum nitride layer can also be used. Sometimes the electrode is called a "contact plug".

[0243] In particular, it is preferable to use a conductive material that does not easily allow impurities to pass through as an electrode in contact with the gate insulating layer. As an example of a conductive material that does not easily allow impurities to pass through, tantalum nitride can be mentioned.

[0244] By using an insulating material that is not easily permeable to impurities as an insulating layer and a conductive material that is not easily permeable to impurities as an electrode, it is possible to further suppress the diffusion of impurities into the transistor. As a result, the reliability of the transistor can be further improved. In other words, the reliability of the storage device can be further improved.

[0245] [Semiconductor layer]

[0246] As the semiconductor layer, one or more of a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or an amorphous semiconductor can be used. As the semiconductor material, for example, silicon or germanium can be used. In addition, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, nitride semiconductors, or organic semiconductors can also be used.

[0247] When an organic semiconductor is used as the semiconductor layer, a low molecular weight organic material having an aromatic ring or a π-electron conjugated conductive polymer can be used. For example, rubrene, tetracene, pentacene, perylene diimide, tetracyanoquinodimethane, polythiophene, polyacetylene, polyparaphenylene vinylene, etc. can be used.

[0248] The semiconductor layer may also adopt a stacked structure. When the semiconductor layer adopts a stacked structure, semiconductors with different crystal states or different semiconductor materials may be used.

[0249] In addition, since the band gap of an oxide semiconductor, which is a type of metal oxide, is greater than 2 eV, when an oxide semiconductor is used as a semiconductor layer, a transistor with extremely small off-state current can be realized. Specifically, the off-state current per 1 μm channel width can be less than 1×10 -20 A, less than 1×10 -22 A, or less than 1×10 -24A. That is, the on-off ratio can be more than 20 digits. In addition, in a transistor using an oxide semiconductor as a semiconductor layer (OS transistor), the insulation withstand voltage between the source and the drain is high. Thus, a transistor with good reliability can be provided. In addition, a transistor with a large output voltage and a high withstand voltage can be provided. In addition, a storage device with good reliability can be provided. In addition, a storage device with a large output voltage and a high withstand voltage can be provided.

[0250] In this specification and the like, a transistor using crystalline silicon in a semiconductor layer forming a channel is referred to as a "crystalline Si transistor".

[0251] Compared with OS transistors, crystalline Si transistors can easily obtain higher mobility. On the other hand, it is difficult for crystalline Si transistors to achieve an extremely small off-state current like OS transistors. Therefore, it is important to appropriately select the semiconductor material used for the semiconductor layer according to the purpose or use. For example, a combination of OS transistors and crystalline Si transistors, etc., can be used according to the purpose or use.

[0252] When an oxide semiconductor layer is used as a semiconductor layer, it is preferred to form the oxide semiconductor layer by a sputtering method. When the oxide semiconductor layer is formed by a sputtering method, the density of the oxide semiconductor layer can be increased, so it is preferred. In the case of forming the oxide semiconductor layer by a sputtering method, as a sputtering gas, a rare gas (typically argon), oxygen, or a mixed gas of a rare gas and oxygen can be used. In addition, the sputtering gas needs to be highly purified. For example, as an oxygen gas or a rare gas used as a sputtering gas, a high-purity gas with a dew point of less than -60°C, preferably less than -100°C, is used. By using a high-purity sputtering gas to form a thin film, it is possible to prevent moisture and the like from mixing into the oxide semiconductor layer as much as possible.

[0253] When the oxide semiconductor layer is formed by sputtering, it is preferable to remove as much water as possible from the film forming chamber of the sputtering device. For example, it is preferable to use an adsorption vacuum pump such as a cryopump to evacuate the film forming chamber to a high vacuum (to 5×10 -7 Pa to 1×10 -4 In particular, when the sputtering device is in standby mode, the partial pressure of the gas molecules corresponding to H2O (the gas molecules corresponding to m / z = 18) in the film forming processing chamber is 1×10 -4 Pa or less, preferably 5×10 -5 Below Pa.

[0254] [Metal oxides]

[0255] The oxide semiconductor, which is a type of metal oxide, preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition, it is preferred that, in addition to these, it also contains aluminum, gallium, yttrium or tin. In addition, it may also contain one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten and magnesium.

[0256] Here, the case where the oxide semiconductor includes indium, element M, and zinc is considered. Note that element M is aluminum, gallium, yttrium, or tin. Other elements that can be used as element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium in addition to the above elements. Note that as element M, a plurality of the above elements may be combined.

[0257] In addition, in this specification and the like, a metal oxide containing nitrogen may be referred to as a metal oxide (metal oxide). In addition, a metal oxide containing nitrogen may also be referred to as a metal oxynitride (metal oxynitride).

[0258] [Composition of Metal Oxides]

[0259] Hereinafter, the configuration of a CAC (Cloud-Aligned Composite)-OS that can be used for the transistor disclosed in one embodiment of the present invention will be described.

[0260] In this specification, etc., it may be described as CAAC (c-axis aligned crystal) or CAC (Cloud-Aligned Composite). Note that CAAC is an example of a crystal structure, and CAC is an example of a function or a material composition.

[0261] CAC-OS or CAC-metal oxide has a conductive function in a part of the material, an insulating function in another part of the material, and has a semiconductor function as a whole. In addition, when CAC-OS or CAC-metal oxide is used in the active layer of a transistor, the conductive function is to allow electrons (or holes) used as carriers to flow through, and the insulating function is to prevent electrons used as carriers from flowing through. Through the complementary effects of the conductive function and the insulating function, CAC-OS or CAC-metal oxide can have a switching function (a function of controlling on / off). By separating each function in CAC-OS or CAC-metal oxide, each function can be maximized.

[0262] In addition, CAC-OS or CAC-metal oxide includes a conductive region and an insulating region. The conductive region has the function of the above-mentioned conductivity, and the insulating region has the function of the above-mentioned insulation. In addition, in the material, the conductive region and the insulating region are sometimes separated with a nanoparticle level. In addition, the conductive region and the insulating region are sometimes distributed unevenly in the material. In addition, sometimes the conductive region whose edge is fuzzy and connected with a cloud shape is observed.

[0263] In CAC-OS or CAC-metal oxide, the conductive region and the insulating region may be dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm.

[0264] In addition, CAC-OS or CAC-metal oxide is composed of components with different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component with a wide gap caused by an insulating region and a component with a narrow gap caused by a conductive region. In this structure, carriers mainly flow through the component with a narrow gap. In addition, the component with a narrow gap interacts with the component with a narrow gap through a complementary effect with the component with a wide gap, so that carriers flow through the component with a wide gap. Therefore, when the above-mentioned CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, a high current driving force, that is, a large on-state current and a high field effect mobility can be obtained in the on-state of the transistor.

[0265] That is, CAC-OS or CAC-metal oxide may also be referred to as a matrix composite material (matrix composite) or a metal matrix composite material (metal matrix composite).

[0266] [Structure of Metal Oxide]

[0267] Oxide semiconductors, which are a type of metal oxide, are classified into single crystal oxide semiconductors and non-single crystal oxide semiconductors. Examples of non-single crystal oxide semiconductors include CAAC-OS (c-axis aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0268] CAAC-OS has c-axis orientation, and its multiple nanocrystals are connected in the ab plane direction and the crystal structure has distortion. Note that distortion refers to the part where the lattice arrangement direction changes between the region where the multiple nanocrystals are connected and the region where the lattice arrangement is consistent.

[0269] Although nanocrystals are basically hexagonal, they are not limited to regular hexagons, and there are cases where they are not regular hexagons. In addition, in the distortion, there is sometimes a lattice arrangement such as a pentagon or a heptagon. In addition, in CAAC-OS, no clear grain boundary is observed even near the distortion. That is, it can be seen that the formation of grain boundaries can be suppressed due to the distortion of the lattice arrangement. This is because CAAC-OS can accommodate distortion due to the low density of oxygen atoms arranged in the ab plane direction or the change in the bonding distance between atoms caused by the substitution of metal elements.

[0270] CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing element M, zinc, and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. In addition, indium and element M can replace each other. When indium replaces element M in the (M, Zn) layer, the layer can also be represented as an (In, M, Zn) layer. In addition, when indium in the In layer is replaced by element M, the layer can also be represented as an (In, M) layer.

[0271] CAAC-OS is a metal oxide with high crystallinity. On the other hand, it is not easy to observe clear grain boundaries in CAAC-OS, so it is not easy to cause a decrease in electron mobility due to grain boundaries. In addition, the crystallinity of metal oxides is sometimes reduced due to the entry of impurities or the generation of defects, so it can be said that CAAC-OS is a metal oxide with few impurities or defects (oxygen vacancies, etc.). Therefore, the physical properties of the metal oxide containing CAAC-OS are stable. Therefore, the metal oxide containing CAAC-OS has high heat resistance and high reliability.

[0272] In nc-OS, the atomic arrangement in a tiny region (e.g., a region between 1 nm and 10 nm, especially a region between 1 nm and 3 nm) is periodic. In addition, in nc-OS, no regularity of crystal orientation is observed between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, sometimes nc-OS is no different from a-like OS or amorphous oxide semiconductors in some analysis methods.

[0273] a-likeOS is a metal oxide having a structure between nc-OS and amorphous oxide semiconductor. a-likeOS contains voids or low-density regions. In other words, the crystallinity of a-likeOS is lower than that of nc-OS and CAAC-OS.

[0274] Oxide semiconductors (metal oxides) have various structures and various characteristics. Oxide semiconductors may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

[0275] [Transistor with metal oxide]

[0276] Next, a case where the above-mentioned metal oxide is used for a channel formation region of a transistor will be described.

[0277] By using the above-mentioned metal oxide in the channel formation region of a transistor, a transistor with high field effect mobility can be realized. In addition, a transistor with high reliability can be realized.

[0278] In addition, metal oxides with low carrier density are preferably used for transistors. When the carrier density of a metal oxide film is to be reduced, the impurity concentration in the metal oxide film can be reduced to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as "high-purity intrinsic" or "substantially high-purity intrinsic". For example, the carrier density in a metal oxide can be less than 8×10 11 / cm 3 , preferably less than 1×10 11 / cm 3 , more preferably less than 1×10 10 / cm 3 , and is 1×10 -9 / cm 3 above.

[0279] Furthermore, high purity intrinsic or substantially high purity intrinsic metal oxide films have a lower defect state density and thus sometimes have a lower trap state density.

[0280] Furthermore, it takes a long time for the charges trapped in the trap states of the metal oxide to disappear, and they may behave like fixed charges. Therefore, the electrical characteristics of a transistor having a channel formation region in a metal oxide with a high trap state density may be unstable.

[0281] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the metal oxide. In order to reduce the impurity concentration in the metal oxide, it is preferable to also reduce the impurity concentration in the nearby film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, etc.

[0282] [Impurities]

[0283] Here, the influence of each impurity in the metal oxide is described.

[0284] When the metal oxide contains silicon or carbon, which is one of the elements of Group 14, a defect level is formed in the metal oxide. Therefore, the concentration of silicon or carbon in the metal oxide or near the interface of the metal oxide (the concentration measured by secondary ion mass spectrometry (SIMS)) is set to 2×10 18 atoms / cm 3 Below, preferably 2×10 17 atoms / cm 3 the following.

[0285] In addition, when the metal oxide contains an alkali metal or an alkaline earth metal, a defect level is sometimes formed to form a carrier. Therefore, a transistor using a metal oxide containing an alkali metal or an alkaline earth metal as a channel formation region tends to have a normally-on characteristic. Therefore, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the metal oxide. Specifically, the concentration of the alkali metal or alkaline earth metal in the metal oxide measured by SIMS is set to 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 the following.

[0286] When the metal oxide contains nitrogen, electrons as carriers are easily generated, which increases the carrier density and turns into n-type. As a result, a transistor using a metal oxide containing nitrogen in a channel formation region tends to have a normally-on characteristic. Therefore, in the metal oxide, it is preferable to reduce the nitrogen in the channel formation region as much as possible. For example, the nitrogen concentration in the metal oxide measured by SIMS is less than 5×10 19 atoms / cm 3 , preferably 5×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 the following.

[0287] Hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to generate water, thus sometimes forming an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons as carriers are sometimes generated. In addition, sometimes electrons as carriers are generated because part of the hydrogen is bonded to the oxygen bonded to the metal atom. Therefore, a transistor using a metal oxide containing hydrogen as a channel formation region tends to have a normally-on characteristic. Therefore, it is preferred to reduce the hydrogen in the metal oxide as much as possible. Specifically, in the metal oxide, the hydrogen concentration measured by SIMS is set to less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , and more preferably less than 1×10 18 atoms / cm 3 .

[0288] By using a metal oxide whose impurity concentration is sufficiently reduced for a channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0289] <Film Formation Method>

[0290] The insulating material used to form the insulating layer, the conductive material used to form the electrode, or the semiconductor material used to form the semiconductor layer can be formed by sputtering, spin coating, chemical vapor deposition (CVD: Chemical Vapor Deposition) method (including thermal CVD method, organic metal CVD (MOCVD: Metal Organic Chemical Vapor Deposition) method, plasma enhanced CVD (PECVD: Plasma Enhanced CVD) method, high density plasma CVD (HDPCVD: High density plasmaCVD) method, reduced pressure CVD (LPCVD: low pressure CVD) method, atmospheric pressure CVD (APCVD: atmospheric pressure CVD) method, etc.), atomic layer deposition (ALD: Atomic Layer Deposition) method or molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method, pulsed laser deposition (PLD: Pulsed Laser Deposition) method, dip coating, spraying, droplet jetting method (inkjet method, etc.), printing method (screen printing, offset printing, etc.).

[0291] The plasma CVD method can obtain a high-quality film at a relatively low temperature. In the case of a film forming method that does not use plasma, such as the MOCVD method, the ALD method, or the thermal CVD method, damage is not easily generated on the formed surface. For example, the wiring, electrodes, elements (transistors, capacitors, etc.) included in the storage device sometimes generate charge accumulation (charge up) due to receiving charges from plasma. At this time, the wiring, electrodes, elements, etc. included in the storage device are sometimes damaged due to the accumulated charges. On the other hand, in the case of a film forming method that does not use plasma, since such plasma damage does not occur, the yield of the storage device can be improved. In addition, since plasma damage does not occur during film formation, a film with fewer defects can be obtained.

[0292] Unlike the film-forming method of depositing particles released from a target material, the CVD method and the ALD method are film-forming methods that form a film due to a reaction on the surface of the object to be processed. Therefore, the film formed by the CVD method and the ALD method is not easily affected by the shape of the object to be processed, and has good step coverage. In particular, the film formed by the ALD method has good step coverage and thickness uniformity, so the ALD method is suitable for covering the surface of an opening with a high aspect ratio. However, the film-forming speed of the ALD method is relatively slow, so it is sometimes preferred to be used in combination with other film-forming methods such as the CVD method with a fast film-forming speed.

[0293] The CVD method and the ALD method can control the composition of the obtained film by adjusting the flow ratio of the source gases. For example, when the CVD method and the ALD method are used, a film of any composition can be formed by adjusting the flow ratio of the source gases. In addition, for example, when the CVD method and the ALD method are used, a film whose composition continuously changes can be formed by changing the flow ratio of the source gases while forming the film. When the film is formed while changing the flow ratio of the source gases, the time required for conveying and adjusting the pressure can be omitted, so the time required for film formation can be shortened compared to the case where the film is formed using multiple film forming chambers. Therefore, the productivity of the storage device can sometimes be improved.

[0294] Note that when the film is formed by the ALD method, it is preferable to use a gas that does not contain chlorine as a material gas.

[0295] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0296] (Implementation 4)

[0297] In this embodiment, a structural example of a transistor which can be used for the semiconductor device or the like described in the above embodiment will be described.

[0298] <Structural Example 1 of Transistor>

[0299] Reference Fig.13A , Fig. 13B and Fig. 13C An example of the structure of the transistor 510 is described. Fig.13A is a top view of transistor 510 . Fig. 13B It is shown Fig.13A A cross-sectional view of the portion indicated by the dot-dash line L1-L2. Fig. 13C It is shown Fig.13A The cross-sectional view of the portion indicated by the dot-dash line W1-W2. Fig.13A In the top view, for the sake of clarity, some of the components in the drawing are omitted.

[0300] exist Fig.13A , Fig. 13B and Fig. 13C 5 shows a transistor 510, an insulating layer 511, an insulating layer 512, an insulating layer 514, an insulating layer 516, an insulating layer 580, an insulating layer 582, and an insulating layer 584 which function as an interlayer film. In addition, a conductive layer 546 (a conductive layer 546a and a conductive layer 546b) which functions as a contact plug electrically connected to the transistor 510 and a conductive layer 503 which functions as a wiring are also shown.

[0301] The transistor 510 includes: a conductive layer 560 (conductive layer 560a and conductive layer 560b) used as a first gate; a conductive layer 505 (conductive layer 505a and conductive layer 505b) used as a second gate; an insulating layer 550 used as a first gate insulating film; insulating layers 521, 522 and 524 used as a second gate insulating layer; an oxide 530 (oxide 530a, oxide 530b and oxide 530c) having a region for forming a channel; a conductive layer 540a used as one of a source and a drain; a conductive layer 540b used as the other of a source and a drain; and an insulating layer 574.

[0302] In addition, FIG. 13A to FIG. 13C In the transistor 510 shown in the figure, an oxide 530c, an insulating layer 550, and a conductive layer 560 are arranged in an opening in an insulating layer 580 via an insulating layer 574. In addition, the oxide 530c, the insulating layer 550, and the conductive layer 560 are arranged between the conductive layer 540a and the conductive layer 540b.

[0303] The insulating layer 511 and the insulating layer 512 function as an interlayer film.

[0304] As the interlayer film, for example, a single layer or a stack of insulators such as silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (Ba, Sr)TiO3 (BST) can be used. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide can be added to the above-mentioned insulators. Alternatively, the above-mentioned insulators can also be nitrided, and silicon oxide, silicon oxynitride or silicon nitride can also be stacked on the above-mentioned insulators.

[0305] For example, the insulating layer 511 is preferably used as a barrier film for suppressing impurities such as water or hydrogen from mixing into the transistor 510 from the substrate side. Therefore, the insulating layer 511 preferably uses an insulating material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (not allowing the above impurities to pass through). In addition, it is preferred to use an insulating material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (not allowing the above oxygen to pass through). In addition, for example, aluminum oxide or silicon nitride can be used as the insulating layer 511. By adopting this structure, impurities such as hydrogen and water can be suppressed from diffusing from the substrate side to the transistor 510 side through the insulating layer 511.

[0306] For example, the dielectric constant of the insulating layer 512 is preferably lower than the dielectric constant of the insulating layer 511. By using a material having a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0307] The conductive layer 503 is formed in a manner of embedding the insulating layer 512. Here, the top surface height of the conductive layer 503 can be made substantially the same as the top surface height of the insulating layer 512. Note that although an example of a single-layer structure of the conductive layer 503 is shown, the present invention is not limited thereto. For example, the conductive layer 503 may also have a multilayer film structure of more than two layers. In addition, the conductive layer 503 preferably uses a highly conductive material having tungsten, copper, or aluminum as a main component.

[0308] In transistor 510, conductive layer 560 is sometimes used as a first gate (also called a top gate). In addition, conductive layer 505 is sometimes used as a second gate (also called a bottom gate) electrode. In this case, the threshold voltage of transistor 510 can be controlled by changing the potential applied to conductive layer 505 alone without linking it with the potential applied to conductive layer 560. In particular, by applying a negative potential to conductive layer 505, the threshold voltage of transistor 510 can be made greater than 0V, thereby reducing the off-state current. Therefore, applying a negative potential to conductive layer 505 can reduce the drain current when the potential applied to conductive layer 560 is 0V, compared with the case where a negative potential is not applied.

[0309] In addition, for example, by stacking conductive layer 505 and conductive layer 560 , when a potential is applied to conductive layer 560 and conductive layer 505 , the electric field generated by conductive layer 560 is connected to the electric field generated by conductive layer 505 , so that a channel formation region formed in oxide 530 can be covered.

[0310] That is, the channel formation region can be electrically surrounded by the electric field of the conductive layer 560 used as the first gate and the electric field of the conductive layer 505 used as the second gate. In this specification, the structure of the transistor in which the channel formation region is electrically surrounded by the electric field of the first gate and the electric field of the second gate is referred to as a surrounded channel (S-channel) structure.

[0311] The insulating layer 514 and the insulating layer 516 are used as an interlayer film in the same manner as the insulating layer 511 or the insulating layer 512. For example, the insulating layer 514 is preferably used as a barrier film for suppressing impurities such as water or hydrogen from being mixed into the transistor 510 from the substrate side. By adopting this structure, it is possible to suppress impurities such as hydrogen and water from diffusing from the substrate side to the transistor 510 side through the insulating layer 514. For example, the dielectric constant of the insulating layer 516 is preferably lower than the dielectric constant of the insulating layer 514. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0312] The conductive layer 505 used as the second gate is formed with a conductive layer 505a in contact with the inner wall of the opening of the insulating layer 514 and the insulating layer 516, and a conductive layer 505b is formed on the inner side. Here, the height of the top surface of the conductive layer 505a and the conductive layer 505b can be substantially the same as the height of the top surface of the insulating layer 516. Note that although the transistor 510 shows a structure in which the conductive layer 505a and the conductive layer 505b are stacked, the present invention is not limited to this. For example, the conductive layer 505 can be a single layer or a stacked structure of more than three layers.

[0313] Here, the conductive layer 505a preferably uses a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (making it difficult for the above impurities to pass through). In addition, it is preferred to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (making it difficult for the above oxygen to pass through). In this specification, etc., "the function of suppressing the diffusion of impurities or oxygen" refers to the function of suppressing the diffusion of any one or all of the above impurities and the above oxygen.

[0314] For example, by providing the conductive layer 505a with a function of suppressing oxygen diffusion, oxidation of the conductive layer 505b and a decrease in conductivity can be suppressed.

[0315] In addition, when the conductive layer 505 also has the function of wiring, the conductive layer 505b is preferably made of a highly conductive material having tungsten, copper, or aluminum as a main component. In this case, it is not necessary to provide the conductive layer 503. Note that although the conductive layer 505b is shown as a single-layer structure in the drawings, a stacked-layer structure may be adopted, for example, a stacked-layer structure of titanium, titanium nitride, and the above conductive materials may be adopted.

[0316] The insulating layer 521 , the insulating layer 522 , and the insulating layer 524 have a function of serving as a second gate insulator.

[0317] Note that the insulating layer 522 preferably has a barrier property. When the insulating layer 522 has a barrier property, impurities such as hydrogen can be prevented from entering the transistor 510 from the periphery of the transistor 510 .

[0318] The insulating layer 522 preferably uses a single layer or a stack of insulators containing so-called high-k materials such as aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (Ba, Sr)TiO3 (BST). When miniaturization and high integration of transistors are carried out, problems such as leakage current sometimes occur due to the thin film of the gate insulator. By using a high-k material as an insulator used as a gate insulator, the gate potential when the transistor is operating can be reduced while maintaining the physical thickness.

[0319] For example, the insulating layer 521 preferably has thermal stability. For example, silicon oxide and silicon oxynitride are thermally stable and therefore preferred. In addition, by combining an insulator of a high-k material with silicon oxide or silicon oxynitride, an insulating layer having a laminated structure with thermal stability and a high relative dielectric constant can be formed.

[0320] Note that although FIG. 13A to FIG. 13C , the second gate insulator is shown as a three-layer stacked structure, but a single layer or a stacked structure of more than two layers may be used. In this case, the stacked structure is not limited to a stacked structure composed of the same material, and a stacked structure formed of different materials may also be used.

[0321] The oxide 530 including a region used as a channel formation region includes an oxide 530a, an oxide 530b on the oxide 530a, and an oxide 530c on the oxide 530b. By providing the oxide 530a under the oxide 530b, it is possible to suppress the diffusion of impurities from a structure formed below the oxide 530a to the oxide 530b. In addition, by providing the oxide 530c on the oxide 530b, it is possible to suppress the diffusion of impurities from a structure formed above the oxide 530c to the oxide 530b. As the oxide 530, an oxide semiconductor which is one of the metal oxides shown in the above embodiment can be used.

[0322] Note that the oxide 530c is preferably provided in an opening in the insulating layer 580 via the insulating layer 574. When the insulating layer 574 has a barrier property, diffusion of impurities in the insulating layer 580 into the oxide 530 can be suppressed.

[0323] One of the conductive layer 540a and the conductive layer 540b functions as a source electrode, and the other functions as a drain electrode.

[0324] Conductive layer 540a and conductive layer 540b can be made of a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing them as main components. In particular, metal nitride films such as tantalum nitride are preferred because they have a barrier property against hydrogen or oxygen and have high oxidation resistance.

[0325] In addition, although FIG. 13A to FIG. 13C Although a single-layer structure is shown in the figure, a stacked structure with more than two layers may be used. For example, a stacked layer of a tantalum nitride film and a tungsten film may be used. In addition, a stacked layer of a titanium film and an aluminum film may be used. In addition, a two-layer structure of an aluminum film stacked on a tungsten film, a two-layer structure of a copper film stacked on a copper-magnesium-aluminum alloy film, a two-layer structure of a copper film stacked on a titanium film, and a two-layer structure of a copper film stacked on a tungsten film may be used.

[0326] Alternatively, a three-layer structure may be used in which an aluminum film or a copper film is stacked on a titanium film or a titanium nitride film and a titanium film or a titanium nitride film is formed thereon, or an aluminum film or a copper film is stacked on a molybdenum film or a molybdenum nitride film and a molybdenum film or a molybdenum nitride film is formed thereon. Alternatively, a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0327] Alternatively, a barrier layer may be provided on the conductive layer 540. The barrier layer is preferably made of a substance that has a barrier property against oxygen or hydrogen. With this structure, the conductive layer 540 can be prevented from being oxidized when the insulating layer 574 is formed.

[0328] As the barrier layer, for example, a metal oxide can be used. In particular, an insulating film having barrier properties to oxygen or hydrogen, such as aluminum oxide, hafnium oxide, and gallium oxide, is preferably used. Alternatively, silicon nitride formed by CVD may be used.

[0329] By providing a barrier layer, the range of material selection for the conductive layer 540 can be expanded. For example, a material with low oxidation resistance and high conductivity, such as tungsten or aluminum, can be used for the conductive layer 540. In addition, for example, a conductor that is easy to form or process can be used.

[0330] The insulating layer 550 functions as a first gate insulator. The insulating layer 550 is preferably provided in the opening of the insulating layer 580 via the oxide 530 c and the insulating layer 574 .

[0331] When miniaturization and high integration of transistors are performed, problems such as leakage current sometimes occur due to the thin film of the gate insulator. In this case, the insulating layer 550 can adopt a laminated structure like the second gate insulator. By using an insulator used as a gate insulator with a laminated structure of a high-k material and a thermally stable material, the gate potential of the transistor during operation can be reduced while maintaining the physical film thickness. In addition, a laminated structure that is thermally stable and has a high relative dielectric constant can be adopted.

[0332] The conductive layer 560 used as the first gate has a conductive layer 560a and a conductive layer 560b on the conductive layer 560a. The conductive layer 560a, like the conductive layer 505a, preferably uses a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0333] By providing the conductive layer 560a with a function of suppressing oxygen diffusion, the material selectivity of the conductive layer 560b can be improved. In other words, by providing the conductive layer 560a, oxidation of the conductive layer 560b can be suppressed, thereby preventing a decrease in conductivity.

[0334] As a conductive material having a function of inhibiting oxygen diffusion, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used. In addition, an oxide semiconductor that can be used for oxide 530 can be used as the conductive layer 560a. In this case, by forming the conductive layer 560b by sputtering, the resistance value of the conductive layer 560a can be reduced to make it a conductor. The above-mentioned conductor can be called an OC (Oxide Conductor) electrode.

[0335] The conductive layer 560b preferably uses a conductive material with tungsten, copper or aluminum as a main component. In addition, in order to make the conductive layer 560 have a wiring function, it is preferable to use a conductor with high conductivity. For example, a conductive material with tungsten, copper or aluminum as a main component can be used. In addition, the conductive layer 560b can also adopt a laminated structure, for example, a laminated structure of titanium, titanium nitride and the above conductive materials can be used.

[0336] An insulating layer 574 is disposed between the insulating layer 580 and the transistor 510. An insulating material that can prevent the diffusion of impurities such as water or hydrogen and oxygen is preferably used for the insulating layer 574. For example, aluminum oxide or hafnium oxide is preferably used. In addition, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon oxynitride, or silicon nitride may also be used.

[0337] By providing the insulating layer 574, impurities such as water and hydrogen in the insulating layer 580 can be prevented from diffusing into the oxide 530b through the oxide 530c and the insulating layer 550. In addition, oxidation of the conductive layer 560 by excess oxygen in the insulating layer 580 can be prevented.

[0338] The insulating layer 580 , the insulating layer 582 , and the insulating layer 584 function as an interlayer film.

[0339] The insulating layer 582 is preferably used as a block insulating film for preventing impurities such as water and hydrogen from being introduced into the transistor 510 from the outside, similarly to the insulating layer 514 .

[0340] In addition, similarly to the insulating layer 516, the insulating layer 580 and the insulating layer 584 preferably have a lower dielectric constant than the insulating layer 582. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0341] Alternatively, the transistor 510 may be electrically connected to other components via a plug or wiring such as a conductive layer 546 embedded in the insulating layer 580 , the insulating layer 582 , and the insulating layer 584 .

[0342] In addition, as the material of the conductive layer 546, a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials can be used, as with the conductive layer 505. For example, a high melting point material such as tungsten or molybdenum having heat resistance and conductivity is preferably used. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. By using a low-resistance conductive material, wiring resistance can be reduced.

[0343] For example, by using a stacked-layer structure of tantalum nitride or the like, a conductor having a barrier property against hydrogen and oxygen, and tungsten having high conductivity as the conductive layer 546, diffusion of impurities from the outside can be suppressed while maintaining conductivity as a wiring.

[0344] By having the above structure, a semiconductor device having a transistor including an oxide semiconductor with a large on-state current can be provided. Alternatively, a semiconductor device having a transistor including an oxide semiconductor with a small off-state current can be provided. In addition, a semiconductor device having improved reliability while suppressing changes in electrical characteristics and having stable electrical characteristics can be provided.

[0345] <Structural Example 2 of Transistor>

[0346] Reference Fig.14A , Fig. 14B and Fig. 14C An example of the structure of the transistor 510 is described. Fig.14A is a top view of transistor 520 . Fig. 14B It is along Fig.14A A cross-sectional view of the portion indicated by the dot-dash line L1-L2. Fig. 14C It is along Fig.14A The cross-sectional view of the portion indicated by the dotted line W1-W2. Fig.14A In the top view, some components are omitted for clarity.

[0347] The transistor 520 is a modified example of the transistor 510. Therefore, in order to avoid duplication of description, mainly the difference from the transistor 510 will be described.

[0348] The transistor 520 includes a region overlapping with the conductive layer 540 (the conductive layer 540a and the conductive layer 540b), the oxide 530c, the insulating layer 550, and the conductive layer 560. With this structure, a transistor with high on-state current can be provided. In addition, a transistor with high controllability can be provided.

[0349] The conductive layer 560 used as the first gate has a conductive layer 560a and a conductive layer 560b on the conductive layer 560a. The conductive layer 560a, like the conductive layer 505a, preferably uses a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0350] By providing the conductive layer 560a with a function of suppressing oxygen diffusion, the material selectivity of the conductive layer 560b can be improved. In other words, by providing the conductive layer 560a, oxidation of the conductive layer 560b can be suppressed, thereby preventing a decrease in conductivity.

[0351] In addition, it is preferable to provide an insulating layer 574 so as to cover the top surface and side surfaces of the conductive layer 560, the side surfaces of the insulating layer 550, and the side surfaces of the oxide 530c. It is preferable to use an insulating material that can prevent the diffusion of impurities such as water or hydrogen and oxygen for the insulating layer 574. For example, aluminum oxide or hafnium oxide is preferably used. In addition, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon oxynitride, or silicon nitride may also be used.

[0352] The insulating layer 574 can suppress oxidation of the conductive layer 560. In addition, the insulating layer 574 can suppress diffusion of impurities such as water and hydrogen in the insulating layer 580 into the transistor 520.

[0353] Alternatively, an insulating layer 576 (insulating layer 576a and insulating layer 576b) having a barrier property may be provided between the conductive layer 546 and the insulating layer 580. Providing the insulating layer 576 can prevent the oxygen in the insulating layer 580 from reacting with the conductive layer 546 to cause oxidation of the conductive layer 546.

[0354] In addition, by providing an insulating layer 576 having a barrier property, the range of choices for the material of the conductor used for the plug or wiring can be expanded. For example, by using a metal material with high conductivity that can absorb oxygen as the conductive layer 546, a semiconductor device with low power consumption can be provided. Specifically, a material with low oxidation resistance and high conductivity such as tungsten and aluminum can be used. In addition, for example, a conductor that is easy to form a film or process can be used.

[0355] <Structural Example 3 of Transistor>

[0356] Reference Fig.15A , Fig. 15B and Fig. 15C A structural example of the transistor 535 is described. Fig.15A is a top view of transistor 535. Fig. 15B It is along Fig.15A A cross-sectional view of the L1-L2 portion indicated by the dotted line. Fig. 15C It is along Fig.15A The cross-sectional view of the W1-W2 portion is shown by the dot-dash line. Fig.15A In the top view, some components are omitted for clarity.

[0357] The transistor 535 is a modified example of the transistor 510. Therefore, in order to avoid duplication of description, the difference from the transistor 510 will be mainly described.

[0358] In the transistor 510, part of the insulating layer 574 is provided in the opening portion in the insulating layer 580 to cover the side surface of the conductive layer 560. In the transistor 535, an opening is formed by removing part of the insulating layer 580 and part of the insulating layer 574.

[0359] Alternatively, an insulating layer 576 (insulating layer 576a and insulating layer 576b) having a barrier property may be provided between the conductive layer 546 and the insulating layer 580. Providing the insulating layer 576 can prevent the oxygen in the insulating layer 580 from reacting with the conductive layer 546 to cause oxidation of the conductive layer 546.

[0360] In addition, when an oxide semiconductor is used as the oxide 530, it is preferable to adopt a stacked structure of an oxide in which the atomic number ratios of each metal atom are different from each other. Specifically, in the metal oxide used for the oxide 530a, the atomic number ratio of the element M in the constituent elements is preferably greater than the atomic number ratio of the element M in the constituent elements of the metal oxide used for the oxide 530b. In addition, in the metal oxide used for the oxide 530a, the atomic number ratio of the element M relative to In is preferably greater than the atomic number ratio of the element M relative to In in the metal oxide used for the oxide 530b. In addition, in the metal oxide used for the oxide 530b, the atomic number ratio of In relative to the element M is preferably greater than the atomic number ratio of In relative to the element M in the metal oxide used for the oxide 530a. In addition, the oxide 530c can use a metal oxide that can be used for the oxide 530a or the oxide 530b.

[0361] The oxide 530a, the oxide 530b, and the oxide 530c preferably have crystallinity, and in particular, CAAC-OS is preferably used. Crystalline oxides such as CAAC-OS have a highly crystalline and dense structure with few impurities and defects (oxygen vacancies, etc.). Therefore, it is possible to suppress the extraction of oxygen from the oxide 530b by the source electrode or the drain electrode. Therefore, even if heat treatment is performed, the oxygen extracted from the oxide 530b can be reduced, so the transistor 535 is also stable to the high temperature (so-called thermal budget) in the manufacturing process.

[0362] In addition, one or both of the oxide 530a and the oxide 530c may be omitted. The oxide 530 may also be a single layer of the oxide 530b. When a stack of oxides 530a, 530b, and 530c is used as the oxide 530, it is preferred that the energy of the conduction band bottom of the oxides 530a and 530c is higher than the energy of the conduction band bottom of the oxide 530b. In other words, the electron affinity of the oxides 530a and 530c is preferably smaller than the electron affinity of the oxide 530b. In this case, the oxide 530c preferably uses a metal oxide that can be used for the oxide 530a. Specifically, in the metal oxide used for the oxide 530c, the atomic number ratio of the element M in the constituent elements is preferably greater than the atomic number ratio of the element M in the constituent elements of the metal oxide used for the oxide 530b. In addition, in the metal oxide used for the oxide 530c, the atomic number ratio of the element M relative to In is preferably greater than the atomic number ratio of the element M relative to In in the metal oxide used for the oxide 530b. In addition, in the metal oxide used for the oxide 530b, the atomic number ratio of In to the element M is preferably larger than the atomic number ratio of In to the element M in the metal oxide used for the oxide 530c.

[0363] Here, in the junction of oxide 530a, oxide 530b, and oxide 530c, the energy level of the conduction band bottom changes smoothly. In other words, the above situation can also be expressed as the energy level of the conduction band bottom of the junction of oxide 530a, oxide 530b, and oxide 530c continuously changes or continuously joins. For this reason, it is preferable to reduce the defect state density of the mixed layer formed at the interface between oxide 530a and oxide 530b and the interface between oxide 530b and oxide 530c.

[0364] Specifically, by making the oxide 530a and the oxide 530b, and the oxide 530b and the oxide 530c contain a common element (as a main component) in addition to oxygen, a mixed layer with a low defect state density can be formed. For example, in the case where the oxide 530b is an In-Ga-Zn oxide, In-Ga-Zn oxide, Ga-Zn oxide, and gallium oxide can be used as the oxide 530a and the oxide 530c. In addition, the oxide 530c can have a stacked structure. For example, a stacked structure of In-Ga-Zn oxide and Ga-Zn oxide on the In-Ga-Zn oxide can be used, or a stacked structure of In-Ga-Zn oxide and gallium oxide on the In-Ga-Zn oxide can be used. In other words, as the oxide 530c, a stacked structure of In-Ga-Zn oxide and an oxide that does not contain In can also be used.

[0365] Specifically, as the oxide 530a, a metal oxide with In:Ga:Zn=1:3:4 [atomic ratio] or 1:1:0.5 [atomic ratio] may be used. Also, as the oxide 530b, a metal oxide with In:Ga:Zn=4:2:3 [atomic ratio] or 3:1:2 [atomic ratio] may be used. Also, as the oxide 530c, a metal oxide with In:Ga:Zn=1:3:4 [atomic ratio], In:Ga:Zn=4:2:3 [atomic ratio], Ga:Zn=2:1 [atomic ratio] or Ga:Zn=2:5 [atomic ratio] may be used. In addition, as specific examples of the case where the oxide 530c has a stacked structure, there can be cited a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:1 [atomic ratio], a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:5 [atomic ratio], a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] and gallium oxide, etc.

[0366] At this time, the main path of the carrier is the oxide 530b. By making the oxide 530a and the oxide 530c have the above structure, the defect state density of the interface between the oxide 530a and the oxide 530b and the interface between the oxide 530b and the oxide 530c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, so that the transistor 535 can obtain high on-state current and high frequency characteristics. In addition, when the oxide 530c has a stacked structure, it is expected to reduce the effect of the defect state density of the interface between the above-mentioned oxide 530b and the oxide 530c and the effect of suppressing the diffusion of the constituent elements of the oxide 530c to the insulating layer 550 side. More specifically, when the oxide 530c has a stacked structure, because the oxide that does not contain In is located above the stacked structure, In that will diffuse to the insulating layer 550 side can be suppressed. Since the insulating layer 550 is used as a gate insulator, the characteristics of the transistor are poor when In is diffused therein. Thus, by making the oxide 530c have a stacked structure, a display device with high reliability can be provided.

[0367] As the oxide 530, a metal oxide used as an oxide semiconductor is preferably used. For example, as the metal oxide to be the channel formation region of the oxide 530, a metal oxide having a band gap of 2 eV or more, preferably 2.5 eV or more is preferably used. In this way, by using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced. By using such a transistor, a semiconductor device with low power consumption can be provided.

[0368] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0369] (Implementation 5)

[0370] This embodiment mode describes an example of an electronic component and an electronic device in which the storage device described in the above embodiment mode and the like are mounted.

[0371] <Electronic components>

[0372] First, refer to Fig.16A and Fig. 16B An example of an electronic component in which the storage device 300 is incorporated will be described.

[0373] Fig.16A A perspective view is shown of an electronic component 700 and a substrate (circuit board 704) on which the electronic component 700 is mounted. Fig.16A The electronic component 700 shown is an IC chip, and includes leads and a circuit portion. The electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of these IC chips are combined and electrically connected to each other on the printed circuit board 702, thereby completing a circuit board 704.

[0374] The storage device 300 described in the above embodiment is provided as a circuit portion of the electronic component 700. Fig.16A In the embodiment, a QFP (Quad Flat Package) is used as a package of the electronic component 700, but the packaging method is not limited to this.

[0375] Fig. 16B 1 is a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In the electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of memory devices 300 are provided on the interposer 731.

[0376] The electronic component 730 shows an example in which the storage device 300 is used as a high bandwidth memory (HBM: High Bandwidth Memory). In addition, the semiconductor device 735 can use an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA.

[0377] The package substrate 732 may be a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like. The interposer 731 may be a silicon interposer, a resin interposer, or the like.

[0378] The plug board 731 has a function of electrically connecting a plurality of wirings to a plurality of integrated circuits having different terminal pitches. The plurality of wirings are composed of a single layer or a plurality of layers. In addition, the plug board 731 has a function of electrically connecting an integrated circuit disposed on the plug board 731 to an electrode disposed on the package substrate 732. Therefore, the plug board is sometimes referred to as a "rewiring substrate" or an "intermediate substrate". In addition, sometimes a through electrode is provided in the plug board 731, and the integrated circuit is electrically connected to the package substrate 732 through the through electrode. In addition, when a silicon plug board is used, TSV (Through Silicon Via) can also be used as a through electrode.

[0379] A silicon interposer is preferably used as the interposer 731. Since a silicon interposer does not need to be provided with active elements, it can be manufactured at a lower cost than an integrated circuit. The wiring formation of a silicon interposer can be performed in a semiconductor process, and a resin interposer is easier to form fine wiring.

[0380] In HBM, many wirings need to be connected to achieve a wide memory bandwidth. For this reason, it is required that fine wirings can be formed at a high density on the interposer on which the HBM is mounted. Therefore, a silicon interposer is preferably used as the interposer on which the HBM is mounted.

[0381] In addition, in SiP or MCM using a silicon interposer, the reliability degradation caused by the difference in expansion coefficient between the integrated circuit and the interposer is not likely to occur. In addition, since the surface flatness of the silicon interposer is high, poor connection between the integrated circuit disposed on the silicon interposer and the silicon interposer is not likely to occur. It is particularly preferred to use the silicon interposer for 2.5D packaging (2.5D mounting) in which a plurality of integrated circuits are arranged horizontally and disposed on the interposer.

[0382] Alternatively, a heat sink (heat sink plate) may be provided so as to overlap the electronic component 730. When a heat sink is provided, it is preferable that the heights of the integrated circuits provided on the interposer 731 are aligned. For example, in the electronic component 730 shown in this embodiment, it is preferable that the heights of the storage device 300 and the semiconductor device 735 are aligned.

[0383] In order to mount the electronic component 730 on another substrate, an electrode 733 may be provided on the bottom of the packaging substrate 732 . Fig. 16B An example of forming the electrode 733 using solder balls is shown. By arranging solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrode 733 can also be formed using conductive pins. By arranging conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0384] The electronic component 730 can be mounted on other substrates by various mounting methods, not limited to BGA and PGA. For example, SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package) or QFN (Quad Flat Non-leaded package) can be used.

[0385] <Electronic equipment>

[0386] Next, refer to Fig.17 An example of an electronic device in which the above-mentioned electronic components are mounted will be described.

[0387] The robot 7100 includes an illumination sensor, a microphone, a camera, a speaker, a display, various sensors (infrared sensor, ultrasonic sensor, acceleration sensor, piezoelectric sensor, optical sensor, gyro sensor, etc.), a moving mechanism, etc. The electronic component 730 includes a processor, etc. and has a function of controlling these peripheral devices. For example, the electronic component 700 has a function of storing data measured by the sensor.

[0388] The microphone has the function of detecting audio signals such as the user's voice and surrounding sounds. In addition, the speaker has the function of emitting audio signals such as sounds and warning sounds. The robot 7100 can analyze the audio signals input through the microphone and emit the required audio signals from the speaker. The robot 7100 can communicate with the user by using the microphone and the speaker.

[0389] The camera has a function of capturing images of the surroundings of the robot 7100. In addition, the robot 7100 has a function of moving using a moving mechanism. The robot 7100 can capture images of the surroundings using the camera and analyze the images to determine the presence or absence of obstacles during movement.

[0390] The flying object 7120 includes propellers, a camera, a battery, etc., and has an autonomous flight function. The electronic component 730 has a function of controlling the above peripheral devices.

[0391] For example, image data captured by a camera is stored in the electronic component 700. The electronic component 730 can analyze the image data to determine the presence or absence of obstacles during movement, etc. In addition, the electronic component 730 can estimate the remaining power of the battery by the change in the storage capacity of the battery.

[0392] The sweeping robot 7140 includes a display configured on the top surface, multiple cameras configured on the side, a brush, operation buttons, and various sensors, etc. Although not shown in the figure, the sweeping robot 7140 is equipped with tires, a suction port, etc. The sweeping robot 7140 can walk automatically, detect garbage, and suck garbage from the suction port on the bottom surface.

[0393] For example, the electronic component 730 can determine the presence or absence of obstacles such as walls, furniture or steps by analyzing the images taken by the camera. In addition, when objects such as wiring that may be wrapped around the brush are detected through image analysis, the rotation of the brush can be stopped.

[0394] The automobile 7160 includes an engine, tires, brakes, a steering device, a camera, etc. For example, the electronic component 730 performs control to optimize the driving state of the automobile 7160 based on data such as navigation information, speed, engine status, gear selection status, brake usage frequency, etc. For example, image data captured by a camera is stored in the electronic component 700.

[0395] The electronic component 700 and / or the electronic component 730 may be installed in a television receiver (TV) device 7200 , a smartphone 7210 , a PC 7220 (personal computer), 7230 , a game console 7240 , a game console 7260 , or the like.

[0396] For example, the electronic component 730 provided in the TV set 7200 may be used as an image engine. For example, the electronic component 730 performs image processing such as noise removal and up-conversion of resolution.

[0397] The smartphone 7210 is an example of a portable information terminal. The smartphone 7210 includes a microphone, a camera, a speaker, various sensors, and a display unit. The electronic component 730 controls the above peripheral devices.

[0398] PC 7220 and PC 7230 are examples of a notebook PC and a desktop PC, respectively. Keyboard 7232 and display device 7233 can be connected to PC 7230 wirelessly or by wire. Game console 7240 is an example of a portable game console. Game console 7260 is an example of a fixed game console. Game console 7260 is connected to controller 7262 wirelessly or by wire. Electronic component 700 and / or electronic component 730 can be installed in controller 7262.

[0399] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0400] (Implementation 6)

[0401] In this embodiment, an application example of a storage device using the semiconductor device shown in the above embodiment is described. The semiconductor device shown in the above embodiment can be applied to, for example, a storage device of various electronic devices (for example, an information terminal, a computer, a smart phone, an e-book reader terminal, a digital camera (including a video camera), a video playback device, a navigation system, etc.). Note that here, the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system. Alternatively, the semiconductor device shown in the above embodiment is applied to various removable storage devices such as a memory card (for example, an SD card), a USB memory, and an SSD (solid state drive). FIG. 18A to FIG. 18E Several structural examples of the removable storage device are schematically shown. For example, the semiconductor device shown in the above embodiment mode is processed into a packaged memory chip and used in various storage devices or removable memories.

[0402] Fig.18A11 is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a cover 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is accommodated in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the substrate 1104. The semiconductor device described in the above embodiment can be assembled to the memory chip 1105 of the substrate 1104.

[0403] Fig.18B This is a schematic diagram of the appearance of an SD card. Fig.18C 11 is a schematic diagram of the internal structure of the SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is accommodated in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the substrate 1113. By also providing the memory chip 1114 on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. In addition, a wireless chip having a wireless communication function can also be provided on the substrate 1113. Thus, data of the memory chip 1114 can be read and written through wireless communication between the host device and the SD card 1110. The semiconductor device shown in the above embodiment can be assembled on the memory chip 1114 of the substrate 1113, etc.

[0404] Fig.18D This is a schematic diagram of the appearance of SSD. Fig.18E 1150 is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is accommodated in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are mounted on the substrate 1153. The memory chip 1155 is a working memory of the controller chip 1156, and a DOSRAM chip can be used, for example. By also providing the memory chip 1154 on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. The semiconductor device shown in the above embodiment can be assembled to the memory chip 1154 of the substrate 1153, etc.

[0405] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0406] [Explanation of symbols]

[0407] 100: semiconductor device, 110: voltage generating circuit, 120: voltage holding circuit, 130: temperature detecting circuit, 131: temperature sensor, 132: analog-digital conversion circuit, 140: voltage control circuit, 145: logic circuit, 146: voltage generating circuit

Claims

1. A semiconductor device comprising: a first circuit, a second circuit, a third circuit, a fourth circuit, and an output terminal, wherein the first circuit is configured to supply voltage to the second circuit, The second circuit is configured to supply a first voltage to the output terminal and maintain the voltage of the output terminal, The second circuit includes a first transistor, One of a source and a drain of the first transistor is electrically connected to the first circuit, The other of the source and the drain of the first transistor is electrically connected to the output terminal, The third circuit is configured to acquire temperature information and supply a digital signal corresponding to the temperature information to the fourth circuit, The fourth circuit is configured to output a second voltage corresponding to the digital signal, Furthermore, the voltage of the output terminal is the sum of the first voltage and the second voltage. 2 . The semiconductor device according to claim 1 , wherein the output terminal is electrically connected to a back gate of the second transistor. 3 . The semiconductor device according to claim 2 , wherein a semiconductor layer of the second transistor includes an oxide semiconductor.

4. The semiconductor device according to claim 1, wherein the fourth circuit comprises a plurality of capacitors, And the plurality of capacitors are electrically connected to the output terminals respectively. The semiconductor device according to claim 4 , wherein the plurality of capacitors have different capacitance values, respectively.

6. A semiconductor device comprising: First Circuit; Second Circuit; Third Circuit; Fourth Circuit; as well as Output terminals, wherein the first circuit is configured to supply voltage to the second circuit, The second circuit is configured to supply a first voltage to the output terminal and maintain the voltage of the output terminal, The second circuit includes a first transistor, One of a source and a drain of the first transistor is electrically connected to the first circuit, The other of the source and the drain of the first transistor is electrically connected to the output terminal, The third circuit is configured to acquire temperature information and supply a digital signal corresponding to the temperature information to the fourth circuit, The fourth circuit is configured to output a second voltage corresponding to the digital signal, The voltage of the output terminal is the sum of the first voltage and the second voltage, The fourth circuit includes a first capacitor, a second capacitor and a third capacitor, Each of the first capacitor, the second capacitor, and the third capacitor is electrically connected to the output terminal, The capacitance value of the second capacitor is twice the capacitance value of the first capacitor. And the capacitance value of the third capacitor is 4 times the capacitance value of the first capacitor.

7. The semiconductor device according to claim 6, wherein the output terminal is electrically connected to the back gate of the second transistor, And wherein the semiconductor layer of the second transistor includes an oxide semiconductor.

8. The semiconductor device according to any one of claims 1 to 7, The other of the source and the drain of the first transistor is electrically connected to the gate of the first transistor.

9. The semiconductor device according to any one of claims 1 to 7, The first transistor includes a first gate and a second gate, wherein the other of the source and the drain of the first transistor is electrically connected to the first gate of the first transistor, and wherein the other of the source and the drain of the first transistor is electrically connected to the second gate of the first transistor.

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