A memristor simulation model

Abstract

The invention discloses a memristor simulation model, comprising a memristor equivalent resistor R1, controlled voltage sources V1 to V3, resistors R2 to R6, a capacitor C, a first operational amplifier and a second operational amplifier. One end of the memristor equivalent resistor R1 is connected to the positive electrode of the controlled voltage source V1; the negative electrode of the controlled voltage source V2 is grounded, the positive electrode of the controlled voltage source V2 is connected to one end of the resistor R2, the other end of the resistor R2 is respectively connected to the inverting input end of the first operational amplifier and one end of the capacitor C, the other end of the capacitor C is connected to the output end of the first operational amplifier, and the positive input end of the first operational amplifier is grounded; the negative electrode of the controlled voltage source V3 is grounded, the positive electrode of the controlled voltage source V3 is connected to one end of the resistor R3, the other end of the resistor R3 is respectively connected to the inverting input end of the second operational amplifier and one end of the resistor R4, the other end of the resistor R4 is connected to the output end of the second operational amplifier, the positive input end of the second operational amplifier is respectively connected to one end of the resistor R5 and the resistor R6, and the other end of the resistor R6 is grounded.

Description

Technical Field

[0001] The invention relates to a memristor simulation model and belongs to the field of circuit design. Background Art

[0002] As the size of integrated circuits approaches the nanometer level, Moore's Law has been seriously challenged in the integrated circuit manufacturing technology based on complementary metal oxide semiconductor (CMOS) transistors. The search for new nanoscale devices has become the key to continuing Moore's Law. Among them, the fourth basic element, the memristor M, proposed by Chua in 1971, in addition to the resistor R, the inductor L and the capacitor C, is considered to be one of the key devices most likely to continue Moore's Law. However, it was not until 2008 that HP Labs disclosed a physical memristor with a P_t-TiO_2-P_t sandwich structure and gave a boundary migration model to explain the working principle of the memristor. Accurate Spice simulation models are helpful to help memristor developers build memristor circuits. However, the existing Spice model can only reflect the inherent pinched hysteresis curve characteristics of the memristor when the circuit is powered on (time t=0) and the phase of the input sinusoidal voltage signal is 0. Otherwise, the iv curve of the Spice model is displayed as a slant line of a non-pinched hysteresis curve, and 100% simulation of the memristor cannot be achieved. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a memristor simulation model, which directly realizes the boundary migration model of the memristor with a controlled source and an ideal operational amplifier as main components.

[0004] The present invention adopts the following technical solutions to solve the above technical problems:

[0005] A memristor simulation model includes a memristor equivalent resistor R1, controlled voltage sources V1 to V3, resistors R2 to R6, a capacitor C, a first operational amplifier and a second operational amplifier;

[0006] One end of the memristor equivalent resistor R1 is connected to the positive electrode of the controlled voltage source V1;

[0007] The negative electrode of the controlled voltage source V2 is grounded, the positive electrode of the controlled voltage source V2 is connected to one end of the resistor R2, the other end of the resistor R2 is respectively connected to the inverting input end of the first operational amplifier and one end of the capacitor C, the other end of the capacitor C is connected to the output end of the first operational amplifier, and the non-inverting input end of the first operational amplifier is grounded;

[0008] The negative electrode of the controlled voltage source V3 is grounded, the positive electrode of the controlled voltage source V3 is connected to one end of the resistor R3, the other end of the resistor R3 is respectively connected to the inverting input terminal of the second operational amplifier and one end of the resistor R4, the other end of the resistor R4 is connected to the output terminal of the second operational amplifier, the non-inverting input terminal of the second operational amplifier is respectively connected to one end of the resistor R5 and the resistor R6, and the other end of the resistor R6 is grounded.

[0009] Furthermore, the positive power supply terminal of the second operational amplifier is connected to a 1V voltage, and the negative power supply terminal is connected to 0V.

[0010] Furthermore, the voltage value of the controlled voltage source V1 is (R ON -R OFF )x(t)i(t), where: R ON is the low resistance of the memristor in the low resistance state, R OFF is the high resistance of the memristor in the high resistance state, w(t) is the width of the doped region at time t, D is the length of the memristor, and i(t) is the current flowing through the memristor at time t.

[0011] Furthermore, the voltage value of the controlled voltage source V2 is i(t), where i(t) is the current flowing through the memristor at time t.

[0012] Furthermore, the voltage value of the controlled voltage source V3 is kq(t), where: R ON is the low resistance of the memristor in the low resistance state, μ V is the carrier mobility in the memristor, D is the length of the memristor, and q(t) is the accumulated charge flowing through the memristor at time t.

[0013] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects:

[0014] 1. Avoid the use of window functions and directly implement the boundary migration model of memristor with controlled source and ideal op amp as main components;

[0015] 2. The current integral in the boundary migration model is simulated by charging the capacitor C;

[0016] 3. The output voltage limiting behavior of the operational amplifier is realized

[0017] 4. For the initial state of the memristor, there is only one restriction that the initial charge is 0 (q(0)=0), and there is no need to restrict the input signal phase and boundary (w(0)=0, x(0)=0). BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic diagram of the memristor simulation model circuit;

[0019] Figure 2 It is the waveform of v(t), i(t), q(t), x(t) when v(t)=sin(πt) and X0=0;

[0020] Figure 3 It is the waveform of i(t)~v(t) when v(t)=sin(πt) and X0=0;

[0021] Figure 4 Yes When X0=0, the waveforms of v(t), i(t), q(t), and x(t);

[0022] Figure 5 Yes When X0=0, the waveform of i(t)~v(t);

[0023] Figure 6 It is the waveform of v(t), i(t), q(t), x(t) when v(t)=sin(πt+π) and X0=0;

[0024] Figure 7 It is the waveform of i(t)~v(t) when v(t)=sin(πt+π) and X0=0;

[0025] Figure 8 The waveforms of v(t), i(t), q(t), and x(t) when v(t) = sin(πt) and X0 = 0.5 are:

[0026] Fig. 9 It is the waveform of i(t)~v(t) when v(t)=sin(πt) and X0=0.5;

[0027] Fig.10 The waveforms of v(t), i(t), q(t), and x(t) when v(t) = sin(4πt) and X0 = 0 are:

[0028] Fig.11 It is the waveform of i(t)~v(t) when v(t)=sin(4πt) and X0=0. DETAILED DESCRIPTION

[0029] The embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be interpreted as limiting the present invention.

[0030] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art in the art to which the present invention belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless defined as herein.

[0031] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings:

[0032] In the memristor boundary migration model, a memristor with a width of D is composed of highly doped and undoped regions, with a positive electrode leading out of the highly doped end and a negative electrode leading out of the undoped end. The current flowing into the positive electrode of the memristor and out of the negative electrode is defined as a positive current; the current flowing into the negative electrode of the memristor and out of the positive electrode is defined as a reverse current. The distance from the positive electrode of the memristor to the boundary between the highly doped region and the undoped region is defined as w. When the memristor is connected to a forward current, as the cumulative charge flowing into the memristor increases, w increases and tends to D. When w = D, the entire memristor appears to be in a highly doped state to the outside, which is called the low resistance state of the memristor. The low resistance is R ON When the memristor is connected to the reverse current, as the accumulated charge flowing into the memristor increases, w decreases and tends to 0. When w = 0, the entire memristor appears to be undoped to the outside, which is called the high resistance state of the memristor. The high resistance is R OFF It can be seen that as the accumulated charge flowing into the memristor changes, w will move between 0 and D, and the corresponding resistance M presented by the memristor to the outside will also change between R ON and R OFF Changes between.

[0033] The memristor boundary migration model can be described by formula (1) the memristor voltage-current relationship formula and formula (2) the boundary formula:

[0034]

[0035]

[0036] Where i(t) is the current flowing through the memristor, v(t) is the voltage across the memristor, v(t) and i(t) are in the associated reference direction; M(w, v, i) is the resistance of the memristor; D is the length of the memristor; w(t) is the width of the doped region at time t; μ V is the carrier mobility in the memristor.

[0037] Dividing both sides of formula (2) by D yields:

[0038]

[0039] in:

[0040]

[0041] Continuing to integrate both sides of formula (3) with respect to t, we can obtain:

[0042] x(t)-x(0)=kq(t)-kq(0)(5)where q(t) is the accumulated charge flowing through the memristor at time t, and the initial charge q(0)=0, q(t)=∫i(t)dt-q(0).

[0043] Take w(0) as the initial width of the doped region (at t = 0); x(0) = X0 is the ratio of the initial width of the doped region to the entire memristor length D:

[0044]

[0045] Formula (5) can finally be simplified to:

[0046] x(t)=X0+kq(t)=X0+∫i(t)dt, x(t)∈[0,1], X0∈[0,1] (7)

[0047] Substituting formula (4) and (7) into formula (1) yields:

[0048] v(t)=(R ON X(t)+R OFF (1-x(t)))i(t)=(R OFF +(R ON -R OFF )x(t))i(t),x(t)∈[0,1] (8)

[0049] The memristor boundary migration model can finally be described by the memristor voltage-current relationship formula (8) and the boundary formula (7).

[0050] The simulation circuit model corresponding to the memristor is as follows Figure 1 As shown in the figure, V1, V2, and V3 are all controlled voltage sources, and the voltage values ​​are (R ON -R OFF )x(t)i(t),i(t),kq(t).

[0051] Voltage at node 7:

[0052]

[0053] Voltage of node 12:

[0054]

[0055] Taking R3=R4=R5=R6, X0∈[0,1V], formula (10) can be simplified to formula (7).

[0056] The voltage between nodes 1 and 3 satisfies formula (8).

[0057] Take R ON =100Ω, R OFF =16kΩ,μ v =10 -10 cm 2 s-1V -1 , D = 10nm, C = 1F, R2 = 1Ω, R3 = R4 = R5 = R6 = 10kΩ. The waveforms of v(t), i(t), q(t), x(t) and i(t) ~ v(t) under different input and different boundary initial conditions are given.

[0058] Implementation 1: Take v(t) = sin(πt), when X0 = 0, the waveform is as follows Figure 2 and Figure 3 shown.

[0059] Implementation 2: Take When X0=0, the waveform is as follows Figure 4 and Figure 5 shown.

[0060] Implementation 3: Take v(t) = sin(πt+π), when X0 = 0, the waveform is as follows Figure 6 and Figure 7 shown.

[0061] Implementation 4: When v(t) = sin(πt) and X0 = 0.5, the waveform is as follows: Figure 8 and Fig. 9 shown.

[0062] Implementation 5: Take v(t) = sin(4πt), when X0 = 0, the waveform is as follows Fig.10 and Fig.11 shown.

[0063] The above description is only a specific implementation of the present invention, but the protection scope of the present invention is not limited thereto. Any person familiar with the technology can understand and think of any changes or substitutions within the technical scope disclosed by the present invention, which should be included in the scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A memristor simulation model, characterized in that: It includes a memristor equivalent resistor R1, controlled voltage sources V1 to V3, resistors R2 to R6, a capacitor C, a first operational amplifier and a second operational amplifier; One end of the memristor equivalent resistor R1 is connected to the positive electrode of the controlled voltage source V1; The negative electrode of the controlled voltage source V2 is grounded, the positive electrode of the controlled voltage source V2 is connected to one end of the resistor R2, the other end of the resistor R2 is respectively connected to the inverting input end of the first operational amplifier and one end of the capacitor C, the other end of the capacitor C is connected to the output end of the first operational amplifier, and the non-inverting input end of the first operational amplifier is grounded; The negative electrode of the controlled voltage source V3 is grounded, the positive electrode of the controlled voltage source V3 is connected to one end of the resistor R3, the other end of the resistor R3 is respectively connected to the inverting input end of the second operational amplifier and one end of the resistor R4, the other end of the resistor R4 is connected to the output end of the second operational amplifier, the non-inverting input end of the second operational amplifier is respectively connected to one end of the resistor R5 and the resistor R6, and the other end of the resistor R6 is grounded; The voltage value of the controlled voltage source V1 is (R ON -R OFF )x(t)i(t), where: R ON is the low resistance of the memristor in the low resistance state, R OFF is the high resistance of the memristor in the high resistance state, w(t) is the width of the doped region at time t, D is the length of the memristor, and i(t) is the current flowing through the memristor at time t; The voltage value of the controlled voltage source V2 is i(t), where i(t) is the current flowing through the memristor at time t; The voltage value of the controlled voltage source V3 is kq(t), where: R ON is the low resistance of the memristor in the low resistance state, μ V is the carrier mobility in the memristor, D is the length of the memristor, and q(t) is the accumulated charge flowing through the memristor at time t; The memristor boundary migration model is described as: v(t)=(R OFF +(R ON -R OFF )x(t))i(t),x(t)∈[0,1] x(t)=X0+∫i(t)dt,x(t)∈[0,1],X0∈[0,1] in is the ratio of the initial width W0 of the doped region to the length D of the memristor.

2. A memristor simulation model as claimed in claim 1, characterized in that: The positive power supply terminal of the second op amp is connected to 1V, and the negative power supply terminal is connected to 0V.

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