A DC coupled differential front end amplifier circuit

Abstract

The present invention discloses a DC-coupled differential front-end amplifier circuit, comprising: a six-input differential amplifier circuit, a first DC offset suppression circuit, a second DC offset suppression circuit, and a closed-loop gain circuit; the first DC offset suppression circuit and the second DC offset suppression circuit are used to suppress DC offset voltage; the closed-loop gain circuit serves as a negative feedback loop to provide closed-loop gain for the DC-coupled differential front-end amplifier circuit. The present invention is suitable for DC-coupled input and has a certain DC electrode offset suppression capability, which can effectively improve the signal-to-noise ratio and anti-interference capability of weak bioelectric signals, thereby improving the accuracy of the entire signal acquisition.

Description

Technical Field

[0001] The present invention relates to the fields of sensor technology and integrated circuit technology, and in particular to a direct current coupled differential front-end amplifier circuit. Background Art

[0002] The front-end amplifier of bioelectric signals is the core module of the health information acquisition system. As the first circuit module of the entire acquisition system that directly contacts the electrode to realize signal acquisition, its acquisition accuracy directly affects the accuracy of the acquired health information. In the acquisition and measurement of weak bioelectric signals such as electrocardiogram and electroencephalogram, skin cleansers and electrodes with conductive glue are usually used to reduce skin impedance and enhance the conductivity between the electrode and the skin. However, this traditional electrode has a certain polarization voltage, which causes the input offset voltage of the acquisition amplifier to be large and causes signal saturation distortion, especially under long-term measurement. The electrode polarization voltage will be greater. In addition, the bioelectric signal has a small amplitude and is extremely weak, so it is very susceptible to interference from environmental noise, electrode contact disturbance, and circuit noise, and the above problems will appear more serious in actual signal acquisition and measurement. Therefore, designing a front-end amplifier with offset voltage suppression, low noise and high energy efficiency is the key to creating a high-performance acquisition system, especially for the application trend of wearable health monitoring. More and more new technologies are beginning to emerge to meet the design needs of high-performance front-end amplifiers. The current mainstream design method is to use AC coupling input, but the disadvantage of AC coupling is that a large coupling capacitor needs to be placed at the input of the preamplifier, and the large capacitor cannot be integrated and there is a large input error caused by device mismatch. In order to solve the above problems, it is necessary to provide a new front-end amplifier circuit with programmable high-pass cutoff frequency and gain. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a DC coupled differential front-end amplifier circuit in view of the defects of the prior art.

[0004] The technical solution adopted by the present invention to solve the technical problem is: construct a DC coupled differential front-end amplifier circuit, including: a six-input differential amplifier circuit, a first DC offset suppression circuit, a second DC offset suppression circuit, and a closed-loop gain circuit, wherein:

[0005] The first DC offset suppression circuit is connected between the first positive input terminal Vpp and the first negative input terminal Vpn of the six-input differential amplifier circuit, and the connection point between the first DC offset suppression circuit and the first positive input terminal Vpp of the six-input differential amplifier circuit is the external signal positive differential input terminal Vip of the DC-coupled differential front-end amplifier circuit; the second DC offset suppression circuit is connected between the second positive input terminal Vnp and the second negative input terminal Vnn of the six-input differential amplifier circuit, and the connection point between the second DC offset suppression circuit and the second positive input terminal Vnp of the six-input differential amplifier circuit is the external signal negative differential input terminal Vin of the DC-coupled differential front-end amplifier circuit; the positive auxiliary input terminal Vpx of the six-input differential amplifier circuit and the closed-loop gain circuit are both input with a common mode voltage Vcm, and the negative auxiliary input terminal Vnx of the six-input differential amplifier circuit is connected to the output terminal Vout of the six-input differential amplifier circuit via the closed-loop gain circuit;

[0006] The first DC offset suppression circuit and the second DC offset suppression circuit are used to suppress DC offset voltage; the closed-loop gain circuit serves as a negative feedback loop to provide closed-loop gain for the DC-coupled differential front-end amplifier circuit.

[0007] Preferably, the six-input differential amplifier circuit comprises: a bias circuit, a multi-input stage circuit, a gain stage circuit, and an output stage circuit; wherein,

[0008] The bias circuit includes PMOS tubes Mp1, Mp2 and a bias current source Ib; the source of the PMOS tube Mp1 is connected to the positive terminal Vdd of the power supply, the drain of the PMOS tube Mp1 is connected to the source of the PMOS tube Mp2, and the source of the PMOS tube Mp2 is connected to the negative terminal Vss of the power supply via the bias current source Ib; the gate and drain of the PMOS tube Mp1 are short-circuited, and the gate and drain of the PMOS tube Mp2 are short-circuited;

[0009] The multi-input stage circuit includes PMOS tubes Mp3, Mp4, Mp5, Mp6, Mp7, Mp8, Mp15, Mp16, Mp17 and NMOS tubes Mn1 and Mn3; the sources of the PMOS tubes Mp3, Mp6 and Mp15 are all connected to the positive end Vdd of the power supply, the gates of the PMOS tubes Mp3, Mp6 and Mp15 are short-circuited and connected to the gate of the PMOS tube Mp1; the gates of the PMOS tubes Mp7 and Mp8 are respectively connected to the positive end Vdd of the power supply, and the gates of the PMOS tubes Mp7 and Mp8 are respectively connected to the positive end Vdd of the power supply. The first positive input terminal Vpp and the first negative input terminal Vpn of the six-input differential amplifier circuit are connected. The sources of the PMOS tubes Mp7 and Mp8 are connected to each other and to the drain of the PMOS tube Mp6. The drain of the PMOS tube Mp7 is connected to the drain of the NMOS tube Mn3. The drain of the PMOS tube Mp8 is connected to the drain of the NMOS tube Mn1. The gates of the PMOS tubes Mp4 and Mp5 serve as the second negative input terminal Vpp and the first negative input terminal Vpn of the six-input differential amplifier circuit. The source electrodes of the PMOS tubes Mp4 and Mp5 are connected to each other and are also connected to the drain electrode of the PMOS tube Mp3. The drain electrode of the PMOS tube Mp4 is connected to the drain electrode of the NMOS tube Mn3. The drain electrode of the PMOS tube Mp5 is connected to the drain electrode of the NMOS tube Mn1. The gate electrodes of the PMOS tubes Mp16 and Mp17 serve as the negative auxiliary input terminal Vnx and the positive auxiliary input terminal Vp of the six-input differential amplifier circuit, respectively. x, the sources of the PMOS tubes Mp16 and Mp17 are connected to each other and to the drain of the PMOS tube Mp15, the drain of the PMOS tube Mp16 is connected to the drain of the NMOS tube Mn1, and the drain of the PMOS tube Mp17 is connected to the drain of the NMOS tube Mn3; the gate and drain of the NMOS tube Mn1 are short-circuited, the gate and drain of the NMOS tube Mn3 are short-circuited, and the sources of the NMOS tubes Mn1 and Mn3 are both connected to the negative power supply terminal Vss;

[0010] The gain stage circuit includes PMOS tubes Mp9, Mp10, Mp11, Mp12, Mp13 and NMOS tubes Mn2, Mn4, Mn5, Mn6; the PMOS tubes Mp9 and Mp10 form an active current mirror as a load, the gate and drain of the PMOS tube Mp10 are short-circuited and connected to the gate of the PMOS tube Mp9, the drain of the PMOS tube Mp9 is connected to the drain of the NMOS tube Mn4, and the drain of the PMOS tube Mp10 is connected to the drain of the NMOS tube Mn4. The NMOS tube Mn2 is connected to the drain of the NMOS tube Mn2; the NMOS tube Mn2 forms a current mirror circuit with the NMOS tube Mn1 in the multi-input stage circuit, the gate of the NMOS tube Mn2 is connected to the gate of the NMOS tube Mn1, and the source of the NMOS tube Mn2 is connected to the negative power supply terminal Vss; the NMOS tube Mn4 forms a current mirror circuit with the NMOS tube Mn3 in the multi-input stage circuit, the gate of the NMOS tube Mn4 is connected to the gate of the NMOS tube Mn3, and the source of the NMOS tube Mn4 is connected to the negative power supply terminal Vss; the PMOS tubes Mp11, Mp12, Mp13 and the NMOS tubes Mn5 and Mn6 form a first-order amplifier structure, the gate of the PMOS tube Mp11 is connected to the gate of the PMOS tube Mp1 in the bias circuit to form a current source, the gates of the PMOS tubes Mp12 and Mp13 are respectively connected to the drains of the PMOS tubes Mp9 and Mp10, and the PMOS The sources of the S transistors Mp12 and Mp13 are connected to each other and to the drain of the PMOS transistor Mp11. The drains of the PMOS transistors Mp12 and Mp13 are connected to the drains of the NMOS transistors Mn5 and Mn6 respectively. The NMOS transistors Mn5 and Mn6 form an active current mirror as a load. The gate and drain of the NMOS transistor Mn5 are short-circuited and then connected to the gate of the NMOS transistor Mn6. The sources of the NMOS transistors Mn5 and Mn6 are both connected to the negative power supply terminal Vss.

[0011] The output stage circuit includes a PMOS tube Mp14 and an NMOS tube Mn7; the gate of the PMOS tube Mp14 is connected to the gate of the PMOS tube Mp1 in the bias circuit to form a mirror current source, the source of the PMOS tube Mp14 is connected to the positive terminal Vdd of the power supply, and the drain of the PMOS tube Mp14 is connected to the drain of the NMOS tube Mn7; the gate of the NMOS tube Mn7 is connected to the drain of the NMOS tube Mn6, and the source of the NMOS tube Mn7 is connected to the negative terminal Vss of the power supply; the connection point between the drain of the PMOS tube Mp14 and the drain of the NMOS tube Mn7 serves as the output terminal Vout of the six-input differential amplifier circuit.

[0012] Preferably, the six-input differential amplifier circuit further includes a Miller compensation resistor-capacitor circuit;

[0013] The Miller compensation resistor-capacitor circuit comprises a resistor R and a capacitor C, and the resistor R and the capacitor C are connected in series between the gate of the PMOS tube Mp13 and the output terminal Vout of the six-input differential amplifier circuit;

[0014] The Miller compensation resistor-capacitor circuit provides phase margin compensation for the six-input differential amplifier circuit.

[0015] Preferably, the first DC offset suppression circuit and the second DC offset suppression circuit both include a PMOS tube M1 and a PMOS tube M2;

[0016] The gate of the PMOS tube M1 is connected to the gate of the PMOS tube M2, the drain of the PMOS tube M1 is connected to the drain of the PMOS tube M2, and the gate connection point of the PMOS tubes M1 and M2 is connected to the drain connection point of the PMOS tubes M1 and M2; in the first DC offset suppression circuit, the source and substrate of the PMOS tube M1 are short-circuited and connected to the external signal positive differential input terminal Vip, and the source and substrate of the PMOS tube M2 are short-circuited and connected to the first negative input terminal Vpn of the six-input differential amplifier circuit; in the second DC offset suppression circuit, the source and substrate of the PMOS tube M1 are short-circuited and connected to the external signal negative differential input terminal Vin, and the source and substrate of the PMOS tube M2 are short-circuited and connected to the second negative input terminal Vnn of the six-input differential amplifier circuit.

[0017] Furthermore, the high-pass cutoff frequency of the first DC offset suppression circuit and the second DC offset suppression circuit is adjustable; the first DC offset suppression circuit and the second DC offset suppression circuit both include a PMOS tube M1 and a PMOS tube M2;

[0018] The gate of the PMOS tube M1 and the gate of the PMOS tube M2 are short-circuited and connected to the bias voltage Vb, the drains of the PMOS tube M1 and the PMOS tube M2 are connected, the substrates of the PMOS tube M1 and the PMOS tube M2 are connected together and connected to the drain connection point of the PMOS tube M1 and the PMOS tube M2; in the first DC offset suppression circuit, the source of the PMOS tube M1 is connected to the external signal positive differential input terminal Vip, and the source of the PMOS tube M2 is connected to the first negative input terminal Vpn of the six-input differential amplifier circuit; in the second DC offset suppression circuit, the source of the PMOS tube M1 is connected to the external signal negative differential input terminal Vin, and the source of the PMOS tube M2 is connected to the second negative input terminal Vnn of the six-input differential amplifier circuit; the bias voltage Vb is generated by a bias voltage generating circuit;

[0019] By adjusting the magnitude of the bias voltage Vb, the high-pass cutoff frequency of the first DC offset suppression circuit and the second DC offset suppression circuit is adjusted.

[0020] Preferably, the DC-coupled differential front-end amplifier circuit further includes a first fast recovery circuit and a second fast recovery circuit;

[0021] The first fast recovery circuit is connected between the external signal positive differential input terminal Vip of the DC-coupled differential front-end amplifier circuit and the first negative input terminal Vpn of the six-input differential amplifier circuit; the second fast recovery circuit is connected between the external signal negative differential input terminal Vin of the DC-coupled differential front-end amplifier circuit and the second negative input terminal Vnn of the six-input differential amplifier circuit;

[0022] The first fast recovery circuit and the second fast recovery circuit are used to improve the response speed of the DC-coupled differential front-end amplifier circuit when the external signal input lead wire is disconnected and reconnected.

[0023] Preferably, the first fast recovery circuit includes a MOS transistor M3, and the second fast recovery circuit includes a MOS transistor M4;

[0024] The source of the MOS transistor M3 is connected to the external signal negative differential input terminal Vip of the DC-coupled differential front-end amplifier circuit, and the drain of the MOS transistor M3 is connected to the first negative input terminal Vpn of the six-input differential amplifier circuit; the source of the MOS transistor M4 is connected to the external signal negative differential input terminal Vin of the DC-coupled differential front-end amplifier circuit, and the drain of the MOS transistor M4 is connected to the second negative input terminal Vnn of the six-input differential amplifier circuit; the gate of the MOS transistor M3 and the gate of the MOS transistor M4 are both controlled by the control signal SW;

[0025] When the external signal input lead wire is disconnected and reconnected, the control signal SW controls the MOS transistor M3 and the MOS transistor M4 to be turned on, and transmits the external signal to the six-input differential amplifier circuit with low impedance.

[0026] Preferably, the closed-loop gain circuit is a variable closed-loop gain circuit, and the variable closed-loop gain circuit provides an adjustable closed-loop gain for the DC-coupled differential front-end amplifier circuit.

[0027] Optionally, the variable closed-loop gain circuit includes a variable resistor array network Rf and a fixed resistor Rg;

[0028] One end of the fixed resistor Rg is connected to the negative auxiliary input terminal Vnx of the six-input differential amplifier circuit, and the other end of the fixed resistor Rg is connected to the output terminal Vout of the six-input differential amplifier circuit; the variable resistor array network Rf is composed of a plurality of resistors with different resistance values, one end of the plurality of resistors with different resistance values ​​is connected and connected to a common mode voltage Vcm, and the other end of the plurality of resistors with different resistance values ​​is connected to the connection point of the fixed resistor Rg and the negative auxiliary input terminal Vnx of the six-input differential amplifier circuit through a selection switch; the selection switch is controlled by a digital control circuit;

[0029] The digital control circuit selects the resistance value of the variable resistor array network Rf connected to the variable closed-loop gain circuit by controlling the selection switch, so that the DC-coupled differential front-end amplifier circuit can achieve different closed-loop gains.

[0030] Optionally, the variable closed-loop gain circuit includes a fixed resistor Rf and a variable resistor Rg;

[0031] One end of the variable resistor Rg is connected to the negative auxiliary input terminal Vnx of the six-input differential amplifier circuit, and the other end of the variable resistor Rg is connected to the output terminal Vout of the six-input differential amplifier circuit; one end of the fixed resistor Rf receives the common mode voltage Vcm, and the other end of the fixed resistor Rf is connected to the connection point between the variable resistor Rg and the negative auxiliary input terminal Vnx of the six-input differential amplifier circuit;

[0032] By changing the resistance value of the variable resistor Rg connected to the variable closed-loop gain circuit, the DC-coupled differential front-end amplifier circuit can achieve different closed-loop gains.

[0033] The implementation of the technical solution of the present invention has the following beneficial effects: the circuit of the present invention has a certain adjustable amplification factor capability, which can improve the transmission signal-to-noise ratio of weak signals. At the same time, it has a certain electrode polarization offset voltage suppression capability, so a DC coupled input can be used without causing system saturation distortion. By introducing a fast recovery circuit, the problem of the slow amplifier response speed when the input signal lead wire is disconnected and reconnected can be solved. Therefore, the present invention can effectively enhance the sensing and collection effect of weak bioelectric signals. In addition, the circuit of the present invention adopts a single operational amplifier structure, the system size is small, the power consumption is low, and it is easy to integrate and implement under the standard CMOS process. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The present invention will be further described below with reference to the accompanying drawings and embodiments, in which:

[0035] Figure 1 is a schematic structural diagram of Embodiment 1 of the present invention;

[0036] Figure 2 is a structural diagram of Embodiment 2 of the present invention;

[0037] Figure 3 is a circuit schematic diagram of a DC offset suppression circuit in an embodiment of the present invention;

[0038] Figure 4 is a circuit schematic diagram of an embodiment of the invention;

[0039] Figure 5 is a circuit schematic diagram of a six-input differential difference amplifier circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to have a clearer understanding of the technical features, purposes and effects of the present invention, specific embodiments of the present invention are now described in detail with reference to the accompanying drawings.

[0041] Figure 1 is a schematic structural diagram of Embodiment 1 of the present invention;

[0042] like Figure 1 As shown, the DC-coupled differential front-end amplifier circuit of the present invention comprises: a six-input differential amplifier circuit 10, a first DC offset suppression circuit 20, a second DC offset suppression circuit 30, and a closed-loop gain circuit 40, wherein:

[0043] The first DC offset suppression circuit 20 is connected between the first positive input terminal Vpp and the first negative input terminal Vpn of the six-input differential amplifier circuit 10, and the connection point between the first DC offset suppression circuit 20 and the first positive input terminal Vpp of the six-input differential amplifier circuit 10 is the external signal positive differential input terminal Vip of the DC-coupled differential front-end amplifier circuit; the second DC offset suppression circuit 30 is connected between the second positive input terminal Vnp and the second negative input terminal Vnn of the six-input differential amplifier circuit 10, and the connection point between the second DC offset suppression circuit 30 and the second positive input terminal Vnp of the six-input differential amplifier circuit 10 is the external signal negative differential input terminal Vin of the DC-coupled differential front-end amplifier circuit; the positive auxiliary input terminal Vpx of the six-input differential amplifier circuit 10 and the closed-loop gain circuit 40 are both input with the common mode voltage Vcm, and the negative auxiliary input terminal Vnx of the six-input differential amplifier circuit 10 is connected to the output terminal Vout of the six-input differential amplifier circuit 10 via the closed-loop gain circuit 40;

[0044] The first DC offset suppression circuit 20 and the second DC offset suppression circuit 30 are used to suppress DC offset voltage; the closed-loop gain circuit 40 serves as a negative feedback loop to provide closed-loop gain for the DC-coupled differential front-end amplifier circuit.

[0045] The common mode voltage Vcm is a preset DC common mode voltage, which is generally half of the power supply voltage.

[0046] The advantages of the technical solution of the present invention are explained below by comparing it with several existing front-end amplifier solutions:

[0047] The first solution is to cascade multiple amplifiers through the front-end unity gain amplifier buffer. The unity gain amplifier is used to provide high input impedance and low output impedance to achieve the function of impedance conversion, and the post-amplifier realizes the signal amplification of the electrophysiological signal. The amplifier generally uses a conventional two-stage operational amplifier.

[0048] The second solution: instrumentation operational amplifier, which adopts a three-op-amp design structure to provide high common-mode rejection ratio capability and achieve signal amplification and collection.

[0049] The third option is to use a larger gain amplifier, which can achieve higher gain by using resistor feedback in a traditional amplifier, or by using digital circuits to assist in eliminating offset voltage.

[0050] The fourth solution: AC coupled differential input front-end amplifier, this design is the current mainstream design method. Generally, an input capacitor pair is used to achieve AC signal coupling input, and a low cutoff frequency high pass is achieved by introducing a virtual resistor in the feedback loop to eliminate the electrode offset voltage.

[0051] The above four front-end amplifier solutions have the following defects:

[0052] In the first solution, the combination of a unity gain buffer and multiple amplifiers has the following main technical disadvantages: on the one hand, since the signal is a differential input, a dual-path buffer is required. This requires very high matching of the buffer and is therefore difficult to achieve. On the other hand, the combination of multiple amplifiers will cause the chip area to be too large and the power consumption to be too high.

[0053] In the second solution, although the instrumentation operational amplifier has very high common-mode noise suppression performance, the three-op-amp structure usually requires very good op-amp matching. Usually, off-chip trimming technology is required to achieve better circuit matching, generally using laser trimming technology and circuit trimming technology. The chip later cost is high, and the three-op-amp structure circuit is complex.

[0054] In the third solution, since the human body's electrophysiological signals have a large DC offset voltage, the operational amplifier with a large gain is very likely to saturate. Introducing a digital circuit to eliminate the offset voltage in a large gain amplifier usually makes the system design more complicated, and the integration of digital circuits will introduce additional circuit noise.

[0055] In the fourth solution, the amplifier of this solution is usually implemented in the form of capacitor feedback. This structure can better eliminate the DC offset voltage, but the input impedance is low and the signal sensing ability is weak. At the same time, the linear performance of the virtual resistor used in the feedback loop is poor. In addition, when realizing an extremely low high-pass cutoff frequency, due to the use of large capacitors, monolithic integration is usually not possible.

[0056] The front-end amplifier circuit of the present invention can realize pre-amplification of electrode sensing signals and suppress a certain electrode offset voltage, so that signal distortion will not be caused by electrode offset voltage during the process of pre-amplification of signals. Based on the front-end amplifier of the present invention, the bioelectric signal acquisition system can realize DC coupled input and have a higher input impedance. It can effectively improve the anti-interference ability of the bioelectric signal acquisition system. The circuit of the present invention can be further applied in an electrical signal acquisition system based on dry electrodes, and the circuit has lower power consumption and low noise performance.

[0057] Figure 2 is a structural diagram of Embodiment 2 of the present invention;

[0058] like Figure 2 As shown, the DC-coupled differential front-end amplifier circuit of this embodiment is based on the first embodiment and further includes a first fast recovery circuit 50 and a second fast recovery circuit 60;

[0059] The first fast recovery circuit 50 is connected between the external signal positive differential input terminal Vip of the DC-coupled differential front-end amplifier circuit and the first negative input terminal Vpn of the six-input differential amplifier circuit 10; the second fast recovery circuit 60 is connected between the external signal negative differential input terminal Vin of the DC-coupled differential front-end amplifier circuit and the second negative input terminal Vnn of the six-input differential amplifier circuit 10;

[0060] The first fast recovery circuit 50 and the second fast recovery circuit 60 are used to improve the response speed of the DC-coupled differential front-end amplifier circuit when the external signal input lead wire is disconnected and reconnected.

[0061] Figure 3 is a circuit schematic diagram of a DC offset suppression circuit in an embodiment of the present invention;

[0062] like Figure 3 As shown, the first DC offset suppression circuit 20 and the second DC offset suppression circuit 30 both include a PMOS tube M1 and a PMOS tube M2;

[0063] The gate of the PMOS tube M1 is connected to the gate of the PMOS tube M2, the drain of the PMOS tube M1 is connected to the drain of the PMOS tube M2, and the gate connection point of the PMOS tubes M1 and M2 is connected to the drain connection point of the PMOS tubes M1 and M2; in the first DC offset suppression circuit 20, the source and substrate of the PMOS tube M1 are short-circuited and connected to the external signal positive differential input terminal Vip, and the source and substrate of the PMOS tube M2 are short-circuited and connected to the first negative input terminal Vpn of the six-input differential amplifier circuit 10; in the second DC offset suppression circuit 30, the source and substrate of the PMOS tube M1 are short-circuited and connected to the external signal negative differential input terminal Vin, and the source and substrate of the PMOS tube M2 are short-circuited and connected to the second negative input terminal Vnn of the six-input differential amplifier circuit 10.

[0064] Figure 4 is a circuit schematic diagram of an embodiment of the invention;

[0065] like Figure 4 As shown, the present invention also provides a circuit structure of a first DC offset suppression circuit 20 and a second DC offset suppression circuit 30 with adjustable high-pass cutoff frequency; in this embodiment, the first DC offset suppression circuit 20 and the second DC offset suppression circuit 30 both include a PMOS tube M1 and a PMOS tube M2;

[0066] The gate of the PMOS tube M1 and the gate of the PMOS tube M2 are short-circuited and connected to the bias voltage Vb, the drains of the PMOS tube M1 and the PMOS tube M2 are connected, the substrates of the PMOS tube M1 and the PMOS tube M2 are connected together and connected to the drain connection point of the PMOS tube M1 and the PMOS tube M2; in the first DC offset suppression circuit 20, the source of the PMOS tube M1 is connected to the external signal positive differential input terminal Vip, and the source of the PMOS tube M2 is connected to the first negative input terminal Vpn of the six-input differential amplifier circuit 10; in the second DC offset suppression circuit 30, the source of the PMOS tube M1 is connected to the external signal negative differential input terminal Vin, and the source of the PMOS tube M2 is connected to the second negative input terminal Vnn of the six-input differential amplifier circuit 10; the bias voltage Vb is generated by the bias voltage generating circuit;

[0067] By adjusting the magnitude of the bias voltage Vb, the high-pass cutoff frequency of the first DC offset suppression circuit 20 and the second DC offset suppression circuit 30 is adjusted.

[0068] like Figure 4 As shown, the first fast recovery circuit 50 of the present invention includes a MOS transistor M3, and the second fast recovery circuit 60 includes a MOS transistor M4;

[0069] The source of the MOS tube M3 is connected to the external signal negative differential input terminal Vip of the DC-coupled differential front-end amplifier circuit, and the drain of the MOS tube M3 is connected to the first negative input terminal Vpn of the six-input differential amplifier circuit 10; the source of the MOS tube M4 is connected to the external signal negative differential input terminal Vin of the DC-coupled differential front-end amplifier circuit, and the drain of the MOS tube M4 is connected to the second negative input terminal Vnn of the six-input differential amplifier circuit 10; the gate of the MOS tube M3 and the gate of the MOS tube M4 are both controlled by the control signal SW;

[0070] When the external signal input lead wire is disconnected and reconnected, the control signal SW controls the MOS transistor M3 and the MOS transistor M4 to be turned on, and transmits the external signal to the six-input differential amplifier circuit 10 with low impedance.

[0071] The working principle of the fast recovery circuit is described in detail below:

[0072] The present invention realizes the rapid discharge of the charge of the high impedance nodes Vpn and Vnn in the circuit of the present invention by introducing two MOS switches controlled by the control signal SW. When the input signal lead line is disconnected and then the amplifier input is reconnected, the amplifier will need a long time to achieve the stability of the output signal due to the existence of these two high impedance nodes. Therefore, when the above situation is detected, the control signal SW controls the MOS tubes M3 and M4 to be turned on, and the signal input from the external signal positive differential input terminal Vip and the external signal negative differential input terminal Vin is transmitted to the input terminal of the operational amplifier with low impedance, avoiding the response delay effect caused by the high impedance of the virtual resistor, so that the output of the amplifier circuit can respond to the output quickly and achieve stability.

[0073] Furthermore, the closed-loop gain circuit 40 of the circuit of the present invention is a variable closed-loop gain circuit, which provides an adjustable closed-loop gain for the DC-coupled differential front-end amplifier circuit.

[0074] like Figure 4 As shown, the variable closed-loop gain circuit includes a variable resistor array network Rf and a fixed resistor Rg;

[0075] One end of the fixed resistor Rg is connected to the negative auxiliary input terminal Vnx of the six-input differential amplifier circuit 10, and the other end of the fixed resistor Rg is connected to the output terminal Vout of the six-input differential amplifier circuit 10; the variable resistor array network Rf is composed of a plurality of resistors with different resistance values, one end of the plurality of resistors with different resistance values ​​is connected and connected to the common mode voltage Vcm, and the other end of the plurality of resistors with different resistance values ​​is connected to the connection point of the fixed resistor Rg and the negative auxiliary input terminal Vnx of the six-input differential amplifier circuit 10 through a selection switch; the selection switch is controlled by a digital control circuit;

[0076] The digital control circuit selects the resistance value of the variable resistor array network Rf connected to the variable closed-loop gain circuit by controlling the selection switch, so that the DC-coupled differential front-end amplifier circuit can achieve different closed-loop gains.

[0077] It can be seen from the above circuit structure that the variable gain of the front-end amplifier of the present invention is realized by the variable feedback resistor network Rf. This scheme is realized by the positive and negative auxiliary input terminals Vpx and Vnx of the six-input differential amplifier. Wherein Vcm is the system common mode level, which is connected to the positive and negative auxiliary negative input terminals Vnx and Vpx of the six-input differential amplifier. After Vpx and Vnx are connected in series with resistors Rg, they are connected to the output terminal Vout of the six-input differential amplifier to form a system negative feedback loop. The resistor network Rf is connected in series between the negative auxiliary input terminals Vnx and Vcm. The resistance value of Rg in the feedback loop is fixed, and the resistor Rf can be realized by a resistor array network with different resistance values, and different Rf resistance values ​​can be selected by a digital control circuit to achieve different system amplification factors. The closed-loop gain of the system is expressed as:

[0078]

[0079] Furthermore, the variable closed-loop gain circuit may also include a fixed resistor Rf and a variable resistor Rg;

[0080] One end of the variable resistor Rg is connected to the negative auxiliary input terminal Vnx of the six-input differential amplifier circuit 10, and the other end of the variable resistor Rg is connected to the output terminal Vout of the six-input differential amplifier circuit 10; one end of the fixed resistor Rf receives the common mode voltage Vcm, and the other end of the fixed resistor Rf is connected to the connection point between the variable resistor Rg and the negative auxiliary input terminal Vnx of the six-input differential amplifier circuit 10;

[0081] By changing the resistance value of the variable resistor Rg connected to the variable closed-loop gain circuit, the DC-coupled differential front-end amplifier circuit can achieve different closed-loop gains.

[0082] Figure 5 is a circuit schematic diagram of a six-input differential difference amplifier circuit in an embodiment of the present invention.

[0083] like Figure 5 As shown, the six-input differential amplifier circuit 10 includes: a bias circuit, a multi-input stage circuit, a gain stage circuit, and an output stage circuit; wherein,

[0084] The bias circuit includes PMOS tubes Mp1, Mp2 and a bias current source Ib; the source of the PMOS tube Mp1 is connected to the positive terminal Vdd of the power supply, the drain of the PMOS tube Mp1 is connected to the source of the PMOS tube Mp2, and the source of the PMOS tube Mp2 is connected to the negative terminal Vss of the power supply via the bias current source Ib; the gate and drain of the PMOS tube Mp1 are short-circuited, and the gate and drain of the PMOS tube Mp2 are short-circuited;

[0085] The multi-input stage circuit includes PMOS tubes Mp3, Mp4, Mp5, Mp6, Mp7, Mp8, Mp15, Mp16, Mp17 and NMOS tubes Mn1 and Mn3; the sources of the PMOS tubes Mp3, Mp6 and Mp15 are all connected to the positive terminal Vdd of the power supply, the gates of the PMOS tubes Mp3, Mp6 and Mp15 are short-circuited and connected to the gate of the PMOS tube Mp1; the gates of the PMOS tubes Mp7 and Mp8 respectively serve as the first positive input terminal Vpp and the first negative input terminal Vpn of the six-input differential amplifier circuit 10, the sources of the PMOS tubes Mp7 and Mp8 are connected and connected to the drain of the PMOS tube Mp6, the drain of the PMOS tube Mp7 is connected to the drain of the NMOS tube Mn3, and the drain of the PMOS tube Mp8 is connected to the drain of the NMOS tube Mn1; the gates of the PMOS tubes Mp4 and Mp5 respectively serve as the first positive input terminal Vpp and the first negative input terminal Vpn of the six-input differential amplifier circuit 10 The second negative input terminal Vnn and the second positive input terminal Vnp, the sources of the PMOS tubes Mp4 and Mp5 are connected and connected to the drain of the PMOS tube Mp3, the drain of the PMOS tube Mp4 is connected to the drain of the NMOS tube Mn3, and the drain of the PMOS tube Mp5 is connected to the drain of the NMOS tube Mn1; the gates of the PMOS tubes Mp16 and Mp17 serve as the negative auxiliary input terminal Vnx and the positive auxiliary input terminal Vpx of the six-input differential amplifier circuit 10, respectively, the sources of the PMOS tubes Mp16 and Mp17 are connected and connected to the drain of the PMOS tube Mp15, the drain of the PMOS tube Mp16 is connected to the drain of the NMOS tube Mn1, and the drain of the PMOS tube Mp17 is connected to the drain of the NMOS tube Mn3; the gate and the drain of the NMOS tube Mn1 are short-circuited, the gate and the drain of the NMOS tube Mn3 are short-circuited, and the sources of the NMOS tubes Mn1 and Mn3 are both connected to the negative power supply terminal Vss;

[0086] The gain stage circuit includes PMOS tubes Mp9, Mp10, Mp11, Mp12, Mp13 and NMOS tubes Mn2, Mn4, Mn5 and Mn6; the PMOS tubes Mp9 and Mp10 form an active current mirror as a load, the gate and drain of the PMOS tube Mp10 are short-circuited and connected to the gate of the PMOS tube Mp9, the drain of the PMOS tube Mp9 is connected to the drain of the NMOS tube Mn4, and the drain of the PMOS tube Mp10 is connected to the drain of the NMOS tube Mn2; the NMOS tube Mn2 forms a current mirror circuit with the NMOS tube Mn1 in the multi-input stage circuit, the gate of the NMOS tube Mn2 is connected to the gate of the NMOS tube Mn1, and the source of the NMOS tube Mn2 is connected to the negative end Vss of the power supply; the NMOS tube Mn4 forms a current mirror circuit with the NMOS tube Mn3 in the multi-input stage circuit, the gate of the NMOS tube Mn4 is connected to the gate of the NMOS tube Mn3 The gates of the NMOS tubes Mn4 and Mn6 are connected, and the source of the NMOS tube Mn4 is connected to the negative power supply terminal Vss; the PMOS tubes Mp11, Mp12, Mp13 and the NMOS tubes Mn5 and Mn6 form a first-order amplifier structure, the gate of the PMOS tube Mp11 is connected to the gate of the PMOS tube Mp1 in the bias circuit to form a current source, the gates of the PMOS tubes Mp12 and Mp13 are connected to the drains of the PMOS tubes Mp9 and Mp10 respectively, the sources of the PMOS tubes Mp12 and Mp13 are connected and connected to the drain of the PMOS tube Mp11, and the drains of the PMOS tubes Mp12 and Mp13 are connected to the drains of the NMOS tubes Mn5 and Mn6 respectively; the NMOS tubes Mn5 and Mn6 form an active current mirror as a load, the gate and drain of the NMOS tube Mn5 are short-circuited and then connected to the gate of the NMOS tube Mn6, and the sources of the NMOS tubes Mn5 and Mn6 are both connected to the negative power supply terminal Vss;

[0087] The output stage circuit includes a PMOS tube Mp14 and an NMOS tube Mn7; the gate of the PMOS tube Mp14 is connected to the gate of the PMOS tube Mp1 in the bias circuit to form a mirror current source, the source of the PMOS tube Mp14 is connected to the positive terminal Vdd of the power supply, and the drain of the PMOS tube Mp14 is connected to the drain of the NMOS tube Mn7; the gate of the NMOS tube Mn7 is connected to the drain of the NMOS tube Mn6, and the source of the NMOS tube Mn7 is connected to the negative terminal Vss of the power supply; the connection point between the drain of the PMOS tube Mp14 and the drain of the NMOS tube Mn7 serves as the output terminal Vout of the six-input differential amplifier circuit 10.

[0088] From the circuit structure of the above six-input differential amplifier circuit 10, it can be known that its circuit feature is a multi-stage amplifier with six input terminals and one output. Because it has six input terminals, it can form three equivalent subtractors (Vpn-Vpp, Vnp-Vnn, Vpx-Vnx) for implementing the DC offset voltage suppression scheme and the adjustable system feedback gain scheme in the scheme of the present invention.

[0089] It can be understood that the NMOS tubes and PMOS tubes in the six-input differential amplifier circuit 10 can be completely swapped for use. For example, the input tubes in the circuit can use NMOS tube inputs, and the PMOS current source can be swapped for an NMOS mirror current source.

[0090] Furthermore, the six-input differential amplifier circuit 10 further includes a Miller compensation resistor-capacitor circuit 101;

[0091] The Miller compensation RC circuit 101 includes a resistor R and a capacitor C, which are connected in series between the gate of the PMOS tube Mp13 and the output terminal Vout of the six-input differential amplifier circuit 10;

[0092] The Miller compensation RC circuit 101 provides phase margin compensation for the six-input differential amplifier circuit 10 , further improving the stability of the system.

[0093] Combine the following Figure 4 and Figure 5 The working principles of the DC offset suppression circuit 20 and the second DC offset suppression circuit 30 in the circuit of the present invention are described in detail.

[0094] Figure 4 The PMOS transistors M1 and M2 are connected in the form of diodes to form a virtual resistor Rp, which has a large equivalent resistance, such as one G ohm, several G ohms, or even tens of G ohms. The first negative input terminal Vpn of the six-input differential amplifier circuit 10 is a MOS transistor (such as Figure 5 The MOS transistor has a parasitic capacitance Cg. The virtual resistance formed by the PMOS tubes M1 and M2 and the parasitic capacitance Cg of the PMOS tube Mp8 form an equivalent integration circuit, that is, an equivalent low-pass filter circuit. Its equivalent integration constant is τ = R p C g The first positive and negative input terminals Vpp and Vpn of the six-input differential amplifier circuit 10 form a differential subtractor, namely Vpp-Vpn. Through this subtractor, the input signal Vip is subtracted from the signal after low-pass filtering of Vip by the virtual resistor Rp formed by the PMOS tubes M1 and M2, thereby realizing a high-pass filter, whose cut-off frequency is τ=R p C g Determine the frequency Since the equivalent resistance value of the virtual resistor Rp is extremely large, the input stage of the six-input differential amplifier circuit 10 can obtain a high-pass filtering characteristic with an extremely low cut-off frequency, which is as low as mHz. With this circuit structure, the DC offset voltage can be filtered out through this equivalent high-pass filtering function, thereby achieving the suppression of the DC offset voltage.

[0095] Furthermore, the principle of the high-pass cutoff frequency adjustable scheme of the present invention is: by setting different bias voltages Vb, the virtual resistance Rp formed by the PMOS tubes M1 and M2 can be adjusted, so the integral constant τ=R p C g By adjusting the high-pass cutoff frequency, the DC offset voltage can be filtered out.

[0096] The present invention realizes adjustable amplification through a closed-loop gain circuit 40 with variable closed-loop gain, thereby improving the transmission signal-to-noise ratio of weak signals; and realizes electrode polarization offset voltage suppression through a first DC offset suppression circuit 20 and a second DC offset suppression circuit 30, so that DC coupling input can be used without causing system saturation distortion. The first fast recovery circuit 50 and the second fast recovery circuit 60 solve the problem that the amplifier responds very slowly when the input signal lead wire is disconnected and reconnected. Therefore, the present invention can effectively enhance the sensing and collection effect of weak bioelectric signals. In addition, the six-input differential amplifier circuit 10 with a single operational amplifier structure makes the circuit have a smaller volume, lower power consumption, and is easy to integrate and implement under a standard CMOS process, with a small chip area and low cost. It can be applied to analog front-end chips for multi-channel signals.

[0097] It should be further explained that although the present invention is designed based on bioelectric signal acquisition, the circuit structure of the present invention is not limited to the field of bioelectric signal acquisition. Its design method and circuit structure can also be applied to other weak electrical signal sensing circuits and signal acquisition systems.

[0098] The present invention is described by specific embodiments, and it should be understood by those skilled in the art that various changes and equivalent substitutions may be made to the present invention without departing from the scope of the present invention. In addition, various modifications may be made to the present invention for specific situations or specific circumstances without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed, but should include all implementation methods falling within the scope of the claims of the present invention.

Claims

1. A DC coupled differential front end amplifier circuit, characterized in that: include: A six-input differential amplifier circuit (10), a first DC offset suppression circuit (20), a second DC offset suppression circuit (30), and a closed-loop gain circuit (40), wherein: The first DC offset suppression circuit (20) is connected between a first positive input terminal Vpp and a first negative input terminal Vpn of the six-input differential amplifier circuit (10); the connection point between the first DC offset suppression circuit (20) and the first positive input terminal Vpp of the six-input differential amplifier circuit (10) is an external signal positive differential input terminal Vip of the DC-coupled differential front-end amplifier circuit; the second DC offset suppression circuit (30) is connected between a second positive input terminal Vnp and a second negative input terminal Vnn of the six-input differential amplifier circuit (10); The connection point between the second DC offset suppression circuit (30) and the second positive input terminal Vnp of the six-input differential amplifier circuit (10) is the external signal negative differential input terminal Vin of the DC-coupled differential front-end amplifier circuit; the positive auxiliary input terminal Vpx of the six-input differential amplifier circuit (10) and the closed-loop gain circuit (40) both input a common mode voltage Vcm, and the negative auxiliary input terminal Vnx of the six-input differential amplifier circuit (10) is connected to the output terminal Vout of the six-input differential amplifier circuit (10) via the closed-loop gain circuit (40); The first DC offset suppression circuit (20) and the second DC offset suppression circuit (30) are used to suppress DC offset voltage; the closed-loop gain circuit (40) serves as a negative feedback loop to provide closed-loop gain for the DC-coupled differential front-end amplifier circuit.

2. The DC coupled differential front-end amplifier circuit according to claim 1, characterized in that: The six-input differential amplifier circuit (10) comprises: a bias circuit, a multi-input stage circuit, a gain stage circuit, and an output stage circuit; wherein: The bias circuit includes PMOS tubes Mp1, Mp2 and a bias current source Ib; the source of the PMOS tube Mp1 is connected to the positive terminal Vdd of the power supply, the drain of the PMOS tube Mp1 is connected to the source of the PMOS tube Mp2, and the source of the PMOS tube Mp2 is connected to the negative terminal Vss of the power supply via the bias current source Ib; the gate and drain of the PMOS tube Mp1 are short-circuited, and the gate and drain of the PMOS tube Mp2 are short-circuited; The multi-input stage circuit includes PMOS tubes Mp3, Mp4, Mp5, Mp6, Mp7, Mp8, Mp15, Mp16, Mp17 and NMOS tubes Mn1 and Mn3; the sources of the PMOS tubes Mp3, Mp6 and Mp15 are all connected to the positive end Vdd of the power supply, the gates of the PMOS tubes Mp3, Mp6 and Mp15 are short-circuited and connected to the gate of the PMOS tube Mp1; the gates of the PMOS tubes Mp7 and Mp8 serve as the The first positive input terminal Vpp and the first negative input terminal Vpn of the six-input differential amplifier circuit (10), the sources of the PMOS tubes Mp7 and Mp8 are connected and connected to the drain of the PMOS tube Mp6, the drain of the PMOS tube Mp7 is connected to the drain of the NMOS tube Mn3, and the drain of the PMOS tube Mp8 is connected to the drain of the NMOS tube Mn1; the gates of the PMOS tubes Mp4 and Mp5 serve as the first positive input terminal Vpp and the first negative input terminal Vpn of the six-input differential amplifier circuit (10), respectively. The gate electrodes of the PMOS tubes Mp16 and Mp17 serve as the negative auxiliary input terminal Vnx and the positive auxiliary input terminal Vnp of the six-input differential amplifier circuit (10), respectively. The source electrodes of the PMOS tubes Mp16 and Mp17 are connected to the drain electrode of the PMOS tube Mp15, the drain electrode of the PMOS tube Mp16 is connected to the drain electrode of the NMOS tube Mn1, and the drain electrode of the PMOS tube Mp17 is connected to the drain electrode of the NMOS tube Mn3; the gate electrode and the drain electrode of the NMOS tube Mn1 are short-circuited, the gate electrode and the drain electrode of the NMOS tube Mn3 are short-circuited, and the source electrodes of the NMOS tubes Mn1 and Mn3 are both connected to the negative power supply terminal Vss; The gain stage circuit includes PMOS tubes Mp9, Mp10, Mp11, Mp12, Mp13 and NMOS tubes Mn2, Mn4, Mn5, Mn6; the PMOS tubes Mp9 and Mp10 form an active current mirror as a load, the gate and drain of the PMOS tube Mp10 are short-circuited and connected to the gate of the PMOS tube Mp9, the drain of the PMOS tube Mp9 is connected to the drain of the NMOS tube Mn4, and the drain of the PMOS tube Mp10 is connected to the drain of the NMOS tube Mn4. The NMOS tube Mn2 is connected to the drain of the NMOS tube Mn2; the NMOS tube Mn2 forms a current mirror circuit with the NMOS tube Mn1 in the multi-input stage circuit, the gate of the NMOS tube Mn2 is connected to the gate of the NMOS tube Mn1, and the source of the NMOS tube Mn2 is connected to the negative power supply terminal Vss; the NMOS tube Mn4 forms a current mirror circuit with the NMOS tube Mn3 in the multi-input stage circuit, the gate of the NMOS tube Mn4 is connected to the gate of the NMOS tube Mn3, and the source of the NMOS tube Mn4 is connected to the negative power supply terminal Vss; the PMOS tubes Mp11, Mp12, Mp13 and the NMOS tubes Mn5 and Mn6 form a first-order amplifier structure, the gate of the PMOS tube Mp11 is connected to the gate of the PMOS tube Mp1 in the bias circuit to form a current source, the gates of the PMOS tubes Mp12 and Mp13 are respectively connected to the drains of the PMOS tubes Mp9 and Mp10, and the PMOS The sources of the S transistors Mp12 and Mp13 are connected to each other and to the drain of the PMOS transistor Mp11. The drains of the PMOS transistors Mp12 and Mp13 are connected to the drains of the NMOS transistors Mn5 and Mn6 respectively. The NMOS transistors Mn5 and Mn6 form an active current mirror as a load. The gate and drain of the NMOS transistor Mn5 are short-circuited and then connected to the gate of the NMOS transistor Mn6. The sources of the NMOS transistors Mn5 and Mn6 are both connected to the negative power supply terminal Vss. The output stage circuit comprises a PMOS tube Mp14 and an NMOS tube Mn7; the gate of the PMOS tube Mp14 is connected to the gate of the PMOS tube Mp1 in the bias circuit to form a mirror current source, the source of the PMOS tube Mp14 is connected to the positive terminal Vdd of the power supply, and the drain of the PMOS tube Mp14 is connected to the drain of the NMOS tube Mn7; the gate of the NMOS tube Mn7 is connected to the drain of the NMOS tube Mn6, and the source of the NMOS tube Mn7 is connected to the negative terminal Vss of the power supply; the connection point between the drain of the PMOS tube Mp14 and the drain of the NMOS tube Mn7 serves as the output terminal Vout of the six-input differential amplifier circuit (10).

3. The DC coupled differential front-end amplifier circuit according to claim 2, characterized in that: The six-input differential amplifier circuit (10) further includes a Miller compensation resistor-capacitor circuit; The Miller compensation resistor-capacitor circuit comprises a resistor R and a capacitor C, wherein the resistor R and the capacitor C are connected in series between the gate of the PMOS tube Mp13 and the output terminal Vout of the six-input differential amplifier circuit (10); The Miller compensation resistor-capacitor circuit provides phase margin compensation for the six-input differential amplifier circuit (10).

4. The DC coupled differential front-end amplifier circuit according to claim 1, characterized in that: The first DC offset suppression circuit (20) and the second DC offset suppression circuit (30) both comprise a PMOS tube M1 and a PMOS tube M2; The gate of the PMOS tube M1 is connected to the gate of the PMOS tube M2, the drain of the PMOS tube M1 is connected to the drain of the PMOS tube M2, and the gate connection point of the PMOS tubes M1 and M2 is connected to the drain connection point of the PMOS tubes M1 and M2; in the first DC offset suppression circuit (20), the source and substrate of the PMOS tube M1 are short-circuited and connected to the external signal positive differential input terminal Vip, and the source and substrate of the PMOS tube M2 are short-circuited and connected to the first negative input terminal Vpn of the six-input differential amplifier circuit (10); in the second DC offset suppression circuit (30), the source and substrate of the PMOS tube M1 are short-circuited and connected to the external signal negative differential input terminal Vin, and the source and substrate of the PMOS tube M2 are short-circuited and connected to the second negative input terminal Vnn of the six-input differential amplifier circuit (10).

5. The DC coupled differential front-end amplifier circuit according to claim 1, characterized in that: The high-pass cut-off frequency of the first DC offset suppression circuit (20) and the second DC offset suppression circuit (30) is adjustable; the first DC offset suppression circuit (20) and the second DC offset suppression circuit (30) both comprise a PMOS tube M1 and a PMOS tube M2; The gate of the PMOS tube M1 and the gate of the PMOS tube M2 are short-circuited and connected to the bias voltage Vb, the drains of the PMOS tube M1 and the PMOS tube M2 are connected, the substrates of the PMOS tube M1 and the PMOS tube M2 are connected together and connected to the drain connection point of the PMOS tube M1 and the PMOS tube M2; in the first DC offset suppression circuit (20), the source of the PMOS tube M1 is connected to the external signal positive differential input terminal Vip, and the source of the PMOS tube M2 is connected to the first negative input terminal Vpn of the six-input differential amplifier circuit (10); in the second DC offset suppression circuit (30), the source of the PMOS tube M1 is connected to the external signal negative differential input terminal Vin, and the source of the PMOS tube M2 is connected to the second negative input terminal Vnn of the six-input differential amplifier circuit (10); The bias voltage Vb is generated by a bias voltage generating circuit; By adjusting the magnitude of the bias voltage Vb, the high-pass cut-off frequency of the first DC offset suppression circuit (20) and the second DC offset suppression circuit (30) is adjusted.

6. The DC coupled differential front-end amplifier circuit according to claim 1, characterized in that: Also includes a first fast recovery circuit (50) and a second fast recovery circuit (60); The first fast recovery circuit (50) is connected between the external signal positive differential input terminal Vip of the DC-coupled differential front-end amplifier circuit and the first negative input terminal Vpn of the six-input differential amplifier circuit (10); the second fast recovery circuit (60) is connected between the external signal negative differential input terminal Vin of the DC-coupled differential front-end amplifier circuit and the second negative input terminal Vnn of the six-input differential amplifier circuit (10); The first fast recovery circuit (50) and the second fast recovery circuit (60) are used to improve the response speed of the DC-coupled differential front-end amplifier circuit when the external signal input lead wire is disconnected and reconnected.

7. The DC coupled differential front-end amplifier circuit according to claim 6, characterized in that: The first fast recovery circuit (50) comprises a MOS transistor M3, and the second fast recovery circuit (60) comprises a MOS transistor M4; The source of the MOS transistor M3 is connected to the external signal negative differential input terminal Vip of the DC-coupled differential front-end amplifier circuit, and the drain of the MOS transistor M3 is connected to the first negative input terminal Vpn of the six-input differential amplifier circuit (10); the source of the MOS transistor M4 is connected to the external signal negative differential input terminal Vin of the DC-coupled differential front-end amplifier circuit, and the drain of the MOS transistor M4 is connected to the second negative input terminal Vnn of the six-input differential amplifier circuit (10); the gate of the MOS transistor M3 and the gate of the MOS transistor M4 are both controlled by a control signal SW; When the external signal input lead wire is disconnected and reconnected, the control signal SW controls the MOS transistor M3 and the MOS transistor M4 to be turned on, so as to transmit the external signal to the six-input differential amplifier circuit (10) with low impedance.

8. The DC coupled differential front-end amplifier circuit according to claim 1, characterized in that: The closed-loop gain circuit (40) is a variable closed-loop gain circuit, which provides an adjustable closed-loop gain for the DC-coupled differential front-end amplifier circuit.

9. The DC coupled differential front-end amplifier circuit according to claim 8, characterized in that: The variable closed-loop gain circuit includes a variable resistor array network Rf and a fixed resistor Rg; One end of the fixed resistor Rg is connected to the negative auxiliary input terminal Vnx of the six-input differential amplifier circuit (10), and the other end of the fixed resistor Rg is connected to the output terminal Vout of the six-input differential amplifier circuit (10); the variable resistor array network Rf is composed of a plurality of resistors with different resistance values, one end of the plurality of resistors with different resistance values ​​is connected to a common mode voltage Vcm, and the other end of the plurality of resistors with different resistance values ​​is connected to the connection point between the fixed resistor Rg and the negative auxiliary input terminal Vnx of the six-input differential amplifier circuit (10) via a selection switch; the selection switch is controlled by a digital control circuit; The digital control circuit selects the resistance value of the variable resistor array network Rf connected to the variable closed-loop gain circuit by controlling the selection switch, so that the DC-coupled differential front-end amplifier circuit can achieve different closed-loop gains.

10. The DC coupled differential front-end amplifier circuit according to claim 8, characterized in that: The variable closed-loop gain circuit includes a fixed resistor Rf and a variable resistor Rg; One end of the variable resistor Rg is connected to the negative auxiliary input terminal Vnx of the six-input differential amplifier circuit (10), and the other end of the variable resistor Rg is connected to the output terminal Vout of the six-input differential amplifier circuit (10); one end of the fixed resistor Rf receives the common mode voltage Vcm, and the other end of the fixed resistor Rf is connected to the connection point between the variable resistor Rg and the negative auxiliary input terminal Vnx of the six-input differential amplifier circuit (10); By changing the resistance value of the variable resistor Rg connected to the variable closed-loop gain circuit, the DC-coupled differential front-end amplifier circuit can achieve different closed-loop gains.

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