Error amplifier circuit and voltage regulation system

Abstract

The present invention relates to the technical field of switching power supplies, and in particular to an error amplifier circuit and a voltage regulation system, wherein a first positive input terminal, a second positive input terminal and one end of a resistor R1 are all connected to a reference voltage port, a second reverse input terminal and one end of a resistor R2 are all connected to the other end of the resistor R1, the other end of the resistor R2 is connected to an error amplifier output port, a feedback port is connected to the first reverse input terminal through a resistor Rc, the error amplifier output port is connected to the first reverse input terminal through a capacitor Cz, the output end of the error amplifier is used to drive a field effect transistor Mn, an input end of a current source Ip is connected to an external power supply, an output end of the current source Ip is connected to a drain of the field effect transistor Mn, an input end of a current source In is connected to a source of the field effect transistor Mn, and an output end of the current source In is grounded. The present invention can achieve the effect of ensuring the output accuracy of the error amplifier circuit by using a low-cost structure.

Description

Technical Field

[0001] The present invention relates to the technical field of switching power supplies, and in particular to an error amplification circuit and a voltage regulation system. Background Art

[0002] Power electronic converters have been widely used in various electronic systems. In the design of all converters, the key technology is how to accurately regulate the voltage to adapt to various electronic loads such as CPUs and memory chipsets. In the voltage regulation system, the error amplifier (EA) plays a vital role in the accuracy and dynamic performance of the voltage regulation. If there is no accurate error amplifier in the control loop of the voltage regulation system, the regulation ability and accuracy of the voltage regulation system will be limited. The error amplifiers currently on the market cannot take into account both cost and accuracy. There is an urgent need for low-cost and high-precision error amplifiers on the market. Summary of the invention

[0003] The present invention aims at solving the problems in the prior art and provides an error amplifier circuit with high precision and low cost.

[0004] The present invention adopts the following technical scheme: an error amplifier circuit, including a feedback port FB, a reference voltage port Vref, an error amplifier output port EAO, an error amplifier EA, a resistor R1, a resistor R2, a resistor Rc, a capacitor Cz, a current source Ip, a current source In and a field effect transistor Mn, the error amplifier EA is provided with a first reverse input terminal INN1, a first positive input terminal INP1, a second reverse input terminal INN2 and a second positive input terminal INP2, the first positive input terminal INP1, the second positive input terminal INP2 and one end of the resistor R1 are all connected to the reference voltage port Vref, the first reverse input terminal INN2 and the second positive input terminal INP2 are connected to the reference voltage port Vref, the first reverse input terminal INN1, the second positive input terminal INP2 and one end of the resistor R1 are connected to the reference voltage port Vref, the first reverse input terminal INN2 and the second positive input terminal INP2 ... The second reverse input terminal INN2 and one end of the resistor R2 are connected to the other end of the resistor R1, the other end of the resistor R2 is connected to the error amplifier output port EAO, the feedback port FB is connected to the first reverse input terminal INN1 through the resistor Rc, the error amplifier output port EAO is connected to the first reverse input terminal INN1 through the capacitor Cz, the output end of the error amplifier EA is used to drive the field effect transistor Mn, the input end of the current source Ip is connected to the external power supply, the output end of the current source Ip is connected to the drain of the field effect transistor Mn, the input end of the current source In is connected to the source of the field effect transistor Mn, and the output end of the current source In is grounded.

[0005] Preferably, the error amplifier EA includes a first differential pair, a second differential pair and an output amplifier stage, the first control end of the first differential pair is connected to the first reverse input end INN1, the second control end of the first differential pair is connected to the first positive input end INP1, the first control end of the second differential pair is connected to the second reverse input end INN2, the second control end of the second differential pair is connected to the second positive input end INP2, the input end of the first differential pair and the input end of the second differential pair are both connected to an external power supply, and the output end of the first differential pair and the output end of the second differential pair are both connected to the error amplifier output port EAO through the output amplifier stage.

[0006] Preferably, the first differential pair includes a first bias current source, a first field effect transistor and a second field effect transistor, the gate of the first field effect transistor is connected to the first reverse input terminal INN1, the gate of the second field effect transistor is connected to the first forward input terminal INP1, the source of the first field effect transistor and the source of the second field effect transistor are both connected to the output terminal of the first bias current source, the input terminal of the first bias current source is connected to an external power supply, and the drain of the first field effect transistor and the drain of the second field effect transistor are both connected to the input terminal of the output amplifier stage.

[0007] Preferably, the second differential pair includes a second bias current source, a third field effect transistor and a fourth field effect transistor, the gate of the third field effect transistor is connected to the second reverse input terminal INN2, the gate of the fourth field effect transistor is connected to the second forward input terminal INP2, the source of the third field effect transistor and the source of the fourth field effect transistor are both connected to the output terminal of the second bias current source, the input terminal of the second bias current source is connected to the external power supply, and the drain of the third field effect transistor and the drain of the fourth field effect transistor are both connected to the input terminal of the output amplifier stage.

[0008] Preferably, the output amplifier stage includes a first current mirror unit, a fifth field effect transistor, a sixth field effect transistor, a third bias current source and a fourth bias current source, the input end of the first current mirror unit is connected to an external power supply, the first output end of the first current mirror unit is connected to the drain of the fifth field effect transistor, the second output end of the first current mirror unit and the drain of the sixth field effect transistor are both connected to the error amplifier output port EAO, the gate of the fifth field effect transistor and the gate of the sixth field effect transistor are both connected to an external bias voltage, the source of the fifth field effect transistor and the output end of the first differential pair are both connected to the input end of the third bias current source, the source of the sixth field effect transistor and the output end of the second differential pair are both connected to the input end of the fourth bias current source, and the output end of the third bias current source and the output end of the fourth bias current source are both grounded.

[0009] Preferably, the error amplifier circuit also includes a buffer Buffer, a reference voltage port Vref is connected to the input end of the buffer Buffer, a first positive input end INP1, a second positive input end INP2 and one end of the resistor R1 are all connected to the output end of the buffer Buffer; the buffer Buffer includes a second current mirror unit, a seventh field effect transistor, an eighth field effect transistor and a fifth bias current source, the input end of the second current mirror unit is connected to an external power supply, the first output end of the second current mirror unit is connected to the drain of the seventh field effect transistor, the second output end of the second current mirror unit is connected to the drain of the eighth field effect transistor, the source of the seventh field effect transistor and the source of the eighth field effect transistor are both grounded, the gate of the seventh field effect transistor is connected to the input end of the buffer Buffer, and the gate of the eighth field effect transistor is connected to the output end of the buffer Buffer.

[0010] Preferably, the buffer Buffer also includes a ninth field effect transistor, a gate of the ninth field effect transistor is connected to the second output end of the second current mirror unit, a source of the ninth field effect transistor is connected to an external power supply, and a drain of the ninth field effect transistor is connected to the output end of the buffer Buffer.

[0011] Preferably, the buffer Buffer further includes a capacitor Cp, one end of the capacitor Cp is connected to the source of the ninth field effect transistor, and the other end of the capacitor Cp is connected to the gate of the ninth field effect transistor.

[0012] Preferably, the buffer Buffer further includes a resistor Ro, one end of the resistor Ro is connected to the drain of the ninth field effect transistor, and the other end of the resistor R0 is grounded.

[0013] Based on the above-mentioned error amplification circuit, the present invention also provides a voltage regulation system, including a voltage conversion circuit, a voltage detection circuit, a driving circuit for driving the voltage conversion circuit and the above-mentioned error amplification circuit, the output end of the voltage conversion circuit is connected to the input end of the voltage detection circuit, the output end of the voltage detection circuit is connected to the input end of the error amplification circuit, and the output end of the error amplification circuit is connected to the control end of the driving circuit.

[0014] The beneficial effect of the present invention is that the output value of the error amplifier EA is clamped by using the resistor R1, the resistor R2, the current source Ip and the current source In, thereby achieving the effect of ensuring the output accuracy of the error amplifier circuit by using a low-cost structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 FIG. 4 is a circuit diagram of a voltage regulation system of the present invention.

[0016] Figure 2FIG. 4 is a circuit diagram of the error amplifier circuit of the present invention.

[0017] Figure 3 FIG. 4 is a circuit diagram of the error amplifier EA of the present invention.

[0018] Figure 4 This is a circuit diagram of the buffer of the present invention.

[0019] Figure 5 It is a simulated Bode diagram of the path from the feedback port FB to the error amplification output port EAO of the present invention.

[0020] Figure 6 It is a simulated Bode diagram of the path from the reference voltage port Vref to the error amplifier output port EAO of the present invention.

[0021] Figure 7 The waveform diagram of the voltage of the error amplifier output port EAO of the present invention changes with the voltage difference between the reference voltage port Vref and the voltage of the feedback port FB.

[0022] The accompanying drawings are marked as follows: 1. error amplifier circuit; 2. first differential pair; 21. first bias current source; 22. first field effect transistor; 23. second field effect transistor; 3. second differential pair; 31. second bias current source; 32. third field effect transistor; 33. fourth field effect transistor; 4. output amplifier stage; 41. first current mirror unit; 42. fifth field effect transistor; 43. sixth field effect transistor; 44. third bias current source; 45. fourth bias current source; 5. second current mirror unit; 51. seventh field effect transistor; 52. eighth field effect transistor; 53. fifth bias current source; 54. ninth field effect transistor; 6. voltage conversion circuit; 7. voltage detection circuit; 8. drive circuit. DETAILED DESCRIPTION

[0023] In order to facilitate the understanding of those skilled in the art, the present invention is further described below in conjunction with the embodiments and drawings, and the contents mentioned in the embodiments are not intended to limit the present invention. The present invention is described in detail below in conjunction with the drawings.

[0024] like Figure 2As shown, an error amplifier circuit 1 includes a feedback port FB, a reference voltage port Vref, an error amplifier output port EAO, an error amplifier EA, a resistor R1, a resistor R2, a resistor Rc, a capacitor Cz, a current source Ip, a current source In and a field effect transistor Mn, wherein the error amplifier EA is provided with a first reverse input terminal INN1, a first forward input terminal INP1, a second reverse input terminal INN2 and a second forward input terminal INP2, the first forward input terminal INP1, the second forward input terminal INP2 and one end of the resistor R1 are all connected to the reference voltage port Vref, and the second reverse input terminal INN2 is connected to the reference voltage port Vref. The input terminal INN2 and one end of the resistor R2 are connected to the other end of the resistor R1, the other end of the resistor R2 is connected to the error amplifier output port EAO, the feedback port FB is connected to the first reverse input terminal INN1 through the resistor Rc, the error amplifier output port EAO is connected to the first reverse input terminal INN1 through the capacitor Cz, the output end of the error amplifier EA is used to drive the field effect transistor Mn, the input end of the current source Ip is connected to the external power supply, the output end of the current source Ip is connected to the drain of the field effect transistor Mn, the input end of the current source In is connected to the source of the field effect transistor Mn, and the output end of the current source In is grounded.

[0025] In the prior art, there are two main methods for clamping the output value of the error amplifier EA. One is to set a Zener diode at the output end of the error amplifier EA, but according to the manufacturing process data, the parameter distribution range of the low-voltage Zener diode is large, which leads to low clamping accuracy; at the same time, the Zener diode is sensitive to temperature and is prone to large drift due to temperature changes, which further leads to low clamping voltage accuracy. Another method is to set an operational amplifier and multiple field effect transistors at the output end of the error amplifier EA. This structure can eliminate the clamping voltage accuracy drift caused by device parameter distribution and temperature changes, but this structure increases the circuit complexity and high manufacturing cost, and the addition of an operational amplifier will affect the dynamic performance of the error amplifier EA. Based on modern integrated circuit technology, it is easy to achieve high-precision resistors with low temperature drift; in addition, a current source with temperature compensation is already a mature solution. Therefore, in some embodiments, clamping is achieved by setting resistors R1, R2, current source Ip and current source In, so as to achieve accurate clamping with lower circuit cost. The working principle is described as follows: First, the input voltage difference is defined as ΔVi, which is equal to the voltage of the reference voltage port Vref minus the voltage of the feedback port FB. When ΔVi is low, the error amplifier EA works in the saturation region, and the field effect tube Mn also works in the saturation region. At this time, the field effect tube Mn acts as a voltage follower. The voltage of the error amplifier output port EAO changes with the input error signal ΔVi, so the entire circuit plays the role of error amplification. When ΔVi is positive and large enough, the output value of the error amplifier output port EAO becomes very high, and the field effect tube Mn is in the linear region. Therefore, the voltage of the error amplifier output port EAO is the voltage drop generated by the current difference between the current source Ip and the current source In flowing through the resistor R1 and the resistor R2 plus the voltage of the reference voltage port Vref, that is, (VREF+(Ip-In)*(R1+R2)), and this voltage is the high clamping voltage. When ΔVi is negative and large enough, the output value of the error amplifier output port EAO becomes very low, and the field effect tube Mn is in the cut-off region. Therefore, the voltage of the error amplifier output port EAO is the voltage of the reference voltage port Vref minus the voltage drop of the current In flowing through the resistors R1 and R2, that is, VREF-In*(R1+R2), which is the low clamping voltage.

[0026] like Figure 3As shown, the error amplifier EA includes a first differential pair 2, a second differential pair 3 and an output amplifier stage 4, the first control end of the first differential pair 2 is connected to the first reverse input end INN1, the second control end of the first differential pair 2 is connected to the first positive input end INP1, the first control end of the second differential pair 3 is connected to the second reverse input end INN2, the second control end of the second differential pair 3 is connected to the second positive input end INP2, the input end of the first differential pair 2 and the input end of the second differential pair 3 are both connected to an external power supply, and the output end of the first differential pair 2 and the output end of the second differential pair 3 are both connected to the error amplifier output port EAO through the output amplifier stage 4. The input of the error amplifier EA is realized through the first differential pair 2 and the second differential pair 3, so that the error amplifier EA has a higher DC gain.

[0027] Specifically, the first differential pair 2 includes a first bias current source 21, a first field effect transistor 22 and a second field effect transistor 23, the gate of the first field effect transistor 22 is connected to the first reverse input terminal INN1, the gate of the second field effect transistor 23 is connected to the first forward input terminal INP1, the source of the first field effect transistor 22 and the source of the second field effect transistor 23 are both connected to the output terminal of the first bias current source 21, the input terminal of the first bias current source 21 is connected to an external power supply, and the drain of the first field effect transistor 22 and the drain of the second field effect transistor 23 are both connected to the input terminal of the output amplifier stage 4. The second differential pair 3 includes a second bias current source 31, a third field effect transistor 32 and a fourth field effect transistor 33, the gate of the third field effect transistor 32 is connected to the second reverse input terminal INN2, the gate of the fourth field effect transistor 33 is connected to the second forward input terminal INP2, the source of the third field effect transistor 32 and the source of the fourth field effect transistor 33 are both connected to the output terminal of the second bias current source 31, the input terminal of the second bias current source 31 is connected to an external power supply, and the drain of the third field effect transistor 32 and the drain of the fourth field effect transistor 33 are both connected to the input terminal of the output amplifier stage 4. The output amplifier stage 4 includes a first current mirror unit 41, a fifth field effect transistor 42, a sixth field effect transistor 43, a third bias current source 44 and a fourth bias current source 45. The input end of the first current mirror unit 41 is connected to an external power supply, the first output end of the first current mirror unit 41 is connected to the drain of the fifth field effect transistor 42, the second output end of the first current mirror unit 41 and the drain of the sixth field effect transistor 43 are both connected to the error amplifier output port EAO, the gate of the fifth field effect transistor 42 and the gate of the sixth field effect transistor 43 are both connected to an external bias voltage, the source of the fifth field effect transistor 42 and the output end of the first differential pair 2 are both connected to the input end of the third bias current source 44, the source of the sixth field effect transistor 43 and the output end of the second differential pair 3 are both connected to the input end of the fourth bias current source 45, and the output end of the third bias current source 44 and the output end of the fourth bias current source 45 are both grounded.

[0028] like Figure 2 As shown, the error amplifier circuit 1 further includes a buffer Buffer, the reference voltage port Vref is connected to the input end of the buffer Buffer, and the first positive input end INP1, the second positive input end INP2 and one end of the resistor R1 are all connected to the output end of the buffer Buffer. The buffer Buffer can keep the input impedance of the reference voltage port Vref high impedance and provide the required current to the resistor R1 and the resistor R2.

[0029] like Figure 4 As shown, the buffer Buffer includes a second current mirror unit 5, a seventh field effect transistor 51, an eighth field effect transistor 52 and a fifth bias current source 53, the input end of the second current mirror unit 5 is connected to an external power supply, the first output end of the second current mirror unit 5 is connected to the drain of the seventh field effect transistor 51, the second output end of the second current mirror unit 5 is connected to the drain of the eighth field effect transistor 52, the source of the seventh field effect transistor 51 and the source of the eighth field effect transistor 52 are both grounded, the gate of the seventh field effect transistor 51 is connected to the input end of the buffer Buffer, and the gate of the eighth field effect transistor 52 is connected to the output end of the buffer Buffer, so that the output voltage of the buffer Buffer is consistent with the input voltage of the buffer Buffer.

[0030] like Figure 4 As shown, the buffer Buffer also includes a ninth field effect transistor 54, the gate of the ninth field effect transistor 54 is connected to the second output end of the second current mirror unit 5, the source of the ninth field effect transistor 54 is connected to the external power supply, and the drain of the ninth field effect transistor 54 is connected to the output end of the buffer Buffer, thereby enhancing the current driving capability.

[0031] like Figure 4 As shown, the buffer Buffer also includes a capacitor Cp, one end of the capacitor Cp is connected to the source of the ninth field effect transistor 54, and the other end of the capacitor Cp is connected to the gate of the ninth field effect transistor 54, thereby increasing the stability of the circuit.

[0032] like Figure 4 As shown, the buffer Buffer further includes a resistor Ro, one end of which is connected to the drain of the ninth field effect transistor 54, and the other end of which is grounded, so as to determine the magnitude of the output current.

[0033] The voltage difference between the first positive input terminal INP1 and the first negative input terminal INN1 is defined as ΔV1, and the voltage difference between the second positive input terminal INP2 and the second negative input terminal INN2 is defined as ΔV2. Assuming that the total gain of the error amplifier EA is G, the voltage of the output error amplifier output port EAO is G(ΔV1+ΔV2).

[0034] An exemplary simulation of the present invention is as follows: set Rc=5Meg, Cc=10p, R1=R / 8, R2=8*R, R=1.6k, Ip=2uA, In=1uA, VREF=600mV.

[0035] As calculated above:

[0036] Av_20dB=20*log(R2 / R1)=20*log64=36.1dB;

[0037] Pole=1 / (2*π*Rc*Cc*Av)=1 / (2*π*5Meg*10p*64)=49.7Hz;

[0038] Vclamp_H=(Ip-In)*(R1+R2)+VREF=(2uA-1uA)*(200+12.8k)+600mV=613mV;

[0039] Vclamp_L=VREF-(In*(R1+R2))=600mV-1uA*(200+12.8k)=587mV.

[0040] like Figure 5 As shown in the figure, the simulated Bode plot of the path from the feedback port FB to the error amplifier output port EAO. The DC gain marked in the figure is 36.10099dB, which is almost consistent with the calculated value Av_20dB=36.1dB. The main pole position marked in the figure is at 52.948Hz, which is almost consistent with the calculated value Pole=49.7Hz. The gain zero crossing frequency is 3.37473kHz, and the phase margin is kept near 90° in a larger bandwidth.

[0041] Figure 6 The simulation Bode diagram of the path from the reference voltage port Vref to the error amplifier output port EAO is shown. The simulation results show that the error amplifier output port EAO can quickly respond to changes in the reference voltage port Vref. As shown in the figure, the DC gain marked in the figure is 36.2623dB, which is almost consistent with the calculated value Av_dB20=36.2dB. The main pole position marked in the figure is 57.7744Hz, which is almost consistent with the calculated value Pole=57.7Hz. The gain zero crossing frequency is 3.2233kHz, and the phase margin is kept near 90° in a larger bandwidth.

[0042] Figure 7 The waveform diagram shows that the voltage of the error amplifier output port EAO changes with the voltage difference between the reference voltage port Vref and the feedback port FB. In this simulation, the voltage of the reference voltage port Vref is set to 600mV, and the voltage of the feedback port FB rises from 599.3mV to 600.7mV. The output voltage of the error amplifier output port EAO is curve 903. In the first stage, the difference between the voltage of the reference voltage port Vref and the voltage of the feedback port FB is positive and large, so the output voltage is limited to a high clamping voltage of 613mV. In the second stage, the difference between the voltage of the reference voltage port Vref and the voltage of the feedback port FB is very small, and the error amplifier EA works in the saturation region. At this time, the voltage value of the error amplifier output port EAO decreases almost linearly with the increase of the voltage of the feedback port FB. In the third stage, the difference between the voltage value of the reference voltage port Vref and the voltage value of the feedback port FB is negative and large, so the voltage value of the error amplifier output port EAO is limited to a low clamping voltage of 587mV. The above results are almost consistent with the calculated values.

[0043] like Figure 1 In some embodiments shown, a voltage regulation system is also provided, including a voltage conversion circuit 6, a voltage detection circuit 7, a driving circuit 8 for driving the voltage conversion circuit 6, and the above-mentioned error amplification circuit 1, the output end of the voltage conversion circuit 6 is connected to the input end of the voltage detection circuit 7, the output end of the voltage detection circuit 7 is connected to the input end of the error amplification circuit 1, and the output end of the error amplification circuit 1 is connected to the control end of the driving circuit 8, so that the voltage regulation system can adjust and output more accurately.

[0044] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention is disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with the profession can make some changes or modifications to equivalent embodiments of equivalent changes by using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent changes and modifications made to the above embodiments according to the technology of the present invention are within the scope of the technical solution of the present invention without departing from the content of the technical solution of the present invention.

Claims

1. An error amplifier circuit, characterized in that: The error amplifier EA includes a feedback port FB, a reference voltage port Vref, an error amplification output port EAO, an error amplifier EA, a resistor R1, a resistor R2, a resistor Rc, a capacitor Cz, a current source Ip, a current source In, and a field effect transistor Mn. The error amplifier EA is provided with a first reverse input terminal INN1, a first forward input terminal INP1, a second reverse input terminal INN2, and a second forward input terminal INP2. The first forward input terminal INP1, the second forward input terminal INP2, and one end of the resistor R1 are all connected to the reference voltage port Vref. The second reverse input terminal INN2 and the resistor One end of R2 is connected to the other end of the resistor R1, the other end of the resistor R2 is connected to the error amplifier output port EAO, the feedback port FB is connected to the first reverse input terminal INN1 through the resistor Rc, the error amplifier output port EAO is connected to the first reverse input terminal INN1 through the capacitor Cz, the output end of the error amplifier EA is used to drive the field effect transistor Mn, the input end of the current source Ip is connected to the external power supply, the output end of the current source Ip is connected to the drain of the field effect transistor Mn, the input end of the current source In is connected to the source of the field effect transistor Mn, and the output end of the current source In is grounded; The error amplifier EA includes a first differential pair, a second differential pair and an output amplifier stage, the first control end of the first differential pair is connected to the first reverse input end INN1, the second control end of the first differential pair is connected to the first positive input end INP1, the first control end of the second differential pair is connected to the second reverse input end INN2, the second control end of the second differential pair is connected to the second positive input end INP2, the input end of the first differential pair and the input end of the second differential pair are both connected to an external power supply, and the output end of the first differential pair and the output end of the second differential pair are both connected to the error amplifier output port EAO through the output amplifier stage; The error amplifier circuit further includes a buffer Buffer, a reference voltage port Vref is connected to an input end of the buffer Buffer, and a first positive input end INP1, a second positive input end INP2 and one end of a resistor R1 are all connected to an output end of the buffer Buffer; The buffer Buffer includes a second current mirror unit, a seventh field effect transistor, an eighth field effect transistor and a fifth bias current source, the input end of the second current mirror unit is connected to an external power supply, the first output end of the second current mirror unit is connected to the drain of the seventh field effect transistor, the second output end of the second current mirror unit is connected to the drain of the eighth field effect transistor, the source of the seventh field effect transistor and the source of the eighth field effect transistor are both grounded, the gate of the seventh field effect transistor is connected to the input end of the buffer Buffer, and the gate of the eighth field effect transistor is connected to the output end of the buffer Buffer.

2. The error amplifier circuit according to claim 1, characterized in that: The first differential pair includes a first bias current source, a first field effect transistor and a second field effect transistor, the gate of the first field effect transistor is connected to the first reverse input terminal INN1, the gate of the second field effect transistor is connected to the first forward input terminal INP1, the source of the first field effect transistor and the source of the second field effect transistor are both connected to the output terminal of the first bias current source, the input terminal of the first bias current source is connected to an external power supply, and the drain of the first field effect transistor and the drain of the second field effect transistor are both connected to the input terminal of the output amplifier stage.

3. The error amplifier circuit according to claim 1, characterized in that: The second differential pair includes a second bias current source, a third field effect transistor and a fourth field effect transistor, the gate of the third field effect transistor is connected to the second reverse input terminal INN2, the gate of the fourth field effect transistor is connected to the second forward input terminal INP2, the source of the third field effect transistor and the source of the fourth field effect transistor are both connected to the output terminal of the second bias current source, the input terminal of the second bias current source is connected to an external power supply, and the drain of the third field effect transistor and the drain of the fourth field effect transistor are both connected to the input terminal of the output amplifier stage.

4. The error amplifier circuit according to claim 1, characterized in that: The output amplifier stage includes a first current mirror unit, a fifth field effect transistor, a sixth field effect transistor, a third bias current source and a fourth bias current source, wherein the input end of the first current mirror unit is connected to an external power supply, the first output end of the first current mirror unit is connected to the drain of the fifth field effect transistor, the second output end of the first current mirror unit and the drain of the sixth field effect transistor are both connected to the error amplifier output port EAO, the gate of the fifth field effect transistor and the gate of the sixth field effect transistor are both connected to an external bias voltage, the source of the fifth field effect transistor and the output end of the first differential pair are both connected to the input end of the third bias current source, the source of the sixth field effect transistor and the output end of the second differential pair are both connected to the input end of the fourth bias current source, and the output end of the third bias current source and the output end of the fourth bias current source are both grounded.

5. The error amplifier circuit according to claim 1, characterized in that: The buffer Buffer also includes a ninth field effect transistor, a gate of the ninth field effect transistor is connected to the second output end of the second current mirror unit, a source of the ninth field effect transistor is connected to an external power supply, and a drain of the ninth field effect transistor is connected to the output end of the buffer Buffer.

6. The error amplifier circuit according to claim 5, characterized in that: The buffer Buffer further includes a capacitor Cp, one end of the capacitor Cp is connected to the source of the ninth field effect transistor, and the other end of the capacitor Cp is connected to the gate of the ninth field effect transistor.

7. The error amplifier circuit according to claim 5, characterized in that: The buffer Buffer further includes a resistor R0, one end of the resistor R0 is connected to the drain of the ninth field effect transistor, and the other end of the resistor R0 is grounded.

8. A voltage regulation system, characterized in that: It includes a voltage conversion circuit, a voltage detection circuit, a driving circuit for driving the voltage conversion circuit, and the error amplifier circuit described in any one of claims 1 to 7, wherein the output end of the voltage conversion circuit is connected to the input end of the voltage detection circuit, the output end of the voltage detection circuit is connected to the input end of the error amplifier circuit, and the output end of the error amplifier circuit is connected to the control end of the driving circuit.

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