Panel structure with double insulating layer and manufacturing method

Abstract

The present invention discloses a panel structure with a double-layer insulating layer and a manufacturing method, wherein the manufacturing method includes the following steps: making a gate on a substrate; making a first insulating layer; making a hole on the first insulating layer in the gate region, the bottom of the hole being the gate; making a second insulating layer, the second insulating layer covering the gate at the bottom of the hole on the first insulating layer; making a semiconductor layer on the second insulating layer, the semiconductor layer being located at the hole on the first insulating layer; making a source electrode and a drain electrode on the semiconductor layer. The above technical solution reduces the film thickness of the first insulating layer in the gate region, and after the thinning, the second insulating layer is covered on the gate, thereby reducing the distance between the gate and the source and drain. After reducing the distance between the gate and the source and drain, the turn-on current Ion can be increased, thereby achieving the purpose of reducing the power consumption of the panel, and having a good improvement in the battery life of the panel.

Description

Technical Field

[0001] The present invention relates to the technical field of display panels, and in particular to a panel structure with a double insulating layer and a manufacturing method thereof. Background Art

[0002] With the development and progress of display technology, people have higher requirements on the quality of displays. At present, achieving better display effects has become an inevitable trend in the future display industry.

[0003] IGZO is an amorphous oxide containing indium, gallium and zinc. Its carrier mobility is 20 to 30 times that of amorphous silicon. It can greatly increase the charge and discharge rate of TFT to pixel electrodes, improve the response speed of pixels, have a faster panel refresh rate, low power consumption, and can achieve ultra-high-resolution TFT LCD. At the same time, IGZO is more competitive than low-temperature polysilicon (LTPS) in terms of cost.

[0004] How to further reduce power consumption based on the low power consumption of IGZO? The existing solution is to use a double-layer insulation layer structure to increase the distance d between the gate and the source and drain, thereby reducing capacitance and panel power consumption (Cox = εS / 4πkd, where S is the overlap area and d is the thickness of the insulation layer). However, when using a double-layer insulation layer, the device turn-on current Ion will be reduced, which requires the panel to be equipped with a larger IC drive voltage, which limits the power consumption of the panel. Summary of the invention

[0005] Therefore, it is necessary to provide a panel structure with a double insulating layer and a manufacturing method to solve the problem of reducing the power consumption of the panel.

[0006] To achieve the above object, the inventor provides a method for manufacturing a panel structure with a double insulating layer, comprising the following steps:

[0007] forming a gate on a substrate;

[0008] Making a first insulating layer;

[0009] A hole is formed on the first insulating layer in the gate region, and the bottom of the hole is the gate;

[0010] Making a second insulating layer;

[0011] Manufacturing a semiconductor layer, wherein the semiconductor layer is located at the hole of the second insulating layer on the first insulating layer;

[0012] A source electrode and a drain electrode are formed on the semiconductor layer.

[0013] Furthermore, when manufacturing the gate on the substrate, the following steps are also included:

[0014] Making a plate 1, the plate 1 is located at one side of the gate, and the plate 1 serves as a component of the capacitor;

[0015] When the source and drain are made and the source and drain are connected to the semiconductor layer, the following steps are also included:

[0016] A second electrode plate is manufactured. The second electrode plate is located at one side of the source electrode and the drain electrode and is located on the second insulating layer in the first electrode plate region. The second electrode plate serves as a component of the capacitor.

[0017] Furthermore, the upper surface of the first insulating layer between the gate and the first electrode plate is a plane or a concave surface.

[0018] Furthermore, the mask used to make the hole on the first insulating layer in the gate region is the same as the mask used to make the source and drain on the semiconductor layer, and the mask makes the shape of the first insulating layer the same as that of the source and drain.

[0019] Furthermore, the semiconductor layer is IGZO.

[0020] The inventor provides a panel structure with a double insulating layer, comprising:

[0021] A gate is provided on one side of the substrate;

[0022] A first insulating layer is arranged on the gate, a hole is arranged on the first insulating layer located in the gate region, and the bottom of the hole is the gate;

[0023] A second insulating layer is disposed on the first insulating layer;

[0024] A semiconductor layer is disposed on the second insulating layer, and the semiconductor layer is located at the hole of the second insulating layer on the first insulating layer;

[0025] A source electrode and a drain electrode are provided on the semiconductor layer.

[0026] Furthermore, a first electrode plate is provided on the other side of the substrate, the first insulating layer covers the first electrode plate, and the first electrode plate serves as a component of the capacitor;

[0027] A second electrode plate is arranged on the second insulating layer in the first electrode plate region, and the second electrode plate serves as a component of the capacitor.

[0028] Furthermore, the upper surface of the first insulating layer between the gate and the first electrode plate is a plane or a concave surface.

[0029] Furthermore, the shape of the first insulating layer is the same as that of the source and the drain.

[0030] Furthermore, the semiconductor layer is IGZO.

[0031] Different from the prior art, the above technical solution reduces the thickness of the first insulating layer in the gate region, and after thinning, the second insulating layer covers the gate, thereby reducing the distance between the gate and the source and drain. After reducing the distance between the gate and the source and drain, the turn-on current Ion can be increased, thereby achieving the purpose of reducing the power consumption of the panel and having a good improvement in the battery life of the panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a schematic cross-sectional structure diagram of manufacturing a gate and a first electrode plate on a substrate in Example 1;

[0033] Figure 2 This is a schematic cross-sectional structure diagram of manufacturing a first insulating layer and a hole on a substrate in Example 1;

[0034] Figure 3 This is a schematic cross-sectional structure diagram of manufacturing a second insulating layer on a substrate in Example 1;

[0035] Figure 4 This is a schematic cross-sectional structure diagram of manufacturing a semiconductor layer on a substrate in Example 1;

[0036] Figure 5 It is a schematic cross-sectional structure diagram of manufacturing a source electrode, a drain electrode and a second electrode plate on a substrate in Example 1;

[0037] Figure 6 It is a schematic cross-sectional structure diagram of a panel structure with a double insulating layer according to the second embodiment;

[0038] Figure 7 This is a schematic cross-sectional structure diagram of manufacturing a first insulating layer and a hole on a substrate in Example 3;

[0039] Figure 8 This is a schematic cross-sectional structure diagram of manufacturing a second insulating layer on a substrate in Example 3;

[0040] Fig. 9 This is a schematic cross-sectional structure diagram of manufacturing a semiconductor layer on a substrate in Example 3;

[0041] Fig.10 This is a schematic diagram of the cross-sectional structure of manufacturing a source electrode, a drain electrode and a second electrode plate on a substrate according to Example 3.

[0042] Description of reference numerals:

[0043] 1. Substrate;

[0044] 2. Gate;

[0045] 3. Plate 1;

[0046] 4. The first insulating layer;

[0047] 41. Hole;

[0048] 5. Second insulation layer;

[0049] 6. Semiconductor layer;

[0050] 7. Source;

[0051] 8. Drain;

[0052] 9. Plate 2. DETAILED DESCRIPTION

[0053] In order to explain the technical content, structural features, achieved objectives and effects of the technical solution in detail, the following is a detailed description in conjunction with specific embodiments and accompanying drawings.

[0054] See also Figures 1 to 10 This embodiment provides a method for manufacturing a panel structure with a double insulating layer. The manufacturing method is manufactured on a substrate 1, such as a glass substrate used in the existing process. In the first embodiment, the following steps are included: manufacturing a gate and a plate 1; refer to Figure 1 Specifically, a photoresist is coated on the front of the substrate 1, and the photoresist is patterned, that is, the exposure and development are performed to open the positions where the gate 2 and the plate 3 are to be made, and then the gate metal is plated by evaporation or sputtering, so that the gate 2 is formed on one side of the substrate and the plate 3 is formed on the other side of the substrate. The gate 2 is a component of the thin film transistor (TFT), and the plate 3 is a lower plate of the capacitor. The gate metal can be a metal with excellent conductivity such as aluminum, molybdenum, titanium, nickel, copper, silver, chromium, etc. After the gate 2 and the plate 3 are made, the photoresist is removed. In some embodiments, the plate 1 (or the plate 2) does not need to be made, and the TFT part can be made directly.

[0055] A first insulating layer 4 covering the gate 2 and the electrode plate 1 3 is formed on the gate 2 and the electrode plate 1 3. The first insulating layer 4 prevents the electrical connection between the electrode plate 1 3 and the electrode plate 2 9; see Figure 2 Specifically, an insulating material such as nitride (silicon nitride, etc.), oxide (silicon oxide, silicon dioxide), silicon oxynitride (SiON) or other insulating materials is plated on the front of the substrate. Thus, a first insulating layer 4 is formed on the front of the substrate, and the first insulating layer 4 covers the gate 2 and the plate 3. The film thickness of the first insulating layer 4 is (Amy).

[0056] In order to solve the problem that the device turn-on current Ion will be reduced when the panel is equipped with a double-layer insulating layer, and the implementation of the technology to reduce the power consumption of the panel is also limited, the present application reduces the film thickness of the first insulating layer in the gate area, and after thinning, the second insulating layer is covered on the gate, thereby reducing the distance between the gate and the source and drain (the turn-on current Ion increases with each thinning of the distance between the gate and the source and drain). can be increased by about 68%) to achieve the purpose of reducing panel power consumption. Figure 2 Specifically, a photoresist is coated on the front side of the substrate, and the photoresist is patterned, that is, the exposure and development are performed to open the part where the hole is to be made. Then, the first insulating layer not covered by the photoresist is etched to the surface of the gate using the photoresist as a mask, and a hole 41 is formed on the first insulating layer. The hole 41 is located on the first insulating layer in the gate 2 area. The hole 41 reduces the film thickness of the first insulating layer in the gate area, and then the second insulating layer covering the hole can isolate the connection between the gate and the semiconductor layer. After the hole 41 on the first insulating layer is made, the photoresist is removed.

[0057] After the first insulating layer 4 and the hole 41 are formed, the second insulating layer 5 is formed on the first insulating layer 4. Similarly, the second insulating layer 5 covers the first insulating layer in the area of ​​the gate 2 and the plate 1 3; see Figure 3 Specifically, an insulating material such as nitride (silicon nitride, etc.), oxide (silicon oxide, silicon dioxide), silicon oxynitride (SiON) or other insulating materials is plated on the front side of the substrate to form a second insulating layer 5 on the front side of the substrate. The thickness of the second insulating layer 5 is (Angstroms), the second insulating layer 5 covers the gate 2 at the bottom of the hole 41 on the first insulating layer, and at the same time, the second insulating layer 5 covers the first insulating layer 4 in the electrode 3 area. The first insulating layer 4 and the second insulating layer 5 in the electrode 3 area serve as dielectric layers of the capacitor to avoid electrical connection between the electrode 1 3 and the electrode 2 9.

[0058] See also Figure 4 After the second insulating layer 5 is made, a semiconductor layer 6 is made on the second insulating layer 5 in the region of the hole 41 on the first insulating layer. The material of the semiconductor layer 6 is such as indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO) or indium gallium zinc titanium oxide (IGZTO) or other materials with similar properties, preferably indium gallium zinc oxide (IGZO). The semiconductor layer 6 is a component of the TFT and a conductive channel part.

[0059] After the semiconductor layer 6 is fabricated, a source electrode 7 and a drain electrode 8 are fabricated on the semiconductor layer 6, and a second electrode plate is fabricated on the second insulating layer; see Figure 5Specifically, a photoresist is coated on the front side of the substrate, and the photoresist is patterned, that is, the exposure and development are performed to open the parts where the source electrode 7, the drain electrode 8 and the electrode plate 9 are to be made, and then the source and drain electrode metal is plated by evaporation or sputtering, so as to form the source electrode 7 and the drain electrode 8 on the semiconductor layer 6, and the electrode plate 9 is formed on the second insulating layer 5 in the electrode plate 1 3 area. The source and drain electrode metal can be a metal with excellent conductivity such as aluminum, molybdenum, titanium, nickel, copper, silver, chromium, etc. The source electrode 7 and the drain electrode 8 are also components of the thin film transistor (TFT), and the electrode plate 9 is used as the upper electrode of the capacitor. The electrode plate 9 forms a capacitor with the second insulating layer 5, the first insulating layer 4, and the electrode plate 3 located in the electrode plate 2 9 area. After the source electrode 7, the drain electrode 8 and the electrode plate 2 9 are made, the photoresist is removed.

[0060] In the second embodiment, in order to reduce the impedance between the capacitor and the TFT or to protect the TFT from other influences, a blind hole can be made on the upper surface of the first insulating layer between the TFT and the capacitor, so that the upper surface of the first insulating layer between the gate and the first electrode plate is a concave surface, and no dielectric exists in the concave portion. The structure is as follows: Figure 6 Similarly, when making a blind hole, it is sufficient to etch part of the first insulating layer.

[0061] In the third embodiment, in order to save the number of masks and reduce the cost of the process, the mask for making the source, drain and plate 2 is used to make the hole on the first insulating layer. Because the mask is required for making the source and drain, and the source and drain are originally located on the gate region, the mask can be used to make a hole on the first insulating layer in the gate region. Figures 7 to 10 Specifically, a photoresist is applied, the photoresist is exposed and developed using the mask, and the first insulating layer not covered by the photoresist after development is etched away, and a hole 41 is formed on the first insulating layer 4 in the gate 2 region, and the bottom of the hole 41 is the gate. Another hole is formed on the first insulating layer 4 in the region between the gate 2 and the plate 3, and the structure is as follows Figure 7 As shown. After the hole is made, the photoresist is removed. Because the photomask is the same, the shape of the first insulating layer (located at the hole 41) is the same as the source and drain. Similarly, after the hole 41 is made, the second insulating layer 5 is made on the first insulating layer 4 in the same way as in the first embodiment. The structure is as shown in FIG. Figure 8 As shown; the semiconductor layer 6 is formed on the second insulating layer 5 by the same method as in the first embodiment, and the structure is as follows Fig. 9 As shown; the same method as in Example 1 is adopted to make the source electrode 7 and the drain electrode 8 on the semiconductor layer 6, and the electrode plate 9 is made on the second insulating layer 5 in the electrode plate region. The structure is as shown Fig.10 shown.

[0062] When the above technical solution uses a double-layer insulating layer as the dielectric layer of the capacitor, the capacitance is reduced and the charging time of the capacitor is reduced, which can improve the pixel charging rate, enhance the quality and refresh frequency of the panel structure, and further reduce the power consumption requirements based on the low power consumption characteristic advantage of the IGZO device.

[0063] This embodiment provides a panel structure with a double insulating layer. Figures 1 to 10 In the first embodiment, the gate 2 is provided on one side of the substrate 1, and the plate 3 is provided on the other side of the substrate 1. Figure 1 As shown. The gate 2 is a component of a thin film transistor (TFT), and the plate 1 3 is a lower plate of the capacitor. The gate metal can be a metal with good conductivity such as aluminum, molybdenum, titanium, nickel, copper, silver, chromium, etc. In some embodiments, the plate 1 3 (plate 2) does not need to be formed.

[0064] In order to avoid electrical connection between the electrode plate 1 3 and the electrode plate 2 9, a first insulating layer 4 is provided on the gate 2 and the electrode plate 1 3. Figure 2 The first insulating layer 4 is made of nitride (silicon nitride, etc.), oxide (silicon oxide, silicon dioxide), silicon oxynitride (SiON) or other insulating materials.

[0065] In order to solve the problem that the device turn-on current Ion is reduced when the panel is equipped with a double insulating layer, and the technical means of reducing the power consumption of the panel is also limited, this embodiment reduces the film thickness of the first insulating layer in the gate area, that is, a hole 41 is provided on the first insulating layer in the gate 2 area, and the bottom of the hole 41 is the first insulating layer, and the structure is as follows: Figure 2 A second insulating layer 5 is disposed on the first insulating layer 4, and the second insulating layer 5 covers the first insulating layer 4 and the gate 2 at the bottom of the hole 41, and the structure is as shown in FIG. Figure 3 It should be noted that the thickness of the first insulating layer 4 and the second insulating layer 5 are both (Angstroms). The above technical solution only reduces the thickness of the insulating layer on the gate of the TFT area, and the insulating layer between the capacitor areas will not be thinned, so as to ensure the original capacitance value. Such a structure can reduce the distance between the gate and the source and drain, increase the device turn-on current Ion, and achieve the purpose of reducing capacitance and panel power consumption.

[0066] A semiconductor layer 6 is disposed on the second insulating layer. The semiconductor layer 6 is disposed at the hole 41 on the first insulating layer. The structure is as follows: Figure 4As shown. The semiconductor layer 6 is made of indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium gallium zinc titanium oxide (IGZTO) or other materials with similar properties, preferably indium gallium zinc oxide (IGZO). The semiconductor layer 6 is a component of the TFT and a conductive channel part.

[0067] A source electrode 7 and a drain electrode 8 are arranged on the semiconductor layer 6, and a second electrode plate 9 is formed on the second insulating layer 5 in the electrode plate 1 3 region. Figure 5 As shown. The source electrode 7 and the drain electrode 8 are also components of a thin film transistor (TFT), and the second plate 9 is used as the upper plate of the capacitor. The second plate 9 forms a capacitor with the second insulating layer 5, the first insulating layer 4, and the first plate 3 located in the region of the second plate 9.

[0068] In the second embodiment, in order to reduce the impedance between the capacitor and the TFT or to protect the TFT from other influences, a blind hole is provided on the upper surface of the first insulating layer between the TFT and the capacitor, so that the upper surface of the first insulating layer between the gate and the electrode plate is a concave surface, and the structure is as follows: Figure 6 As shown in the figure, there is no dielectric in the concave part, so the impedance between the capacitor and the TFT is reduced.

[0069] In the third embodiment, the mask used to make the hole on the first insulating layer in the gate region is the same as the mask used to make the source and drain, so that the shape of the first insulating layer (located at the hole 41) is the same as that of the source and drain. This also results in the distance between the source and the drain being the same as the width of the hole on the first insulating layer. At the same time, if the electrode plate 2 needs to be made when making the source and the drain, then when making the hole on the first insulating layer, another hole will be formed on the electrode plate 1 and the first insulating layer in the gate region. The width of the hole is the same as the distance between the drain and the electrode plate 2. The structure is as follows: Figures 7 to 10 shown.

[0070] It should be noted that, although the above embodiments have been described in this article, the patent protection scope of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, changes and modifications made to the embodiments described herein, or equivalent structures or equivalent process changes made using the contents of the present invention specification and drawings, directly or indirectly applying the above technical solutions to other related technical fields, are all included in the patent protection scope of the present invention.

Claims

1. A method for manufacturing a panel structure with a double insulating layer, characterized in that: The steps include: forming a gate on a substrate; Making a first insulating layer; A hole is formed on the first insulating layer in the gate region, and the bottom of the hole is the gate; Making a second insulating layer; Manufacturing a semiconductor layer, wherein the semiconductor layer is located at the hole of the second insulating layer on the first insulating layer; forming a source electrode and a drain electrode on the semiconductor layer; When making a gate on a substrate, the following steps are also included: Making a plate 1, the plate 1 is located at one side of the gate, and the plate 1 serves as a component of the capacitor; When the source and drain are made and the source and drain are connected to the semiconductor layer, the following steps are also included: A second electrode plate is manufactured. The second electrode plate is located at one side of the source electrode and the drain electrode and is located on the second insulating layer in the first electrode plate region. The second electrode plate serves as a component of the capacitor.

2. The method for manufacturing a panel structure with a double insulating layer according to claim 1, characterized in that: The upper surface of the first insulating layer between the gate and the first electrode plate is a plane or a concave surface.

3. The method for manufacturing a panel structure with a double insulating layer according to claim 1, characterized in that: The photomask used to make the hole on the first insulating layer in the gate region is the same as the photomask used to make the source and drain on the semiconductor layer, and the photomask makes the shape of the first insulating layer the same as that of the source and drain.

4. The method for manufacturing a panel structure with a double insulating layer according to claim 1, characterized in that: The semiconductor layer is IGZO.

5. A panel structure with a double insulating layer, characterized in that: include: A gate is provided on one side of the substrate; A first insulating layer is arranged on the gate, a hole is arranged on the first insulating layer located in the gate region, and the bottom of the hole is the gate; A second insulating layer is disposed on the first insulating layer; A semiconductor layer is disposed on the second insulating layer, and the semiconductor layer is located at the hole of the second insulating layer on the first insulating layer; A source electrode and a drain electrode are arranged on the semiconductor layer; A first electrode plate is disposed on the other side of the substrate, the first insulating layer covers the first electrode plate, and the first electrode plate serves as a component of the capacitor; A second plate is arranged on the second insulating layer in the first plate region, and the second plate serves as a component of the capacitor; The upper surface of the first insulating layer between the gate and the first electrode plate is a plane or a concave surface.

6. The panel structure with double insulating layers according to claim 5, characterized in that: The first insulating layer has the same shape as the source and drain.

7. The panel structure with double insulating layers according to claim 5, characterized in that: The semiconductor layer is IGZO.

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