Device with physical non-clonable function of transistor and manufacturing method

Abstract

Devices and methods of manufacturing a physical unclonable function of transistors are described herein. According to one embodiment, a physical unclonable function device includes a set of transistor pairs, transistors in the set of transistor pairs having randomly distributed effective threshold voltages belonging to a common random distribution; a differential read circuit configured to measure a threshold difference between the effective threshold voltages of transistors of transistor pairs in the set of transistor pairs, and identify transistor pairs in which the measured threshold difference is less than a margin value as unreliable transistor pairs; and a write circuit configured to shift the effective threshold voltages of transistors of the unreliable transistor pairs to within the common random distribution.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of French patent application No. 1901792, filed on February 22, 2019, which is hereby incorporated by reference herein. Technical Field

[0003] Implementations and embodiments of the present invention relate to physically unclonable functions (PUFs), particularly in structures including transistors. Background Art

[0004] Physically unclonable functions allow for the automatic generation of unique unpredictable codes that rely on random physical properties. Therefore, cloning such functions is very difficult, if not impossible.

[0005] On the one hand, it is desirable that the physical unclonable functions are sufficiently robust so that they do not change over time, in particular after repeated use or in case of temperature changes. On the other hand, it is desirable that random changes in physical properties are easily identifiable so that various data can be clearly distinguished. Furthermore, it is desirable that the generation of the physical unclonable functions requires no or only few dedicated manufacturing steps.

[0006] The unique unpredictable code usually consists of a random sequence of data and is primarily used as an encryption key. This data is usually kept secret.

[0007] The fact is that there are some techniques, in particular those using scanning capacitance microscopy (SCM) or scanning electron microscopy (SEM), which are able to extract secret data, ie to read the data by measurement, inspection and / or analysis.

[0008] This is especially true for conventional structures that are intended to achieve robust data retention and data readability. Specifically, conventional techniques that increase the ability to retain and distinguish data for readout also typically increase the ability of extraction techniques to distinguish data. Summary of the invention

[0009] According to one embodiment, a physically unclonable functional device includes: a set of transistor pairs, transistors in the set of transistor pairs having randomly distributed effective threshold voltages belonging to a common random distribution; a differential read circuit configured to measure a threshold difference between the effective threshold voltages of transistors of transistor pairs in the set of transistor pairs, and identify transistor pairs in which the measured threshold difference is less than a margin value as unreliable transistor pairs; and a write circuit configured to shift the effective threshold voltages of transistors of the unreliable transistor pairs to within the common random distribution.

[0010] According to another embodiment, a method includes: providing a set of transistor pairs, wherein effective threshold voltages of transistors in the set of transistor pairs are randomly distributed according to a common random distribution; measuring a threshold difference between the effective threshold voltages of transistors in the set of transistor pairs, and identifying transistor pairs in the set of transistor pairs whose measured threshold difference is less than a margin value as unreliable transistor pairs; and shifting the effective threshold voltages of transistors in the unreliable transistor pairs to within the common random distribution.

[0011] According to yet another embodiment, an integrated circuit includes: a plurality of transistor pairs, wherein a first transistor of each of the plurality of transistor pairs is coupled to a first bit line, and a second transistor of each of the plurality of transistor pairs is coupled to a second bit line, and the transistors in the plurality of transistor pairs have effective threshold voltages that are randomly distributed according to a common random distribution; a read circuit having a first input coupled to the first bit line and a second input coupled to the second bit line, wherein the read circuit is configured to measure a threshold difference between the first transistor and the second transistor of each of the plurality of transistor pairs, and compare the measured threshold difference with a predetermined threshold; and a write circuit coupled to gates of the first transistor and the second transistor of each of the plurality of transistor pairs, wherein the write circuit is configured to shift the effective threshold voltage of the first transistor and the second transistor of each transistor pair so that the measured threshold difference is greater than the predetermined threshold and within the common random distribution. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Other advantages and features of the invention will become apparent by examining the detailed description of a purely non-limiting implementation and embodiment and the accompanying drawings, in which:

[0013] Figure 1A The threshold distribution of the memory is illustrated;

[0014] Figure 1B A scanning capacitance micrograph SC of a transistor storing data is shown;

[0015] Figure 2 An example embodiment of the present invention is illustrated;

[0016] Figure 3 An example embodiment of the present invention is illustrated;

[0017] Figure 4 An example embodiment of the present invention is illustrated;

[0018] Figure 5 An example embodiment of the present invention is illustrated;

[0019] Figure 6 An example embodiment of the present invention is illustrated;

[0020] Figure 7 An example embodiment of the present invention is illustrated;

[0021] Figure 8 An example embodiment of the present invention is illustrated;

[0022] Fig. 9 An example implementation of the present invention is illustrated;

[0023] Fig.10 An example implementation of the present invention is illustrated;

[0024] Fig.11 An exemplary embodiment of the present invention is illustrated. DETAILED DESCRIPTION

[0025] Implementations and embodiments of the present invention relate to physically unclonable functions (PUFs), particularly in structures including transistors.

[0026] According to one embodiment, the differential read circuit is further configured to read a logic state of a pair of transistors, the logic state being defined by a difference between values ​​of effective threshold voltages of the pair of transistors that is greater than a margin value.

[0027] According to one embodiment, the write circuit is configured to shift the effective threshold voltage of each unreliable pair of transistors so as to increase the difference between the effective threshold voltages above a margin value.

[0028] According to one embodiment, a write circuit is configured to shift an effective threshold voltage of a transistor by generating conditions for hot carrier injection to trap charge in a gate dielectric of the transistor.

[0029] Advantageously, the write circuit for shifting the effective threshold voltage of the transistor is configured to generate a series of write pulses, the series of write pulses each generating conditions for hot carrier injection.

[0030] Advantageously, the differential read circuit is configured to perform a margin verification between at least some of the write pulses, the margin verification comprising comparing a difference between the values ​​of the effective threshold voltages of the pair of transistors with a margin value.

[0031] According to one embodiment, the logic states of the sets of paired transistors are intended to form a random data sequence.

[0032] An integrated circuit may comprise a physically unclonable functional device such as defined in the following embodiments, and an encryption device configured to encrypt data using a key, the key advantageously comprising a random data sequence.

[0033] According to another aspect, a process is provided that includes producing a physically unclonable function, the production including: manufacturing a set of pairs of transistors intended to have the same threshold voltage; randomly dispersing the effective values ​​of the threshold voltages of the transistors to form a common random distribution of the threshold voltages of the transistors; measuring the difference between the effective threshold voltages of the pairs of transistors, and identifying so-called unreliable pairs of transistors whose difference between their effective threshold voltages is less than a margin value; and shifting the effective threshold voltage of the transistors in each unreliable pair in a controlled and limited manner so that the shifted threshold voltages remain within the common random distribution.

[0034] According to one embodiment, the process further includes reading a logic state of a pair of transistors, the logic state defined by a difference between values ​​of effective threshold voltages of the pair of transistors that is greater than a margin value.

[0035] For example, the shifting includes increasing the difference between the effective threshold voltages of transistors in the unreliable pair above a margin value.

[0036] According to one implementation, shifting the effective threshold voltage of the transistor includes generating conditions for hot carrier injection and trapping charge in a gate dielectric of the transistor.

[0037] Advantageously, shifting the effective threshold voltage of one of the transistors comprises generating a sequence of write pulses, each write pulse generating conditions for hot carrier injection.

[0038] Advantageously, the shifting comprises a margin verification between at least some of the write pulses, the margin verification comprising measuring the difference between the values ​​of the effective threshold voltages of pairs of transistors and comparing the measured difference with a margin value.

[0039] According to one implementation, the logic states of the sets of paired transistors are intended to form a random data sequence.

[0040] The encryption method may advantageously comprise encrypting the data using a key, wherein the key comprises a random data sequence obtained using a process such as defined by the latter implementation.

[0041] Figure 1A A conventional technique for achieving robust data retention and data readability is illustrated, in which data is defined by the level of a transistor threshold voltage Vt. A first transistor has a threshold voltage Vt belonging to a low level distribution D1 that allows, for example, a first logic value "1" to be defined. A second transistor has a threshold voltage Vt belonging to a high level distribution D0 that allows, for example, a second logic value "0" to be defined.

[0042] Figure 1B Illustrated using reference Figure 1AScanning capacitance micrograph SC of transistors using the technique presented to store data. If the positions of the transistors are known, the stored data sequence 1010 can be easily extracted. Specifically, the channel region of the first transistor in the black circle (whose threshold voltage belongs to the low level distribution D1) and the channel region of the second transistor in the white circle (whose threshold voltage belongs to the high level distribution D0) can be seen in the image SC. Of course, this is problematic.

[0043] Therefore, there is a need to provide a physically unclonable functional structure that is robust against external changes or aging and whose data can be clearly distinguished for readout while being difficult to extract. Furthermore, it would be beneficial if the structure could be easily manufactured in the prior art.

[0044] According to one aspect, a physically unclonable functional device is provided, comprising: a set of paired transistors intended to have the same threshold voltage but each having an effective threshold voltage belonging to a common random distribution; a differential read circuit configured to measure the difference between the effective threshold voltages of the paired transistors and identify so-called unreliable pairs of transistors whose difference between their effective threshold voltages is less than a margin value; and a write circuit configured to shift the effective threshold voltage of the transistors in each unreliable pair in a controlled and limited manner so that the shifted threshold voltages remain within the common random distribution.

[0045] Therefore, the device according to this aspect benefits from the advantages of transistor data storage, i.e. very good retention, robustness and well characterized manufacturing processes and operating parameters. Since the effective threshold voltages all belong to a common random distribution, the functionality is not only physically unclonable, but also cannot be extracted using state of the art microscopy techniques. In unreliable pairs, the shift of the effective threshold voltage allows to ensure the feasibility of the technology, in particular to ensure the distinction between two effective threshold voltages that may be equal or initially very close.

[0046] The transistor may be a MOS (metal oxide silicon) transistor specifically comprising a gate and a gate dielectric, or in a specific embodiment, may be a transistor comprising a floating gate and a control gate and a gate dielectric, the floating gate and the control gate being superimposed and electrically coupled to each other. The gate dielectric is advantageously capable of trapping charge by hot carrier injection.

[0047] Figure 2 An example embodiment of a physically unclonable functional device DIS is shown.The device DIS comprises a set ENS of pairs P of transistors OTP1, OTP2.

[0048] A transistor typically includes source and drain regions implanted into a semiconductor body, a channel region in the body between the source and drain regions, and a conductive gate region insulated from the channel region by a gate dielectric. Typically, the gate dielectric comprises a formation of silicon oxide or optionally silicon nitride.

[0049] According to an example embodiment, the transistors have a floating gate transistor structure (ie, they are transistors whose gate region includes a floating gate that is electrically insulated from the channel region and from a control gate located above the floating gate), wherein the floating gate and the control gate of the transistor are electrically connected to each other.

[0050] The threshold voltage of a transistor is the voltage between the source region and the control gate at which the channel region depletes and becomes conductive.

[0051] A logical state defined by the level of the threshold voltage of the transistor can be stored in such a transistor.In order to modify the level of the threshold voltage of the generated transistor, charges can be trapped in the gate dielectric, in particular by hot carrier injection.

[0052] The transistors OTP1 , OTP2 of the set ENS are intended to have the same threshold voltage.

[0053] As such, the effective threshold voltage (i.e., the actual value of the threshold voltage) varies slightly according to random dispersion, for example due to physical manufacturing variables. This type of dispersion is common and known per se. The effective threshold voltage of each pair of transistors referenced by OTP1 is referenced by A1-F1, and the effective threshold voltage of each pair of transistors referenced by OTP2 is referenced by A2-F2.

[0054] The transistors of the example embodiments in which the transistor structure is a floating gate structure with the gate electrically connected inherently have greater variability in response to these variables and therefore have a wider distribution than other types of electronic components (e.g., resistors or MOS (metal oxide silicon) transistors).

[0055] Therefore, the transistors OTP1, OTP2 of the set ENS each have an effective threshold voltage A1-F1, A2-F2 belonging to a common random distribution.

[0056] In particular, the transistors OTP1 , OTP2 may advantageously be kept in a pristine state, ie initially without trapped charges in their gate dielectrics.

[0057] Figure 3 The scanning capacitance micrograph of transistors belonging to the set ENS is illustrated. Each transistor has its own effective threshold voltage within the distribution of the original transistor threshold voltage Vteff. In this way, it is impossible to see any difference between the values ​​of the threshold voltages in this image.

[0058] Reference again Figure 2 , the device DIS comprises a differential read circuit LECT, which is configured to measure the difference between the effective threshold voltages of the transistors OTP1, OTP2 of the pair P.

[0059] The differential read circuit LECT comprises two differential inputs to which each pair P of transistors OTP1 , OTP2 is coupled, in particular, via a respective bit line BL1 , BL2 .

[0060] In this regard, now refer to Figure 4 and Figure 5 . Figure 4 An example of an embodiment of a differential read circuit LECT coupled to a pair of transistors OTP1 , OTP2 via respective bit lines BL1 , BL2 is shown.

[0061] In this example, the transistors OTP1 , OTP2 belong to the respective memory cells CEL1 , CEL2 , wherein the access transistors TA1 , TA2 are connected via their drains to the sources of the transistors OTP1 , OTP2 and via their sources to the ground GND.

[0062] The access transistors TA1, TA2 are controlled via their gates by signals transmitted on the respective word lines WL1, WL2.As will become clear below, the word lines WL1, WL2 may optionally be common to a pair, ie electrically connected or even formed by the same conductive line.

[0063] The gates of the transistors OTP1, OTP2 are connected to respective gate control lines CGL1, CGL2. Likewise, the gate control lines CGL1, CGL2 may optionally be common to a pair of transistors, i.e. electrically connected or even formed by the same conductive line. The drains of the transistors OTP1, OTP2 are connected, for their part, to respective bit lines BL1, BL2.

[0064] Bit line BL1 allows one transistor OTP1 of the pair to be coupled to a first input E1 of a sense amplifier AMP. Bit line BL2 allows the other transistor OTP2 of the pair to be coupled to a second input E2 of the sense amplifier AMP.

[0065] The other transistors in the set ENS of pairs P are coupled in the same way to the sense amplifier AMP, and respective input switches TBL1 , TBL2 allow selection of the pair of bit lines BL1 , BL2 that are desired to be coupled to the inputs E1 , E2 .

[0066] Furthermore, the read circuit LECT comprises a reference current generator IGEN which generates a reference current IREF drawn by the first input E1 or by the second input E2 depending on the position of the respective switch SW1 , SW2 .

[0067] Figure 5 An example of an embodiment of a differential read circuit LECT in operation is shown. The read amplifier AMP is configured to amplify the difference between the current through its first input E1 and the current through its second input E2. To this end, the input switches TBL1, TBL2 are controlled so as to connect the bit lines BL1, BL2 of the desired pair of transistors.

[0068] The access transistor TA1, TA2 of each transistor OTP1, OTP2 is turned on by the voltage transmitted on the word line WL1, WL2. Likewise, the transistor OTP1, OTP2 is controlled by the control voltage transmitted on the gate control line CGL1, CGL2.

[0069] Thus, the transistor OTP1 of the pair is placed so that the read current I1 flows from the first input E1 to the ground GND. The other transistor OTP2 of the pair is likewise placed so that the read current I2 flows from the second input E2 to the ground GND.

[0070] Since the read currents I1 , I2 represent the effective threshold voltages of the respective transistors OTP1 , OTP2 , the difference between the currents I1 , I2 represents the difference between the effective threshold voltages of the paired transistors OTP1 , OTP2 .

[0071] The differential read circuit LECT is therefore able to measure the difference between the effective threshold voltages of the pair of transistors OTP1 , OTP2 .

[0072] Furthermore, an additional current IREF generated by one of the reference current generators IGEN can be added to one of the currents I1, I2 through the inputs E1, E2 via control of the switches SW1, SW2. In the example shown, the switch SW2 is closed and the current IREF is added to the current I2 of the second input E2.

[0073] This allows the difference between the effective threshold voltages to be measured relative to a certain margin. The value of the margin corresponds to the current IREF, which represents the reference voltage deviation.

[0074] In particular, the margin value is selected according to the accuracy of the differential read circuit LECT.

[0075] Reference now Figure 6, which shows examples of various threshold voltage values ​​A1, B1, C1, D1, E1, F1 of one transistor OTP1 in each pair of the set ENS, and threshold voltage values ​​A2, B2, C2, D2, E2, F2 of the corresponding other transistor OTP2 in each pair. The values ​​A1 to F1, A2 to F2 all belong to a common random distribution DST of effective threshold voltages Vteff.

[0076] According to an example embodiment, a differential read circuit LECT (eg, as shown in FIG. Figure 4 and Figure 5 The described) is also configured to read the logic state DAT of each pair of transistors OTP1, OTP2. The logic state DAT is defined by the difference between the values ​​of the effective threshold voltages of the pair being greater than the margin value MRG.

[0077] For example, if X1>X2+MRG, then DAT=1, and if X2>X1+MRG, then DAT=0, where X1 is any one of values ​​A1 to F1, and X2 is any one of values ​​A2 to F2.

[0078] Thus, a logical state is obtained in a physically unclonable manner using random deviations in the values ​​of the effective threshold voltages of the two transistors in a pair. Assuming that these effective threshold voltages are close and belong to a common random distribution DST, the two stored data cannot be distinguished by microscopic inspection.

[0079] It will be noted that in the figure, some pairs of threshold voltage values ​​C1, C2 and E1, E2 may be so close as to have a deviation less than the margin value MRG. Pairs of transistors having these pairs of values ​​are referred to as unreliable pairs NF.

[0080] Reference again Figure 2 , the differential read circuit LECT is configured to use, for example, a reference circuit such as the above Figure 4 and Figure 5 The differential measurement is used to identify transistors of a pair P belonging to a so-called unreliable pair NF. If the difference between the effective threshold voltages of the transistors is less than a margin value (e.g., as described above with reference to Figure 4 and Figure 5 The margin value MRG), then the transistors OTP1 and OTP2 in pair P are called unreliable.

[0081] The device DIS finally comprises a write circuit ECR capable, inter alia, of generating a write pulse IMP.

[0082] The write pulse IMP may comprise applying a potential difference between the gate and drain of the transistor sufficient to cause injection of charge into the gate dielectric via hot carrier injection.

[0083] Hot carrier injection is well known in the art. Briefly, conditions that lead to hot carrier injection can be achieved by applying high voltages to the drain and gate regions of a transistor. Stress can also be applied to the gate dielectric. For example, applying V D =4.5V drain voltage and V G =8V gate voltage allows hot carrier injection to trap negative charges in the SiO 2 The trapping of negative charge in the gate dielectric increases the value of the transistor's threshold voltage.

[0084] Therefore, rather than creating two populations of transistors whose threshold voltages are strictly different (e.g. Figure 1A In contrast to the conventional technique of FIG. 1 , the write pulse IMP is controlled and limited, and the threshold voltage is allowed to shift slightly enough so that the newly shifted threshold voltage can be reasonably considered to belong to the same common random distribution.

[0085] According to the following reference Fig.10 Implementation described, the write circuit ECR (optionally in cooperation with the read circuit LECT) may according to an example embodiment be configured to generate write pulses.

[0086] In this regard, reference Figure 7 , which returns Figure 6 In the example shown, the effective threshold voltages C2 and E1 of one transistor in each unreliable pair NF have been shifted to shifted values ​​C2', E1'. The write circuit ECR is configured to shift the effective threshold voltages C2, E1 of the transistors in each unreliable pair NF so as to increase the difference between the effective threshold voltages to above the margin value MRG. This allows the logic state DAT defined by the difference between the values ​​of the effective threshold voltages of the pair that is greater than the margin value MRG to be reliably read in the pair identified as the unreliable pair NF.

[0087] Of course, in theory, this means slightly modifying the initial distribution DST to a shifted distribution DST'. In this way, it is reasonable to assume that the shifted values ​​C2' and E1' belong to the initial common distribution (i.e., the common random distribution DST obtained at the time of manufacture). Specifically, the distribution of the low-level threshold voltage D1 and the high-level threshold voltage D0 (also corresponding to Figure 1A ), distributions DST and DST' are very similar and are considered to be the same.

[0088] In other words, the write circuit ECR is configured to shift the effective threshold voltage of the transistors in each unreliable pair NF in a controlled and limited manner within the common random distribution DST.

[0089] In any case, as long as the values ​​of the shifted threshold voltages cannot be distinguished using scanning microscopy techniques, they can be considered to lie within a common random distribution DST.

[0090] The populations of transistors of the low-level threshold voltage distribution D1 and the high-level threshold voltage D2 can be distinguished by scanning microscopy, but the populations of transistors of the initial distribution DST and the shifted distribution DST′ cannot be distinguished.

[0091] Figure 8 is a box plot showing the threshold voltage value results for the shift achieved under various conditions. The boxes in the figure are defined by the values ​​of the first quartile and the third quartile and intersect with the median. The segments at the ends extend all the way to the extreme values, possibly excluding abnormal data. The measurement results of the threshold voltage Vteff of transistors Sp1, Sp2, Sp3, and Sp4 for four populations are shown by corresponding boxes, and the measurement results of the threshold voltage Vteff for six measurement environments T0, T1, T2, T3, T4, and T5 are shown. Populations Sp1, Sp2, Sp3, and Sp4 correspond to structural variations of transistors. The measurement environment T0 corresponds to a transistor in its initial production state. In the initial state, each population has an effective threshold voltage dispersed with a random distribution of approximately -1.0V to -1.5V.

[0092] The measurement environment T1 corresponds to a transistor that has been subjected to a voltage stress for 0.1 seconds. The voltage stress condition allows the injection of hot carriers into the gate dielectric of the transistor. As a result, charges are trapped in the gate dielectric and the effective threshold voltage of the transistor is shifted.

[0093] The stress state corresponds to V D =4.5V drain voltage and V G =8V gate voltage. Figure 4 and Figure 5 In the example embodiment described, a voltage of 1V is applied to the gate of transistor TA in order to saturate transistor TA and obtain optimal stress conditions (particularly in terms of hot carrier population in the drain region of transistor TA). The shifted threshold voltage under these conditions is centered around 0.0V to 0.5V.

[0094] Measurement environments T2 and T3 correspond to the same stress conditions applied for 1.0s and 2.0s duration, respectively. The measured values ​​show an additional shift in the threshold voltage after 1 second of stress, to substantially about 1.0V to 1.5V; and no significant change between 1 second and 2 seconds of stress. Measurement environments T4 and T5 correspond to transistors that have been subjected to the stress conditions of environment T2 or T3 and corresponding annealing for 24h and 72h.

[0095] The values ​​measured in environments T4 and T5 are very similar and show that the values ​​after annealing are more uniform and reduced. In this way, the reduction in value does not mean that the initial threshold voltage value is reestablished and they remain shifted relative to the latter. The values ​​of the threshold voltage after annealing are basically centered around -0.5V to 0.0V.

[0096] about Figure 8 The proposed measurement environment is an experimental measurement representing the overall behavior of a transistor in response to a stress condition.

[0097] Of course, the shift of the effective threshold voltage achieved by the write circuit ECR in a controlled and limited manner within the common random distribution DST is not as large as these experimental measurements.

[0098] Fig. 9 Examples of implementations, including in particular the process of generating a physical unclonable function, are shown. Figures 2 to 8 related.

[0099] The process comprises a step 71 of manufacturing a set ENS of transistors OTP1, OTP2 in pairs P. The manufacturing of the transistors is identical so that the transistors manufactured are intended to have the same threshold voltage.

[0100] This process includes a random dispersion 72 of the effective values ​​of the threshold voltages Vteff of the transistors. The dispersion is caused in particular by physical manufacturing variations and is therefore at least partly accomplished directly in the manufacturing step 71. The dispersion of the effective values ​​forms a common random distribution DST of the threshold voltages of the transistors of the set ENS.

[0101] It is conceivable that a situation in which random dispersion of the enhancement threshold voltage is achieved in a dedicated step or in the manufacturing step 71 .

[0102] The process comprises the steps of measuring 73 the difference between the effective threshold voltages Vteff of pairs of transistors and identifying 74 pairs of transistors considered to be unreliable pairs NF, the difference between the effective threshold voltages of the unreliable pairs NF being smaller than a margin value MRG.

[0103] Finally, the process consists in shifting 75 the effective threshold voltage of the transistors in each unreliable pair NF in a controlled and limited manner within the common random distribution DST.

[0104] The shift 75 is implemented in order to increase the difference between the effective threshold voltages of the transistors in the unreliable pair NF above the margin value MRG.

[0105] Reference now Fig.10 , Fig.10An example of an implementation of the shift 75 is illustrated. In this example, the shift 75 of the effective threshold voltage comprises a series of write pulses 751. Each write pulse 751 generates conditions allowing hot carrier injection to be obtained in order to trap charge in the floating gate of the transistor whose threshold voltage is to be shifted.

[0106] In this sequence, margin verification (752, 753) is performed between at least some of the write pulses 751. The margin verification comprises measuring 752 the difference between the values ​​of the effective threshold voltages of pairs of transistors after one or more write pulses 751 and then comparing 753 the measured difference with a margin value MRG.

[0107] If the measured difference 752 is smaller than the margin value MRG(nok), a new cycle including a write pulse 751 and margin verification 752, 753 is added to the sequence.

[0108] When the measured difference 752 is greater than or equal to the margin value MRG(ok), the shift 75 ends 754. By means of the margin verification 752, 753 in the sequence of write pulses 751, the threshold voltage is shifted in a controlled and limited manner so as not to cause the threshold voltage value to lie outside the common random distribution DST obtained during manufacturing.

[0109] Reference again Fig. 9 , the process further comprises a step 76 of reading a logic state DAT of the pair of transistors, the logic state being defined by a difference between the values ​​of the effective threshold voltage Vteff being greater than a margin value MRG.

[0110] The logic state DAT thus formed in the set ENS of transistors OTP1 , OTP2 of the pair P can be intended, for example, to form a random data sequence.

[0111] Fig.11 For example, using references such as those above Fig. 9 and Fig.10 The integrated circuit CI obtained by the described process includes the integrated circuit CI as described above. Figures 2 to 8 The physically unclonable functional device DIS described.

[0112] In the device DIS, the logic states DAT of the set ENS of transistors OTP1, OTP2 of pairs P are therefore intended to form a random data sequence.

[0113] In this example, the integrated circuit CI is able to execute an encryption method consisting in encrypting the CFR data DNC using a key K comprising a random data sequence formed and stored in the set ENS of pairs of transistors.

[0114] The encryption circuit CFR incorporated in the integrated circuit CI is configured to encrypt the data DNC using the key K.

[0115] Furthermore, the integrated circuit CI may comprise a non-volatile memory NVM comprising memory cells each having a floating gate transistor advantageously manufactured in the same manufacturing step 71 as the set ENS of pairs of transistors OTP1, OTP2 of pairs P. In this case, the pairs of transistors OTP1, OTP2 of the set ENS are obtained by subsequently electrically connecting the floating gate of the floating gate transistor structure thus manufactured to the control gate.

[0116] In summary, a physical unclonable function technology has been proposed in which the logic state is defined by the relative difference between two pieces of information belonging to the same distribution. The data cannot be extracted using prior art methods (scanning capacitance microscopy (SCM) or scanning electron microscopy (SEM)). The technology does not necessarily require a specific and dedicated process.

[0117] Furthermore, the present invention is not limited to these embodiments, but covers, for example, all modifications thereof, even if the above reference Figure 4 and Figure 5 The example embodiments described involve current mode differential sense amplifiers, but differential sensing can also be performed in voltage mode, or indeed even Figure 6 and Figure 7 The shift direction shown in is increasing, but it can also be reduced by injecting charges of opposite sign.

Claims

1. A physically unclonable functional device, comprising: a set of transistor pairs, transistors in the set of transistor pairs having randomly distributed effective threshold voltages belonging to a common random distribution, wherein a first set of transistor pairs in the set of transistor pairs comprises logic states, and each logic state is one of a first logic state or a second logic state; The differential read circuit is configured as: measuring a threshold difference between effective threshold voltages of transistors of transistor pairs in the set of transistor pairs, identifying transistor pairs in which the measured threshold difference is less than the margin value as unreliable transistor pairs, detecting the first logic state when an effective threshold of a first transistor of a corresponding transistor pair in the set of transistor pairs is greater than a sum of an effective threshold of a second transistor of the corresponding transistor pair and a predetermined threshold; as well as detecting the second logic state when the effective threshold of the second transistor is greater than the sum of the effective threshold of the first transistor and the predetermined threshold; as well as A write circuit is configured to shift effective threshold voltages of transistors of the unreliable transistor pair to within the common random distribution. 2 . The device of claim 1 , wherein the write circuit is configured to shift the effective threshold voltage of the transistor of the unreliable transistor pair to increase the threshold difference above the margin value.

3. The device of claim 1 , wherein the write circuit is configured to shift the effective threshold voltage of the transistor of the unreliable transistor pair by generating a condition for hot carrier injection to trap charge in the gate dielectric of the transistor of the unreliable transistor pair. 4 . The device of claim 3 , wherein the write circuit is configured to generate the condition for hot carrier injection by applying a series of write pulses to the transistor of the unreliable transistor pair.

5. The device of claim 4, wherein the differential read circuit is configured to perform a margin verification after at least one write pulse in the series of write pulses, wherein performing the margin verification comprises comparing the measured threshold difference with the margin value. 6 . The device of claim 1 , wherein a sequence of first logic states and second logic states detected by the differential read circuit forms a random data sequence.

7. An integrated circuit comprising: The physically unclonable functional device according to claim 6; as well as The encryption device is configured to encrypt data using a key, wherein the key includes the random data sequence.

8. A method for manufacturing a physically unclonable functional device, comprising: providing a set of transistor pairs, wherein effective threshold voltages of transistors in the set of transistor pairs are randomly distributed according to a common random distribution, wherein a first set of transistor pairs in the set of transistor pairs includes logic states, and each logic state is one of a first logic state or a second logic state; measuring a threshold difference between effective threshold voltages of the transistors in the set of transistor pairs; identifying a transistor pair in the set of transistor pairs whose measured threshold difference is less than a margin value as an unreliable transistor pair; as well as shifting the effective threshold voltages of transistors of the unreliable transistor pair to within the common random distribution; detecting the first logic state when an effective threshold of a first transistor of a corresponding transistor pair in the set of transistor pairs is greater than a sum of an effective threshold of a second transistor of the corresponding transistor pair and a predetermined threshold; as well as The second logic state is detected when the effective threshold of the second transistor is greater than the sum of the effective threshold of the first transistor and the predetermined threshold.

9. The method of claim 8, wherein the shifting comprises: The threshold difference of the unreliable transistor pair is increased above the margin value.

10. The method of claim 8, wherein shifting the effective threshold voltage of the transistor of the unreliable transistor pair comprises: Conditions for hot carrier injection are generated to trap charge in the gate dielectric of the transistor of the unreliable transistor pair.

11. The method of claim 10, wherein generating the conditions for hot carrier injection comprises: A series of write pulses are applied, each generating the conditions for hot carrier injection.

12. The method according to claim 11, further comprising: A margin verification is performed after at least one write pulse in the series of write pulses, wherein performing the margin verification includes comparing the measured threshold difference with the margin value.

13. The method according to claim 8, further comprising: Based on detecting the first logic state and detecting the second logic state, a sequence of a first logic state and a second logic state is detected. The method of claim 13 , wherein the sequence of first logic states and second logic states forms a random data sequence.

15. The method according to claim 14, further comprising: Data is encrypted using a key, wherein the key includes the random data sequence.

16. The method according to claim 8, further comprising: The set of transistor pairs is fabricated, wherein each transistor in the set of transistor pairs is fabricated to have a same nominal threshold voltage.

17. An integrated circuit comprising: A plurality of transistor pairs, wherein A first transistor of each transistor pair of the plurality of transistor pairs is coupled to a first bit line, A second transistor of each transistor pair of the plurality of transistor pairs is coupled to a second bit line, transistors in the plurality of transistor pairs have randomly distributed effective threshold voltages according to a common random distribution, A first set of transistor pairs in the plurality of transistor pairs comprises a logic state, and Each logic state is one of a first logic state or a second logic state; a read circuit having a first input coupled to the first bit line and a second input coupled to the second bit line, wherein the read circuit is configured to: measuring a threshold difference between the first transistor and the second transistor of each transistor pair of the plurality of transistor pairs, and comparing the measured threshold difference with a predetermined threshold value, The first logic state is detected when the effective threshold of the first transistor is greater than the sum of the effective threshold of the second transistor and the predetermined threshold, and detecting the second logic state when the effective threshold of the second transistor is greater than the sum of the effective threshold of the first transistor and the predetermined threshold; as well as A write circuit is coupled to the gates of the first transistor and the second transistor of each transistor pair of the plurality of transistor pairs, wherein the write circuit is configured to shift the effective threshold voltage of the first transistor and the second transistor of each transistor pair so that the measured threshold difference is greater than the predetermined threshold and within the common random distribution.

18. The integrated circuit of claim 17, wherein the read circuit comprises: a read amplifier coupled to the first input and the second input of the read circuit; as well as A reference current generator is coupled to the first input or the second input, wherein the read circuit is configured to compare the measured threshold difference with the predetermined threshold by activating the reference current generator and measuring a voltage difference between the first input and the second input.

19. The integrated circuit of claim 17, wherein the write circuit is configured to shift the effective threshold voltage of the first transistor or the second transistor of each transistor pair by applying at least one write pulse to the corresponding first transistor or the second transistor.

20. The integrated circuit of claim 17, further comprising an encryption circuit coupled to the plurality of transistor pairs, wherein the encryption circuit is configured to use the logic states of the plurality of transistor pairs as an encryption key.

Images