Memory

Abstract

The present invention provides a memory. By further extending the node contact portion into the substrate to electrically connect with the active region, the contact area between the node contact portion and the active region is increased, and the node contact portion can be electrically connected to a region with a high ion concentration. Based on this, even if there are voids formed in the node contact portion, the connection performance of the node contact portion can still be maintained. For the node contact portion that allows voids, its manufacturing difficulty is greater and the preparation process is faster, and accordingly, the production capacity of the memory can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a memory. Background Art

[0002] A memory, such as a Dynamic Random Access Memory (DRAM), generally includes a storage capacitor and a storage transistor electrically connected to the storage capacitor. The storage capacitor is used to store charges representing storage information, and the storage transistor can be electrically connected to the storage capacitor through a node contact portion.

[0003] Based on existing memories, there are still problems of high manufacturing difficulty and cumbersome preparation processes. For example, when preparing the node contact portion, in order to ensure good electrical connection between the node contact portion and the storage transistor, the requirements for the preparation process of the node contact portion are also relatively high. For example, the deposition process used needs to have good filling performance. At this time, it will inevitably lead to strict production requirements and a slow preparation process for the node contact portion, which will not only affect the production efficiency of the memory but also result in low utilization of semiconductor processing equipment. Summary of the Invention

[0004] The purpose of the present invention is to provide a memory to reduce the manufacturing difficulty of the memory and speed up the preparation process of the memory, so as to facilitate the improvement of production capacity.

[0005] To solve the above technical problems, the present invention provides a memory, including:

[0006] A substrate, in which a plurality of active regions are formed;

[0007] A plurality of bit line structures formed on the substrate, and a node contact window is defined by adjacent bit line structures, and the bottom of the node contact window also extends into the substrate and exposes at least part of the active region; and

[0008] A plurality of node contact portions filled in the node contact window and electrically connected to the active region, and at least one void is formed in the node contact portion, and the top of the void is not lower than the bottom of any adjacent bit line structure.

[0009] In the memory provided by the present invention, the node contact portion can be embedded into the substrate to be electrically connected to the active region. On the one hand, the contact area between the node contact portion and the active region can be increased; on the other hand, the node contact portion can be brought into contact with the region having a higher ion concentration in the active region. Thus, it is beneficial to improve the contact resistance between the node contact portion and the active region. Based on this, in the memory provided by the present invention, voids can be allowed to be formed in the node contact portion. Therefore, when fabricating the node contact portion, a rapid deposition method can be adopted to fabricate the node contact portion faster, thereby accelerating the fabrication process of the memory, effectively improving the production capacity, and increasing the utilization rate of semiconductor processing equipment. That is, in the memory provided by the present invention, even if voids are formed in the node contact portion, for the node contact portion embedded in the substrate, the electrical connection performance between the node contact portion and the active region can be effectively compensated, ensuring the electrical conduction quality of the node contact portion. Based on this, the production capacity of the memory can be further improved.

[0010] Further, a node contact window can be defined by using a bit line structure, and the bottom of the node contact window also extends into the substrate so that the bottom of the node contact window is more sunken relative to the top surface of the substrate. At this time, since the top of the void in the node contact portion is not lower than the bottom of any adjacent bit line structure (for example, the void in the node contact portion has a part protruding above the top surface of the substrate), the void is correspondingly prevented from approaching the active region, ensuring the connection performance between the node contact portion and the active region.

[0011] Furthermore, the portion of the node contact window extending into the substrate, for example, includes a first groove and a second groove. The first groove corresponds to the trench isolation structure, and the second groove corresponds to the active region. By making the depth position of the second groove lower than the depth position of the first groove, the area of the active region exposed to the node contact window can be further increased, and thus the contact area between the node contact portion and the active region can be increased again. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a top view of a memory in an embodiment of the present invention;

[0013] Figure 2 is a cross-sectional schematic view of the memory in an embodiment of the present invention along the aa' direction with the node contact portion omitted;

[0014] Figure 3 is a cross-sectional schematic view of the memory in an embodiment of the present invention along the aa' direction;

[0015] Figure 4 is another structural schematic view of the memory in an embodiment of the present invention;

[0016] Figure 5Another structural schematic diagram of the memory in an embodiment of the present invention.

[0017] Among them, the reference numerals are as follows:

[0018] 100 - Substrate;

[0019] 101 - First source / drain region;

[0020] 102 - Second source / drain region;

[0021] 110 - Trench isolation structure;

[0022] 200a - Node contact window;

[0023] 200 - Node contact portion;

[0024] 200G - Void;

[0025] 210G - First void;

[0026] 220G - Second void;

[0027] 300 - Bit line structure;

[0028] 300a - Depression;

[0029] 310 - Bit line;

[0030] 311 - First conductive layer;

[0031] 312 - Second conductive layer;

[0032] 313 - Third conductive layer;

[0033] 320 - Masking layer;

[0034] 330 - Isolation sidewall;

[0035] 331 - First isolation layer;

[0036] 332 - Second isolation layer;

[0037] 333 - Third isolation layer;

[0038] 400 - Spacing insulating line;

[0039] AA - Active region. Detailed implementation manners

[0040] The memory proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0041] Figure 1 The top view of the memory in an embodiment of the present invention Figure 2 The schematic cross-sectional view of the memory in an embodiment of the present invention, omitting the node contact part along the aa' direction Figure 3 The schematic cross-sectional view of the memory in an embodiment of the present invention along the aa' direction. It should be noted that Figure 1 In the shown top view, the schematic of some components is omitted. For example Figure 1 Components such as word lines and node contact parts are not schematically shown in to facilitate a clearer understanding of this solution

[0042] Combined with Figures 1 to 3 As shown, the memory includes a substrate 100, and a bit line structure 300 and a node contact part 200 formed on the substrate 100

[0043] Specifically, a plurality of active regions AA are formed in the substrate 100. For example, a first source / drain region 101 and a second source / drain region 102 are formed in the plurality of active regions AA for constituting a memory transistor. Among them, adjacent active regions AA can be separated from each other by a trench isolation structure 110, for example

[0044] Furthermore, a plurality of word lines WL (not shown in the figure) are further formed in the substrate 100. The word lines WL extend along a first direction (X direction) and intersect with the corresponding active regions AA, and the part of the word lines WL intersecting with the active regions AA is located between the first source / drain region 101 and the second source / drain region 102, for constituting the gate structure of the memory transistor

[0045] Continuing to refer to Figures 1 to 3 As shown, a plurality of bit line structures 300 in the memory are formed on the substrate 100. Among them, the bit line structures 300 extend along a second direction (Y direction) and intersect with the corresponding active regions AA in space. The part of the bit line structures 300 intersecting with the active regions AA constitutes a bit line contact part, for example, and the bit line contact part is electrically connected to the active regions AA. In this embodiment, the bit line contact part is electrically connected to the second source / drain region 102 of the active regions AA

[0046] It can be considered that the bit line structure 300 has a bit line contact part and a bit line connection part connecting adjacent bit line contact parts, and the bit line connection part is formed on the top surface of the substrate 100

[0047] Focus on referring to Figure 1As shown, in this embodiment, there is at least one first source / drain region 101 corresponding between adjacent bit line structures 300. Based on this, the node contact window 200a can be further defined by using the adjacent bit line structures 300. It can be considered that the side walls facing each other between the adjacent bit line structures 300 also constitute the side walls of the node contact window 200a at the same time.

[0048] It should be recognized that when multiple bit line structures 300 all extend along the second direction (Y direction), at this time, the adjacent bit line structures 300 in the first direction are used to constitute the side walls facing each other in the first direction (X direction) of the node contact window 200a.

[0049] Continue to refer to Figure 1 As shown, on the surface of the substrate 100, for example, there may also be formed spacer insulating lines 400 extending along the first direction (X direction). The spacer insulating lines 400 intersect with the bit line structures 300 to define a plurality of grid openings, and the grid openings correspond to the node contact windows 200a. And the adjacent spacer insulating lines 400 in the second direction are used to constitute the side walls facing each other in the second direction (Y direction) of the node contact window 200a. That is to say, in this embodiment, the bit line structures 300 and the spacer insulating lines 400 can be used together to define the node contact window 200a.

[0050] Focus on referring to Figure 2 and Figure 3 As shown, the bottom of the node contact window 200a further extends into the substrate 100, so that a larger area of the active region AA (that is, at least part of the active region AA is exposed in the node contact window 200a) can be exposed in the node contact window 200a. That is, the bottom of the node contact window 200a is lower than the top surface of the substrate. In this way, it is beneficial to realize the electrical connection between the node contact portion 200 filled in the node contact window and the active region AA. In this embodiment, the first source / drain region 101 in the active region AA is exposed in the node contact window 200a.

[0051] And, the node contact portion 200 is filled in the node contact window 200a, and correspondingly, the bottom of the node contact portion 200 extends into the substrate 100 to be electrically connected to the active region AA. In this embodiment, the bottom of the node contact portion 200 is electrically connected to the first source / drain region 101 in the active region AA. In addition, the top of the node contact portion 200 is used to further connect a storage capacitor (not shown in the figure), for example.

[0052] Focus on referring to Figure 3As shown, at least one void 200G is formed in the node contact portion 200. In this embodiment, the top of the void 200G in the node contact portion 200 is not lower than the bottom of any adjacent bit line structure 300. For example, the void 200G in the node contact portion 200 has a portion protruding above the top surface of the substrate, so that the void 200G in the node contact portion 200 is set away from the active region AA, thus avoiding the void 200G approaching the active region AA, which is beneficial to ensuring the connection performance between the node contact portion 200 and the active region AA.

[0053] Of course, it is also possible to further lower the bottom of the void 200G in the node contact portion 200 below the top surface of the substrate 100, as long as it is ensured that the void 200G in the node contact portion 200 does not extend to the inner wall of the node contact window 200a.

[0054] It should be noted that although a void 200G is formed in the node contact portion 200, the node contact portion 200 in this embodiment is embedded in the substrate 100, which is beneficial to increasing the contact area between the node contact portion 200 and the active region AA. Moreover, in the active region AA into which ions are implanted, the ion concentration corresponding to the inside of the substrate is usually higher than the ion concentration corresponding to the surface of the substrate. Therefore, extending the node contact portion 200 into the substrate 100 can enable the node contact portion 200 to be electrically connected to the region with a higher ion concentration. In this way, it is beneficial to reduce the contact resistance between the node contact portion 200 and the active region AA.

[0055] It can be seen that due to the larger contact area between the node contact portion 200 and the active region AA, and the node contact portion 200 can be electrically connected to the high ion concentration region of the active region AA, the connection performance between the node contact portion 200 and the active region AA can be further improved. Based on this, even if a void 200G is formed in the node contact portion 200, it will not have a great impact on the performance of the node contact portion 200.

[0056] It should also be noted that since a void 200G can be allowed to be formed in the node contact portion 200, based on this, when preparing the node contact portion 200, the node contact portion 200 can be prepared faster by using a rapid deposition method, which can then accelerate the preparation process of the memory, effectively improve the production capacity, and increase the utilization rate of semiconductor processing equipment.

[0057] Continue to refer to Figure 2 and Figure 3As shown, the bit line contact portion in the bit line structure 300 that intersects with the active region AA is further embedded into the substrate 100. That is, the bottom of the bit line contact portion is lower than the top surface of the substrate. In this way, the bit line contact portion of the bit line structure 300 can be in full contact with the second source / drain region 102, reducing the contact resistance between the bit line structure 300 and the second source / drain region 102.

[0058] In this embodiment, the depth position at which the bit line contact portion in the bit line structure 300 is embedded into the substrate 100 is further lower than the depth position at which the node contact portion 200 is embedded into the substrate 100.

[0059] Specifically, a bit line contact window for accommodating the bit line contact portion is formed in the substrate 100. The bit line contact window extends to a predetermined depth position of the substrate 100 and exposes the second source / drain region 102 of the active region AA. And, the bit line contact portion in the bit line structure 300 fills the bit line contact window to be electrically connected to the second source / drain region 102. Correspondingly, the bottom position of the bit line contact window is lower than the bottom position of the node contact window 200a.

[0060] Focus on Figure 3 As shown, the void 200G in the node contact portion 200 includes a first void 210G. The first void 210G is close to the bottom of the bit line structure 300, and the top of the first void 210G is located in the region facing each other between adjacent bit line structures 300. Correspondingly, the top of the first void 210G is not lower than the bottom of any adjacent bit line structure 300.

[0061] Specifically, the region facing each other between adjacent bit line structures 300 is usually the region of the bit line structure 300 that protrudes above the top surface of the substrate. For example, the portions of adjacent bit line structures 300 that form the node contact window 200a include: a bit line connection portion corresponding to one of the bit line structures (formed on the top surface of the substrate), and a bit line contact portion corresponding to the other bit line structure (embedded into the substrate). At this time, the region facing each other between adjacent bit line structures 300 is the region between the bottom of the bit line connection portion and the top of the bit line structure.

[0062] In this embodiment, the bottom position of the bit line connection portion corresponds to the first height position H1. Therefore, the bottom boundary of the region facing each other between adjacent bit line structures 300 corresponds to the first height position H1, and the top position of the first void 210G is higher than the first height position H1. In this embodiment, the bottom position of the first void 210G can also be lower than the first height position H1.

[0063] Continue to refer to Figure 2 andFigure 3 As shown, the bit line structure 300 includes a bit line 310 , which is formed on the substrate 100 and electrically connected to the corresponding active area AA.

[0064] Specifically, the bit line 310 includes a first conductive layer 311, a second conductive layer 312, and a third conductive layer 313 which are stacked in sequence. The material of the first conductive layer 311 includes, for example, doped polysilicon, the material of the second conductive layer 312 includes, for example, titanium nitride, and the material of the third conductive layer 313 includes, for example, tungsten. In this embodiment, the bottom position of the first conductive layer 311 of the bit line connection portion in the bit line structure 300 corresponds to the first height position H1, and the top of the first gap 210G is located in the region where two first conductive layers 311 in the adjacent bit line structures 300 face each other.

[0065] Continue to refer Figure 2 As shown, a recess 300a is further formed on the outer side wall of the bottom of the bit line structure 300, and the opening of the recess 300a is laterally exposed in the gap between adjacent bit line structures 300. It can be considered that in this embodiment, by forming the recess 300a at the bottom of the bit line structure 300, the spacing size of the adjacent bit line structures 300 at the bottom is increased, and at this time, the node contact part 200 fills the recess 300a accordingly, and the bottom of the node contact part 200 also has a larger size, so as to increase the contact area between the active area AA.

[0066] Furthermore, the recesses 300a formed on the adjacent bit line structures 300 are arranged opposite to each other. Also, in this embodiment, the first gap 210G in the node contact portion 200 is located in the region where two recesses 300a in the adjacent bit line structures 300 are opposite to each other.

[0067] Continue to refer Figure 2 As shown, in this embodiment, a groove is further formed in the substrate between adjacent bit line structures 300, and the opening of the groove is exposed in the gap between adjacent bit line structures 300. It can be considered that the portion of the node contact window 200a extending into the substrate 100 includes a groove formed in the substrate 100, and the first source / drain region 101 is exposed in the groove. And, in this embodiment, the bottom boundary of the recess 300a in the bit line structure 300 is also connected to the boundary of the groove to jointly define a first opening portion with a larger opening size in the bit line contact window 200a. Specifically, the inner wall of the recess 300a and the inner wall of the groove are smoothly connected.

[0068] Key References Figure 2As shown, a trench isolation structure 110 is further formed in the substrate 100 to separate adjacent active regions AA, and at least a part of the active region (i.e., the first source / drain region 101) and at least a part of the trench isolation structure 110 are simultaneously exposed in the node contact window 200a.

[0069] In this embodiment, the grooves formed in the substrate 100 include a first groove and a second groove. The first groove corresponds to the trench isolation structure 110, and the second groove corresponds to the active region AA. The depth position of the second groove is lower than that of the first groove. Thus, a larger area of the active region (i.e., the first source / drain region 101) can be exposed through the second groove, which is more conducive to extending the node contact portion into the high ion concentration region in the active region.

[0070] Based on this, in this embodiment, the bottom boundary of the recess 300a at the bottom of the bit line structure 300 abuts against the adjacent first groove and second groove to jointly define the first opening of the bit line contact window 200a.

[0071] As described above, in the bit line structure 300, the bit line contact portion is embedded in the substrate 100, and the bit line connection portion for connecting adjacent bit line contact portions is formed on the top surface of the substrate 100, that is, the bottom of the bit line contact portion is lower than the bottom of the bit line connection portion. Based on this, the bottom of the recess 300a in the bit line connection portion can stop at the top surface of the substrate 100, and the recess 300a in the bit line connection portion is smoothly connected to the groove in the substrate 100 on the top surface of the substrate; and the bottom of the recess 300a in the bit line contact portion is lower than the top surface of the substrate, and the recess 300a in the bit line contact portion is smoothly connected to the groove in the substrate 100 inside the substrate.

[0072] Further, the bit line connection portion in the bit line structure 300 is formed above the trench isolation structure 110, and the side of the bit line connection portion corresponds to the active region AA (i.e., the first source / drain region 101). Therefore, the recess 300a in the bit line connection portion is connected to the second groove in the active region. And the bit line contact portion in the bit line structure 300 is formed on the active region (i.e., the second source / drain region 102), and the bit line contact portion also extends laterally into the trench isolation structure 110, so that the recess 300a in the bit line contact portion can be connected to the first groove in the trench isolation structure 110.

[0073] Continue to combine Figure 2 and Figure 3As shown, the first void 210G in the node contact portion 200 of the present embodiment is formed in the first opening portion, and the top of the first void 210G is located in the region where two recesses 300a in adjacent bit line structures 300 face each other. At this time, the top of the first void 210G is not lower than the bottom boundary of the recess 300a in the bit line structure 300.

[0074] Of course, in an alternative embodiment, the bottom of the first void 210G may also extend into the groove of the substrate 100, so that the bottom of the first void 210G is lower than the top surface of the substrate 100.

[0075] Continue to refer to Figure 3 As shown, the first void 210G is located between adjacent bit line structures 300, and the first void 210G is more biased towards one bit line structure than the other. That is, the first void 210G is more biased towards the other bit line structure between adjacent bit line structures 300, rather than corresponding to the intermediate position between adjacent bit line structures 300.

[0076] Specifically, in the present embodiment, the depth position of the second groove formed in the active region AA is lower than the depth position of the first groove formed in the trench isolation structure 110. Based on this, the vertical center line of the first void 210G is more biased towards the second groove than the first groove.

[0077] Continue to refer to Figure 3 As shown, a second void 220G is also formed in the node contact portion 200. The top and bottom of the second void 220G are both located in the region where adjacent bit line structures 300 face each other, and the second void 220G is located at the intermediate position between adjacent bit line structures 300.

[0078] It should be noted that the portion where adjacent bit line structures 300 face each other is the portion of the bit line structure 300 that protrudes above the top surface of the substrate, that is, the portion of the bit line structure 300 that is higher than the first height position H1. Equivalently, the overall height position of the second void 220G is higher than the first height position H1.

[0079] In the present embodiment, the second void 220G is specifically located in the region where two third conductive layers 313 in adjacent bit line structures 300 face each other. Specifically, the bottom position of the third conductive layer 313 corresponds to the third height position H3, and the top position of the third conductive layer 313 corresponds to the fourth height position H4. Therefore, the second void 220G is located between the third height position H3 and the fourth height position H4.

[0080] It should be noted that in this embodiment, the first opening of the bit line contact window 200a can be defined jointly by the recess 300a at the bottom of the bit line structure 300 and the groove in the substrate 100. In addition, the second opening of the bit line contact window 200a with a smaller opening size can be defined by the corresponding part of the adjacent bit line structures 300 above the recess 300a. That is, the area corresponding to the recess 300a above the adjacent bit line structures 300 is used to form the second opening.

[0081] It can be understood that the node contact window 200a in this embodiment has a first opening and a second opening that are vertically connected. Among them, the first opening is defined by the recess 300a in the bit line structure 300 and the groove in the substrate 100, so that the bottom of the first opening extends into the substrate 100, and the top of the first opening is higher than the top surface of the substrate 100. The second opening communicates with the top of the first opening and corresponds to the area of the bit line structure 300 above the recess 300a.

[0082] Correspondingly, the maximum opening size of the first opening is larger than the maximum opening size of the second opening. That is, the node contact window 200a in this embodiment has a structure that is narrower at the top and wider at the bottom. Among them, since the first opening extends into the substrate 100 and also has a larger opening size, it is beneficial to further increase the area of the active region AA exposed in the node contact window 200a, and further increase the contact area between the node contact portion 200 and the active region AA.

[0083] In this embodiment, the second gap 220G is formed in the second opening. And, the maximum width size of the first gap 210G is greater than twice the maximum width size of the second gap 220G.

[0084] Continue to refer to Figure 2 As shown, the bit line structure 300 may further include a shielding layer 320 and an isolation sidewall 330. Among them, the shielding layer 320 is formed above the bit line 310 to cover the bit line 310 from above. And, the isolation sidewall 330 covers at least the sidewall of the bit line 310 and the sidewall of the shielding layer 320.

[0085] As described above, the bit line contact portion of the bit line structure 300 fills the bit line contact window. In this regard, in this embodiment, the width size of the bit line 310 of the bit line contact portion in the direction perpendicular to the extension direction of the bit line structure is smaller than the opening size of the bit line contact window, so that the bit line 310 and the sidewall of the bit line contact window are spaced apart from each other. Based on this, the isolation sidewall 330 can be further used to fill the gap between the bit line 310 and the bit line contact window.

[0086] In this embodiment, the recess 300a at the bottom of the bit line structure 300 can be formed in the isolation sidewall 330. Specifically, the recess 300a extends laterally from the outer sidewall of the isolation sidewall 330 in the direction towards the bit line and stops extending in the isolation sidewall 300 to prevent the bit line 310 from being exposed.

[0087] Among them, the isolation sidewall 330 may include a plurality of stacked structures. For example, in this embodiment, the isolation sidewall 330 includes a first isolation layer 331, a second isolation layer 332, and a third isolation layer 333 that sequentially cover the bit line 310. The first isolation layer 331 adheres to the sidewall of the bit line 310 and conforms to the sidewall of the bit line 310 into the bit line contact window to cover the sidewall of the bit line contact window. The second isolation layer 332 covers the first isolation layer 331 and can fill the gap between the bit line 310 and the bit line contact window. And the third isolation layer 333 covers the second isolation layer 332.

[0088] It should be noted that the first isolation layer 331, the second isolation layer 332, and the third isolation layer 333 may be made of the same material or different materials. In this embodiment, for example, both the first isolation layer 313 and the third isolation layer 333 are made of silicon oxide, and the second isolation layer 332 is made of silicon nitride, so that the isolation sidewall 330 with an O - N - O structure can be formed.

[0089] Based on this, in this embodiment, the recess 300a in the bit line structure 300 can specifically extend from the third isolation layer 333 to the second isolation layer 332 and stop extending in the second isolation layer 332. And the top boundary of the recess 300a in the bit line structure 300 is not higher than the top of the first conductive layer 311.

[0090] In Figure 3 In the shown embodiment, the top position of the first void 210G in the node contact portion 200 is higher than the first height position H1, and its bottom position is lower than the first height position H1.

[0091] However, in other embodiments, the top and bottom of the first void in the node contact portion 200 may both be located in the region where the adjacent bit line structures 300 face each other.

[0092] For example, as shown in Figure 4 In Figure 4 In the shown first void 210G', both its top position and bottom position are higher than the first height position H1. Further, Figure 4The first gap 210' in [the structure] is located in the region where two first conductive layers 311 in adjacent bit line structures 300 face each other. Specifically, in the mutually facing portions of adjacent bit line structures 300, the bottom position of the first conductive layer 311 formed on the top surface of the substrate corresponds to the first height position H1, and the top position of the first conductive layer 311 corresponds to the second height position H2. The first gap 210G' is located between the first height position H1 and the second height position H2.

[0093] In addition, in another embodiment, only one gap 200G may be formed in the node contact portion 200. For example, referring to Figure 5 As shown, it schematically shows a gap 200G, and the gap 200G is formed in the region where two first conductive layers 311 in adjacent bit line structures face each other.

[0094] In summary, in the memory provided in this embodiment, by further extending the node contact portion into the substrate to be electrically connected to the active region in the substrate, the contact area between the node contact portion and the active region can be increased, and the node contact portion can be electrically connected to the region with a high ion concentration in the active region, which is beneficial to improving the connection performance of the node contact portion. Based on this, even if a gap is formed in the node contact portion, the performance of the node contact portion can still be maintained. For the node contact portion that allows a gap, its manufacturing difficulty is lower, which is beneficial to accelerating the preparation process of the node contact portion, correspondingly improving the production capacity of the memory, and improving the utilization rate of semiconductor processing equipment.

[0095] It should be noted that the above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible changes and modifications can be made to the technical solution of the present invention by using the disclosed technical content above, or modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the protection of the technical solution of the present invention.

Claims

1. A memory, It is characterized in that include: A substrate having a plurality of active regions formed therein, wherein the active regions include a first source / drain region and a second source / drain region; A plurality of bit line structures are formed on the substrate, and node contact windows are defined by using adjacent bit line structures, the bottom of the node contact window also extends into the substrate and exposes at least part of the active area, the bit line structure includes a first conductive layer, a second conductive layer and a third conductive layer sequentially formed on the substrate; as well as, A plurality of node contacts are filled in the node contact windows and electrically connected to the active area, and at least one gap is formed in the node contact portions, wherein the at least one gap includes a first gap, and the top of the first gap is not lower than the bottom of any adjacent bit line structure, and the top of the first gap is located in a region where two first conductive layers in adjacent bit line structures face each other.

2. The memory according to claim 1, It is characterized in that The first gap is between two adjacent bit line structures and is closer to one bit line structure than to the other bit line structure.

3. The memory as claimed in claim 2, It is characterized in that A recess is formed on the outer sidewall of the bottom of the bit line structure, an opening of the recess is laterally exposed in the gap between adjacent bit line structures, and the node contact portion is formed between adjacent bit line structures and fills the recess.

4. The memory as claimed in claim 3, It is characterized in that The portion of the node contact window extending into the substrate includes a groove formed in the substrate, and the bottom boundary of the recess in the bit line structure receives the boundary of the groove to define a first opening portion of the bit line contact window.

5. The memory as claimed in claim 4, It is characterized in that The first gap is formed in the first opening, and a top of the first gap is located in a region where two recesses in adjacent bit line structures face each other.

6. The memory as claimed in claim 4, It is characterized in that A trench isolation structure is also formed in the substrate, and the adjacent active regions are separated by the trench isolation structure, and at least a portion of the trench isolation structure is exposed in the node contact window; The groove includes a first groove and a second groove, the first groove corresponds to the trench isolation structure, the second groove corresponds to the active area, and the depth position of the second groove is lower than the depth position of the first groove.

7. The memory as claimed in claim 3, It is characterized in that The bit line structure comprises a bit line and an isolation spacer, wherein the bit line is formed on a substrate and electrically connected to a corresponding active region, and the isolation spacer at least covers a side wall of the bit line; Furthermore, the recess in the bit line structure extends laterally from the outer sidewall of the isolation spacer in a direction toward the bit line, and stops in the isolation spacer.

8. The memory according to claim 1, It is characterized in that The at least one void includes a second void, the top and bottom of the second void are both between the regions where adjacent bit line structures face each other, and the second void is located at an intermediate position between adjacent bit line structures.

9. The memory according to claim 8, wherein, the bit line structure includes a first conductive layer, a second conductive layer, and a third conductive layer formed in sequence on the substrate, and the second void is located in the region where two third conductive layers in adjacent bit line structures face each other.

10. The memory according to claim 8, wherein, the at least one void further includes a first void, at least the top of the first void is between the regions where adjacent bit line structures face each other, and the first void is located below the second void, and the maximum width dimension of the first void is greater than twice the maximum width dimension of the second void.

11. The memory according to claim 8, wherein, a second opening of the bit line contact window is defined by a part of the adjacent bit line structures that protrudes above the top surface of the substrate, and the second void is formed in the second opening.

12. The memory according to claim 1, wherein, the bit line structure extends along a predetermined direction and intersects with a corresponding active region, a part of the bit line structure that intersects with the active region constitutes a bit line contact portion, the bit line contact portion is embedded in the substrate to be electrically connected to the active region, and the depth position of the bit line contact portion extending in the substrate is lower than the depth position of the node contact portion extending in the substrate.

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