A GIP circuit and control method thereof and GIP output signal detection circuit
By introducing precharge circuit, output circuit, pull-down circuit and transistor T10 into the GIP circuit, the output signal is introduced into the test signal line, which solves the problem that the GIP output signal cannot be detected in the prior art, improves the monitoring capability, and realizes the Quickly locate abnormal GIP series.
Patent Information
- Application Number
- CN202010325090.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-04-23
- Publication Date
- 2025-01-10
- Estimated Expiration
- 2040-04-23
AI Technical Summary
It is difficult to detect output signals at each level in existing GIP technology, resulting in insufficient monitoring and problem-solving capabilities.
A GIP circuit including a precharge circuit, an output circuit, a pull-down circuit and a transistor T10 is designed. The output signal is introduced into the test signal line through the transistor T10, connected to the test Pad, and each stage is detected by measuring the signal on the test Pad. output signal.
It effectively solves the situation in the existing GIP technology that the GIP output signal cannot be detected at each level, improves the ability to monitor and solve problems, can stably output the waveform of the test signal line, and quickly locate abnormal GIP series.
Smart Images
Figure CN111724750B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of panel technology, and in particular to a GIP circuit and a control method thereof, and a GIP output signal detection circuit. Background Art
[0002] In recent decades, with the progress of the times and the development of information technology, people's demand for electronic consumer products has increased day by day, which has promoted the development of the liquid crystal display industry. With the development of the times, electronic products are constantly developing in the direction of lightness, thinness and power saving. In the display industry, liquid crystal display occupies an important position. In the liquid crystal display screen, each pixel has a TFT (Thin Film Transistor, thin film field effect transistor), whose gate (Gate) is connected to the horizontal scanning line, the source (Drain) is connected to the vertical data line, and the source (Source) is connected to the pixel electrode. If a sufficient positive voltage is applied to a certain horizontal scanning line, all TFTs on the line will be turned on. At this time, the pixel electrode on the line will be connected to the vertical data line, and the video signal voltage on the data line will be written into the pixel, controlling the transmittance of different liquid crystals and thus achieving the effect of controlling color.
[0003] There are two main methods for driving the gate circuit: one is to bind the IC chip outside the panel; the other is to use GIP (GIP In Panel, that is, the gate is made on the glass substrate) technology; however, with the development of the times, people have higher and higher requirements for high screen-to-body ratio of panel displays, and GIP technology has become the main way to drive the gate circuit; and the basic concept of GIP is to integrate the gate driver of the LCD Panel (i.e. liquid crystal panel) on the glass substrate to replace the technology of external silicon wafer to form a scanning drive for the panel; compared with the traditional COF and COG processes, this technology not only saves costs, but also eliminates the process of binding the gate direction, which is extremely beneficial to improving production capacity and improving TFT-LCD (ThinFilm Transistor-Liquid Crystal Display, Thin Film Transistor Liquid Crystal Display) panel integration; therefore, GIP technology reduces the use of gate drive IC chips, reduces power consumption and cost, and can reduce the border of the display panel to achieve a narrow border design, which is a technology worthy of attention; however, since the GIP circuit relies on level transmission to drive and shut down the upper and lower circuits, in general, if there is a problem with the output signal of a certain level of the panel, it is difficult for us to determine which level of the output signal has a problem through measurement. Summary of the invention
[0004] The technical problem to be solved by the present invention is to provide a GIP circuit capable of effectively monitoring the output signal of each stage and a control method thereof and a GIP output signal detection circuit.
[0005] In order to solve the above technical problems, the first technical solution adopted by the present invention is:
[0006] A GIP circuit comprises a pre-charging circuit, an output circuit, a pull-down circuit and a transistor T10, wherein the pre-charging circuit is electrically connected to the output circuit, the pull-down circuit and the gate of the transistor T10 respectively, the output circuit is electrically connected to the pull-down circuit, the source of the transistor T10 and the clock signal of the peripheral device respectively, and the pre-charging circuit is electrically connected to the scanning signal line G n-4 The pull-down circuit is electrically connected to the scanning signal line G n+4 Electrically connected, the scanning signal line G n-4 and scanning signal line G n+4 The parameter n in is a positive integer greater than or equal to 4.
[0007] The second technical solution adopted by the present invention is:
[0008] A method for controlling a GIP circuit comprises the following steps:
[0009] Step S1, in a first time period, controlling the pre-charging circuit to input a high level;
[0010] Step S2, in the second time period, controlling the output circuit to input a high level;
[0011] Step S3, in the third time period, controlling the pull-down circuit to input a high level; the first time period, the second time period and the third time period are consecutive time periods.
[0012] The third technical solution adopted by the present invention is:
[0013] A GIP output signal detection circuit comprises more than two test signal lines, each of which is electrically connected to more than two of the above-mentioned GIP circuits.
[0014] The beneficial effects of the present invention are:
[0015] The GIP circuit designed by this scheme can introduce the output signal into the test signal line through the transistor T10 and connect it to the test pad. By measuring the signal on the test pad, the output signal of each level of GIP can be detected, which effectively solves the problem that the output signal of each level of GIP cannot be detected in the existing GIP technology, thereby improving the monitoring and problem-solving capabilities. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1A circuit connection block diagram of a GIP circuit according to the present invention;
[0017] Figure 2 A circuit schematic diagram of a GIP circuit according to the present invention;
[0018] Figure 3 A flow chart of the steps of a method for controlling a GIP circuit according to the present invention;
[0019] Figure 4 A circuit connection block diagram of a GIP output signal detection circuit according to the present invention;
[0020] Figure 5 A circuit simulation schematic diagram of a GIP output signal detection circuit according to the present invention;
[0021] Description of labels:
[0022] 1. Pre-charge circuit; 2. Output circuit; 3. Pull-down circuit; 4. Test signal line. DETAILED DESCRIPTION
[0023] In order to explain the technical content, achieved objectives and effects of the present invention in detail, the following is an explanation in conjunction with the implementation modes and the accompanying drawings.
[0024] Please refer to Figure 1 , a technical solution provided by the present invention:
[0025] A GIP circuit comprises a pre-charging circuit, an output circuit, a pull-down circuit and a transistor T10, wherein the pre-charging circuit is electrically connected to the output circuit, the pull-down circuit and the gate of the transistor T10 respectively, the output circuit is electrically connected to the pull-down circuit, the source of the transistor T10 and the clock signal of the peripheral device respectively, and the pre-charging circuit is electrically connected to the scanning signal line G n-4 The pull-down circuit is electrically connected to the scanning signal line G n+4 Electrically connected, the scanning signal line G n-4 and scanning signal line G n+4 The parameter n in is a positive integer greater than or equal to 4.
[0026] From the above description, it can be seen that the beneficial effects of the present invention are:
[0027] The GIP circuit designed by this scheme can introduce the output signal of the GIP circuit into the test signal line through the transistor T10 and connect it to the test pad. By measuring the signal on the test pad, the output signal of each level of GIP can be detected, which effectively solves the problem that the output signal of each level of GIP cannot be detected in the existing GIP technology, thereby improving the monitoring and problem-solving capabilities.
[0028] Furthermore, the pre-charging circuit includes a transistor T1, the gate of the transistor T1 is connected to the scanning signal line G n-4 The source of the transistor T1 is electrically connected to the output circuit and the pull-down circuit respectively.
[0029] It can be seen from the above description that in the pre-charging stage, the Q point is first charged by using the transistor T1.
[0030] Furthermore, the output circuit includes a transistor T4 and a capacitor C1, the gate of the transistor T4 is electrically connected to the pre-charging circuit, the pull-down circuit, the gate of the transistor T10 and one end of the capacitor C1, the drain of the transistor T4 is electrically connected to the clock signal, and the source of the transistor T4 is electrically connected to the other end of the capacitor C1, the source of the transistor T10 and the pull-down circuit.
[0031] From the above description, it can be seen that the output signal G is n Output, at the same time, the transistor T10 and Q point can be used to output the output signal G n It is introduced into the test signal line through transistor T10 to effectively monitor the output signal of each level.
[0032] Further, the pull-down circuit includes a transistor T2, a transistor T3, a transistor T5, a transistor T7, a transistor T8 and a transistor T9, the gate of the transistor T2 is electrically connected to the pre-charging circuit, the drain of the transistor T7, the output circuit and the gate of the transistor T10, the drain of the transistor T2 is electrically connected to the gate of the transistor T3, the drain of the transistor T8, the drain of the transistor T9 and the gate of the transistor T5, the source of the transistor T2 is electrically connected to the source of the transistor T3, the source of the transistor T9 and the source of the transistor T5, the gate of the transistor T8 is electrically connected to the source of the transistor T8, and the drain of the transistor T5 is electrically connected to the output circuit and the source of the transistor T10.
[0033] From the above description, it can be seen that the transistor in the pull-down circuit is connected to the Q point and the output signal G n After the pull-down is completed, the transistor in the pull-down circuit continues to be used to connect the Q point and the output signal G. n Pull down and stabilize; pull out the output signal of GIP through transistor T10 for testing, and through the voltage doubling effect of Q point, the output signal of each level can be effectively detected without introducing more signal lines.
[0034] Furthermore, the transistor T10 is a thin film transistor.
[0035] Furthermore, the drain of the transistor T10 of the GIP circuit is electrically connected to a test signal line of an external device.
[0036] Please refer to Figure 3 , the second technical solution provided by the present invention is:
[0037] A method for controlling a GIP circuit comprises the following steps:
[0038] Step S1, in a first time period, controlling the pre-charging circuit to input a high level;
[0039] Step S2, in the second time period, controlling the output circuit to input a high level;
[0040] Step S3, in the third time period, control the pull-down circuit to input a high level; the first time period, the second time period and the third time period are consecutive time periods, and the time periods of the first time period, the second time period and the third time period are all equal.
[0041] Please refer to Figure 4 , the third technical solution provided by the present invention is:
[0042] A GIP output signal detection circuit comprises more than two test signal lines, each of which is electrically connected to more than two of the above-mentioned GIP circuits.
[0043] From the above description, it can be seen that the beneficial effects of the present invention are:
[0044] The waveform of the test signal line of the GIP output signal detection circuit designed in this scheme can be output stably. If the output waveform of a certain level is abnormal, the output waveform on the test signal line can be used to deduce the abnormal GIP level, which is conducive to users to better solve panel problems. At the same time, due to the voltage doubling effect of the Q point of the GIP circuit designed in this scheme, the output signal of each level can be effectively monitored without introducing too many TFT elements and signal lines.
[0045] Furthermore, the drain of the transistor T10 of the GIP circuit is electrically connected to the test signal line.
[0046] Please refer to Figure 1 and Figure 2 , Embodiment 1 of the present invention is:
[0047] Please refer to Figure 1 A GIP circuit comprises a pre-charging circuit 1, an output circuit 2, a pull-down circuit 3 and a transistor T10, wherein the pre-charging circuit 1 is electrically connected to the output circuit 2, the pull-down circuit 3 and the gate of the transistor T10 respectively, the output circuit 2 is electrically connected to the pull-down circuit 3, the source of the transistor T10 and the clock signal of the peripheral device respectively, and the pre-charging circuit 1 is electrically connected to the scanning signal line G n-4 The pull-down circuit 3 is electrically connected to the scanning signal line G n+4Electrically connected, the scanning signal line G n-4 and scanning signal line G n+4 The parameter n in is a positive integer greater than or equal to 4.
[0048] Please refer to Figure 2 The pre-charging circuit 1 includes a transistor T1, the gate of the transistor T1 is connected to the scanning signal line G n-4 The source of the transistor T1 is electrically connected to the output circuit 2 and the pull-down circuit 3 respectively.
[0049] Please refer to Figure 2 The output circuit 2 includes a transistor T4 and a capacitor C1, the gate of the transistor T4 is electrically connected to the pre-charging circuit 1, the pull-down circuit 3, the gate of the transistor T10 and one end of the capacitor C1, the drain of the transistor T4 is electrically connected to the clock signal, and the source of the transistor T4 is electrically connected to the other end of the capacitor C1, the source of the transistor T10 and the pull-down circuit 3.
[0050] Please refer to Figure 2 The pull-down circuit 3 includes a transistor T2, a transistor T3, a transistor T5, a transistor T7, a transistor T8 and a transistor T9, the gate of the transistor T2 is electrically connected to the pre-charging circuit 1, the drain of the transistor T7, the output circuit 2 and the gate of the transistor T10, the drain of the transistor T2 is electrically connected to the gate of the transistor T3, the drain of the transistor T8, the drain of the transistor T9 and the gate of the transistor T5, the source of the transistor T2 is electrically connected to the source of the transistor T3, the source of the transistor T9 and the source of the transistor T5, the gate of the transistor T8 is electrically connected to the source of the transistor T8, and the drain of the transistor T5 is electrically connected to the output circuit 2 and the source of the transistor T10.
[0051] The sizes of the above-mentioned transistors are as follows (the width and length of the transistor (i.e., TFT) will affect the electrical properties of the transistor, so the width and length size design of the transistor will affect the circuit operation during circuit design. The full name of W in the above is Width, which means the width of the transistor channel, and the full name of L is Length, which means the length of the transistor channel. Therefore, W / L represents the size of the width and length of the transistor):
[0052] The W / L of T1 is 100um / 4um;
[0053] The W / L of T2 is 120um / 4.5um;
[0054] The W / L of T3 is 120um / 4.5um;
[0055] The W / L of T4 is 2700um / 4um;
[0056] The W / L of T5 is 200um / 4um;
[0057] The W / L of T7 is 100um / 4um;
[0058] The W / L of T8 is 30um / 5um;
[0059] The W / L of T9 is 30um / 5um;
[0060] The above-mentioned transistor size is only one of them. In practical application, the appropriate size can be selected according to the requirements.
[0061] The capacitance values of capacitor C1 and capacitor C2 are both 1000fF.
[0062] The pull-down circuit 3 works in two different intervals (pre-charge period and pull-down period):
[0063] During pre-charge: Scan signal line G n-4 is a high potential (or high level), the transistor T1 is turned on, the source of the transistor T1 is connected to the high potential FW, the Q point is charged to a high potential, at this time the transistor T2 is turned on, the drain of the transistor T2 is connected to the low potential VGL, and the P point is pulled to a low potential;
[0064] Pull-down period: Scan signal line G n+4 =High potential (or high level), transistor T7 is turned on, the source of transistor T7 is connected to BW which is low potential, point Q is pulled down by transistor T7, and the gate of transistor T8 is VH which is high potential, transistor T8 is turned on, point P is charged to high potential, then transistor T3 and transistor T5 are turned on, the source of transistor T3 and the source of transistor T5 are connected to low potential VGL, then the potential of point Q and G n The potential is pulled low.
[0065] The transistor T2 , the transistor T3 , the transistor T4 , the transistor T5 , the transistor T6 , the transistor T7 , the transistor T8 , the transistor T9 and the transistor T10 are all thin film transistors.
[0066] The drain of the transistor T10 of the GIP circuit is electrically connected to a test signal line of an external device.
[0067] In the pre-charge stage, the transistor T1 in the GIP circuit pre-charge circuit 1 is used to charge the Q point first; after the charging is completed, it is the output stage, at this time, the transistor T4 of the output circuit 2 is used to output the output signal G n At the same time, the output signal G can be output by using the transistor T10 and Q point of the test circuit. nThrough the transistor T10, it is introduced to the test signal line 4, effectively monitoring the output signal of each level; after the output is completed, the transistor in the pull-down circuit 3 is first used to connect the Q point and the output signal G n After the pull-down is completed, the transistor in the pull-down circuit 3 continues to be used to connect the Q point and the output signal G n Pull down and stabilize; use transistor T10 to pull out the output signal of GIP for testing, and use the voltage doubling effect of Q point to effectively detect the output signal of each level without introducing more signal lines; when there is a problem with the output signal of panel GIP, the test result can be used to quickly find the problematic GIP level; using this circuit, the double voltage effect of Q point is used to make the waveform of the output signal more stable, which is conducive to the test line to test the output signal more effectively.
[0068] Please refer to Figure 3 , Embodiment 2 of the present invention is:
[0069] A method for controlling a GIP circuit comprises the following steps:
[0070] Step S1, in the first time period, controlling the pre-charging circuit 1 to input a high level;
[0071] Step S2, in the second time period, controlling the output circuit 2 to input a high level;
[0072] Step S3, in the third time period, control the pull-down circuit 3 to input a high level; the first time period, the second time period and the third time period are consecutive time periods, and the time periods of the first time period, the second time period and the third time period are equal.
[0073] Please refer to Figure 4 and Figure 5 , Embodiment 3 of the present invention is:
[0074] Please refer to Figure 4 , a GIP output signal detection circuit includes more than two test signal lines 4, each of which is electrically connected to more than two of the above-mentioned GIP circuits.
[0075] The drain of the transistor T10 of the GIP circuit is electrically connected to the test signal line 4 .
[0076] Please refer to Figure 5Through the simulation, we can see that the waveform of the test signal line 4 can be output stably. If the output waveform of a certain level is abnormal, the user can use the output waveform on the test signal line 4 to deduce the abnormal GIP level, which is helpful for users to better solve panel problems. At the same time, due to the voltage doubling effect of the Q point of the GIP circuit designed in this solution, the output signal of each level can be effectively monitored without introducing too many TFT elements and signal lines.
[0077] The specific embodiments of this scheme are:
[0078] It can be divided into four stages: pre-charge stage, output stage, pull-down stage and pull-down maintenance stage;
[0079] During the pre-charge period: control transistor T1 inputs a high level, that is, the scanning signal line G n-4 The signal is high potential. At this time, the Q point is charged through the transistor T1 of the pre-charge circuit 1, and the potential of the Q point is high potential (recorded as V H ), G n and P is at a low potential (denoted as V L ), in this stage, the pre-charging of the Q point is completed. At the same time, affected by the Q point, the drain of the transistor T10 outputs a low potential, which can pull down the output signal of the previous stage;
[0080] During the output period, the drain of the control transistor T4 inputs a high level, that is, the CK1 signal is at a high potential, and the potential of the Q point is also at a high potential. Due to the coupling effect of the capacitor, the potential of the Q point increases by about 2V. H , stabilized G n The output voltage V H At the same time, affected by the double voltage of point Q, the transistor T10 in the test circuit will be turned on, and the output signal G n Output to the test end to achieve the purpose of monitoring each level of output signal;
[0081] During the pull-down period: the gate of the control transistor T7 is input high level, that is, G n+4 The signal is at high potential, and the P point and other signal lines are also at high potential. Through the transistor in the pull-down circuit 3, the Q point and G n Pull down from the original high potential to V L ;
[0082] During the pull-down maintenance period: use P point and other signal lines to maintain Q point and G point through the transistor in the pull-down circuit 3. n of low potential.
[0083] In summary, the present invention provides a GIP circuit and its control method and a GIP output signal detection circuit. The GIP circuit designed in this scheme can introduce the output signal into the test signal line through the transistor T10 and connect it to the test pad. By measuring the signal on the test pad, the output signal of each level of GIP can be detected, which effectively solves the problem that the output signal of each level of GIP cannot be detected in the existing GIP technology, thereby improving the monitoring and problem-solving capabilities.
[0084] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent transformations made using the contents of the present invention's specification and drawings, or directly or indirectly applied in related technical fields, are also included in the patent protection scope of the present invention.
Claims
1. A GIP circuit, characterized in that: The present invention comprises a pre-charging circuit, an output circuit, a pull-down circuit and a transistor T10, wherein the pre-charging circuit is electrically connected to the output circuit, the pull-down circuit and the gate of the transistor T10 respectively, and the output circuit is electrically connected to the pull-down circuit, the source of the transistor T10 and the clock signal of the peripheral device respectively, and the pre-charging circuit is electrically connected to the scanning signal line G n-4 The pull-down circuit is electrically connected to the scanning signal line G n+4 Electrically connected, the scanning signal line G n-4 and scanning signal line G n+4 The parameter n in is a positive integer greater than or equal to 4; The pre-charging circuit includes a transistor T1, the gate of the transistor T1 is connected to the scanning signal line G n-4 The source of the transistor T1 is electrically connected to the output circuit and the pull-down circuit respectively; The output circuit includes a transistor T4 and a capacitor C1, the gate of the transistor T4 is electrically connected to the pre-charging circuit, the pull-down circuit, the gate of the transistor T10 and one end of the capacitor C1, the drain of the transistor T4 is electrically connected to the clock signal, and the source of the transistor T4 is electrically connected to the other end of the capacitor C1, the source of the transistor T10 and the pull-down circuit; The pull-down circuit includes a transistor T2, a transistor T3, a transistor T5, a transistor T7, a transistor T8 and a transistor T9, the gate of the transistor T2 is electrically connected to the pre-charging circuit, the drain of the transistor T7, the output circuit and the gate of the transistor T10, the drain of the transistor T2 is electrically connected to the gate of the transistor T3, the drain of the transistor T8, the drain of the transistor T9 and the gate of the transistor T5, the source of the transistor T2 is electrically connected to the source of the transistor T3, the source of the transistor T9 and the source of the transistor T5, the gate of the transistor T8 is electrically connected to the source of the transistor T8, and the drain of the transistor T5 is electrically connected to the output circuit and the source of the transistor T10.
2. The GIP circuit according to claim 1, characterized in that: The transistor T10 is a thin film transistor.
3. The GIP circuit according to claim 1, characterized in that: The drain of the transistor T10 of the GIP circuit is electrically connected to a test signal line of an external device.
4. A method for controlling a GIP circuit according to any one of claims 1 to 3, characterized in that: The following steps are involved: Step S1, in a first time period, controlling the pre-charging circuit to input a high level; Step S2, in the second time period, controlling the output circuit to input a high level; Step S3, in the third time period, control the pull-down circuit to input a high level; the first time period, the second time period and the third time period are consecutive time periods, and the time periods of the first time period, the second time period and the third time period are all equal.
5. A GIP output signal detection circuit, characterized in that: It comprises more than two test signal lines, each of which is electrically connected to more than two GIP circuits according to any one of claims 1 to 3.
6. The GIP output signal detection circuit according to claim 5, characterized in that: The drain of the transistor T10 of the GIP circuit is electrically connected to the test signal line.
Citation Information
Patent Citations
GIP circuit and GIP output signal detection circuit
CN212256869U